Circuit board and electronic element package

Abstract

To provide a circuit board that can suppress cracks in a resin area at the edge of a cavity of a printed circuit board.SOLUTION: A circuit board includes a substrate having a first and second surface facing each other, including an insulating layer disposed between the first and second surfaces, and having a cavity penetrating in the direction perpendicular to the first surface, a first wiring pattern embedded in the insulating layer on the first surface and configured to enable signal transmission, and a first reinforcement pattern embedded in the insulating layer on the first surface, disposed around the cavity at a distance from the edge of the cavity, and separated from the first wiring pattern.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to circuit boards and electronic device packages. [Background technology]

[0002] Due to the trend towards miniaturization and multi-functionality of electronic products, semiconductor packaging technology is becoming more highly integrated and functional. Conventional interposer POP packaging technology has limitations in heat dissipation due to the constraints on the thickness of the mounted chip. As a result, PLP (Panel Level Package) packaging technology, which improves heat dissipation by relaxing the constraints on chip thickness, is attracting attention. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-80030 A Summary of the Invention [Problem to be solved by the invention]

[0004] PLP packaging uses a prepreg (PPG) type printed circuit board. PPG is a laminate of resin and glass fabric. When the smear removal process is performed after cavity processing, the glass fabric is etched, which can cause cracks in the PPG resin due to mechanical / physical loads during the packaging process.

[0005] These cracks can cause coating defects when applying photosensitive insulating material during the PLP packaging process. Therefore, there is a need to improve the structure of the circuit board and its manufacturing method to ensure the quality of the cavity area of ​​the printed circuit board in the chip mounting area.

[0006] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a circuit board, an electronic device package, and a method for manufacturing the circuit board, which are capable of suppressing cracks in the resin area at the edge of a cavity in a printed circuit board. However, the problems to be solved by the embodiments of the present invention are not limited to the above problems and may be variously expanded within the scope of the technical ideas included in the present invention. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, one embodiment of the present invention provides a circuit board comprising a substrate having a first surface and a second surface facing each other, an insulating layer disposed between the first surface and the second surface, and a cavity extending in a direction perpendicular to the first surface; a first wiring pattern embedded in the insulating layer on the first surface to enable signal transmission; and a first reinforcement pattern embedded in the insulating layer on the first surface, disposed around the cavity and spaced apart from the edge of the cavity, and separated from the first wiring pattern.

[0008] The first reinforcement pattern may include a metal. The first reinforcement pattern may be electrically isolated. The first reinforcement pattern may be covered with the insulating layer so as not to be exposed in the cavity. The first reinforcement pattern may have the same height as the first wiring pattern. The first wiring pattern may be spaced apart from the first reinforcing pattern in a direction away from the cavity.

[0009] The circuit board may further include a second wiring pattern disposed on the insulating layer at the second surface and configured to enable signal transmission, a second reinforcement pattern disposed on the insulating layer at the second surface, disposed around the cavity and spaced apart from an edge of the cavity, and separated from the second wiring pattern, and a via embedded in the insulating layer and connecting the first wiring pattern and the second wiring pattern to each other. The second reinforcement pattern may protrude above the second surface to have the same height as the second wiring pattern. The second wiring pattern may be spaced apart from the second reinforcing pattern in a direction away from the cavity. The first reinforcement pattern and the second reinforcement pattern may be disposed to at least partially overlap each other along a direction perpendicular to the first surface. The first reinforcement pattern may include a plurality of reinforcement pads spaced apart from one another along an edge of the cavity. The first reinforcement pattern may be configured to be continuous along an edge of the cavity to surround the cavity. The cavity may include four sides, and the first reinforcement pattern may include reinforcement pads disposed on each of the four sides.

[0010] In order to achieve the above-mentioned object, an electronic element package according to one embodiment of the present invention includes a substrate having a first surface and a second surface facing each other, an insulating layer disposed between the first surface and the second surface, and a cavity penetrating in a direction perpendicular to the first surface, a first wiring pattern embedded in the insulating layer on the first surface to enable signal transmission, a first reinforcement pattern embedded in the insulating layer on the first surface, disposed around the cavity and spaced apart from the edge of the cavity, and separated from the first wiring pattern, an electronic element accommodated in the cavity, and a redistribution layer disposed on the first surface side of the substrate to which the electronic element is connected.

[0011] The semiconductor device may further include an insulating protection layer disposed between the first surface of the substrate and the redistribution layer so as to cover the first reinforcement pattern. The first reinforcement pattern may be electrically isolated. The first reinforcement pattern may be covered with the insulating layer so as not to be exposed in the cavity. The first wiring pattern may be spaced apart from the first reinforcing pattern in a direction away from the cavity. Effect of the Invention

[0012] According to the circuit board of the present invention, the packaging yield can be secured by preventing cracks from occurring in the resin area at the edge of the cavity during a panel level package (PLP) process. In addition, it can improve coating defects when applying photo-imageable dielectric (PID) in the PLP process. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of an electronic device package showing a state in which an electronic device is mounted on a circuit board according to an embodiment; [Diagram 2] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Diagram 3] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 13]1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating process steps of a method for manufacturing a circuit board according to an embodiment of the present invention. [Figure 15] FIG. 2 is a bottom view of a circuit board according to one embodiment. [Figure 16] FIG. 13 is a bottom view of a circuit board according to another embodiment. [Figure 17] FIG. 13 is a bottom view of a circuit board according to another embodiment. [Figure 18] FIG. 13 is a bottom view of a circuit board according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, with reference to the drawings, the embodiments of the present invention will be described in detail so that those skilled in the art can easily carry out the present invention. In order to clearly explain the present invention in the drawings, parts unnecessary for the explanation are omitted, and the same or similar components are given the same reference numerals throughout the specification. In addition, in the drawings, some components are exaggerated, omitted, or shown in a schematic manner, and the size of each component does not completely reflect the actual size.

[0015] The drawings are intended to facilitate understanding of the embodiments disclosed in this specification, and are not intended to limit the technical ideas disclosed in this specification. It should be understood that the drawings include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0016] Terms including ordinal numbers such as first, second, etc. are used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0017] Furthermore, when a part such as a layer, film, region, or plate is "on" or "above" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when a part is "directly on" another part, it means that there is no other part in between. Furthermore, when a part is "on" or "above" a reference part, it means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "above" the direction opposite to gravity.

[0018] Throughout the specification, the terms "comprise" or "have" and the like are intended to specify the presence of a specified feature, number, step, operation, component, part, or combination thereof, but should be understood as not precluding the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part is said to "comprise" a certain component, this means that it can further include other components, but not to the exclusion of other components, unless specifically stated to the contrary.

[0019] Also, throughout the specification, the term "on a plane" means when the part is viewed from above, and the term "on a cross section" means when the part is cut vertically and viewed from the side.

[0020] In addition, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, or that they are not only physically connected, but also electrically connected, or that they are referred to by different names depending on their location or function but are integrated.

[0021] FIG. 1 is a cross-sectional view of an electronic device package showing a state in which an electronic device is mounted on a circuit board according to an embodiment.

[0022] 1, an electronic device package 100 is configured by mounting an electronic device 70 on a circuit board 101 according to the present embodiment. The electronic device 70 includes various elements such as an active element, a passive element, an integrated circuit (IC), etc., and may be, for example, a semiconductor chip. The circuit board 101 is used for a semiconductor package and is configured as a printed circuit board.

[0023] The circuit board 101 includes a substrate 110 having a first surface 110a and a second surface 110b facing each other, an insulating layer 112, and wiring patterns 121 and 122 disposed inside or on the surface of the substrate 110. The substrate 110 has a cavity 119 that penetrates vertically through the first surface 110a. Reinforcing patterns 131 and 132 are disposed inside or on the surface of the insulating layer 112 around the cavity 119.

[0024] The wiring patterns 121, 122 include a first wiring pattern 121 embedded in the insulating layer 112 on the first surface 110a, and a second wiring pattern 122 disposed on the insulating layer 112 on the second surface 110b. The first wiring pattern 121 and the second wiring pattern 122 are each configured to be capable of transmitting signals. The first wiring pattern 121 and the second wiring pattern 122 are connected to each other through a via 124 embedded in the insulating layer 112.

[0025] The reinforcement patterns 131, 132 include a first reinforcement pattern 131 embedded in the insulating layer 112 on the first surface 110a. The first reinforcement pattern 131 is arranged around the cavity 119 at a distance from the edge of the cavity 119 and is separated from the first wiring pattern 121. That is, the first reinforcement pattern 131 is a physically or electrically isolated pattern not used for signal transmission, or is connected to a ground pattern. The first reinforcement pattern 131 includes a metal, specifically, copper (Cu).

[0026] When the direction parallel to the first surface 110a is used as a reference, the first reinforcement pattern 131 is covered with the insulating layer 112 so as not to be exposed in the cavity 119. In terms of height measured in a direction perpendicular to the first surface 110a, the first reinforcement pattern 131 has the same height as the first wiring pattern 121. Here, "the same height" refers to a height that is evaluated as the same level in the relevant technical field, and includes cases where the heights differ due to limitations and / or errors in the manufacturing process or measurement method. The first wiring pattern 121 is disposed away from the first reinforcement pattern 131 in a direction away from the cavity 119.

[0027] The reinforcement patterns 131 and 132 include a second reinforcement pattern 132 disposed on the insulating layer 112 on the second surface 110b. The second reinforcement pattern 132 is disposed around the cavity 119 at a distance from the edge of the cavity 119 and is separated from the second wiring pattern 122. That is, the second reinforcement pattern 132 is configured as a physically or electrically isolated pattern so as not to be used for signal transmission. The second reinforcement pattern 132 includes a metal, specifically, copper (Cu).

[0028] The second reinforcement pattern 132 protrudes above the second surface 110b to have the same height as the second wiring pattern 122. Here, "the same height" refers to a height that is evaluated as the same level in the relevant technical field, and includes cases where the heights differ due to limitations and / or errors in the manufacturing process or measurement method. The second wiring pattern 122 is disposed apart from the second reinforcement pattern 132 in a direction away from the cavity 119. The second reinforcement pattern 132 is disposed so that at least a portion of it overlaps with the first reinforcement pattern 131 along a direction perpendicular to the first surface 110a.

[0029] By providing the metal reinforcing patterns 131 and 132 around the cavity 119 on the substrate 110 containing insulating resin as described above, it is possible to prevent cracks from occurring in the resin area around the edge of the cavity 119 during the PLP (Panel Level Package) process.

[0030] The electronic element package 100 may be a fan-out semiconductor package, and is disposed in a cavity 119 of a circuit board 101 such that a connection end of the electronic element 70 is located on the first surface 110a side of the substrate 110. On the first surface 110a side of the substrate 110, one surface of a rewiring layer 150 is disposed and the electronic element 70 is connected, and the first wiring pattern 121 of the circuit board 101 is also connected to the rewiring layer 150. On the other surface of the rewiring layer 150, a connection pad 151 is disposed, and a connection terminal 154 is connected to the connection pad 151.

[0031] At least a portion of the electronic element 70 and the second surface 110b of the substrate 110 are covered with a sealant 92. The sealant 92 covers the second reinforcement pattern 132 disposed on the second surface 110b, and covers at least a portion of the second wiring pattern 122. The second wiring pattern 122 disposed on the second surface 110b is partially exposed from the sealant 92 and functions as a connection pad.

[0032] An insulating protection layer 141 is disposed between the first surface 110a of the substrate 110 and the redistribution layer 150. The insulating protection layer 141 may be an underfill resin that is filled between the electronic element 70 and the redistribution layer 150 to protect the connection. The insulating protection layer 141 is configured by disposing a photosensitive insulating (Photo Imageable Dielectric, PID) resin between the substrate 110 and the redistribution layer 150. A first metallic reinforcement pattern 131 is provided around the edge of the cavity 119 on the first surface 110a of the circuit board 101, thereby improving coating defects when coating the photosensitive insulating resin in the PLP process.

[0033] 2 to 14 are cross-sectional views showing the steps of a method for manufacturing a circuit board according to an embodiment.

[0034] 2 to 5, a carrier substrate 60 having a first seed layer 81 disposed on at least one surface is prepared, and a first wiring pattern layer 121A and a first reinforcing pattern layer 131A are formed on the first seed layer 81 through a circuit formation process. The carrier substrate 60 is a substrate having copper foil layers 62 laminated on both surfaces of an insulating material 61, and the first seed layer 81 and the copper foil layers 62 are separated from each other (see FIG. 2). A plating resist pattern 83 is formed on the carrier substrate 60 by removing only the portions where the first wiring pattern layer 121A and the first reinforcing pattern layer 131A are to be formed by exposure and development (see FIG. 3). The first wiring pattern layer 121A and the first reinforcing pattern layer 131A are formed by plating a conductive metal on the portions of the first seed layer 81 exposed through the openings of the patterned plating resist pattern 83 (see FIG. 4). After the first wiring pattern layer 121A and the first reinforcing pattern layer 131A are formed, the plating resist pattern is removed (see FIG. 5).

[0035] The first seed layer 81 can be applied without any restrictions as long as it is used as a conductive metal for circuits in the field of circuit boards, and copper (Cu) is generally used. The first wiring pattern layer 121A and the first reinforcing pattern layer 131A are connected to the first seed layer 81 of the carrier substrate 60 and contain the same type of metal as the first seed layer 81. For example, the first seed layer 81, the first wiring pattern layer 121A, and the first reinforcing pattern layer 131A contain copper (Cu).

[0036] In this embodiment, the first wiring pattern layer 121A and the first reinforcement pattern layer 131A are formed on both sides of the carrier substrate 60, but it is also possible to form the first wiring pattern layer 121A and the first reinforcement pattern layer 131A only on one side of the carrier substrate 60, which also falls within the scope of the present invention.

[0037] 6, an insulating layer 112 is laminated so that the first wiring pattern layer 121A and the first reinforcement pattern layer 131A are embedded, and a second seed layer 85 is formed on the upper surface of the insulating layer 112. The second seed layer 85 is formed to form the second wiring pattern layer 122A and the second reinforcement pattern layer 132A, and any conductive metal may be used without limitation, but copper is generally used.

[0038] The insulating layer 112 includes a resin insulating layer. The insulating layer 112 may be made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin impregnated with a reinforcing material such as glass fiber or an inorganic filler, for example, a prepreg, and may include, but is not limited to, a thermosetting resin and / or a photocurable resin.

[0039] 7 to 10, a second wiring pattern layer 122A and a second reinforcement pattern layer 132A are formed on an insulating layer 112 by a circuit formation process. The second wiring pattern layer 122A and the second reinforcement pattern layer 132A are formed by a method similar to the method for forming the first wiring pattern layer 121A and the first reinforcement pattern layer 131A. At this time, in order to form a via 124 connecting the first wiring pattern layer 121A and the second wiring pattern layer 122A to each other, the insulating layer 112 is partially etched to expose a part of the first wiring pattern layer 121A (see FIG. 7), and a plating process is performed on the part of the first wiring pattern layer 121A thus exposed.

[0040] A plating resist pattern 87 is formed on the second seed layer 85, which is removed by exposure and development only in the areas where the second wiring pattern layer 122A and the second reinforcing pattern layer 132A are to be formed (see FIG. 8). The second wiring pattern layer 122A and the second reinforcing pattern layer 132A are formed by plating a conductive metal on the areas of the second seed layer 85 exposed through the openings of the patterned plating resist pattern 87 (see FIG. 9). After the second wiring pattern layer 122A and the second reinforcing pattern layer 132A are formed, the plating resist pattern 87 is removed (see FIG. 10). This completes embedded pattern substrate parts on both sides of the carrier substrate 60.

[0041] According to the illustrated embodiment, each embedded pattern substrate portion is illustrated as including one insulating layer 112 and a first wiring pattern layer 121A and a second wiring pattern layer 122A of metal layers arranged on both sides thereof, but is not limited to this and may include a greater number of build-up insulating layers and a greater number of build-up wiring pattern layers, which also falls within the scope of the present invention.

[0042] 11, the first seed layer 81 and the carrier substrate 60 are separated to prepare a buried pattern substrate. The first seed layer 81 formed on both sides of the carrier substrate 60 can be separated from the copper foil layer 62 to obtain a pair of buried pattern substrates, and a process is applied to each of the pair of buried pattern substrates individually.

[0043] 12, the embedded pattern substrate obtained in FIG. 11 is soft-etched to remove the first seed layer 81 and the second seed layer 85. After the first seed layer 81 and the second seed layer 85 are removed, the first wiring pattern layer 121A and the first reinforcement pattern layer 131A embedded in the insulating layer 112 form the first wiring pattern 121 and the first reinforcement pattern 131, respectively, and the second wiring pattern layer 122A and the second reinforcement pattern layer 132A disposed on one surface of the insulating layer 112 form the second wiring pattern 122 and the second reinforcement pattern 132, respectively.

[0044] 13 and 14, the center of the embedded pattern substrate obtained from FIG. 12 is etched to form a cavity 119. The cavity can be processed using a variety of known processes, such as laser drilling, mechanical drilling, a router process, and etching. An electronic element 70 is received in the cavity 119 (see FIG. 14).

[0045] Fig. 15 is a bottom view of a circuit board according to an embodiment, showing a first surface of the circuit board on which an embedded pattern is formed.

[0046] 15, the circuit board 102 according to this embodiment includes a first reinforcement pattern 1312 embedded in an insulating layer 112 on a first surface 110a of a substrate 110. The first reinforcement pattern 1312 includes a plurality of reinforcement pads spaced apart from one another along an edge of a cavity 119.

[0047] A ground pattern 138 is disposed on the first surface 110a of the circuit board 102, and the ground pattern 138 has a shape surrounding the cavity 119. At this time, a plurality of reinforcing pads of the first reinforcement pattern 1312 are connected to the ground pattern 138. That is, the first reinforcement pattern 1312 is configured in a shape that protrudes from the edge of the ground pattern 138 surrounding the cavity 119 toward the cavity 119 in a direction parallel to the first surface 110a.

[0048] 16 to 18 are bottom views of circuit boards according to other embodiments.

[0049] 16, the first reinforcement pattern 1313 embedded in the first surface 110a of the circuit board 103 according to this embodiment includes a plurality of reinforcement pads spaced apart from one another along the edge of the cavity 119. At this time, the plurality of reinforcement pads of the first reinforcement pattern 1313 are spaced apart from the ground pattern 138 surrounding the cavity 119 and have an isolated shape.

[0050] 17, the first reinforcement pattern 1314 embedded in the first surface 110a of the circuit board 104 according to this embodiment includes reinforcement pads disposed on each of the four sides along the edge of the cavity 119 including the four sides. At this time, the reinforcement pads of the first reinforcement pattern 1314 are spaced apart from the ground pattern 138 surrounding the cavity 119 and have an isolated shape.

[0051] 18, in the circuit board 105 according to the present embodiment, the first reinforcement pattern 1315 embedded in the first surface 110a is configured to be continuously connected along the edge of the cavity 119 and surround the cavity 119. In this case, the first reinforcement pattern 1315 has an isolated shape separated from the ground pattern 138 surrounding the cavity 119.

[0052] Although the preferred embodiment of the present invention has been described above, the present invention is not limited thereto, and various modifications can be made within the scope of the description and drawings of the invention, which of course also fall within the scope of the present invention. [Explanation of symbols]

[0053] 70 Electronic Elements 92 Sealing material 100 Electronic device package 101 Circuit Board 112 Insulating layer 119 Cavity 121, 122 First and second wiring patterns 124 Via 131, 132 First and second reinforcement patterns 138 Ground Pattern 141 Insulating protective layer 150 redistribution layer 151 Connection Pad 154 Connection terminal

Claims

1. a substrate having a first surface and a second surface opposed to each other, including an insulating layer disposed between the first surface and the second surface, and having a cavity extending therethrough in a direction perpendicular to the first surface; a first wiring pattern that is embedded in the insulating layer on the first surface and is configured to be capable of transmitting signals; a first reinforcement pattern embedded in the insulating layer at the first surface, arranged around the cavity and spaced apart from an edge of the cavity, and separated from the first wiring pattern.

2. The circuit board according to claim 1 , wherein the first reinforcing pattern includes a metal.

3. The circuit board according to claim 1 , wherein the first reinforcing pattern is electrically isolated.

4. The circuit board according to claim 1 , wherein the first reinforcement pattern is covered with the insulating layer so as not to be exposed in the cavity.

5. The circuit board according to claim 1 , wherein the first reinforcing pattern has the same height as the first wiring pattern.

6. The circuit board according to claim 1 , wherein the first wiring pattern is spaced apart from the first reinforcing pattern in a direction away from the cavity.

7. a second wiring pattern disposed on the insulating layer on the second surface and configured to be capable of transmitting signals; a second reinforcing pattern disposed on the insulating layer at the second surface, the second reinforcing pattern disposed around the cavity and spaced apart from an edge of the cavity, and separated from the second wiring pattern; The circuit board according to claim 1 , further comprising a via embedded in the insulating layer and connecting the first wiring pattern and the second wiring pattern to each other.

8. The circuit board according to claim 7 , wherein the second reinforcing pattern protrudes above the second surface to have the same height as the second wiring pattern.

9. The circuit board according to claim 7 , wherein the second wiring pattern is spaced apart from the second reinforcing pattern in a direction away from the cavity.

10. The circuit board according to claim 7 , wherein the first reinforcement pattern and the second reinforcement pattern are disposed to overlap each other at least partially in a direction perpendicular to the first surface.

11. The circuit board according to claim 1 , wherein the first reinforcing pattern comprises a plurality of reinforcing pads spaced apart from one another along an edge of the cavity.

12. The circuit board according to claim 1 , wherein the first reinforcing pattern is configured to be continuously connected along an edge of the cavity to surround the cavity.

13. the cavity includes four sides; The circuit board according to claim 1 , wherein the first reinforcement pattern includes reinforcement pads disposed on each of the four sides.

14. a substrate having a first surface and a second surface opposed to each other, including an insulating layer disposed between the first surface and the second surface, and having a cavity extending therethrough in a direction perpendicular to the first surface; a first wiring pattern that is embedded in the insulating layer on the first surface and is configured to be capable of transmitting signals; a first reinforcing pattern embedded in the insulating layer at the first surface, disposed around the cavity and spaced apart from an edge of the cavity, and separated from the first wiring pattern; an electronic element housed within the cavity; a rewiring layer disposed on the first surface side of the substrate, the rewiring layer being connected to the electronic element.

15. The electronic device package of claim 14 , further comprising an insulating protection layer disposed between the first surface of the substrate and the redistribution layer to cover the first reinforcement pattern.

16. The electronic device package according to claim 14 , wherein the first reinforcing pattern is electrically isolated.

17. The electronic device package of claim 14 , wherein the first reinforcing pattern is covered by the insulating layer so as not to be exposed in the cavity.

18. The electronic device package of claim 14 , wherein the first wiring pattern is spaced apart from the first reinforcing pattern in a direction away from the cavity.

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