Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing an increase of a temperature due to a concentration of a heat in an element region.SOLUTION: The present invention provides a semiconductor device containing: a first element region 17 that is formed to a main surface 8 of a semiconductor chip 2, and in which a first element of which a heat generation amount is relatively large is formed; and a second element region 18 in which a second element of which the heat generation amount is relatively smaller than the first element is formed, and which is adjacent to the first element region 17 while being separated from an element boundary 24. In the case where the element boundary 24 is divided into a first boundary 34 and a second boundary 35 by a division line 33 along a second direction Y, at least one of the first boundary 34 and a second boundary 35 contains: a pair of first lines 36 that is arranged with a gap each other; and a U-shaped boundary 38 that is formed by a second line 37 for connecting both of one end parts of the pair of first lines 36.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a first system transistor that generates a first system current and a second system transistor that generates a second system current independent of the first system transistor, a main transistor that generates an output current including the first system current and the second system current, a first system monitor transistor that generates a first system monitor current corresponding to the first system current, and a second system monitor transistor that generates a second system monitor current corresponding to the second system current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 210033

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device capable of suppressing a rise in temperature due to heat concentration in an element region.

[0005] One embodiment of the present disclosure provides a semiconductor device including: a semiconductor chip formed in a rectangular shape in a planar view, having a pair of first sides extending in a first direction and a pair of second sides extending in a second direction perpendicular to the first direction, and having a main surface surrounded by the pair of first sides and the pair of second sides; a first element region formed on the main surface of the semiconductor chip, in which a first element having a relatively large amount of heat generation is formed; and a second element region formed adjacent to the first element region across an element boundary, in which a second element having a relatively smaller amount of heat generation than the first element is formed; and when the element boundary is divided into a first boundary and a second boundary by a dividing line along the second direction, at least one of the first boundary and the second boundary includes a U-shaped boundary formed by a pair of first lines arranged side by side and spaced apart from each other, and a second line connecting one ends of the pair of first lines. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view of the semiconductor chip shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. [Figure 4] FIG. 4 is a plan view showing an example of the layout of elements in the semiconductor chip. [Figure 5] FIG. 5 is a diagram showing a first pattern of element boundaries of the semiconductor chip. [Figure 6] FIG. 6 is a diagram in which FIG. 4 is superimposed on FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view showing an example of the element structure of the control IC shown in FIG. [Figure 9] FIG. 9 is a diagram showing the second pattern of the element boundaries. [Figure 10] FIG. 10 is a diagram showing the third pattern of the element boundaries. [Figure 11]FIG. 11 is a diagram showing a fourth pattern of the element boundaries. [Figure 12] FIG. 12 is a diagram showing a fifth pattern of the element boundary. [Figure 13] FIG. 13 is a diagram showing a sixth pattern of the element boundaries. [Figure 14] FIG. 14 is a diagram showing a seventh pattern of the element boundary. [Figure 15] FIG. 15 is a diagram showing an eighth pattern of the element boundaries. [Figure 16] FIG. 16 is a diagram showing a ninth pattern of the element boundaries. [Figure 17] FIG. 17 is a diagram showing a tenth pattern of the element boundaries. [Figure 18] FIG. 18 is a diagram showing an eleventh pattern of the element boundaries. [Figure 19] FIG. 19 is a diagram showing a twelfth pattern of the element boundary.

[0007] [Detailed explanation] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings: Fig. 1 is a schematic perspective view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0008] 1, the semiconductor device 1 in this embodiment is a so-called SOP (Small Outline Package) package. In this embodiment, the semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape, a die pad 3, a conductive bonding material 4, a plurality of (eight in this embodiment) lead electrodes 5A-5H, a plurality of (eight in this embodiment) conductors 6A-6E, and a molding resin 7. The numbers of the lead electrodes 5A-5H and the conductors 6A-6E are selected depending on the function of the semiconductor device 1 and are not limited to the numbers shown in FIG. 1.

[0009] The semiconductor chip 2 has a first main surface 8 on one side and a second main surface 9 on the other side. The first main surface 8 is a device surface on which functional devices are formed. The second main surface 9 is a mounting surface, and may be a ground surface having grinding marks.

[0010] The semiconductor chip 2 includes a plurality of terminal electrodes 10 to 15. In this embodiment, the plurality of terminal electrodes 10 to 15 include a drain terminal 10 (power supply terminal VBB), a source terminal 11 (output terminal OUT), an input terminal 12, a ground terminal 13, an enable terminal 14, and a sense terminal 15. The role of each of the terminal electrodes 10 to 15 will be described in detail later.

[0011] The die pad 3 is made of a metal plate formed in a rectangular parallelepiped shape. The die pad 3 supports the semiconductor chip 2 from the second main surface 9 side. The die pad 3 is connected to a drain terminal 10 of the semiconductor chip 2 via a conductive bonding material 4. The conductive bonding material 4 may be a metal paste or solder.

[0012] The lead electrodes 5A to 5H include a first lead electrode 5A, a second lead electrode 5B, a third lead electrode 5C, a fourth lead electrode 5D, a fifth lead electrode 5E, a sixth lead electrode 5F, a seventh lead electrode 5G, and an eighth lead electrode 5H. The lead electrodes 5A to 5H may contain iron, aluminum, or copper. The lead electrodes 5A to 5E are arranged around the die pad 3 at intervals from the die pad 3. Meanwhile, the lead electrodes 5F to 5H are integrally connected to the die pad 3 and extend around the die pad 3. More specifically, the four lead electrodes 5A to 5D are arranged at intervals along one side of the die pad 3. The remaining four lead electrodes 5E to 5H are arranged at intervals along the side of the die pad 3 along which the lead electrodes 5A to 5D are arranged.

[0013] The lead electrodes 5A to 5H are each formed in a strip shape extending in a direction perpendicular to the arrangement direction, and each of the lead electrodes 5A to 5H has one end facing the die pad 3 and the other end on the opposite side. One end of the lead electrodes 5A to 5H is internally connected to the semiconductor chip 2. The other end of the lead electrodes 5A to 5H is externally connected to a wiring board or the like.

[0014] The plurality of conductive wires 6A to 6E include a first conductive wire 6A, a second conductive wire 6B, a third conductive wire 6C, a fourth conductive wire 6D, and a fifth conductive wire 6E.

[0015] The first conductive wire 6A is electrically connected to one end of the first lead electrode 5A and the source terminal 11. In this embodiment, the first conductive wire 6A is made of a metal clip. The first conductive wire 6A may contain gold, aluminum, or copper. The first conductive wire 6A efficiently dissipates heat generated in the semiconductor chip 2 to the outside. The first conductive wire 6A may also be made of a bonding wire.

[0016] The second conducting wire 6B is electrically connected to one end of the second lead electrode 5B and a ground terminal 13. The third conducting wire 6C is electrically connected to one end of the third lead electrode 5C and an enable terminal 14. The fourth conducting wire 6D is electrically connected to one end of the fourth lead electrode 5D and a sense terminal 15.

[0017] The fifth conducting wire 6E is electrically connected to one end of the fifth lead electrode 5E and the input terminal 12.

[0018] In this embodiment, the second to fifth conductive wires 6B to 6E are made of bonding wires. The second to fifth conductive wires 6B to 6E may each contain gold, aluminum, or copper. The connection of the conductive wires 6A to 6E to the semiconductor chip 2 and the lead electrodes 5A to 5E may be any connection configuration and is not limited to the connection configuration shown in FIG.

[0019] On the other hand, one end of each of the plurality of lead electrodes 5F to 5H is integrally connected to the die pad 3 and electrically connected to the drain terminal 10 via the conductive bonding material 4.

[0020] The molding resin 7 seals the semiconductor chip 2, the die pad 3, one ends of the lead electrodes 5A to 5H, and the conductors 6A to 6E so as to expose the other ends of the lead electrodes 5A to 5H. The molding resin 7 is formed in a rectangular parallelepiped shape. The molding resin 7 is made of an insulating resin and may contain epoxy resin. The semiconductor device 1 is not limited to the sealed form shown in FIG. 1, and may be in a form that does not include the molding resin 7.

[0021] The package form of the semiconductor device 1 is not limited to SOP, but may be a transistor outline (TO), a quad for non-lead package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), a small outline J-leaded package (SOJ), or various other similar forms.

[0022] Fig. 2 is a plan view of the semiconductor chip 2 shown in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 2. Fig. 4 is a plan view showing an example of the layout of elements in the semiconductor chip 2.

[0023] 2 to 4, semiconductor chip 2 is made of a chip containing Si (silicon). Semiconductor chip 2 may be made of a chip containing Si single crystal or SiC single crystal. Semiconductor chip 2 has first to fourth side surfaces 16A to 16D connecting first main surface 8 and second main surface 9.

[0024] The first main surface 8 and the second main surface 9 are formed in a rectangular shape in a plan view seen from their normal direction Z (hereinafter simply referred to as a "plan view"). The "rectangle" defining the shape of the semiconductor chip 2 means a quadrilateral with all four interior angles being right angles. The semiconductor chip 2 having a rectangular shape in a plan view may be a square with all four equal sides, a rectangle in the narrow sense having a pair of long sides and a pair of short sides, or a substantially rectangular shape with four rounded corners.

[0025] The first to fourth side surfaces 16A to 16D include a first side surface 16A, a second side surface 16B, a third side surface 16C, and a fourth side surface 16D. The first side surface 16A and the second side surface 16B extend in a first direction X along the first main surface 8 and face a second direction Y that intersects with (specifically, is perpendicular to) the first direction X. The third side surface 16C and the fourth side surface 16D extend in the second direction Y and face the first direction X. The first main surface 8 and the second main surface 9 are formed in an area surrounded by the first to fourth side surfaces 16A to 16D.

[0026] The semiconductor chip 2 includes a first element region 17 and a second element region 18 provided on the first main surface 8. The first element region 17 and the second element region 18 are each defined by a region isolation structure 19. The region isolation structure 19 defining the first element region 17 and the region isolation structure 19 defining the second element region 18 may be formed physically independent of each other as shown in FIG. 4, or may share a portion of the structure. For example, the region isolation structure 19 forming the element boundary between the first element region 17 and the second element region 18 may be shared and may be part of the region isolation structure 19 defining both the first element region 17 and the second element region 18.

[0027] The first element region 17 and the second element region 18 are regions in which elements with different heat generation amounts are formed. The first element region 17 generates a relatively large amount of heat compared to the second element region 18, so the temperature rises significantly, while the second element region 18 generates a relatively small amount of heat compared to the first element region 17, so the temperature rise hardly occurs. The temperature rise due to heat generation can be compared, for example, based on the results of the following calculation formula (1).

[0028] Tj=Ta+Rth(ja)×P (1) Tj: Junction temperature (temperature of the element region within the semiconductor device) Ta: Ambient temperature (room temperature in the room where the measurement was performed) Rth(ja): Thermal resistance between junction and ambient air P: Power consumption of the element area In this embodiment, first element region 17 is an output region in which an output signal that is output to the outside is generated. First element region 17 is defined on first main surface 8 as a region on the first side surface 16A side. First element region 17 may be defined in a quadrangular shape in plan view, or in a polygonal shape other than a quadrangular shape. The arrangement and planar shape of first element region 17 are arbitrary and are not limited to a specific shape.

[0029] An insulated gate output transistor 20 is formed in the first element region 17. The output transistor 20 may also be called a "gate split transistor," a "power transistor," or a "power MISFET (Metal Insulator Semiconductor Field Effect Transistor)." In addition to the output transistor 20, the first element region 17 may also be formed with a monitor transistor that monitors the current of the output transistor 20, a temperature sensing device that detects the temperature of the output transistor 20, and the like.

[0030] In this embodiment, the second element region 18 is an input region to which an external electrical signal is input. In this embodiment, the second element region 18 is partitioned into a region on the second side surface 16B side relative to the first element region 17. The second element region 18 may be partitioned into a rectangular shape in a plan view, or into a polygonal shape other than a rectangular shape. The layout and planar shape of the second element region 18 are arbitrary and are not limited to a specific shape. A control IC 21 (Control Integrated Circuit) as an example of a control circuit is formed in the second element region 18. The control IC 21 includes multiple functional circuits that realize various functions. The multiple functional circuits include a circuit that generates a gate control signal that drives and controls the output transistor 20 based on an external electrical signal. The control IC 21 and the output transistor 20 form a so-called IPD (Intelligent Power Device). The IPD is also called an IPM (Intelligent Power Module).

[0031] An interlayer insulating layer 22 is formed on the first main surface 8. Wiring 23 is formed in the interlayer insulating layer 22, connecting the elements in the first element region 17 and the elements in the second element region 18. In this embodiment, the wiring 23 includes a plurality of wirings 23 that connect the output transistor 20 and the control IC 21. The plurality of wirings 23 may include a gate wiring to which a gate signal that controls the gate of the output transistor 20 is transmitted. The gate wiring transmits the gate signal generated by the control IC 21 to the gate of the output transistor 20.

[0032] The semiconductor chip 2 includes a plurality of terminal electrodes 10 to 15. In Fig. 2, the plurality of terminal electrodes 10 to 15 are indicated by hatching. The number, arrangement, and planar shape of the plurality of terminal electrodes 10 to 15 can be adjusted to any form depending on the specifications of the output transistor 20 and the specifications of the control IC 21, and are not limited to the form shown in Fig. 2. In this form, the plurality of terminal electrodes 10 to 15 include the drain terminal 10 (power supply terminal VBB), the source terminal 11 (output terminal OUT), the input terminal 12, the ground terminal 13, the enable terminal 14, and the sense terminal 15, as described above.

[0033] The drain terminal 10 is electrically connected to the drain of the output transistor 20 and the control IC 21. The drain terminal 10 transmits a power supply voltage VB to various circuits such as the drain of the output transistor 20 and the control IC 21. The source terminal 11 is electrically connected to the source of the output transistor 20 and the control IC 21. The source terminal 11 transmits an output current generated by the output transistor 20 to the outside.

[0034] The input terminal 12 transmits an input voltage that drives the control IC 21. The ground terminal 13 transmits a ground voltage GND. The enable terminal 14 transmits an electrical signal for enabling or disabling some or all of the functions of the control IC 21. The sense terminal 15 transmits an electrical signal for detecting abnormalities in the output transistor 20, the control IC 21, etc.

[0035] Source terminal 11, input terminal 12, ground terminal 13, enable terminal 14, and sense terminal 15 are arranged on interlayer insulating layer 22 (see FIG. 3). Source terminal 11 is formed on first element region 17 on first main surface 8. Input terminal 12, ground terminal 13, enable terminal 14, and sense terminal 15 are each arranged on a region outside first element region 17 (specifically, second element region 18) on first main surface 8.

[0036] The terminal electrodes 10 to 15 may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer. A plating layer may be formed on the outer surface of each of the terminal electrodes 10 to 15. The plating layer may include at least one of a Ni layer, a Pd layer, and an Au layer.

[0037] FIG. 5 is a plan view schematically showing the configuration of the first element region 17, the second element region 18, and the element boundary 24 of the semiconductor chip 2 shown in FIG. 4, and is a diagram showing a first pattern of the element boundary 24.

[0038] 5, on the first main surface 8 of the semiconductor chip 2, a first element region 17 is formed on one side in the second direction Y, and a second element region 18 is formed on the other side. In Fig. 5, the first element region 17 is shown as a white region, and the second element region 18 is shown as a dot-hatched region.

[0039] An element boundary 24 is formed between the first element region 17 and the second element region 18. The element boundary 24 physically and electrically separates the first element region 17 and the second element region 18. The element boundary 24 is formed by the region isolation structure 19 shown in FIG. 4 (for example, a trench isolation structure 41, which will be described later). In this embodiment, the element boundary 24 is shared between the first element region 17 and the second element region 18.

[0040] Element boundary 24 has one end 25 and the other end 26 on a pair of opposing side surfaces of semiconductor chip 2 (third side surface 16C and fourth side surface 16D in FIG. 5). One end 25 and the other end 26 of element boundary 24 do not need to reach and be exposed all the way to third side surface 16C and fourth side surface 16D. For example, if first main surface 8 is divided roughly into two element regions, first element region 17 on the first side surface 16A side and second element region 18 on the second side surface 16B side, one end 25 and the other end 26 of element boundary 24 may be located near third side surface 16C and fourth side surface 16D.

[0041] Therefore, the peripheries of the first element region 17 and the second element region 18, excluding the element boundary 24, each form a part of the peripheral region 27 of the semiconductor chip 2. In FIG. 5, the peripheral region 27 is indicated by diagonal hatching. The peripheral region 27 of the semiconductor chip 2 is a region of a predetermined width formed around the entire periphery of the semiconductor chip 2 along the first to fourth side surfaces 16A to 16D, and may be a region in which a breakdown voltage structure such as a guard ring of the semiconductor chip 2 is formed, for example. In this embodiment, the first element region 17 forms the peripheral region 27 along the entire first side surface 16A and parts of the third and fourth side surfaces 16C and 16D. The second element region 18 forms the peripheral region 27 along the entire second side surface 16B and parts of the third and fourth side surfaces 16C and 16D.

[0042] The second element region 18 integrally includes a base portion 28 and a protrusion 29 that protrudes from the outer periphery of the base portion 28.

[0043] 5, base portion 28 may be a rectangular region in plan view having the largest area among regions surrounded by at least three of the multiple sides that constitute region isolation structure 19 that partitions second element region 18. In this embodiment, base portion 28 is formed so as to be surrounded by three sides: second side surface 16B, third side surface 16C, and fourth side surface 16D. The boundary between base portion 28 and protrusion 29 is indicated by a dashed line.

[0044] More specifically, the base portion 28 is formed in a rectangular shape in a plan view, having a pair of long sides 30 and a pair of short sides 31. At least one of the pair of long sides 30 is a long side boundary 32 that forms the element boundary 24, and the other forms a peripheral region 27 along the second side surface 16B.

[0045] In this embodiment, a plurality of protrusions 29 are formed so as to protrude from the base portion 28 toward the first element region 17 and be spaced apart in the first direction X. Each of the protrusions 29 is formed in a quadrangular shape in plan view. The shape and number of the plurality of protrusions 29 are not limited to the embodiment in FIG. 5. Furthermore, the plurality of protrusions 29 may have different shapes, or may have the same shape as each other, as shown in FIG. 5.

[0046] Consider a case where the element boundary 24 is divided into a first boundary 34 and a second boundary 35 by a dividing line 33 along the second direction Y. In this case, at least one of the first boundary 34 and the second boundary 35 (both in this embodiment) includes a U-shaped boundary 38 formed by a pair of first lines 36 spaced apart from each other and a second line 37 connecting one end of the pair of first lines 36. In FIG. 5 , the U-shaped boundary 38 is indicated by a thick solid line. In this embodiment, a pair of sides of the rectangular protrusion 29 in plan view that extend along the second direction Y are the first lines 36, and a side that extends along the first direction X is the second line 37. More specifically, the multiple protrusions 29 are arranged along the long side boundary 32 so that the first line 36 of the U-shaped boundary 38 is continuous with the long side boundary 32 of the base portion 28.

[0047] The parting line 33 may be a parting line 33 that passes through the center of the semiconductor chip 2 in the first direction X. More specifically, the parting line 33 may be a line segment that connects the midpoint of the first side surface 16A in the first direction X and the midpoint of the second side surface 16B in the first direction X.

[0048] As described above, according to this semiconductor chip 2, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, so the element boundary 24 between the output transistor 20 and the control IC 21 per unit section can be made longer than in the case of a linear boundary or a stepped boundary. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0049] In particular, in this configuration, the Si constituting the semiconductor chip 2 has a higher thermal conductivity than the molding resin 7 (epoxy resin) that seals the semiconductor chip 2. Therefore, by lengthening the element boundary 24, the cooling effect can be further improved. For example, momentary heat generated in the output transistor 20 during active clamp operation can be efficiently dissipated via the second element region 18.

[0050] Furthermore, since the element boundary 24 is formed across the semiconductor chip 2 between the third side surface 16C and the fourth side surface 16D of the semiconductor chip 2, a relatively long element boundary 24 can be ensured.

[0051] Furthermore, since the area of ​​the base portion 28 is larger than that of the protruding portion 29, a large space can be secured for the control IC 21 in the base portion 28. This improves the degree of freedom in the layout of the control IC 21.

[0052] Fig. 6 is a diagram in which Fig. 4 is superimposed on Fig. 2. Fig. 6 is a diagram showing the relationship in size between the multiple protrusions 29 shown in Fig. 5 and the multiple terminal electrodes 11 to 15 on the semiconductor chip 2. Fig. 6 shows only the reference numerals of the components described above that are necessary for comparing the sizes of the protrusions 29 and the terminal electrodes 11 to 15.

[0053] 6, each protrusion 29 has an area larger than some of the terminal electrodes 13-15 among the plurality of terminal electrodes 11-15, and an area smaller than the remaining terminal electrodes 11-12. In this embodiment, each protrusion 29 has an area larger than the ground terminal 13, the enable terminal 14, and the sense terminal 15, and an area smaller than the source terminal 11 and the input terminal 12.

[0054] For example, the length L1A in the first direction X and the length L2A in the second direction Y of each protrusion 29 are respectively greater than the length L1B in the first direction X and the length L2B in the second direction Y of the ground terminal 13, the length L1C in the first direction X and the length L2C in the second direction Y of the enable terminal 14, and the length L1D in the first direction X and the length L2D in the second direction Y of the sense terminal 15. On the other hand, the lengths L1A and L1B of each protrusion 29 are respectively smaller than the length L1E in the first direction X and the length L2E in the second direction Y of the source terminal 11, and the length L1F in the first direction X and the length L2F in the second direction Y of the input terminal 12.

[0055] In other words, each protrusion 29 may be smaller than the terminal electrodes essential for forming a channel between the source and drain of the output transistor 20 (in this embodiment, the source terminal 11 and the input terminal 12), and larger than other auxiliary terminal electrodes (in this embodiment, the enable terminal 14, etc.).

[0056] Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 5. In the following, the cross-sectional structure of the output transistor 20 will be described in detail with reference to Fig. 7.

[0057] 7, the semiconductor chip 2 includes an n-type (first conductivity type) first semiconductor region 39 formed in a surface layer portion of the second main surface 9. The first semiconductor region 39 forms the drain of the output transistor 20. The first semiconductor region 39 may also be referred to as a "drain region." The first semiconductor region 39 is formed over the entire surface layer portion of the second main surface 9 of the output transistor 20.

[0058] The n-type impurity concentration of the first semiconductor region 39 is 1×10 18 cm -3 More than 1×10 21 cm -3 The thickness of the first semiconductor region 39 may be 10 μm or more and 450 μm or less. The thickness of the first semiconductor region 39 is preferably 50 μm or more and 150 μm or less. In this embodiment, the first semiconductor region 39 is formed of an n-type semiconductor substrate (Si substrate).

[0059] The semiconductor chip 2 includes an n-type second semiconductor region 40 formed in a surface layer portion of the first main surface 8. The second semiconductor region 40, together with the first semiconductor region 39, forms the drain of the output transistor 20. The second semiconductor region 40 may also be referred to as a "drain region." The second semiconductor region 40 is formed over the entire surface layer portion of the first element region 17 so as to be electrically connected to the first semiconductor region 39.

[0060] The second semiconductor region 40 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 39. The n-type impurity concentration of the second semiconductor region 40 is 1×10 15 cm -3 More than 1×10 18 cm -3 The second semiconductor region 40 may have a thickness less than that of the first semiconductor region 39. The thickness of the second semiconductor region 40 may be 1 μm or more and 25 μm or less. The thickness of the second semiconductor region 40 is preferably 5 μm or more and 15 μm or less. In this embodiment, the second semiconductor region 40 is formed by an n-type epitaxial layer (Si epitaxial layer).

[0061] The semiconductor chip 2 includes a trench isolation structure 41 as an example of the aforementioned region isolation structure 19. The trench isolation structure 41 may also be referred to as a "DTI (deep trench isolation) structure." The trench isolation structure 41 forms the element boundary 24 (see FIG. 5) of the first main surface 8 in plan view and defines the first element region 17.

[0062] The trench isolation structure 41 has a single electrode structure including an isolation trench 42, an isolation insulating film 43 (isolation insulator), and an isolation electrode 44. The isolation trench 42 is dug down from the first main surface 8 toward the second main surface 9. The isolation trench 42 is formed at an interval from the bottom of the second semiconductor region 40 toward the first main surface 8.

[0063] The isolation trench 42 includes a sidewall and a bottom wall. The angle that the sidewall of the isolation trench 42 forms with the first main surface 8 within the semiconductor chip 2 may be 90° or more and 92° or less. The isolation trench 42 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the isolation trench 42 are preferably formed in a curved shape. The entire bottom wall of the isolation trench 42 may be formed in a curved shape toward the second main surface 9.

[0064] The isolation insulating film 43 is formed on the wall surface of the isolation trench 42. Specifically, the isolation insulating film 43 is formed in the form of a film over the entire wall surface of the isolation trench 42, and defines a recess space within the isolation trench 42. The isolation insulating film 43 preferably includes a silicon oxide film. It is particularly preferable that the isolation insulating film 43 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0065] The isolation electrode 44 is embedded as an integrated member in the isolation trench 42 with the isolation insulating film 43 sandwiched therebetween. In this embodiment, the isolation electrode 44 includes conductive polysilicon. A source potential is applied to the isolation electrode 44. The isolation electrode 44 has an electrode surface (isolation electrode surface) exposed from the isolation trench 42. The electrode surface of the isolation electrode 44 may be recessed in a curved shape toward the bottom wall of the isolation trench 42.

[0066] The semiconductor chip 2 includes a p-type (second conductivity type) body region 45 formed in the surface layer portion of the first main surface 8 in the first element region 17. The p-type impurity concentration of the body region 45 is 1×10 16 cm -3 More than 1×10 18 cm -3 The body region 45 may be formed in the first element region 17 over the entire surface portion of the first main surface 8, and is in contact with the sidewall of the trench isolation structure 41. The body region 45 is formed in a region on the first main surface 8 side of the bottom wall of the trench isolation structure 41. The body region 45 is preferably formed in a region on the first main surface 8 side of the intermediate portion of the trench isolation structure 41.

[0067] The configuration of one trench structure 46 will be described below. The trench structure 46 has a multi-electrode structure including a trench 47, an upper insulating film 48, a lower insulating film 49, an upper electrode 50, a lower electrode 51, and an intermediate insulating film 52. The trench 47 may also be referred to as a "gate trench." The trench structure 46 includes a buried electrode (gate electrode) buried in the trench 47 with a buried insulator sandwiched therebetween. The buried insulator is composed of the upper insulating film 48, the lower insulating film 49, and the intermediate insulating film 52. The buried electrode is composed of the upper electrode 50 and the lower electrode 51.

[0068] The trench 47 is dug down from the first main surface 8 toward the second main surface 9. The trench 47 penetrates the body region 45 and is formed at a distance from the bottom of the second semiconductor region 40 toward the first main surface 8. The trench 47 includes a sidewall and a bottom wall. The angle that the sidewall of the trench 47 forms with the first main surface 8 within the semiconductor chip 2 may be greater than or equal to 90° and less than or equal to 92°. The trench 47 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall. The corners of the bottom wall of the trench 47 are preferably formed in a curved shape. The entire bottom wall of the trench 47 may be formed in a curved shape toward the second main surface 9.

[0069] The upper insulating film 48 covers the upper wall surface of the trench 47. Specifically, the upper insulating film 48 covers the upper wall surface located in a region on the opening side of the trench 47 relative to the bottom of the body region 45. The upper insulating film 48 crosses the boundary between the second semiconductor region 40 and the body region 45. The upper insulating film 48 has a portion covering the body region 45 and a portion covering the second semiconductor region 40. The upper insulating film 48 preferably includes a silicon oxide film. It is particularly preferable that the upper insulating film 48 includes a silicon oxide film made of an oxide of the semiconductor chip 2. The upper insulating film 48 is formed as a gate insulating film.

[0070] The lower insulating film 49 covers the lower wall surface of the trench 47. Specifically, the lower insulating film 49 covers the lower wall surface located in a region on the bottom wall side of the trench 47 relative to the bottom of the body region 45. The lower insulating film 49 defines a recess space in the region on the bottom wall side of the trench 47. The lower insulating film 49 is in contact with the second semiconductor region 40. The lower insulating film 49 preferably includes a silicon oxide film. It is particularly preferable that the lower insulating film 49 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0071] The upper electrode 50 is embedded in the upper side (opening side) of the trench 47 with the upper insulating film 48 sandwiched therebetween. The upper electrode 50 is embedded in a strip shape extending in the second direction Y in a plan view. The upper electrode 50 faces the body region 45 and the second semiconductor region 40 with the upper insulating film 48 sandwiched therebetween. The facing area of ​​the upper electrode 50 with respect to the body region 45 is larger than the facing area of ​​the upper electrode 50 with respect to the second semiconductor region 40. The upper electrode 50 includes conductive polysilicon.

[0072] The upper electrode 50 has an electrode surface (buried electrode surface) exposed from the trench 47. The electrode surface of the upper electrode 50 may be recessed in a curved shape toward the bottom wall of the trench 47.

[0073] The lower electrode 51 is embedded in the lower side (bottom wall side) of the trench 47 with the lower insulating film 49 sandwiched therebetween. The lower electrode 51 is embedded in a strip shape extending in the second direction Y in a plan view. The lower electrode 51 has a thickness (length) in the depth direction of the trench 47 that exceeds the thickness (length) of the upper electrode 50. The lower electrode 51 faces the second semiconductor region 40 with the lower insulating film 49 sandwiched therebetween. The lower electrode 51 has an upper end portion that protrudes from the lower insulating film 49 toward the first main surface 8. The upper end portion of the lower electrode 51 engages with the bottom portion of the upper electrode 50 and faces the upper insulating film 48 in the lateral direction along the first main surface 8 with the bottom portion of the upper electrode 50 sandwiched therebetween.

[0074] The lower electrode 51 includes conductive polysilicon. In this embodiment, the lower electrode 51 is formed as a gate electrode. The lower electrode 51 is fixed to the same potential as the upper electrode 50.

[0075] The intermediate insulating film 52 is interposed between the upper electrode 50 and the lower electrode 51, and electrically insulates the upper electrode 50 from the lower electrode 51. Specifically, the intermediate insulating film 52 covers the lower electrode 51 exposed from the lower insulating film 49 in the region between the upper electrode 50 and the lower electrode 51. The intermediate insulating film 52 is continuous with the upper insulating film 48 and the lower insulating film 49. The intermediate insulating film 52 preferably includes a silicon oxide film. It is particularly preferable that the intermediate insulating film 52 include a silicon oxide film made of an oxide of the lower electrode 51.

[0076] At least one n-type source region 53 is included in the surface layer portion of the body region 45. The n-type impurity concentration of the source region 53 exceeds the n-type impurity concentration of the second semiconductor region 40. The n-type impurity concentration of the source region 53 is 1×10 18 cm -3 More than 1×10 21 cm -3 The plurality of source regions 53 are formed in a region on the first main surface 8 side at intervals from the bottom of the body region 45, and face the upper electrode 50 with the upper insulating film 48 interposed therebetween.

[0077] The semiconductor chip 2 includes a third semiconductor region 54 formed in a surface layer portion of the first main surface 8 of the semiconductor chip 2. The third semiconductor region 54 is formed in the first element region 17 at a distance inward from the trench isolation structure 41. In this embodiment, the third semiconductor region 54 is formed in a surface layer portion of the second semiconductor region 40 at a distance toward the first main surface 8 from the boundary between the first semiconductor region 39 and the second semiconductor region 40. As a result, the lower portion and outer periphery of the third semiconductor region 54 are surrounded by the second semiconductor region 40. The third semiconductor region 54 faces the first semiconductor region 39 in the normal direction Z, with the second semiconductor region 40 therebetween, and faces the trench isolation structure 41 in the first direction X and the second direction Y, with the second semiconductor region 40 therebetween.

[0078] The third semiconductor region 54 is n-type, as are the first semiconductor region 39 and the second semiconductor region 40. The third semiconductor region 54, together with the first semiconductor region 39 and the second semiconductor region 40, forms the drain of the drain of the output transistor 20. The third semiconductor region 54 may also be referred to as a "first drift layer," and the second semiconductor region 40 may also be referred to as a "second drift layer."

[0079] The third semiconductor region 54 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 40. The n-type impurity concentration of the third semiconductor region 54 is 1×10 16 cm -3 More than 1×10 19 cm -3 It may be the following:

[0080] As described above, in the semiconductor chip 2, the multiple trench structures 46 are arranged at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. In relation to the multiple trench structures 46, the third semiconductor region 54 is formed so as to surround the side walls and bottom walls of the multiple trench structures 46. The third semiconductor region 54 covers the side walls and bottom walls of the multiple trench structures 46, and may be exposed from the side walls and bottom walls of the multiple trench structures 46 and be in contact with the upper insulating film 48 and the lower insulating film 49.

[0081] The third semiconductor region 54 may cover all of the sidewalls and bottom walls of the multiple trench structures 46, or may selectively cover some of the multiple trench structures 46. For example, the third semiconductor region 54 has an outer periphery end at a position separated from the trench isolation structure 41 by one or more trench structures 46. In other words, the sidewalls and bottom walls of the one or more trench structures 46 interposed between the third semiconductor region 54 and the trench isolation structure 41 are not covered by the third semiconductor region 54, but are covered by the second semiconductor region 40.

[0082] The position of the outer circumferential edge of the third semiconductor region 54 may be between adjacent trench structures 46. The position of the outer circumferential edge may coincide with the position of the sidewall of the outermost trench structure 46 of the multiple trench structures 46 covered by the third semiconductor region 54. The position of the outer circumferential edge may coincide with the position of the sidewall of the innermost trench structure 46 of the multiple trench structures 46 that is not covered by the third semiconductor region 54. The trench structure 46 covered by the third semiconductor region 54 may be selected arbitrarily. For example, the trench structure 46 covered by the third semiconductor region 54 may be continuous or discontinuous in the second direction Y.

[0083] In this embodiment, the third semiconductor region 54 continuously covers the sidewalls and bottom walls of the trench structures 46 except for the trench structures 46 on both ends adjacent to the trench isolation structure 41 .

[0084] The semiconductor chip 2 includes at least one p-type contact region 55 formed in a region different from the source region 53 in the surface layer portion of the body region 45. The p-type impurity concentration of the contact region 55 is higher than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the contact region 55 is 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following:

[0085] In the semiconductor chip 2, the trench isolation structures 41 that form the device boundary 24 are partially opposed to each other with a gap therebetween. In FIG. 7, parts of the trench isolation structures 41 are opposed to each other with a gap therebetween in the first direction X. The parts of the trench isolation structures 41 surround the protruding portion 29 of the second device region 18 shown in FIGS. 5 and 6. In this embodiment, the protruding portion 29 is surrounded on three sides by the trench isolation structures 41. The device structure of the control IC 21 shown in FIG. 8 is formed in the protruding portion 29.

[0086] The aforementioned interlayer insulating layer 22 is formed on the first main surface 8. A source wiring 56 is formed in the interlayer insulating layer 22. The source wiring 56 is electrically connected to the aforementioned source terminal 11 (see FIGS. 1 and 2). In this embodiment, the source wiring 56 is connected to the separation electrode 44, the source region 53, and the contact region 55 via a plug electrode 57.

[0087] FIG. 8 is a cross-sectional view showing an example of the element structure of the control IC 21 shown in FIG.

[0088] The semiconductor chip 2 has a CMIS 58 as the element structure of the control IC 21. Specifically, the CMIS 58 includes a first n-type MISFET 59 and a second p-type MISFET 60 that are complementarily connected. The first MISFET 59 is driven and controlled under voltage application conditions that differ from those of the output transistor 20. The second MISFET 60 is driven and controlled under voltage application conditions that differ from those of the output transistor 20 and the first MISFET 59. Note that the first n-type MISFET 59 and the second p-type MISFET 60 may be combined complementarily as in this embodiment, or may be formed as independent elements.

[0089] The semiconductor chip 2 includes a second trench isolation structure 61 as an example of the aforementioned region isolation structure 19. The second trench isolation structure 61 may also be referred to as a "DTI (deep trench isolation) structure." The second trench isolation structure 61 forms an element boundary 24 (see FIG. 5 ) on the first main surface 8 in plan view, and defines the second element region 18. When the element boundary 24 is shared by the first element region 17 and the second element region 18, the aforementioned trench isolation structure 41 and the second trench isolation structure 61 may coincide with each other.

[0090] Similar to the trench isolation structure 41, the second trench isolation structure 61 has a single electrode structure including an isolation trench 42, an isolation insulating film 43, and an isolation electrode 44. The "isolation trench 42," "isolation insulating film 43," and "isolation electrode 44" of the second trench isolation structure 61 may be referred to as a "second isolation trench," a "second isolation insulating film," and a "second isolation electrode," respectively. The explanation of the isolation trench 42, isolation insulating film 43, and isolation electrode 44 of the second trench isolation structure 61 is omitted here because the explanation of the isolation trench 42, isolation insulating film 43, and isolation electrode 44 of the trench isolation structure 41 also applies.

[0091] A first well region 62 is formed in the surface layer portion of the first main surface 8 in the second element region 18. The first well region 62 is formed throughout the surface layer portion of the first main surface 8 in the second element region 18, and is in contact with the second trench isolation structure 61.

[0092] A first contact region 63 is formed in a surface layer portion of the first well region 62. The first contact region 63 may also be referred to as a "first back gate region" or a "guard ring region." The first contact region 63 has a p-type impurity concentration that exceeds the p-type impurity concentration of the first well region 62. The first contact region 63 is formed at a distance from the second trench isolation structure 61.

[0093] In the second element region 18, a second well region 64 is formed in a surface layer portion of the first main surface 8. The second well region 64 is an impurity region that selectively protrudes from the bottom of the first well region 62 toward the second main surface 9. The second well region 64 is formed across the first MISFET 59 and the second MISFET 60.

[0094] The semiconductor chip 2 further includes a first element isolation structure 66 on the first main surface 8 of the second element region 18, which defines the first MIS region 65. The first element isolation structure 66 may also be referred to as an STI (shallow trench isolation) structure. The first MIS region 65 may also be referred to as a "first active region" or an "n-side active region."

[0095] The first element isolation structure 66 is formed in a ring shape surrounding a portion of the first main surface 8 in a plan view, and defines a first MIS region 65 of a predetermined shape. The first element isolation structure 66 may have any planar shape and may be formed in a polygonal ring shape. The first MIS region 65 may be defined in a polygonal shape according to the planar shape of the first element isolation structure 66.

[0096] A first outer region 67 is formed outside the first element isolation structure 66. The first outer region 67 is a region sandwiched between the first element isolation structure 66 and a first outer isolation structure 68 that surrounds the first element isolation structure 66. The first outer isolation structure 68 forms the boundary between the first MISFET 59 and the second MISFET 60.

[0097] In the first MIS region 65, a first gate electrode 69 is formed on the first main surface 8. The first gate electrode 69 may include conductive polysilicon.

[0098] A first gate insulating film 70 is formed between the first gate electrode 69 and the semiconductor chip 2. The first gate insulating film 70 may include a silicon oxide film. The first gate insulating film 70 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0099] A first sidewall structure 71 is formed around the first gate electrode 69. The first sidewall structure 71 is continuously formed over the entire periphery of the first gate electrode 69 so as to cover the side surfaces of the first gate electrode 69. The first sidewall structure 71 includes at least one of silicon oxide and silicon nitride. In this embodiment, the first sidewall structure 71 includes silicon oxide. The first sidewall structure 71 may also include silicon nitride. In other words, the first sidewall structure 71 may include an insulator different from the first gate insulating film 70.

[0100] A pair of n-type first source region 72 and n-type first drain region 73 are formed at an interval in a surface layer portion of the first well region 62. The first source region 72 and the first drain region 73 have an n-type impurity concentration that exceeds the p-type impurity concentration of the first well region 62. The first source region 72 and the first drain region 73 are formed in self-alignment with the first gate electrode 69.

[0101] In the first MIS region 65, a p-type region between a pair of first source region 72 and first drain region 73 is a first channel region 74. A first gate electrode 69 faces this first channel region 74 with a first gate insulating film 70 sandwiched therebetween. The first channel region 74 is formed in a part of the first well region 62.

[0102] The semiconductor chip 2 includes one or more first drain wirings 75 formed in an interlayer insulating layer 22 (not shown in FIG. 8). The one or more first drain wirings 75 are electrically connected to the first drain region 73 via a first plug electrode 78.

[0103] The semiconductor chip 2 includes one or more first source wirings 76 formed in the interlayer insulating layer 22. The one or more first source wirings 76 are electrically connected to the isolation electrode 44, the first source region 72, and the first contact region 63 via a first plug electrode 78.

[0104] The semiconductor chip 2 includes one or more first gate wirings 77 formed in the interlayer insulating layer 22. The one or more first gate wirings 77 are electrically connected to the first gate electrode 69 via a first plug electrode 78.

[0105] In the second element region 18, a blank region 79 where the first well region 62 does not exist is formed in a part of the first well region 62. The second well region 64 enters this blank region 79 and is exposed from the first main surface 8.

[0106] A third well region 80 is formed in the surface layer portion of the second well region 64 in the blank region 79. The third well region 80 is formed inward and spaced apart from the first well region 62. The bottom of the third well region 80 is formed in a region on the first main surface 8 side with respect to the intermediate portion of the second trench isolation structure 61.

[0107] In the blank region 79, a fourth well region 81 is further formed in a surface layer portion of the second well region 64. The fourth well region 81 is an impurity region that selectively protrudes from the bottom of the third well region 80 toward the second main surface 9. The fourth well region 81 is formed inward and spaced apart from the first well region 62. The fourth well region 81 is formed in a region on the first main surface 8 side with respect to the bottom wall of the second trench isolation structure 61.

[0108] The semiconductor chip 2 further includes a second element isolation structure 83 on the first main surface 8 of the second element region 18, which defines the second MIS region 82. The second element isolation structure 83 may also be referred to as an STI (shallow trench isolation) structure. The second MIS region 82 may also be referred to as a "second active region" or a "p-side active region."

[0109] The second element isolation structure 83 is formed in a ring shape surrounding a portion of the first main surface 8 in a plan view, and defines a second MIS region 82 of a predetermined shape. The second element isolation structure 83 may have any planar shape and may be formed in a polygonal ring shape. The second MIS region 82 may be defined in a polygonal shape according to the planar shape of the second element isolation structure 83.

[0110] A second outer region 84 is formed outside the second element isolation structure 83. The second outer region 84 is a region sandwiched between the second element isolation structure 83 and a second outer isolation structure 85 surrounding the second element isolation structure 83. The second outer isolation structure 85 forms the boundary between the first MISFET 59 and the second MISFET 60. The second outer isolation structure 85 is formed integrally with the first outer isolation structure 68 between the first outer region 67 and the second outer region 84.

[0111] In the second MIS region 82, a second gate electrode 86 is formed on the first main surface 8. The second gate electrode 86 may include conductive polysilicon.

[0112] A second gate insulating film 87 is formed between the second gate electrode 86 and the semiconductor chip 2. The second gate insulating film 87 may include a silicon oxide film. The second gate insulating film 87 preferably includes a silicon oxide film made of an oxide of the semiconductor chip 2.

[0113] A second sidewall structure 88 is formed around the second gate electrode 86. The second sidewall structure 88 is continuously formed over the entire periphery of the second gate electrode 86 so as to cover the side surfaces of the second gate electrode 86. The second sidewall structure 88 includes at least one of silicon oxide and silicon nitride. In this embodiment, the second sidewall structure 88 includes silicon oxide. The second sidewall structure 88 may also include silicon nitride. In other words, the second sidewall structure 88 may include an insulator different from the second gate insulating film 87.

[0114] A pair of n-type second source region 89 and n-type second drain region 90 are formed at an interval in a surface layer portion of the third well region 80. The second source region 89 and the second drain region 90 have a p-type impurity concentration that exceeds the n-type impurity concentration of the third well region 80. The second source region 89 and the second drain region 90 are formed in self-alignment with the second gate electrode 86.

[0115] In the second MIS region 82, an n-type region between a pair of second source regions 89 and second drain regions 90 is a second channel region 91. A second gate electrode 86 faces this second channel region 91 with a second gate insulating film 87 sandwiched therebetween. The second channel region 91 is formed in a part of the third well region 80.

[0116] A second contact region 92 is formed in the surface layer portion of the third well region 80 in the second outer region 84. The second contact region 92 may be referred to as a "second back gate region." The second contact region 92 has an n-type impurity concentration that exceeds the n-type impurity concentration of the third well region 80. The second contact region 92 is formed at a distance from the second trench isolation structure 61. The second contact region 92 may be in contact with the second trench isolation structure 61.

[0117] The semiconductor chip 2 includes one or more second drain wirings 93 formed in the interlayer insulating layer 22 (not shown in FIG. 8). The one or more second drain wirings 93 are electrically connected to the second drain region 90 via a second plug electrode 96. The second drain wirings 93 and the first drain wiring 75 are common wirings, which electrically connect the first drain region 73 and the second drain region 90 to each other.

[0118] The semiconductor chip 2 includes one or more second source wirings 94 formed in the interlayer insulating layer 22. The one or more second source wirings 94 are electrically connected to the second source region 89 and the second contact region 92 via second plug electrodes 96.

[0119] The semiconductor chip 2 includes one or more second gate wirings 95 formed in the interlayer insulating layer 22. The one or more second gate wirings 95 are electrically connected to the second gate electrode 86 via a second plug electrode 96. The second gate wiring 95 and the first gate wiring 77 are common wirings, and thereby the first gate electrode 69 and the second gate electrode 86 are electrically connected to each other.

[0120] 9 to 19, other patterns of the element boundary 24 that are different from those in Fig. 5 will be described below. In Fig. 9 to 19, the same reference numerals are used for the configurations that have already been described, and detailed description thereof will be omitted.

[0121] 9 is a diagram showing a second pattern of element boundary 24. Referring to Fig. 9, element boundary 24 has one end 25 and the other end 26 on one side surface (second side surface 16B in Fig. 9) of semiconductor chip 2 that face each other. As a result, element boundary 24 is formed along three side surfaces (first side surface 16A, third side surface 16C, and fourth side surface 16D in this embodiment) excluding the side surface on which one end 25 and the other end 26 are formed.

[0122] The long sides 30 of the base portion 28 are sides that extend along the third side surface 16C and the fourth side surface 16D, and the short sides 31 are sides that extend along the first side surface 16A and the second side surface 16B. Only one of the pair of short sides 31 of the base portion 28 (the side on the first side surface 16A side) is the side that forms the element boundary 24. As a result, the second element region 18 is surrounded by the first element region 17 on three sides: the first side surface 16A side, the third side surface 16C side, and the fourth side surface 16D side, and the periphery on the second side surface 16B side forms the second side surface 16B of the semiconductor chip 2.

[0123] In this embodiment, a pair of protrusions 29 protruding in opposite directions from base portion 28 toward a pair of opposing side surfaces (third side surface 16C and fourth side surface 16D in this embodiment) are formed at both ends of long side boundary 32 of base portion 28. As a result, protrusions 29 are formed as corner protrusions 29C at each of the four corners of base portion 28, which is rectangular in plan view.

[0124] One first line 36 of the U-shaped boundary 38 of the protruding portion 29 is integrated with the short side portion 31 of the base portion 28 to form the linear element boundary 24. In this embodiment, the first line 36 of the protruding portion 29 formed at the end of each long side portion 30 on the first side surface 16A side is integrated with the short side portion 31 on the first side surface 16A side to form the linear element boundary 24.

[0125] Next, consider a case where the element boundary 24 is divided into a first boundary 34 and a second boundary 35 by a dividing line 33 along the second direction Y. In this case, two protrusions 29 are arranged on each of the first boundary 34 side and the second boundary 35 side, and the protrusions 29 form a total of four U-shaped boundaries 38.

[0126] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0127] 10 is a diagram showing a third pattern of element boundary 24. Referring to FIG. 10, element boundary 24 is formed endlessly in a region spaced inward from peripheral region 27. In this embodiment, element boundary 24 is formed in a rectangular ring shape in plan view. Of course, element boundary 24 may also be in a circular or elliptical shape in plan view. As a result, first element region 17 surrounds the entire periphery of second element region 18 and forms the entire peripheral region 27 of semiconductor chip 2. Second element region 18 is formed in a rectangular shape in plan view, and forms element boundary 24 with first element region 17, having a pair of long sides 30 and a pair of short sides 31.

[0128] Next, consider a case where the element boundary 24 is divided into a first boundary 34 and a second boundary 35 by a parting line 33 along the second direction Y. In this case, the parting line 33 crosses the pair of long sides 30 of the element boundary 24 in the second direction Y. As a result, the U-shaped boundary 38 includes a pair of first lines 36 formed by the pair of long sides 30 of each second element region 18 divided by the parting line 33 crossing the pair of long sides 30, and a second line 37 formed by the short sides 31 connecting the ends of the pair of first lines 36.

[0129] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0130] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0131] 11 is a diagram showing a fourth pattern of element boundaries 24. Referring to Fig. 11, like the third pattern, element boundaries 24 are formed endlessly in a region spaced inward from peripheral region 27. As a result, first element region 17 surrounds the entire periphery of second element region 18 and forms the entire peripheral region 27 of semiconductor chip 2.

[0132] The second element region 18 integrally includes a base portion 28 that is rectangular in plan view and protrusions 29 that protrude from the base portion 28 toward the outer circumferential region 27. In this embodiment, the protrusions 29 are formed as corner protrusions 29C at each of the four corners of the base portion 28 that is rectangular in plan view. At a pair of corners on the first side surface 16A side of the second element region 18, a pair of protrusions 29 protrude in opposite directions. At a pair of corners on the second side surface 16B side of the second element region 18, a pair of protrusions 29 protrude in opposite directions.

[0133] In this embodiment, the second element region 18 is formed in a generally X-shape in plan view. Each protrusion 29 protrudes from both the long side 30 and the short side 31 of the base portion 28 toward the outer circumferential region 27. Each protrusion 29 includes one first line 36 that is continuous with the long side 30 of the base portion 28, the other first line 36 on the opposite side, and a third line 97 that connects the other first line 36 to the short side 31 of the base portion 28. The third line 97 is aligned with the second line 37 of the protrusion 29 at a distance and forms part of the element boundary 24.

[0134] Next, consider a case where the element boundary 24 is divided into a first boundary 34 and a second boundary 35 by a dividing line 33 along the second direction Y. In this case, two protrusions 29 are arranged on each of the first boundary 34 side and the second boundary 35 side, and the protrusions 29 form a total of four U-shaped boundaries 38.

[0135] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0136] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0137] Furthermore, since the third line 97 is formed in addition to the U-shaped boundary 38, the element boundary 24 can be made even longer, and the cooling effect can be further improved.

[0138] 12 is a diagram showing a fifth pattern of element boundaries 24. Referring to FIG. 12, like the third pattern, element boundaries 24 are formed endlessly in a region spaced inward from peripheral region 27. As a result, first element region 17 surrounds the entire periphery of second element region 18 and forms the entire peripheral region 27 of semiconductor chip 2.

[0139] The second element region 18 integrally includes a base portion 28 that is rectangular in plan view and a protrusion 29 that protrudes from the base portion 28 toward the outer circumferential region 27. In this embodiment, the protrusions 29 are formed as corner protrusions 29C at each of two corners on the first side surface 16A side of the base portion 28 that is rectangular in plan view. At a pair of corners on the first side surface 16A side of the second element region 18, a pair of protrusions 29 protrude in the same direction (toward the first side surface 16A).

[0140] One first line 36 of the U-shaped boundary 38 of the protruding portion 29 is integrated with the short side portion 31 of the base portion 28 to form the linear element boundary 24. In this embodiment, the first lines 36 of the protruding portion 29 formed at the end portions of each long side portion 30 on the third side surface 16C side and the fourth side surface 16D side are integrated with the short side portion 31 to form the linear element boundary 24. As a result, the second element region 18 is formed in a concave shape in plan view.

[0141] Next, consider a case where the element boundary 24 is divided into a first boundary 34 and a second boundary 35 by a dividing line 33 along the second direction Y. In this case, one protrusion 29 is disposed on each of the first boundary 34 side and the second boundary 35 side, and the protrusions 29 form a total of two U-shaped boundaries 38.

[0142] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0143] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0144] FIG. 13 is a diagram showing a sixth pattern of the element boundary 24. Referring to FIG. 13, one or more additional protrusions 29 may be formed between the pair of protrusions 29 in the fifth pattern of FIG. 12. In this embodiment, two additional protrusions 29 are formed between the pair of protrusions 29 on the long side 30 on the first side surface 16A side of the base 28. The multiple protrusions 29 may be arranged at equal intervals or at different intervals. In this case, the pair of protrusions 29 at both ends of the long side 30 may be referred to as first protrusions 29A, and the protrusion 29 between the pair of first protrusions 29A may be referred to as second protrusion 29B.

[0145] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0146] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0147] Furthermore, at least three U-shaped boundaries 38, each consisting of a pair of first protrusions 29A and second protrusions 29B, are formed on the long-side boundary 32, so that the element boundary 24 can be made even longer.

[0148] 14 is a diagram showing a seventh pattern of element boundaries 24. Referring to FIG. 14, protrusions 29 are also formed as corner protrusions 29C at each of the two corners on the second side face 16B side of base portion 28 in the fifth pattern of FIG. 12. As a result, protrusions 29 are formed as corner protrusions 29C at each of the four corners of base portion 28, which is rectangular in plan view. A pair of protrusions 29 protrude in opposite directions from a pair of corners on the third side face 16C side of second element region 18. Furthermore, a pair of protrusions 29 protrude in opposite directions from a pair of corners on the fourth side face 16D side of second element region 18. In this embodiment, second element region 18 is formed in a generally H-shape in plan view.

[0149] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0150] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0151] FIG. 15 is a diagram showing an eighth pattern of the element boundary 24. Referring to FIG. 15, one or more additional protrusions 29 may be formed between the pair of protrusions 29 in the seventh pattern of FIG. 14. In this embodiment, two additional protrusions 29 are formed between the pair of protrusions 29 on each of the long side portions 30 on the first side surface 16A side and the second side surface 16B side of the base portion 28. The multiple protrusions 29 may be arranged at equal intervals or at different intervals. In this case, the pair of protrusions 29 at both ends of the long side portion 30 may be referred to as first protrusions 29A, and the protrusion 29 between the pair of first protrusions 29A may be referred to as second protrusion 29B.

[0152] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0153] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0154] Furthermore, at least three U-shaped boundaries 38, each consisting of a pair of the first protrusion 29A and the second protrusion 29B, are formed on each long side boundary 32, so that the element boundary 24 can be made even longer.

[0155] 16 is a diagram showing a ninth pattern of element boundaries 24. Referring to Fig. 16, like the third pattern, element boundaries 24 are formed endlessly in a region spaced inward from peripheral region 27. As a result, first element region 17 surrounds the entire periphery of second element region 18 and forms the entire peripheral region 27 of semiconductor chip 2.

[0156] The second element region 18 integrally includes a base portion 28 that is rectangular in plan view and protruding portions 29 that protrude from the base portion 28 toward the outer circumferential region 27. In this embodiment, the protruding portions 29 are formed on each of the four sides of the base portion 28 that is rectangular in plan view. The protruding portions 29 are disposed at intervals from the four corners of the base portion 28.

[0157] A step 98 is formed between the first lines 36 of the protrusions 29 formed on the pair of long sides 30 of the base portion 28 and the short sides 31 of the base portion 28. Similarly, a step 98 is formed between the first lines 36 of the protrusions 29 formed on the pair of short sides 31 of the base portion 28 and the long sides 30 of the base portion 28.

[0158] In this embodiment, the four protrusions 29 are disposed at the center of each side of the base portion 28, forming a symmetrical relationship in the first direction X and the second direction Y. As a result, the second element region 18 is formed into a shape that is, for example, line-symmetric with respect to the dividing line 33 as the axis of symmetry, and point-symmetric with respect to the center of gravity of the base portion 28 as the center of symmetry.

[0159] Next, consider a case where the element boundary 24 is divided into a first boundary 34 and a second boundary 35 by a dividing line 33 along the second direction Y. In this case, one protrusion 29 is disposed on each of the first boundary 34 side and the second boundary 35 side, and a total of four U-shaped boundaries 38 are formed by the protrusions 29 as a whole.

[0160] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0161] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0162] Furthermore, because the four protrusions 29 are arranged in a symmetrical positional relationship, both the first element region 17 and the second element region 18 can be secured as regions with line-symmetric and point-symmetric shapes. As a result, the element structures can be arranged in a balanced manner in the first element region 17 and the second element region 18, and the amount of heat generated can be dispersed evenly.

[0163] 17 is a diagram showing a tenth pattern of the element boundary 24. Referring to FIG. 17, the four protrusions 29 of the ninth pattern of FIG. 16 are arranged in an asymmetrical positional relationship. In this configuration, a step 98 is formed between the first line 36 of the protrusions 29 formed on the pair of short side portions 31 of the base portion 28 and the long side portion 30 of the base portion 28, as in the ninth pattern. Meanwhile, the first line 36 of the protrusions 29 formed on the pair of long side portions 30 of the base portion 28 is integrated with the short side portions 31 of the base portion 28 to form a linear element boundary 24.

[0164] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0165] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0166] 18 is a diagram showing an eleventh pattern of the element boundary 24. Referring to Fig. 18, in the tenth pattern of Fig. 17, one protrusion 29 protrudes from both the long side 30 and the short side 31 of the base portion 28 toward the outer circumferential region 27. The protrusion 29 includes one first line 36 that is continuous with the short side 31 of the base portion 28, the other first line 36 on the opposite side, and a third line 97 that connects the other first line 36 to the long side 30 of the base portion 28.

[0167] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0168] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0169] Furthermore, since the third line 97 is formed in addition to the U-shaped boundary 38, the element boundary 24 can be made even longer, and the cooling effect can be further improved.

[0170] Fig. 19 is a diagram showing a twelfth pattern of the element boundary 24. Referring to Fig. 19, in the ninth pattern of Fig. 16, a second protruding portion 99 is formed that protrudes further from one protruding portion 29 toward the outer circumferential region 27. This forms protruding portions 29, 99 having a two-tiered structure of protruding portion 29 and second protruding portion 99. This two-tiered structure of protruding portions 29, 99 may be applied to the protruding portions 29 of all the patterns described above, not limited to the ninth pattern of Fig. 16.

[0171] Even with this configuration, the U-shaped boundary 38 is formed between the first element region 17 and the second element region 18, thereby lengthening the element boundary 24. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21, improving the cooling effect.

[0172] Furthermore, since the second element region 18 is surrounded by the first element region 17, the heat of the first element region 17 can be transferred from the entire periphery of the second element region 18. This allows the heat generated in the output transistor 20 to be efficiently transferred to the control IC 21 side, regardless of the position where the output transistor 20 is formed in the first element region 17.

[0173] Furthermore, since the protrusions 29, 99 are formed in a two-stage structure, the element boundary 24 can be made even longer, and the cooling effect can be further improved.

[0174] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0175] In the above-described embodiment, the first element region 17 is a region for the output transistor 20, and the second element region 18 is a region for the control IC 21, but various element structures can be arranged in the first element region 17 and the second element region 18. This is because if there is a difference in the amount of heat generated between the element structures arranged in the first element region 17 and the second element region 18, the above-described cooling effect can be achieved.

[0176] In the above-described embodiment, an example was shown in which the first conductivity type was n-type and the second conductivity type was p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing the n-type regions with p-type regions and the p-type regions with n-type regions in the above description and accompanying drawings.

[0177] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0178] The following additional features can be extracted from the description of this specification and the drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments.

[0179] [Appendix 1-1] a semiconductor chip (2) formed in a rectangular shape in a plan view, having a pair of first side portions (16A, 16B) extending in a first direction (X) and a pair of second side portions (16C, 16D) extending in a second direction (Y) perpendicular to the first direction (X), and having a main surface (8) surrounded by the pair of first side portions (16A, 16B) and the pair of second side portions (16C, 16D); The semiconductor chip (2) includes a first element region (17) formed on the main surface (8) of the semiconductor chip (2) and having a first element (20) with a relatively large amount of heat generated therein, and a second element region (18) formed with a second element (21) with a relatively smaller amount of heat generated therein than the first element (20), the second element region (18) being adjacent to the first element region (17) across an element boundary (24), A semiconductor device (1), wherein when the element boundary (24) is divided into a first boundary (34) and a second boundary (35) by a dividing line (33) along the second direction (Y), at least one of the first boundary (34) and the second boundary (35) includes a U-shaped boundary (38) formed by a pair of first lines (36) arranged at a distance from each other and a second line (37) connecting one ends of the pair of first lines (36).

[0180] According to this configuration, the U-shaped boundary (38) is formed, so that the element boundary (24) between the first element (20) and the second element (21) per unit section can be made longer than in the case of a linear boundary or a stepped boundary, which allows the heat generated in the first element (20) to be efficiently transferred to the second element (21), thereby improving the cooling effect.

[0181] [Appendix 1-2] The semiconductor device (1) described in Appendix 1-1, wherein the first element region (17) surrounds the second element region (18) so as to form an endless element boundary (24), and forms at least a part of a peripheral region (27) of the semiconductor chip (2).

[0182] According to this configuration, since the second element region (18) is surrounded by the first element region (17), heat from the first element region (17) can be transferred from the entire periphery of the second element region (18). As a result, heat generated in the first element (20) can be efficiently transferred to the second element (21) regardless of the formation position of the first element (20) in the first element region (17).

[0183] [Appendix 1-3] the element boundary (24) has one end (25) and the other end (26) on two of the pair of first side portions (16A, 16B) and the pair of second side portions (16C, 16D); The semiconductor device (1) described in Appendix 1-1, wherein the first element region (17) forms at least a part of a peripheral region (27) of the semiconductor chip (2) on the opposite side of the element boundary (24) from the second element region (18).

[0184] According to this configuration, the element boundary (24) is formed across the semiconductor chip (2) between one of the two sides of the semiconductor chip (2) and the other side, so that a relatively long element boundary (24) can be ensured.

[0185] [Appendix 1-4] the second element region (18) integrally includes a base portion (28) having a rectangular shape in a plan view and a protruding portion (29) protruding from the base portion (28) toward the outer circumferential region (27), The semiconductor device (1) according to Supplementary Note 1-2 or Supplementary Note 1-3, wherein the U-shaped boundary (38) is formed between the protrusion (29) and the first element region (17).

[0186] [Appendix 1-5] The semiconductor device (1) according to appendix 1-4, wherein the base portion (28) has an area larger than that of the protrusion (29).

[0187] According to this configuration, the area of ​​the base portion (28) is larger than that of the protrusion portion (29), so that a large space can be secured for the second element (21) in the base portion (28), thereby improving the degree of freedom in the layout of the second element (21).

[0188] [Appendix 1-6] The base portion (28) is formed in a rectangular shape in a plan view, having a pair of long sides (30) and a pair of short sides (31), At least one of the pair of long side portions (30) is a long side boundary (32) that forms the element boundary (24), The semiconductor device (1) described in Appendix 1-4, wherein a plurality of the protrusions (29) are arranged along the long side boundary (32) so that the first line (36) of the U-shaped boundary (38) is continuous with the long side boundary (32).

[0189] According to this configuration, a plurality of U-shaped boundaries (38) are further formed on the long side boundary (32), thereby making it possible to ensure a relatively long element boundary (24).

[0190] [Appendix 1-7] The protrusion (29) is formed at the end of the long side boundary (32), The semiconductor device (1) according to appendix 1-6, wherein one of the first lines (36) of the U-shaped boundary (38) of the protrusion (29) is integrated with the short side portion (31) of the base portion (28) to form the linear element boundary (24).

[0191] [Appendix 1-8] The pair of long side portions (30) are long side boundaries (32) that form the element boundary (24), The semiconductor device (1) according to appendix 1-7, wherein at least one pair of the protrusions (29) protrudes in opposite directions from each of the long side boundaries (32).

[0192] According to this configuration, the protrusions (29) are formed on both sides of the base portion (28) in the width direction, so that the element boundary (24) can be made even longer.

[0193] [Appendix 1-9] A plurality of the protrusions (29) are formed at both ends of the long side boundary (32) and between the both ends, The semiconductor device (1) described in Appendix 1-7, wherein the plurality of protrusions (29) include a pair of first protrusions (29A) that are integrated with the short side portion (31) of the base portion (28) at both ends of the long side boundary (32) to form the linear element boundary (24), and at least one second protrusion (29B) formed between the pair of first protrusions (29A).

[0194] According to this configuration, at least three U-shaped boundaries (38) are formed on the long side boundary (32), so that the element boundary (24) can be made even longer.

[0195] [Appendix 1-10] The base portion (28) is formed in a rectangular shape in a plan view, having a pair of long sides (30) and a pair of short sides (31), The semiconductor device (1) according to appendix 1-4, wherein the protrusion (29) includes a corner protrusion (29C) formed on at least one corner of the base portion (28) so that one of the first lines (36) is connected to the long side portion (30).

[0196] [Appendix 1-11] The semiconductor device (1) according to appendix 1-10, wherein the corner protrusions (29C) are formed at the four corners of the base portion (28).

[0197] [Appendix 1-12] the corner protrusions (29C) protrude from both the long side portions (30) and the short side portions (31) toward the outer circumferential region (27); the corner protrusion (29C) further includes a third line (97) that is aligned with the second line (37) at a distance and connects the other first line (36) to the short side portion (31); The semiconductor device (1) according to appendix 1-10, wherein the third line (97) forms a part of the element boundary (24).

[0198] According to this configuration, since the third line (97) is further formed in addition to the U-shaped boundary (38), the element boundary (24) can be made longer, and the cooling effect can be further improved.

[0199] [Appendix 1-13] The semiconductor chip (2) is divided into two element regions, the first element region (17) on one of the first side portions (16A) and the second element region (18) on the other of the first side portions (16B), such that the element boundary (24) extends from one of the second side portions (16C) to the other of the second side portions (16D), the second element region (18) includes a plurality of protrusions (29) protruding toward the first element region (17) between one of the second side portions (16C) and the other of the second side portions (16D), The semiconductor device (1) according to appendix 1-1, wherein the U-shaped boundary (38) is formed between the plurality of protrusions (29) and the first element region (17).

[0200] [Appendix 1-14] the second element region (18) is surrounded by the first element region (17) from three sides, namely, one of the first side portions (16A) and the pair of second side portions (16C, 16D), and the periphery of the other of the first side portions (16B) forms the first side portion (16B) of the semiconductor chip (2); the second element region (18) integrally includes a base portion (28) formed in a rectangular shape in a plan view, the base portion (28) having sides parallel to the pair of first side portions (16A, 16B) and the pair of second side portions (16C, 16D), and a pair of protrusions (29) protruding in opposite directions from the base portion (28) toward the pair of second side portions (16C, 16D), The semiconductor device (1) according to appendix 1-1, wherein the U-shaped boundary (38) is formed between the pair of protrusions (29) and the first element region (17).

[0201] [Appendix 1-15] the second element region (18) is formed in a rectangular shape in a plan view, and forms an element boundary (24) between the second element region (18) and the first element region (17) that has a pair of long side portions (30) and a pair of short side portions (31); The semiconductor device (1) described in Appendix 1-2, wherein the U-shaped boundary (38) includes the pair of first lines (36) formed by the pair of long side portions (30) of each of the second element regions (18) divided by the dividing line (33) crossing the pair of long side portions (30), and a second line (37) formed by the short side portions (31) connecting the ends of the pair of first lines (36).

[0202] [Appendix 1-16] The first element (20) includes an output element (20), The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-15, wherein the second element (21) includes a control element (21) that controls on / off of the output element.

[0203] [Appendix 1-17] The semiconductor device (1) according to any one of Appendices 1-1 to 1-16, wherein the element boundary (24) includes a trench (42) formed in the semiconductor chip (2), an insulating film (43) formed on a wall surface of the trench (42), and an embedded body (44) embedded in the trench (42) via the insulating film (43).

[0204] [Appendix 1-18] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-17, wherein the semiconductor chip (2) is a silicon chip.

[0205] [Appendix 1-19] The semiconductor device (1) according to any one of Appendix 1-1 to Appendix 1-18, further comprising a molding resin that covers the semiconductor chip (2). [Explanation of symbols]

[0206] 1: Semiconductor device 2: Semiconductor chip 3: Die pad 4: Conductive bonding material 5A: First lead electrode 5B: Second lead electrode 5C: Third lead electrode 5D: 4th lead electrode 5E: 5th lead electrode 5F: 6th lead electrode 5G: 7th lead electrode 5H: 8th lead electrode 6A: 1st conductor 6B: 2nd conductor 6C: 3rd conductor 6D: 4th conductor 6E: 5th conductor 7: Mold resin 8: First main surface 9: Second main surface 10: Drain terminal 11: Source terminal 12: Input terminal 13: Ground terminal 14: Enable terminal 15: Sense terminal 16A: 1st side 16B: 2nd side 16C: 3rd side 16D: 4th side 17: First element region 18: Second element region 19: Area separation structure 20: Output transistor 21: Control IC 22: Interlayer insulating layer 23: Wiring 24: Element boundary 25: one end 26: Other end 27:Outer area 28: Base part 29:Protruding part 29A: 1st protrusion 29B:Second protrusion 29C: Corner protrusion 30: Long side 31: Short side 32: Long side boundary 33:Dividing line 34 :1st boundary 35:Second boundary 36: First line 37: Second line 38 :U-shaped boundary 39: First semiconductor region 40: Second semiconductor region 41: Trench isolation structure 42: Isolation trench 43: Isolation insulating film 44: Separation electrode 45: Body region 46: Trench structure 47: Trench 48: Upper insulating film 49: Lower insulating film 50: Upper electrode 51: Lower electrode 52: Intermediate insulating film 53: Source area 54: Third semiconductor region 55: Contact area 56: Source wiring 57: Plug electrode 61: Second trench isolation structure 62: First well region 63: First contact area 64: Second well region 65: 1st MIS area 66: 1st element isolation structure 67: 1st outer area 68:First outer separation structure 69: First gate electrode 70: First gate insulating film 71: First sidewall structure 72: First source area 73: First drain region 74: First channel region 75: First drain wiring 76: First source wiring 77: First gate wiring 78: First plug electrode 79 :Blank area 80: Third well region 81: Fourth well region 82: 2nd MIS area 83:Second element isolation structure 84 :Second outer area 85:Second outer separation structure 86: Second gate electrode 87: Second gate insulating film 88: Second sidewall structure 89: Second source area 90: Second drain region 91: Second channel region 92: Second contact area 93: Second drain wiring 94: Second source wiring 95: Second gate wiring 96: Second plug electrode 97: Third line 98: Step 99:Second protrusion

Claims

1. a semiconductor chip formed in a rectangular shape in a plan view having a pair of first sides extending in a first direction and a pair of second sides extending in a second direction perpendicular to the first direction, the semiconductor chip having a main surface surrounded by the pair of first sides and the pair of second sides; a first element region formed on the main surface of the semiconductor chip, the first element having a relatively large heat generation amount formed therein, and a second element region formed with a second element having a relatively smaller heat generation amount than the first element, the second element region being adjacent to the first element region across an element boundary; A semiconductor device, wherein when the element boundary is divided into a first boundary and a second boundary by a dividing line along the second direction, at least one of the first boundary and the second boundary includes a U-shaped boundary formed by a pair of first lines arranged at a distance from each other and a second line connecting one ends of the pair of first lines.

2. 2 . The semiconductor device according to claim 1 , wherein the first element region surrounds the second element region so that the element boundary is endless, and forms at least a part of a peripheral region of the semiconductor chip.

3. the element boundary has one end and the other end on two of the pair of first side portions and the pair of second side portions, 2 . The semiconductor device according to claim 1 , wherein the first element region forms at least a part of a peripheral region of the semiconductor chip on an opposite side of the element boundary to the second element region.

4. the second element region integrally includes a base portion having a rectangular shape in a plan view and a protruding portion protruding from the base portion toward the outer circumferential region, The semiconductor device according to claim 2 , wherein the U-shaped boundary is formed between the protruding portion and the first element region.

5. The semiconductor device according to claim 4 , wherein the base portion has an area larger than that of the protruding portion.

6. The base portion is formed in a rectangular shape in a plan view having a pair of long sides and a pair of short sides, At least one of the pair of long side portions is a long side boundary that forms the element boundary, The semiconductor device according to claim 4 , wherein the plurality of protrusions are arranged along the long side boundary so that the first line of the U-shaped boundary is continuous with the long side boundary.

7. The protrusion is formed at an end of the long side boundary, 7. The semiconductor device according to claim 6, wherein one of said first lines of said U-shaped boundary of said protruding portion is integrated with said short side portion of said base portion to form said element boundary in a straight line.

8. each of the pair of long side portions is a long side boundary that forms the element boundary, The semiconductor device according to claim 7 , wherein at least a pair of said protruding portions protrude in mutually opposite directions from each of said long side boundaries.

9. A plurality of the protrusions are formed at both ends of the long side boundary and between the both ends, 8. The semiconductor device according to claim 7, wherein the plurality of protrusions include a pair of first protrusions that are integrated with the short side portion of the base portion at both ends of the long side boundary to form a linear element boundary, and at least one second protrusion formed between the pair of first protrusions.

10. The base portion is formed in a rectangular shape in a plan view having a pair of long sides and a pair of short sides, 5. The semiconductor device according to claim 4, wherein said protrusion includes a corner protrusion formed in at least one corner of said base portion so that one of said first lines is connected to said long side portion.

11. 11. The semiconductor device according to claim 10, wherein the corner protrusions are formed at four of the corners of the base portion.

12. the corner protrusions protrude from both the long side portion and the short side portion toward the outer circumferential region, the corner protrusion further includes a third line spaced apart from the second line and connecting the other of the first lines to the short side portion, The semiconductor device according to claim 10 , wherein the third line forms a part of the device boundary.

13. the semiconductor chip is divided into two element regions, the first element region on one of the first side portions and the second element region on the other of the first side portions, such that the element boundary extends from one of the second side portions to the other of the second side portions; the second element region includes a plurality of protruding portions protruding toward the first element region between one of the second side portions and the other of the second side portions, The semiconductor device according to claim 1 , wherein the U-shaped boundary is formed between the plurality of protrusions and the first element region.

14. the second element region is surrounded by the first element region from three sides, i.e., one of the first side portions and the pair of second side portions, and a periphery of the other first side portion forms the first side portion of the semiconductor chip; the second element region integrally includes a base portion formed in a rectangular shape in a plan view having sides parallel to the pair of first side portions and the pair of second side portions, and a pair of protrusions protruding in opposite directions from the base portion toward the pair of second side portions, The semiconductor device according to claim 1 , wherein the U-shaped boundary is formed between the pair of protrusions and the first element region.

15. the second element region is formed in a rectangular shape in a plan view, and forms an element boundary between the second element region and the first element region, the element boundary having a pair of long sides and a pair of short sides; 3. The semiconductor device of claim 2, wherein the U-shaped boundary includes a pair of first lines formed by a pair of long sides of each of the second element regions divided by the dividing line that crosses the pair of long sides, and a second line formed by the short side portions that connect ends of the pair of first lines.

16. the first element includes an output element; 16. The semiconductor device according to claim 13, wherein the second element includes a control element that controls turning on and off of the output element.

17. The semiconductor device according to any one of claims 13 to 15, wherein the element boundary includes a trench formed in the semiconductor chip, an insulating film formed on a wall surface of the trench, and a buried body buried in the trench via the insulating film.

18. 4. The semiconductor device according to claim 1, wherein the semiconductor chip is a silicon chip.

19. The semiconductor device according to claim 18 , further comprising a molding resin that covers the semiconductor chip.

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