High aspect ratio etching with infinite selectivity

Abstract

SOLUTION: To provide a method and an apparatus for processing a substrate by exposing a substrate to a plasma to simultaneously (i) etch features into an underlying material (e.g., including one or more dielectric materials) and (ii) deposit a top mask protector layer on a mask disposed over the dielectric material, the top mask protector layer being formed on the mask by selective vertical directional deposition, which may be used to achieve infinite etch selectivity, even when etching high aspect ratio features.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] Incorporation by Reference A PCT application has been filed contemporaneously herewith as a part of this application. Each application to which this application claims benefit or priority as identified in the contemporaneously filed PCT application is hereby incorporated by reference in its entirety for all purposes. [Background technology]

[0002] One process that is often utilized during the manufacture of semiconductor devices is the formation of etched cylinders and other recessed features in dielectric materials. Example contexts in which such processes may be performed include, but are not limited to, memory applications such as DRAM and 3D NAND structures. As the semiconductor industry develops and device dimensions become smaller, it becomes increasingly difficult to etch such features in a uniform manner, especially due to high aspect ratio features having narrow widths and / or large depths.

[0003] The background discussion provided herein is intended to provide a general context for the present disclosure. Work by the currently named inventors within the scope of what is described in this background section, as well as aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, either expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] Methods and apparatus for processing a substrate are described herein. In particular, embodiments herein relate to simultaneously etching a substrate and depositing a top mask protector layer formed by selective vertical directional deposition.

[0005] In one aspect of the embodiments herein, there is provided a method of processing a substrate, the substrate comprising a dielectric material and a mask, the dielectric material comprising at least one layer of silicon oxide, the mask disposed over the dielectric material and patterned to define locations where features are to be etched into the dielectric material, the method comprising: (a) generating a plasma in a reaction chamber; and (b) exposing the substrate to the plasma in the reaction chamber to simultaneously (i) etch features into the dielectric material and (ii) depositing a top mask protector layer on the mask, the top mask protector layer being formed over the mask by selective vertical directional deposition.

[0006] In various embodiments, the mask is not consumed during the etch, thereby resulting in an infinite etch selectivity with respect to the dielectric material compared to the mask. In various embodiments, the top mask protector layer protects the mask from erosion during the etch, such that the etch selectivity with respect to the dielectric material compared to the mask is infinite. The top mask protector layer may have one of several compositions. In some cases, the top mask protector layer includes a graphitic carbon rich polymer. In these or other cases, the top mask protector layer includes a C x Br y F z system material, C x Cl y F z system material, C x I y F z The material may include a polyimide-based material, ... or a combination thereof.

[0007] Generating the plasma may include flowing a reaction mixture into the reaction chamber and generating a plasma from the reaction mixture. In various embodiments, the reaction mixture may include (1) hydrogen (H2) and (2) at least one reactant selected from the group consisting of fluoromethane (CH3F), difluoromethane (CH2F2), and trifluoromethane (CHF3). In these or other embodiments, the reaction mixture may further include a non-fluorine halogen source. The non-fluorine halogen source may include one or more reactants selected from the group consisting of HBr, Cl2, SiCl4, and CF3I. In these or other embodiments, the reaction mixture may further include one or more additives selected from the group consisting of nitrogen trifluoride (NF3), hexafluorobutadiene (C4F6), octofluoropropane (C3F8), octafluorocyclobutane (C4F8), sulfur hexafluoride (SF6), tetrafluoromethane (CF4), and methane (CH4).

[0008] In certain cases, certain reaction conditions may be used. For example, the pressure in the reaction chamber may be maintained at about 10-80 mT during (b). In these or other embodiments, the substrate may be supported on a substrate holder that is maintained at a temperature of about 0° C. to −100° C. during (b). In these or other embodiments, the ion energy may be about 1-10 kV at the surface of the substrate during (b). In these or other embodiments, the RF energy used to generate the plasma may be pulsed during (b) at a power level of about 3-50 kW. In these or other embodiments, the plasma may be a capacitively coupled plasma.

[0009] In various embodiments, the mask may have a particular thickness. In one example, the mask may have a thickness of about 3500 nm or less before a top mask protector layer is formed over the mask. In these or other embodiments, the feature etched in (b) may have a depth-to-width aspect ratio of about 20 or more and a final depth of about 100 nm or more. In some cases, the feature etched in (b) includes a concave cylinder. In some cases, the feature etched in (b) includes a concave trench. In some cases, the feature etched in (b) includes at least one of a concave cylinder and a convex trench.

[0010] In various embodiments, selective vertical directional deposition results in the formation of an upper mask protector layer in areas where the mask is present, without forming an upper mask protector layer over locations where features will be etched into the dielectric material.

[0011] The dielectric material may be provided in a number of different forms depending on the application. In one example, the dielectric material includes at least one layer of silicon oxide and at least one layer of silicon nitride. The silicon oxide and silicon nitride may be provided in alternating layers. This structure, sometimes referred to as an ONON stack, may be used in creating 3D NAND devices in certain implementations. In other cases, the silicon oxide may be sandwiched between two or more silicon nitride layers. This structure may be used in creating DRAM devices. In some other cases, the dielectric material may be provided as layers of silicon oxide alternating with layers of polysilicon. This structure may be used in creating 3D NAND devices in certain implementations.

[0012] In another aspect of embodiments herein, an apparatus for processing a substrate is provided, the apparatus including: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate a plasma in the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller having at least one processor and a memory, the at least one controller and the one memory being communicatively coupled to each other, the memory storing computer executable instructions for controlling the at least one controller to: (i) disposing a substrate in the reaction chamber; (ii) generating a plasma in the reaction chamber; and (iii) exposing the substrate to the plasma in the reaction chamber to (i) etch features in a dielectric material on the substrate and (ii) deposit a top mask protector layer on a mask disposed over the dielectric material, the top mask protector layer being formed over the mask by selective vertical directional deposition.

[0013] In some embodiments, the plasma generator may be configured to generate a capacitively coupled plasma. In various cases, the controller may be configured to perform (e)(ii) such that the upper mask protector layer comprises a graphitic carbon-rich polymer. In these or other embodiments, the upper mask protector layer comprises a C x Br y F z system material, C x Cl y F z system material, C x I y F zIn these or other embodiments, the controller may be configured to perform (e)(ii) by flowing a reaction mixture into the reaction chamber such that a plasma is generated from the reaction mixture, the reaction mixture including (1) hydrogen (H2) and (2) at least one reactant selected from the group consisting of fluoromethane (CH3F), difluoromethane (CH2F2), and trifluoromethane (CHF3). In these or other embodiments, the reaction mixture may further include a non-fluorine halogen source. The non-fluorine halogen source may include at least one reactant selected from the group consisting of HBr, Cl2, SiCl4, and CF3I. In these or other embodiments, the reaction mixture may further include one or more additives selected from the group consisting of nitrogen trifluoride (NF3), hexafluorobutadiene (C4F6), octofluoropropane (C3F8), octafluorocyclobutane (C4F8), sulfur hexafluoride (SF6), tetrafluoromethane (CF4), and methane (CH4).

[0014] These and other aspects are further described below with reference to the drawings. [Brief description of the drawings]

[0015] [Figure 1A] FIG. 1A shows a semiconductor substrate undergoing an etching process and illustrates a typical mask erosion problem that occurs with conventional etching methods. [Figure 1B] FIG. 1B shows a semiconductor substrate undergoing an etching process, illustrating the typical mask erosion problem that occurs with conventional etching methods. [Figure 1C] FIG. 1C shows a semiconductor substrate undergoing an etching process, illustrating the typical mask erosion problem that occurs with conventional etching methods.

[0016] [Figure 2A] FIG. 2A illustrates a semiconductor substrate undergoing an etching process according to one embodiment herein, where a top mask protector layer is deposited over a mask layer during etching. [Figure 2B] FIG. 2B illustrates a semiconductor substrate undergoing an etching process according to an embodiment herein, where a top mask protector layer is deposited over the mask layer during etching. [Figure 2C] FIG. 2C illustrates a semiconductor substrate undergoing an etching process according to an embodiment herein, where a top mask protector layer is deposited over the mask layer during etching.

[0017] [Diagram 3] FIG. 3 shows a flow chart illustrating a method for etching a substrate according to various embodiments described herein.

[0018] [Figure 4A] FIG. 4A illustrates an etch reactor according to a specific embodiment. [Figure 4B] FIG. 4B illustrates an etch reactor according to a specific embodiment. [Figure 4C] FIG. 4C illustrates an etch reactor according to a specific embodiment.

[0019] [Figure 5A] Experimental results are shown in FIG. 5A, where FIG. 5A illustrates the substrate before etching, FIG. 5B illustrates the substrate after etching by a conventional method, and FIG. 5C illustrates the substrate after etching by the method described herein. [Figure 5B] FIG. 5B shows the experimental results, where FIG. 5A illustrates the substrate before etching, FIG. 5B illustrates the substrate after etching by a conventional method, and FIG. 5C illustrates the substrate after etching by the method described herein. [Figure 5C] FIG. 5C shows the experimental results, where FIG. 5A illustrates the substrate before etching, FIG. 5B illustrates the substrate after etching by a conventional method, and FIG. 5C illustrates the substrate after etching by the method described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. It will be understood that while the disclosed embodiments will be described in conjunction with specific embodiments, it is not intended to be limited to the disclosed embodiments.

[0021] I. Technique for etching high aspect ratio features in dielectric materials The fabrication of certain semiconductor devices involves etching features into one or more dielectric materials provided on a substrate. The dielectric material may be a single layer of one material or a stack of multiple materials. In some cases, the stack includes alternating layers of dielectric materials (e.g., silicon nitride and silicon oxide, or silicon oxide and polysilicon). One example of an etched feature is a cylinder, which may have a high aspect ratio. Another example of an etched feature is a trench, which also has a high aspect ratio. As the aspect ratio of such features continues to increase, it becomes increasingly difficult to etch the features into the dielectric material.

[0022] To etch high aspect ratio features on a substrate, the substrate is first prepared as desired for a particular application. This may include depositing one or more layers of dielectric material on the substrate, as described further below. Such dielectric layers include the layers in which the features are to be etched. After the dielectric material is deposited on the substrate, a mask layer is deposited and then patterned on the substrate. The patterned mask layer serves to define where the features are to be etched on the substrate. Notably, the features are etched in the areas where the mask layer has been removed, while the areas where the mask remains are protected during etching.

[0023] 1A-1C together illustrate one challenge that may arise during etching of high aspect ratio features. FIG. 1A shows a substrate 100 before etching. The substrate 100 has an underlying material 102 and a mask 104 thereon. The underlying material 102 may include one or more layers of a dielectric material, such as silicon oxide and / or silicon nitride. In a particular example, the underlying material 102 includes alternating layers of silicon oxide and silicon nitride, as discussed further below. In another particular example, the underlying material 102 includes alternating layers of silicon oxide and polysilicon. Other layers and / or structures may optionally also be present. The mask 104 may be an ashing hard mask material, such as amorphous carbon. As shown in FIG. 1A, the mask 104 is patterned. FIG. 1B illustrates the substrate 100 as features 106 are being etched into the underlying material 102. As discussed above, the features 106 are formed in areas where the mask 104 is not present. However, due to the severity of the etching conditions, the mask 104 is substantially eroded during etching. As such, the mask 104 in FIG. 1B is much thinner than the mask 104 in FIG. 1A. FIG. 1C illustrates the substrate 100 after etching (or further etched compared to FIG. 1B), where the mask 104 has been completely eroded away. At this point, it is difficult or impossible to etch the feature 106 any deeper, since the top of the underlying material 102 is exposed to the etching conditions after the mask 104 has been eroded away. Thus, further etching would erode both the bottom of the feature 106 and the top / exposed portions of the underlying material 102, preventing the feature 106 from becoming any deeper.

[0024] The problem described in connection with Figures 1A-1C concerns etch selectivity. Etch selectivity is related to the fact that some materials are etched more quickly than other materials. In the context of Figures 1A-1C, it is desirable to selectively etch the underlying material 102 as compared to the mask 104. In other words, it is desirable to etch the underlying material 102 faster than the mask 104.

[0025] Etch selectivity for a particular etch process and set of materials can be defined numerically as: (thickness etched through material A) / (thickness etched through material B). For example, an etch process that will etch 2 μm of underlying material and 0.5 μm of mask is understood to have an etch selectivity of 4 (e.g., 2 μm / 0.5 μm=4), which may also be expressed as an etch selectivity of 4:1. If the etch selectivity is not high enough, the mask layer will be eroded away before the feature reaches the desired final depth.

[0026] Another problem encountered during etching of high aspect ratio features is a non-uniform etch profile. In other words, the feature is not etched straight down or vertically. Instead, the sidewalls of the feature are often bowed, with the middle portion of the etched feature being wider (i.e., etched laterally further) than the top and / or bottom of the feature. This over-etching near the middle of the feature can compromise the structural and / or electronic integrity of the remaining material. The portion of the feature that bows outward may occupy a relatively small or a relatively large portion of the total feature depth. The portion of the feature that bows outward is the portion of the feature where the critical dimension is greatest. In general, it is desirable for the maximum CD of the feature to be approximately the same as the CD of other portions of the feature, such as at or near the bottom of the feature. Unfortunately, the formation of bowed features is observed even when the aspect ratio is as low as about 5.

[0027] Due to these and other limitations, conventional etching methods have been limited in practice to the formation of features with relatively low aspect ratios, however, several recent applications require cylindrical or other concave features with higher aspect ratios than can be achieved with conventional techniques.

[0028] II. Context and Application In various embodiments herein, features are etched into a substrate (typically a semiconductor wafer) having a dielectric material on a surface thereof, the etching process being typically a plasma-based etching process.

[0029] A feature is a depression in the surface of a substrate. Features can have many different shapes, including but not limited to, cylindrical, elliptical, rectangular, square, other polygonal depressions, trenches, and the like.

[0030] Aspect ratio is the depth of a feature compared to the critical dimension of that feature (usually the width or diameter). For example, a cylinder that is 2 μm deep and 50 nm wide has an aspect ratio of 40:1, often simply written as 40. Because features can have non-uniform critical dimensions relative to their depth, aspect ratios can vary depending on where they are measured. For example, an etched cylinder sometimes has a middle section that is wider than the top and bottom. This wider middle section is sometimes referred to as a bow shape, as discussed above. An aspect ratio measured based on the critical dimension at the top (i.e., neck) of the cylinder will be higher than an aspect ratio measured based on the critical dimension at the wider middle / bow shape of the cylinder. As used herein, aspect ratios are measured based on the critical dimension close to the opening of the feature, unless otherwise specified.

[0031] The features formed through the methods of the present disclosure may be high aspect ratio features. In some applications, high aspect ratio features are features having an aspect ratio of at least about 5, at least about 10, at least about 20, at least about 30, at least about 40, at least about 50, at least about 60, at least about 80, or at least about 100. The critical dimension of the features formed through the disclosed methods may be about 200 nm or less, such as about 100 nm or less, about 50 nm or less, or about 20 nm or less.

[0032] The underlying material from which the features are etched may include a dielectric material in various cases. Examples of materials include, but are not limited to, silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, and stacks from any combination of these materials. Specific examples of materials include stoichiometric and non-stoichiometric formulations of SiO2, SiN, SiC, SiCN, and the like. The material or materials to be etched may further include other elements, for example, hydrogen in various cases. In some embodiments, the nitride and / or oxide materials to be etched have a composition that includes hydrogen. As used herein, silicon oxide materials, silicon nitride materials, and the like include both stoichiometric and non-stoichiometric versions of such materials, with the understanding that such materials may include other elements, as described above. In some cases, the underlying material may include layers of other materials, including, but not limited to, polysilicon.

[0033] One application of the disclosed method is in the context of forming DRAM devices. In this case, the features may be etched primarily in silicon oxide. The substrate may further include, for example, one, two, or more silicon nitride layers. In one example, the substrate includes a silicon oxide layer sandwiched between two silicon nitride layers, the silicon oxide layer being about 800-1800 nm thick, and one or more of the silicon nitride layers being about 20-600 nm thick. The etched features may be cylinders having a final depth of between about 1-3 μm, for example, about 1.5-2 μm. The cylinders may have a width of between about 10-50 nm, for example, about 15-30 nm. After the cylinders are etched, a capacitor memory cell can be formed therein.

[0034] Another application of the disclosed method is in the context of forming vertical NAND (VNAND, also called 3D NAND) devices. In this case, the material from which the features are etched may have a repeating layer structure. For example, the material may include alternating layers of oxide (e.g., SiO2) and nitride (e.g., SiN), or alternating layers of oxide (e.g., SiO2) and polysilicon. The alternating layers form pairs of materials. In some cases, the number of pairs may be at least about 20, at least about 30, at least about 40, at least about 60, at least about 70, at least about 120, at least about 240, or at least about 380. In various cases, the number of pairs may be about 10-60 (e.g., about 20-120 individual layers), or about 100-200, or about 200-400. Based on current device dimensions, the oxide layer may be between about 20-50 nm thick, for example about 30-40 nm thick. The nitride or polysilicon layers may be between about 20-50 nm, e.g., about 30-40 nm, thick. As device dimensions continue to shrink, these layers will become thinner, e.g., each layer may even reach a thickness of less than 10 nm. The techniques described herein are expected to achieve infinite selectivity in these embodiments as well. The features etched in the alternating layers may have a depth between about 2-15 μm, e.g., about 4-7 μm. The features may have a width between about 50-450 nm, e.g., about 50-100 nm. Details of dimensions / parameters provided herein, such as height, aspect ratio, thickness, width, and depth, are for illustrative and descriptive purposes only. It is understood that various dimensions / parameters may further be applied or used based on the disclosure described herein.

[0035] III. Etching Process In various embodiments, the etching process is a reactive ion etching process that involves flowing a chemical etchant into a reaction chamber (often via a showerhead), generating a plasma from the etchant, and exposing the substrate to the plasma. The plasma dissociates the etchant compounds into neutral and ionic species (e.g., charged or neutral species such as CF, CF2, CF3, etc.). The plasma is often a capacitively coupled plasma, although other types of plasmas may be used as appropriate. Ions in the plasma are directed toward the substrate, causing the underlying material to be etched away by bombardment or ion-induced chemical reactions.

[0036] Examples of equipment that may be used to perform the etching process include the FLEX™ and VANTEX™ product families of reactive ion etch reactors available from Lam Research Corporation of Fremont, California.

[0037] The methods disclosed herein are particularly useful for etching semiconductor substrates having dielectric materials thereon. As mentioned above, examples of dielectric materials include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, and stacks of any combination of these materials. Specific examples of materials include stoichiometric and non-stoichiometric combinations of SiO2, SiN, SiC, SiCN, and the like. As mentioned above, the underlying material to be etched may include multiple types / layers of material. In certain cases, the underlying material may be provided as alternating layers of SiN and SiO2, or alternating layers of polysilicon and SiO2. The substrate typically has an overlying mask layer that defines where the features are to be etched. In various embodiments herein, the mask layer is an ashing hard mask material, such as amorphous carbon.

[0038] As discussed above, problems with etch selectivity and bow formation typically limit the aspect ratio achievable when etching recessed features. However, the inventors have discovered that high aspect ratio features can be successfully etched with infinite selectivity and without forming substantial bows. For example, the methods herein provide infinite selectivity because they perform selective vertical directional deposition on a mask layer rather than eroding the mask layer during etching as in conventional methods. As a result, the mask layer is protected from erosion, thereby allowing etching of the feature in the underlying material to continue to a desired depth. As used herein, selective vertical directional deposition is a deposition process that selectively deposits material on exposed horizontal surfaces (e.g., the horizontal top surface of the mask layer), where the material accumulates in a vertical direction perpendicular to the horizontal surfaces. The bottom surface of the feature being etched is not considered an exposed horizontal surface.

[0039] The material that builds up on the mask layer during etching is sometimes referred to as the top mask protector, and the layer of such material formed during etching is sometimes referred to as the top mask protector layer, which is formed during the etching process and acts to protect the mask layer and the underlying material below the mask layer.

[0040] The top mask protector layer is different from a protective sidewall layer that may be formed on the sidewall of a feature, for example because the locations of the associated layers are different. For example, a protective sidewall layer is formed on the sidewall of a feature, while a top mask protector layer is formed on a mask layer. Sidewall deposition can be problematic, especially if it is extensive enough to close or narrow the feature and prevent further etching. Advantageously, the selective vertical directional deposition described herein does not deposit on the vertical surfaces (e.g., sidewalls) of the mask or underlying material, thus avoiding the risk of narrowing the feature to an extent that could stop the etching process.

[0041] Furthermore, it should be emphasized that the top mask protector layer forms while the substrate is being actively and continuously etched. In contrast, in many cases where a protective sidewall layer is present, the protective sidewall layer is deposited in a deposition step separate from the etching step (e.g., the deposition and etching steps are not performed simultaneously). Similarly, the top mask protector layer is separate from the mask shrink layer, which may also be deposited in a separate deposition step to deposit additional material on the mask layer. The top mask protector layer also forms part of the conventional CCD that may also build up on the sidewalls during certain etching processes. x F y The sidewall polymer of the system is different from that of the conventional C x F y Sidewall polymer in the system may also build up during etching at the same time that the top mask protector layer is deposited. x F y The sidewall polymer of the system is deposited at a different location compared to the top mask protector layer described herein. x F y The sidewall polymer of the system is deposited on the sidewalls of the features, while the top mask protector layer is deposited only on the top surface of the mask layer. x F y The sidewall polymer of the system is typically deposited on the vertical surfaces, while the top mask protector layer is deposited only on the horizontal top surface of the mask layer. x F y The sidewall polymer of the system is deposited conformally along the sidewall of the feature (eg, along the entire depth of the feature, or at least near the top / opening of the feature).

[0042] Notably, the top mask protector layer is deposited in a selective vertical directional deposition process (which occurs during etching) so that the pattern provided in the mask layer is maintained. In other words, the top mask protector layer is built up vertically on the horizontal top surface of the mask layer in areas where the mask is present. The top mask protector is not built up on vertical surfaces such as sidewalls. In this manner, the deposition process is selective in that it only deposits on the horizontal mask surfaces. In areas where there is no mask (e.g., areas where the mask has been removed as part of a pattern to define where the feature is to be etched), the top mask protector layer is not formed. This selective deposition on the horizontal top surface of the mask layer ensures that the features to be etched remain open and are not closed during etching. Furthermore, the methods described herein do not form significant bow shapes in the etched features.

[0043] 2A-2C show a partially fabricated semiconductor substrate as it undergoes etching, according to embodiments described herein. FIG. 2A shows substrate 200 before etching. Substrate 200 includes an underlying material 202 and a mask 204. In comparison to FIGS. 1A-1C, underlying material 202 is similar to underlying material 102, and mask 204 is similar to mask 104. One difference is that mask 204 may be thinner than mask 104. Because the methods herein provide infinite selectivity, the mask can be made very thin without compromising the etching results. FIG. 2B illustrates substrate 200 during an etching process described herein that is performed to form feature 206. By comparing FIGS. 2A and 2B, it can be seen that mask 204 is not eroded during the etching process. Instead, as illustrated in FIG. 2B, a top mask protector layer 208 is formed over mask 204, thereby preventing mask 204 from eroding during etching. FIG. 2C shows the substrate 200 after etching (or further along in the etching process compared to FIG. 2B). Here, it can be seen that the mask 204 is still the same thickness before etching compared to during etching. As shown in FIG. 2C, the thickness of the top mask protector layer 208 increases as the feature 206 is etched deeper. This process exhibits infinite etch selectivity since the underlying material 202 is etched to a certain depth while the mask 204 is not etched. Here, the selectivity is calculated as: (etch depth of the underlying material) / (etch depth of the mask, which is 0). Since the denominator is 0 and dividing by 0 equals infinity, the etch selectivity is considered to be infinite.

[0044] In some cases, for example, at the very beginning of the etch before the top mask protector layer is fully formed, a small amount of the mask may be consumed during the etch. However, such consumption of the mask is quickly mitigated by the growth of the top mask protector layer on the mask layer, and once the top mask protector layer is formed, there is no further etching of the mask layer below. Furthermore, the amount / thickness of the top mask protector layer that is formed is greater than the small amount / thickness of the original mask that may be removed. As shown in FIG. 2C, the top mask protector layer essentially extends the height of the mask to the top edge of the top mask protector layer. Thus, any small amount of etching of the mask that occurs during the etch should not be considered in the etch selectivity calculation, so long as (a) the mask thickness consumed during the etch is less than 20% of the starting mask thickness, and (b) the final top mask protector layer plus mask thickness after the etch is at least the same as the starting mask thickness. For example, a substrate that starts with a 500 nm thick mask before etching and ends with a 490 nm thick mask with a 10 nm or more thick top mask protector layer after etching is understood to have infinite etch selectivity. In this example, etching of the mask was insignificant (10 nm, i.e., 2%), but such mask consumption was mitigated by the formation of a 10 nm or more thick top mask protector layer that acts as a mask. In this example, the thickness of the mask consumed during etching (10 nm) was equal to the thickness of the top mask protector layer deposited during etching (10 nm), but in most embodiments herein, the thickness of the top mask protector layer deposited during etching is greater than the thickness of the mask consumed during etching, at least in part because of the insignificant etching that occurs, as described above. In such cases, the ending thickness of the material on the underlying material (e.g., the combined thickness of the final mask and top mask protector layer) is greater than the starting thickness of the material on the underlying material (e.g., the thickness of the mask before etching). Such infinite selectivity is highly advantageous for etching high aspect ratio features.

[0045] FIG. 3 illustrates a flow chart describing a method for etching high aspect ratio features according to various embodiments herein. The method begins with operation 301, where a substrate is placed into a reaction chamber. An example of a reaction chamber is described below with reference to FIGS. 4A-4C. The substrate may optionally be mounted to a substrate support, such as an electrostatic chuck. The method continues with operation 303, where a reaction mixture is flowed into the chamber. The reaction mixture may include various reactants, each of which may serve one or more purposes. The reaction mixture includes an etch chemistry, which is discussed further below.

[0046] Next, in operation 305, a plasma is struck in the chamber. The plasma is typically a capacitively coupled plasma. The substrate may be exposed to the plasma. In operation 307, the substrate is etched. The substrate may be etched by ions and / or radicals in the plasma. Then, in operation 309, the plasma is extinguished and the substrate is removed from the chamber. The substrate may be subjected to further processing after removal from the reaction chamber. For example, the substrate may be transferred to an ashing reactor where the top mask protector layer and the mask may be removed from the substrate in an ashing procedure. In operation 311, the reaction chamber may be optionally cleaned. Cleaning may be performed while the substrate is not present. Cleaning may include exposing the chamber surfaces to a cleaning chemistry, which may be provided, for example, in the form of a plasma. In operation 313, it is determined whether there are additional substrates to be processed. If so, the method is repeated from operation 301 on the new substrate. Otherwise, the method is complete.

[0047] The actions depicted in Figure 3 do not necessarily occur in the order depicted: some actions may overlap in time, or some actions may occur earlier or later than those depicted.

[0048] IV. Processing conditions There are many process conditions that can be controlled when carrying out the embodiments described herein. For example, the reaction mixture provided to the reaction chamber may include certain reactants. In various embodiments, the reaction mixture includes (1) hydrogen (H2) and (2) at least one reactant selected from the group consisting of fluoromethane (CH3F), difluoromethane (CH2F2), and trifluoromethane (CHF3). In various embodiments, the reaction mixture may further include one or more non-fluorine halogen sources (e.g., a bromine source such as HBr; a chlorine source such as Cl2, SiCl4; an iodine source such as CF3I). The reaction mixture may also include one or more inert gases (e.g., Ar, Kr, etc.). In some cases, the reaction mixture may include one or more additives selected from the group consisting of nitrogen trifluoride (NF3), octofluoropropane (C3F8), hexafluorobutadiene (C4F6), octafluorocyclobutane (C4F8), sulfur hexafluoride (SF6), tetrafluoromethane (CF4), and methane (CH4). A plasma is formed from the reaction mixture and the resulting species interact with the underlying material being etched (e.g., silicon oxide and silicon nitride, often silicon oxide and polysilicon). This interaction forms a material described herein as a top mask protector layer, which is formed in a selective vertical directional deposition during the etching process. The top mask protector layer may be a graphitic carbon-rich polymer. The carbon-rich polymer of the top mask protector layer may include fluorine and may further include a non-fluorine halogen from a non-fluorine halogen source in the reaction mixture. For example, when the non-fluorine halogen source includes bromine, the upper mask protector layer may include a C x Br y F z If the non-fluorine halogen source includes chlorine, the upper mask protector layer may include a C x Cl y F z When the non-fluorine halogen source includes iodine, the upper mask protector layer may include a C x I y F zThe material may include a material based on the above-mentioned.

[0049] In various embodiments, the flow rates of the various reactants in the reaction mixture may be controlled. In various cases, the flow rate of H2 may be about 10-400 sccm, or may be about 20-400 sccm. In these or other cases, the flow rate of CH3F may be about 0-200 sccm. In these or other cases, the flow rate of CH2F2 may be about 0-200 sccm. In these or other cases, the flow rate of CHF3 may be about 0-200 sccm. The total flow rate of CH3F+CH2F2+CHF3 may be about 20-300 sccm. In some cases, the flow rate of NF3 may be about 0-100 sccm. In these or other cases, the flow rate of SF6 may be about 0-20 sccm. In these or other cases, the flow rate of CF4 may be about 0-100 sccm. In these or other cases, the flow rate of the non-fluorine halogen source may be about 0-100 sccm. In these or other cases, the flow rate of C3F8 may be about 0-50 sccm. In these or other cases, the flow rate of C4F8 may be about 0-50 sccm. In these or other cases, the flow rate of C4F6 may be about 0-50 sccm. The total flow rate of C3F8+C4F8+C4F6 may be about 0-50 sccm. In these or other cases, the flow rate of CH4 may be about 0-100 sccm. Any of the reactants / additives described herein may be flowed at a rate of at least about 1 sccm, or at least about 5 sccm, or at least about 10 sccm. While many of the flow rate ranges described herein include a minimum of 0 sccm, it is understood that these species may or may not be present in the reaction mixture, and if present, may be flowed at a rate of at least about 1 sccm, or at least about 5 sccm, or at least about 10 sccm. These rates are appropriate for a reactor volume of about 50 liters and can be adjusted accordingly.

[0050] The pressure within the reaction chamber may be controlled during etching. In various embodiments, the pressure may be about 10-80 mTorr, or about 15-40 mTorr. The temperature of a substrate holder used to support the substrate within the reaction chamber may be controlled. The temperature of such substrate holder affects the temperature of the substrate during etching, although the actual temperature of the substrate is also affected by additional factors such as plasma conditions. In certain embodiments, the substrate holder may be cooled to a low temperature before and / or during exposure to the plasma. This low temperature may be about 0° C. or lower. In some embodiments, this low temperature may be as low as about −100° C.

[0051] The substrate provided to the reaction chamber has a particular structure including an underlying material (typically including one or more dielectric materials) and an overlying mask, as described above in connection with FIGS. 1A-1C and 2A-2C. In various embodiments, the underlying material may include a DRAM or 3D NAND structure as described above. The methods described herein provide infinite etch selectivity because the mask is not eroded during etching, and therefore the mask can be substantially thinner than conventional masks typically used in these applications. In various embodiments, the mask may have a thickness of about 100-1000 nm. In some cases, the mask is at least about 100 nm thick, or at least about 300 nm thick, or at least about 500 nm thick. In these or other cases, the mask may have a thickness of about 1000 nm or less, or about 500 nm or less, or about 300 nm or less. Such mask thicknesses may be appropriate for etching features having a final depth of at least about 3000 nm, or at least about 15000 nm, and / or an aspect ratio of at least about 20, or at least about 200. Of course, masks having conventional thicknesses (e.g., mask thicknesses >3 μm) may also be used in some cases.

[0052] Plasma generating conditions may be controlled to provide specific conditions at the substrate surface. In various embodiments, the maximum ion energy at the substrate may be relatively high, for example, about 1-10 kV. The maximum ion energy is determined by the applied RF power in combination with the details of the electrode size, electrode arrangement, and chamber geometry. In various cases, a dual frequency RF power is used to generate the plasma. Thus, the RF power may include a first frequency component (e.g., about 400 kHz) and a second frequency component (e.g., about 60 MHz). A different power may be provided at each frequency component. For example, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 3-50 kW or between about 3-15 kW, for example, about 5 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example, between about 0.5-5 kW, for example, about 4 kW. These power levels assume that the RF power is provided to a single 300 mm wafer. The power level can be adjusted linearly based on the substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other embodiments, a three-frequency RF power can be used to generate the plasma. In various embodiments, the applied RF power can be pulsed at a repetition rate of 1-20,000 Hz. The RF power can be pulsed between two non-zero values ​​(e.g., between a higher and a lower power state) or between zero and a non-zero value (e.g., between an off state and an on state). When the RF power is pulsed between two non-zero values, the powers mentioned above relate to a higher power state, and the lower power state can correspond to an RF power of about 600 W or less.

[0053] The timing may vary between different embodiments. Typically, deeper features with higher aspect ratios take longer to etch compared to shallower features with lower aspect ratios. Thus, the duration the substrate is exposed to the plasma may depend on the desired depth of the feature, with deeper features requiring longer plasma exposure durations. In various embodiments, the substrate may be exposed to the plasma for a duration of about 10 to 120 minutes. Similarly, the total etch depth will depend on the particular application. In some cases (e.g., DRAM), the total etch depth may be about 1.5 to 2 μm. In other cases (e.g., VNAND), the total etch depth may be at least about 3 μm, such as at least about 4 μm. In these or other cases, the total etch depth may be about 15 μm or less.

[0054] V. advantage The embodiments described herein provide many advantages. For example, the selective vertical directional deposition of the top mask protector layer provides infinite etch selectivity. This means that the mask is not consumed during etching. Rather, the top mask protector layer is formed on top of the mask, thereby ensuring that the mask remains intact at its full starting thickness during etching.

[0055] In particular, infinite etch selectivity allows for the formation of deeper, high aspect ratio features than was previously achievable with conventional methods. Deeper features can be formed because there is no risk of the mask layer being consumed during etching. The problem of mask consumption and its limitations on the formation of high aspect ratio features is discussed above in connection with Figures 1A-1C. Such problems do not occur with the disclosed methods.

[0056] Another advantage of the infinite etch selectivity achieved by the disclosed embodiments is that the amount of mask material (e.g., mask thickness) can be reduced compared to that required for conventional etching techniques. This reduction in mask material is beneficial because it results in substantial time and cost savings. For example, thinner masks are formed faster than thicker masks, and can likewise be patterned / developed faster. Thus, thinner masks result in increased throughput for the particular processing equipment used to prepare the mask. Additionally, thinner masks cost less to deposit because less material is required. These advantages taken together represent a significant and unexpected improvement over conventional etching techniques.

[0057] VI. Device The methods described herein may be performed by any suitable apparatus. Suitable apparatus includes hardware for performing process operations and a system controller having instructions for controlling the process operations in accordance with the present embodiments. For example, in some embodiments, the hardware may include one or more process stations included in a process tool.

[0058] 4A-4C illustrate an embodiment of an adjustable gap capacitively coupled confined RF plasma reactor 400 that may be used to perform the etching operations described herein. As shown, a vacuum chamber 402 includes a chamber housing 404 that encloses an interior space that houses a lower electrode 406. At the top of the chamber 402, an upper electrode 408 is vertically spaced apart from the lower electrode 406. The planar surfaces of the upper electrode 408 and the lower electrode 406 are substantially parallel and perpendicular to the vertical direction between the electrodes. Preferably, the upper electrode 408 and the lower electrode 406 are circular and coaxial with the vertical axis. The lower surface of the upper electrode 408 faces the upper surface of the lower electrode 406. The spaced apart opposing electrode surfaces define an adjustable gap 410 therebetween. In operation, the lower electrode 406 is RF powered by an RF power source (matched) 420. RF power is supplied to the lower electrode 406 via an RF supply conduit 422, an RF strap 424, and an RF power member 426. A ground shield 436 may surround the RF power member 426 to provide a more uniform RF field to the lower electrode 406. A wafer is inserted through a wafer port 482 and supported in a gap 410 on the lower electrode 406 for processing, and a process gas is supplied to the gap 410 and excited into a plasma state by RF power. The upper electrode 408 may be powered or may be grounded.

[0059] 4A-4C, the bottom electrode 406 is supported on a bottom electrode support plate 416. An insulator ring 414 interposed between the bottom electrode 406 and the bottom electrode support plate 416 insulates the bottom electrode 406 from the support plate 416.

[0060] RF bias housing 430 supports lower electrode 406 on RF bias housing bowl 432. Bowl 432 is connected by arm 434 of RF bias housing 430 to conduit support plate 438 through an opening in chamber wall plate 418. In a preferred embodiment, RF bias housing bowl 432 and RF bias housing arm 434 are integrally formed as one component, however, arm 434 and bowl 432 could also be two separate components bolted or joined together.

[0061] The RF bias housing arm 434 includes one or more hollow passages for passing RF power and equipment, such as gas coolant, liquid coolant, RF energy, cables for lift pin control, electrical monitoring and operating signals, from the exterior of the vacuum chamber 402 to the interior of the vacuum chamber 402 in the space behind the lower electrode 406. The RF supply conduit 422 is insulated from the RF bias housing arm 434, which provides a return path for RF power to the RF power source 420. Equipment conduits 440 provide passage for equipment components. The gap 410 is preferably surrounded by a containment ring assembly or shroud (not shown). The interior of the vacuum chamber 402 is maintained at low pressure by connection to a vacuum pump through a vacuum portal 480.

[0062] The conduit support plate 438 is attached to an actuation mechanism 442. The actuation mechanism 442, such as a servomechanical motor, stepper motor, or the like, is attached to a vertical linear bearing 444 by a screw gear 446, such as a ball screw, and a motor for rotating the ball screw. During an operation to adjust the size of the gap 410, the actuation mechanism 442 moves along the vertical linear bearing 444. FIG. 4A illustrates an arrangement in which the actuation mechanism 442 is in a high position relative to the linear bearing 444, resulting in a small gap 410a. FIG. 4B illustrates an arrangement when the actuation mechanism 442 is in an intermediate position relative to the linear bearing 444. As shown, the lower electrode 406, RF bias housing 430, conduit support plate 438, and RF power supply 420 have all been moved low relative to the chamber housing 404 and upper electrode 408, resulting in a medium-sized gap 410b.

[0063] 4C illustrates a large gap 410c when the actuation mechanism 442 is in a low position relative to the linear bearing. Preferably, the upper electrode 408 and the lower electrode 406 remain coaxial during the gap adjustment, and the facing surfaces of the upper and lower electrodes across the gap remain parallel.

[0064] This embodiment allows for adjusting the gap 410 between the bottom electrode 406 and the top electrode 408 in the CCP chamber 402 during multi-step process recipes (such as BARC, HARC, and STRIP) to maintain uniform etching across large diameter substrates such as, for example, 300 mm wafers or flat panel displays. In particular, the chamber relates to a mechanical arrangement that allows linear motion to provide an adjustable gap between the bottom electrode 406 and the top electrode 408.

[0065] 4A illustrates a laterally deflected bellows 450 sealed at its proximal end to a conduit support plate 438 and at its distal end to a stepped flange 428 of a chamber wall plate 418. The inner diameter of the stepped flange defines an opening 412 in the chamber wall plate 418 through which an RF bias housing arm 434 passes. The distal end of the bellows 450 is secured by a clamp ring 452.

[0066] The laterally deflected bellows 450 provides a vacuum seal while allowing vertical movement of the RF bias housing 430, conduit support plate 438, and actuation mechanism 442. The RF bias housing 430, conduit support plate 438, and actuation mechanism 442 may also be referred to as a cantilever assembly. Preferably, the RF power supply 420 moves with the cantilever assembly and may be attached to the conduit support plate 438. FIG. 4B shows the bellows 450 in a neutral position when the cantilever assembly is in an intermediate position. FIG. 4C shows the laterally deflected bellows 450 when the cantilever assembly is in a low position.

[0067] A labyrinth seal 448 provides a particle barrier between the bellows 450 and the interior of the plasma processing chamber housing 404. A fixed shield 456 is fixedly attached to the inner wall of the chamber housing 404 at the chamber wall plate 418 to provide a labyrinth groove 460 (slot) within which a movable shield plate 458 moves vertically to accommodate vertical movement of the cantilever assembly. An outer portion of the movable shield plate 458 remains within the slot at all vertical positions of the lower electrode 406.

[0068] In the illustrated embodiment, the labyrinth seal 448 includes a fixed shield 456 attached to an inner surface of the chamber wall plate 418 at the periphery of an opening 412 in the chamber wall plate 418 that defines a labyrinth groove 460. A movable shield plate 458 is attached to and extends radially from an RF bias housing arm 434 that passes through the opening 412 in the chamber wall plate 418. The movable shield plate 458 extends into the labyrinth groove 460 while being spaced a first gap from the fixed shield 456 and a second gap from the inner surface of the chamber wall plate 418 to allow vertical movement of the cantilever assembly. The labyrinth seal 448 prevents movement of particles that are stripped from the bellows 450 into the vacuum chamber interior 405 and prevents migration of radicals from the process gas plasma to the bellows 450 (where they may form deposits that are subsequently stripped).

[0069] FIG 4A shows the movable shield plate 458 in a high position within the labyrinth groove 460 above the RF bias housing arm 434 when the cantilever assembly is in a high position (small gap 410a). FIG 4C shows the movable shield plate 458 in a low position within the labyrinth groove 460 above the RF bias housing arm 434 when the cantilever assembly is in a low position (large gap 410c). FIG 4B shows the movable shield plate 458 in a neutral or intermediate position within the labyrinth groove 460 when the cantilever assembly is in an intermediate position (medium gap 410b). Although the labyrinth seal 448 is shown as symmetrical with respect to the RF bias housing arm 434, in other embodiments the labyrinth seal 448 may be asymmetrical with respect to the RF bias housing arm 434.

[0070] In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" can refer to a silicon wafer during any of the many stages of integrated circuit fabrication on a silicon wafer. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the embodiments are implemented on a wafer. However, the embodiments are not so limited. Workpieces may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0071] VII. System Controller In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics, sometimes referred to as a "controller," may control various components or subparts of one or more systems. Depending on the processing requirements and / or type of system, the controller may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, liquid delivery settings, position and motion settings, wafer loading and unloading to and from the tool, and wafer loading and unloading to and from other transfer tools and / or load locks connected or interlocked with the particular system.

[0072] Broadly speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0073] In some implementations, the controller may be part of or connected to a computer that is integrated into, connected to, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a "cloud" or fab host computer system, which allows remote access of wafer processing. The computer may allow remote access to the system to monitor the current progress of a manufacturing operation, to study the history of past manufacturing operations, to study trends or performance criteria of multiple manufacturing operations, to change parameters of a current process, to set processing steps and track a current process, or to start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as discussed above, the controller may be distributed, such as by including one or more individual controllers networked together and operating toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such purposes is one or more integrated circuits on the chamber that are located remotely (such as at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that cooperatively control the processes in the chamber.

[0074] Examples of systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an ashing chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0075] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from containers of wafers to and from tool locations and / or load ports within a semiconductor manufacturing factory.

[0076] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, such tools / processes are used or performed together in a common manufacturing facility.

[0077] Lithographic patterning of a film typically includes some or all of the following steps, each of which is performed using a number of possible tools: (1) applying a photoresist onto a workpiece (e.g., a substrate having a silicon nitride film formed thereon) using a spin-on or spray-on tool, (2) curing the photoresist using a hotplate or furnace or other suitable curing tool, (3) exposing the photoresist to visible, or ultraviolet, or x-ray light using a tool such as a wafer stepper, (4) developing the resist to selectively remove and thereby pattern the resist using a tool such as a wet bench or spray developer, (5) transferring the resist pattern to an underlying film or workpiece by using a dry etch or plasma-assisted etch tool, and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashing hardmask layer (such as an amorphous carbon layer) and another suitable hardmask (such as an antireflective layer) may be deposited prior to applying the photoresist.

[0078] It is understood that the configurations and / or approaches described herein are exemplary in nature and are subject to numerous variations, and therefore the specific embodiments or examples should not be considered in a limiting sense. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, the various illustrated acts may be performed in the illustrated order, in other orders, in parallel, or in some cases omitted. Similarly, the order of the processes described above may be altered.

[0079] The subject matter of the present disclosure includes all novel and non-obvious combinations and subcombinations of the various processes, systems, and configurations, as well as other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

[0080] VIII. experiment 5A-5C together illustrate both the shortcomings of conventional etching techniques and the new and surprising results obtained through the disclosed method. These figures should be considered and compared with one another. FIG. 5A shows a substrate before etching. The substrate includes an underlying material 502 and a mask 504 patterned on the underlying material 502. FIG. 5B shows the substrate after etching by a conventional method. FIG. 5C shows the substrate after etching by a method described herein. The dimensions of the different substrates (e.g., the thickness of the underlying material 502, the thickness of the mask 504, the substrate diameter, etc.) are the same before processing, so that the results can be easily compared. Furthermore, the results are all shown to the same scale, further facilitating comparison. A horizontal line 520 extends throughout all of FIGS. 5A-5C. For visual clarity, FIG. 5A shows the line 520 in black, while FIGS. 5B and 5C show the line 520 in white. The line 520 represents the starting height of the mask 504 before etching.

[0081] In Figure 5B, arrow 521 indicates the thickness of mask 504 consumed when etched according to the prior art. In this case, mask 504 was significantly eroded during etching, with more than 25% of the mask material being lost.

[0082] In Figure 5C, arrow 522 indicates the thickness of the top mask protector layer 508 deposited over the mask 504 during etching when implementing the embodiments described herein. Here, it can be seen that the mask 504 was not consumed during etching. Instead, the deposited top mask protector layer 508 builds up during etching, thereby protecting the underlying mask 504 from erosion. As the mask was not consumed during etching, the etch selectivity is infinite.

[0083] The results shown in FIG. 5C were surprising and unexpected. In previous etching techniques, the mask is always consumed during etching. This is true even when some deposition is occurring during etching (e.g., fluorocarbon-based polymers on the sidewalls of the recessed features). Previously, any such deposition was insufficient to cause the vertical directional deposition shown in FIG. 5C. In such previous cases, deposition during etching would have narrowed the recessed features, causing them to clog with material and close. Such clogging is not seen in the results of FIG. 5C. Moreover, the etched features shown in FIG. 5C are very straight, without any substantial bowing.

[0084] Moreover, this result is unexpected since deposition during etching was selective and limited to the horizontal mask surfaces. As discussed above, conventional etching techniques often result in deposition of material on the sidewalls of features. Such sidewall deposition was not observed in the results of FIG. 5C.

[0085] IX. conclusion Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Thus, the present embodiments are considered to be illustrative and not restrictive, and the present embodiments are not limited to the details given herein.

Claims

1. 1. A method of processing a substrate, the substrate comprising an underlying material and a mask, the underlying material comprising at least one layer of silicon oxide, the mask disposed over the underlying material and patterned to define locations where features are to be etched into the underlying material, the method comprising: a. generating a plasma in a reaction chamber; b. exposing the substrate to the plasma in the reaction chamber; (i) etching the feature into the underlying material; (ii) depositing an upper mask protector layer on the mask, the upper mask protector layer being formed on the mask by selective vertical directional deposition; and The method includes:

2. 2. The method of claim 1 , The method of claim 1, wherein the top mask protector layer protects the mask from erosion during etching such that the etch selectivity with respect to the underlying material is infinite compared to the mask.

3. A method of processing a substrate, the substrate comprising an underlying material and a mask, the underlying material comprising at least one layer of silicon oxide, the mask disposed over the underlying material and patterned to define locations where features are to be etched into the underlying material, the method comprising: a. generating a plasma in a reaction chamber; b. exposing the substrate to the plasma in the reaction chamber; (i) etching the feature into the underlying material; (ii) depositing an upper mask protector layer on the mask, the upper mask protector layer being formed on the mask by selective vertical directional deposition; and Including, generating the plasma in the reaction chamber includes flowing a reaction mixture into the reaction chamber and generating the plasma from the reaction mixture; The reaction mixture is: (1) hydrogen (H 2 ) and (2) fluoromethane (CH 3 F), difluoromethane (CH 2 F 2 ), and trifluoromethane (CHF 3 and at least one reactant selected from the group consisting of:

4. 4. The method of claim 3, The method, wherein the reaction mixture further comprises a non-fluorine halogen source.

5. 5. The method of claim 4, The non-fluorine halogen source is HBr, Cl 2 , SiCl 4 , and C.F. 3 The method of claim 1, further comprising at least one reactant selected from the group consisting of I.

6. A method of processing a substrate, the substrate comprising an underlying material and a mask, the underlying material comprising at least one layer of silicon oxide, the mask disposed over the underlying material and patterned to define locations where features are to be etched into the underlying material, the method comprising: a. generating a plasma in a reaction chamber; b. exposing the substrate to the plasma in the reaction chamber; (i) etching the feature into the underlying material; (ii) depositing an upper mask protector layer on the mask, the upper mask protector layer being formed on the mask by selective vertical directional deposition; and Including, generating the plasma in the reaction chamber includes flowing a reaction mixture into the reaction chamber and generating the plasma from the reaction mixture; The reaction mixture comprises: (1) hydrogen (H2); and (2) at least one reactant selected from the group consisting of fluoromethane (CH3F), difluoromethane (CH2F2), and trifluoromethane (CHF3); The reaction mixture contains nitrogen trifluoride (NF 3 ), hexafluorobutadiene (C 4 F 6 ), octofluoropropane (C 3 F 8 ), octafluorocyclobutane (C 4 F 8 ), sulfur hexafluoride (SF 6 ), tetrafluoromethane (CF 4 ), and methane (CH 4 (c) a mixture of a tertiary ingredient and a tertiary ingredient selected from the group consisting of:

7. 4. The method of claim 3, (i) the pressure in the reaction chamber is maintained at 10-80 mT during (b); (ii) the substrate is supported on a substrate holder that is maintained at a temperature between 0° C. and −100° C. during (b); (iii) the ion energy is 1-10 kV at the surface of the substrate during (b); (iv) the RF energy used to generate the plasma is pulsed during (b) at a power level of 3-50 kW; and (v) the plasma is a capacitively coupled plasma; method.

8. The method of claim 1 , wherein the plasma is a capacitively coupled plasma.

9. 2. The method of claim 1 , The method, wherein the mask has a thickness of 3500 nm or less before the top mask protector layer is formed over the mask.

10. 10. The method of claim 9, The feature etched in (b) has a depth-to-width aspect ratio of 20 or greater and a final depth of 100 nm or greater.

11. 2. The method of claim 1 , The method, wherein the features etched in (b) include at least one of a recessed cylinder and a recessed trench.

12. 2. The method of claim 1 , The method of claim 1, wherein the selective vertical directional deposition results in the formation of the top mask protector layer in areas where the mask is present without forming the top mask protector layer over the locations where the features will be etched into the underlying material.

13. 2. The method of claim 1 , The method of claim 1, wherein the underlayer material comprises the at least one layer of silicon oxide and at least one layer of silicon nitride.

14. 2. The method of claim 1, wherein the underlying material comprises alternating layers of silicon oxide and polysilicon, and the at least one layer of silicon oxide is one of the alternating layers of silicon oxide.

15. 1. An apparatus for processing a substrate, comprising: The apparatus comprises: a. a reaction chamber; b. a substrate support disposed within the reaction chamber; c. a plasma generating device configured to generate a plasma within the reaction chamber; d. one or more inlets to the reaction chamber; e. a controller having at least one processor; Including, The controller: i. the substrate is disposed in the reaction chamber, the substrate including an underlying material and a mask disposed on the underlying material, the underlying material including a dielectric material; ii. the plasma is generated in the reaction chamber; iii. exposing the substrate to the plasma in the reaction chamber; (i) etching features into the underlying material on the substrate; (ii) depositing a top mask protector layer over the mask, the top mask protector layer being formed over the mask by selective vertical directional deposition; The apparatus is configured to:

16. 16. The apparatus of claim 15, The apparatus, wherein the plasma generation device is configured to generate a capacitively coupled plasma.

17. 16. The apparatus of claim 15, the controller is configured to cause (e)(ii) to occur by flowing the reaction mixture into the reaction chamber such that the plasma is generated from the reaction mixture; The reaction mixture is: (1) hydrogen (H 2 ) and (2) fluoromethane (CH 3 F), difluoromethane (CH 2 F 2 ), and trifluoromethane (CHF 3 and at least one reactant selected from the group consisting of:

18. 18. The apparatus of claim 17, The reaction mixture further comprises a non-fluorine halogen source.

19. 20. The apparatus of claim 18, The non-fluorine halogen source is HBr, Cl 2 , SiCl 4 , and C.F. 3 An apparatus comprising at least one reactant selected from the group consisting of I.

20. 20. The apparatus of claim 19, The reaction mixture contains nitrogen trifluoride (NF 3 ), hexafluorobutadiene (C 4 F 6 ), octofluoropropane (C 3 F 8 ), octafluorocyclobutane (C 4 F 8 ), sulfur hexafluoride (SF 6 ), tetrafluoromethane (CF 4 ), and methane (CH 4 The apparatus further comprises one or more additives selected from the group consisting of:

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