Power supply device and image forming apparatus

Abstract

To reduce component cost and reduce the substrate occupied area of an entire power supply circuit.SOLUTION: A power supply device comprises booster circuits each including an MOSFET Q101, a transformer T101, a diode D101 and a comparator CP101, and a CPU 200 which outputs a PWM signal corresponding to a target voltage to the comparator CP101. The power supply device includes at least two booster circuits, and a plurality of booster circuits (100DEV, 100TRP and 100PR) are capable of outputting different high voltages (development output, transfer output and charge output). The CPU 200 outputs a common driving signal (CommCLK) to the plurality of booster circuits (100DEV, 100TRP and 100PR).SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a power supply device and an image forming apparatus, and more particularly to the generation of various high voltages required in, for example, an electrophotographic image forming apparatus, which includes, for example, a copying machine, a laser printer, an LED (Light Emitting Diode) printer, and an electrophotographic facsimile machine. [Background technology]

[0002] Conventionally, electrophotographic image forming apparatuses that copy images onto recording paper using electrophotographic technology have been in widespread use. In this image forming apparatus, a photosensitive drum is uniformly charged to a positive or negative high potential, and light such as a laser is projected onto the photosensitive drum according to the image to be copied, creating a latent image on the photosensitive drum by electrostatic charge. Then, a developer such as toner is blown onto the part where the latent image is created by electrostatic force, and the developer image is formed by developing it on the photosensitive drum. Next, a recording paper is placed on the formed developer image, and a charge of the opposite polarity to the charge held by the developer is applied from the back side of the recording paper, and the developer is adsorbed to the surface of the recording paper by electrostatic force and transferred. After that, the transferred developer is fixed onto the recording paper by applying heat and pressure to the recording paper. In this way, in the electrophotographic method, the developer is moved using electrostatic force in each process, so various polarities and various high voltages are required. There are various types of high-voltage power supplies that can be applied to such voltages, but Patent Document 1 is an example that describes a circuit that can be constructed at low cost with a small number of parts in particular. Furthermore, a technique for reducing the ripple of the output voltage by using the circuit of Patent Document 1 and improving the control method has been disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 09-191644 [Patent Document 2] JP 2019-213409 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, as shown in Figure 5, for example, the conventional method requires the use of two CPU output ports (input 1 and input 2). In Figure 5, one high-voltage power supply circuit is shown. In electrophotographic image forming devices, at least three high-voltage power supplies are generally required. The three refer to the three types: transfer, charging, and development. In other words, the high-voltage circuit as a whole requires input 1 and input 2, so at least six CPU ports in total are used. Figure 6 shows a block diagram of this situation. Also, when driving Q101 directly from the CPU port as shown in Figure 5, Q101 must be able to be driven at 3.3V because the power supply voltage of the CPU is generally 3.3V. However, as the supply is decreasing year by year, using "low-voltage drive, high-voltage FET" poses issues regarding supply stability and future prospects, and it is being adopted less and less. Instead, 4V drive, high-voltage FET is adopted. This means that the ON resistance (ON resistance) between the drain and source is guaranteed at a gate-source voltage of 4V or more. Therefore, to drive this FET from a CPU that operates at 3.3V, it is necessary to add a circuit between input 1 and Q101 that converts the voltage level from 3.3V to 4V or more. An example of a voltage level conversion circuit is shown in Figure 7. Figure 7 is a comparison with Figure 5 in which a voltage level conversion circuit has been added between input 1 and Q101. The newly added components are R201 to R203, Q201, and ZD201. These five components are added for each high voltage power supply, so if there are three types of high voltage power supplies for charging, transfer, and development, a total of 15 components will be added. This is not desirable because it increases costs and occupies a large area on the board.

[0005] The present invention has been made under these circumstances, and has an object to reduce component costs and the area occupied by the entire power supply circuit on the board. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, the present invention has the following configuration.

[0007] (1) A power supply device comprising: a boost circuit having a generating means having a switching element and a transformer that are turned on or off by a drive signal and that generates a high voltage; a rectifying means for rectifying the high voltage generated by the generating means; a detecting means for detecting the output of the high voltage rectified by the rectifying means; a comparing means for comparing a detection result by the detecting means with a target voltage; and a control means for controlling the drive signal to be turned on or off so that the high voltage becomes a constant output voltage based on the comparison result by the comparing means; and an output means for outputting the drive signal and outputting a PWM signal corresponding to the target voltage to the comparing means, wherein the power supply device has at least two boost circuits, each of the multiple boost circuits is capable of outputting a different high voltage, and the output means outputs the drive signal common to the multiple boost circuits.

[0008] (2) An image forming apparatus comprising a charging means for charging a photosensitive member, a developing means for developing a latent image on the photosensitive member with a developer, a transfer means for transferring the developer image to a recording material, and the power supply device described in (1), wherein the power supply device generates a charging voltage to be supplied to the charging means, a developing voltage to be supplied to the developing means, and a transfer voltage to be supplied to the transfer means. Effect of the Invention

[0009] According to the present invention, it is possible to reduce component costs and the area occupied by the entire power supply circuit on the board. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is an explanatory diagram of an image forming apparatus according to first to third embodiments; [Diagram 2] Block diagram showing voltage control in the first embodiment [Diagram 3] Block diagram showing voltage control in the second embodiment [Figure 4]FIG. 11 is a sequence diagram showing an image forming operation according to the third embodiment. [Diagram 5] FIG. 1 shows a conventional power supply device. [Figure 6] Block diagram showing voltage control in a conventional example [Figure 7] FIG. 1 shows a conventional power supply device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [General power supply circuit (example 1)] 5 is a circuit diagram of a high-voltage power supply as a power supply device using two output ports of a CPU (Central Processing Unit). The boost circuit 100 includes resistors R101-R107, capacitors C101-C103, and diodes D101 and D102. The boost circuit 100 also includes a metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) Q101, a high voltage transformer (hereinafter referred to as transformer) T101, and a comparator CP101. The boost circuit 100 outputs a negative high voltage from output 1. The generating means includes a MOSFET Q101 and a transformer T101, which are switching elements. The diode D101 functions as a rectifying means.

[0012] Power supply V1 is a power supply that generates the primary current of transformer T101, and is a DC power supply of a relatively large voltage such as 24 V. Power supply V2 is a power supply for the control circuit, and is a relatively small, high-precision DC power supply of 3.3 V or 5 V. A pulse signal, which is a drive signal for driving MOSFET Q101 (turning it on or off), is input to input 1 from a control device such as a CPU. A PWM signal that determines the target voltage of output 1 is also input to input 2 from the control device.

[0013] [Power supply operation] The operation of the boost circuit 100 will be described below. First, a pulse signal of, for example, 16 kHz and a duty of about 10% is input from the control device to input 1. Then, MOSFET Q101 turns ON / OFF according to the input pulse signal, and an excitation current flows through transformer T101. Transformer T101 is a transformer with a primary winding and a secondary winding, and the winding ratio is set to 84:2700 for boosting. Furthermore, the primary winding of transformer T101 has a center tap, and when MOSFET Q101 is ON, the current that flows through the primary winding flows in the order of V1 → R107 → T101 → Q101. On the other hand, when MOSFET Q101 is OFF, the regenerative current flows in the order of T101 → C103 → D102. The secondary side of transformer T101 operates as follows: when MOSFET Q101 is on, diode D101 is on and current flows in the order T101 → GND → C102 → D101, and a negative high voltage is output to Output 1. If the direction of diode D101 is reversed, a positive high voltage is output to Output 1.

[0014] Next, feedback control will be explained. Output 1 is input to the non-inverting input terminal of comparator CP101 via resistor R105. As MOSFET Q101 is repeatedly turned on and off and the negative voltage appearing at output 1 increases (as an absolute value), the voltage applied to the non-inverting input terminal of comparator CP101 gradually decreases. The PWM signal input from input 2 is integrated by resistor R103 and capacitor C101, becoming a DC voltage according to the duty of the PWM signal and being added to the inverting input terminal of comparator CP101. The PWM signal from input 2 is the target voltage (target value) for the output voltage from output 1, and the low duty ratio is proportional to the output voltage of output 1.

[0015] Specifically, when the negative voltage of output 1 increases (as an absolute value) and the voltage applied to the non-inverting input terminal of comparator CP101 falls below the voltage applied to the inverting terminal, the output of comparator CP101 goes low. This makes the gate voltage of MOSFET Q101 zero. At this time, even if a pulse signal is input from input 1, current is drawn by comparator CP101, so MOSFET Q101 remains OFF while the output voltage of output 1 exceeds the target value. After a while, the voltage of output 1 decreases (as an absolute value), and the potential relationship between the non-inverting input terminal and the inverting input terminal of comparator CP101 is reversed. As a result, MOSFET Q101 resumes oscillation, and the output voltage from output 1 (its absolute value) begins to increase again. By repeating this operation, the voltage of output 1 is maintained at the target voltage. Comparator CP101 functions as a detection means for detecting high-voltage output 1, a comparison means for comparing output 1 (detection result) with a target voltage, and a control means for controlling the pulse signal to be turned on or off based on the comparison result so that output 1 becomes a constant output voltage.

[0016] (General Power Supply Issues) Next, the problem of having at least two of the above-mentioned boost circuits 100 will be described. The boost circuit 100 in FIG. 5 is one high-voltage power supply circuit. In an electrophotographic image forming apparatus, at least three high-voltage power supplies are generally required. The three refer to the three types: transfer, charging, and development. In other words, the high-voltage power supply circuit as a whole requires input 1 and input 2, respectively, so at least six CPU ports (inputs) are used in total. A block diagram of this is shown in FIG. 6.

[0017] In FIG. 6, the CPU 200 corresponds to the control device described above. The CPU 200 functions as an output means for outputting a drive signal to the input 1 of the boost circuit 100 described above and outputting a PWM signal according to a target voltage to the input 2. The development power supply 100DEV, the transfer power supply 100TRP, and the charging power supply 100PR are all configured similarly to the boost circuit 100 described in FIG. 5. The development power supply 100DEV outputs a development output (development voltage). The transfer power supply 100TRP outputs a transfer output (transfer voltage). The charging power supply 100PR outputs a charging output (charging voltage). Each of the multiple boost circuits 100 (100DEV, 100TRP, 100PR) can output a different high voltage. In addition, a pulse signal and a PWM signal are input from the CPU 200 via the input 1 and the input 2 to each of them. Specifically, the CPU 200 outputs a pulse signal from DEVCLK to the input 1 of the development power supply 100DEV, and outputs a PWM signal from DEVPWM to the input 2. The CPU 200 outputs a pulse signal from TRPCLK to input 1 of the transfer power supply 100TRP, and outputs a PWM signal from TRPPWM to input 2. The CPU 200 outputs a pulse signal from PRCLK to input 1 of the charging power supply 100PR, and outputs a PWM signal from PRPWM to input 2.

[0018] Also, when the MOSFET Q101 is driven directly from the port of the CPU 200 as shown in Figure 5, the power supply voltage of the CPU 200 is generally 3.3V, so the MOSFET Q101 must be capable of being driven at 3.3V. In the past, there were many "low-voltage-driven, high-voltage FETs" on the market that could be driven at 3.3V and had a drain-source voltage of about 150V. However, the production and distribution of such FETs in the market began to decrease around 2010, and there are now almost no options. Therefore, in the 2020s, the use of "low-voltage-driven, high-voltage FETs" poses issues regarding the stability and future prospects of supply, and they are being adopted less and less. Instead, 4V-driven, high-voltage FETs are being adopted for FETs with a drain-source voltage of over 100V. However, these are FETs that are driven at 4V, or more specifically, FETs whose drain-source ON resistance is guaranteed at a gate-source voltage of 4V or more. Therefore, to drive this FET from CPU 200 operating at 3.3V (first voltage) as shown in Fig. 5, it is necessary to do the following: A conversion circuit that converts the voltage level from 3.3V to 4V or more (a second voltage higher than the first voltage) must be added between input 1 and MOSFET Q101.

[0019] [Conversion circuit] FIG. 7 shows a boost circuit 120 including a conversion circuit 130 that converts the voltage level of the input 1. The boost circuit 120 in FIG. 7 is obtained by adding a conversion circuit 130 that converts the voltage level between the input 1 and a MOSFET Q101 to the boost circuit 100 in FIG. 5. The same components as those in FIG. 5 are given the same reference numerals and will not be described. The conversion circuit 130 has resistors R201 to R203, a transistor Q201, and a Zener diode ZD201. These five components are added for each high-voltage power supply, so that in the case of three types of high-voltage power supplies for charging, transferring, and developing as shown in FIG. 6, a total of 15 components are added. This is not preferable because it increases the cost and occupies a large area on the board.

[0020] [Output voltage ripple] A method for reducing the ripple of the output voltage will be described using the boost circuit 100 of FIG. 5. Here, the reason why the ripple of the output voltage becomes large is that the pulse signal applied to the input 1 is significantly thinned out by the comparator CP101, resulting in an intermittent oscillation state. For this reason, in the conventional boost circuit 100, the frequency of the clock signal applied to the input 1 is changed according to the target voltage applied to the input 2. This reduces the amount of pulse signals thinned out by the comparator CP101, thereby lowering the ripple of the output voltage. For example, when the target voltage of the output voltage is low, the frequency of the pulse signal applied to the input 1 is lowered so that the comparator CP101 hardly thins out the signal, thereby preventing intermittent oscillation and suppressing the ripple of the output voltage. Conversely, when the target voltage of the output voltage is high, the frequency of the clock signal applied to the input 1 is increased to a level where the signal is not thinned out by the comparator CP101, thereby making it possible to reduce the ripple of the output voltage even in the high voltage region. EXAMPLES

[0021] The present invention is applied to an image forming apparatus, and therefore a laser printer (hereinafter referred to as an image forming apparatus), which is one type of image forming apparatus, will be described first.

[0022] <Configuration of Image Forming Apparatus> Fig. 1 shows a cross-sectional view of a monochrome laser printer (hereinafter referred to as printer) 300 as an image forming apparatus. Printer 300 includes a paper feed section 101, a laser scanner 102, a toner tank 103, a developing roller 104 as a developing means, a photosensitive drum 105 as a photosensitive body, a transfer roller 106 as a transferring means, a charging roller 107 as a charging means, and a waste toner tank 108. Printer 300 also includes a fixing roller 109, a pressure roller 110, a discharge section 111, and a conveying path 112. Note that in Fig. 1, a laser optical path 113 is also shown by a dashed line.

[0023] A paper feeder 101 stores paper, which is a recording material to be printed, and the paper is stacked inside. A toner tank 103 contains magnetic toner. A blade 114 regulates the amount of toner on a developing roller 104.

[0024] <Explanation of the operation of the image forming apparatus> Next, the operation of the printer 300 will be described. When the printer 300 receives a print job, it starts the operation of each roller and the laser scanner 102. The charging roller 107 receives power from the circuit board, is charged with a negative high voltage, and charges the surface of the photosensitive drum 105. When an image signal is sent from a personal computer or the like, the laser scanner 102 scans the surface of the photosensitive drum 105 in the longitudinal direction (main scanning direction) while blinking the laser according to the pixels. The charge of the photosensitive drum 105 disappears at the part where the laser hits, and a latent image is formed. A magnet is contained inside the developing roller 104. When a negative high voltage is supplied to the developing roller 104, the developing roller 104 attracts the magnetic toner in the toner tank 103 by magnetic force, and moves the toner (developer) to the photosensitive drum 105 according to the latent image by electrostatic force, forming a toner image (developer image). The developing blade 114 is provided with a potential difference of several hundred volts with respect to the developing roller 104, and the toner on the developing roller 104 is uniformly coated by electrostatic force in addition to physical regulation by the blade 114 body.

[0025] Meanwhile, paper fed from paper feed unit 101 passes through transport path 112 and is sandwiched between transfer roller 106 and photosensitive drum 105. At this time, a positive high voltage is applied to transfer roller 106, and the toner on photosensitive drum 105 (photosensitive body) is attracted to transfer roller 106 and transferred to the paper. The paper with the toner on it then moves toward discharge unit 111 and is sandwiched between fixing roller 109 and pressure roller 110. Here, the paper is heated to several hundred degrees by fixing roller 109 and pressed by pressure roller 110, and the toner on the paper is fixed only by electrostatic force. After the fixing process is completed, the paper is discharged to discharge unit 111 and stacked.

[0026] Meanwhile, some toner remains on the surface of the photosensitive drum 105 even after transfer to the paper. Ideally, all of the toner should be transferred to the paper, but in reality, the amount of charge that the toner has is not uniform, so some toner remains on the photosensitive drum 105 even after transfer. The waste toner tank 108 is where the remaining toner is scraped off and collected by a blade that is in contact with the photosensitive drum 105. This removes the toner from the photosensitive drum 105, which is then charged again by the charging roller 107, and the next latent image is drawn by the scanner 102. The printer 300 forms an image by repeating the above operations.

[0027] <Description of the circuit of the present invention> Thus, the printer 300 requires various high voltages, and has a built-in high voltage generation circuit for that purpose. The circuit is the same as the system in FIG. 5 described above, so FIG. 5 is used. FIG. 2 shows a block diagram of the entire high voltage circuit (charging, transfer, development). In the block diagram of FIG. 2, the same components as those in FIG. 6 are given the same symbols. DEVPWM, TRPPWM, and PRPWM correspond to the PWM signals for development, transfer, and charging, respectively, and correspond to input 2 in FIG. 5 for each voltage. The target values ​​of the output voltages for each voltage are input to these as PWM signals. Although the multiple boost circuits 100 in the first embodiment can each output a different high voltage, the CPU 200 outputs a common drive signal (CommCLK, described later) to the multiple boost circuits 100.

[0028] In Fig. 2, DEVCLK, TRPCLK, and PRCLK in Fig. 6 are commonized and unified as CommCLK. The same components as in Fig. 6 are given the same reference numerals and their explanations are omitted. Note that DEVCLK was a pulse signal that drives the MOSFET Q101 of the development power supply 100DEV, and TRPCLK was a pulse signal that drives the MOSFET Q101 of the transfer power supply 100TRP. Also, PRCLK was a pulse signal that drives the MOSFET Q101 of the charging power supply 100PR.

[0029] Furthermore, instead of assembling the part that converts the voltage level from 3.3V to 5.4V with discrete components as shown in Figure 7, logic ICs (buffers or inverters) 151, 152, and 153 are used as the conversion means. Since a logic IC usually has multiple logic elements in one IC, replacing each voltage level conversion with one logic IC takes up less space on the board than performing voltage level conversion for each voltage in separate locations with discrete components. In other words, the three elements can be combined into one logic IC.

[0030] Also, conventionally, when charging, transferring, and developing were driven or stopped, DEVCLK, TRPCLK, and PRCLK in Fig. 6 were oscillated or stopped individually, but in the configuration shown in Fig. 2, they are unified into CommCLK and cannot be controlled individually. Therefore, for example, if you want to stop the output of the developing voltage, you can set DEVPWM, which is the target value of the developing voltage (developing output), to zero, and the output voltage will be set to zero through feedback control. The same applies to charging and transferring.

[0031] By adopting such a configuration, the number of ports used by the CPU 200 can be reduced, and the circuitry that performs voltage level conversion can also reduce the board area it occupies. In Fig. 2, the six ports required in Fig. 6 have been reduced to four ports. There are two types of logic ICs: TTL and CMOS. Generally, TTL logic ICs can drive larger currents and have faster operating speeds. However, some recent CMOS logic ICs have faster operating speeds than TTL logic ICs by adopting fine processes, so CMOS logic ICs may be used if attention is paid to their characteristics.

[0032] As described above, according to the first embodiment, it is possible to reduce the cost of components and the area occupied by the entire power supply circuit on the board. EXAMPLES

[0033] Example 2 is shown in FIG. 3. FIG. 3 is a block diagram of the entire high voltage circuit (charging, transfer, development). In addition, in the block diagram of FIG. 3, the same components as those in FIG. 6 are given the same reference numerals. In FIG. 3, the logic ICs 151, 152, and 153 (buffers or inverters) were placed for each voltage in FIG. 2 to convert the voltage level. In Example 2, the CLK of each voltage is first commonized as CommCLK, and the voltage level is converted by one logic IC 154 as a conversion means. Then, after the voltage level conversion is performed by one logic IC 154, it is branched to input 1 of the development power supply 100DEV, input 1 of the transfer power supply 100TRP, and input 1 of the charging power supply 100PR. With this configuration, the number of logic ICs can be reduced to one, so an IC with one element can be used, and the area occupied on the board can be further reduced.

[0034] On the other hand, if a single element is used to supply pulse signals to three inputs, a slightly larger current is required. For example, if the resistor R101 in FIG. 7 used in the conversion circuit 130 is 1 kΩ, then (3.3V-0.6V)÷1kΩ=2.7mA This requires a current of 2.7 mA. The printer 300 requires three boost circuits 100 (100DEV, 100TRP, 100PR), so it needs to supply a current of 8.1 mA (= 2.7 mA x 3). Some CMOS logic ICs have a low sink current capacity per element and cannot tolerate 8.1 mA, but an example of a single-element CMOS buffer that can drive a large current is the SN74LVC1G07 from Texas Instruments. This IC comes in several packages, but the smallest one is as small as 0.85 mm x 0.85 mm and has a maximum sink current of 32 mA, so it is possible to drive the circuit in Figure 3. In this way, you can select a logic IC according to the required current. Note that some ICs have an open-drain output stage, such as the SN74LVC1G07, so in Figure 3, the output is pulled up to 5.4 V by resistor R301. This can solve the problem of insufficient current supply as well as the problem of voltage level conversion.

[0035] As described above, according to the second embodiment, it is possible to reduce the cost of components and the area occupied by the entire power supply circuit on the board. EXAMPLES

[0036] In the first and second embodiments, the three conventional clocks DEVCLK, TRPCLK, and PRCLK are unified into CommCLK. Each high voltage power supply is feedback controlled, so that each can output a different output voltage. In the third embodiment, the ripple of the output voltage is further explained. In the third embodiment, the CPU 200 reduces the ripple of the output voltage by successively changing the frequency and on-time (ON time) of a common drive signal (CommCLK) in accordance with each timing of the print sequence in the electrophotographic process.

[0037] In Fig. 6, the CPU 200 outputs pulse signals as DEVCLK, TRPCLK, and PRCLK so that each high-voltage circuit outputs the optimal output voltage. This is because each high-voltage circuit uses different transformers and FETs. For example, PRCLK has a frequency of 16.7 kHz and a duty of 10%, DEVCLK has a frequency of 25 kHz and a duty of 12%, and TRPCLK has a frequency of 5 kHz and a duty of 3.6%, etc.

[0038] In Figures 2 and 3, in order to ensure that all voltages can produce maximum output, it is necessary to select the pulse signal with the highest frequency and the longest ON time as CommCLK from among the combinations of values. If the high-voltage circuit is configured as the boost circuit 100 in Figure 5, if the ON time of CommCLK is too long, it will be clamped by the comparator CP101, and the output can be suppressed. On the other hand, if the ON time of CommCLK is short, there is a problem. In other words, if the ON time of CommCLK is short, the high-voltage circuit that requires the highest output among charging, developing, and transferring may not be able to output the target high voltage. Therefore, in the above example, it is necessary to find out which is the highest frequency and which is the longest ON time for the CommCLK frequency and ON time.

[0039] The definition (ON time) of each pulse signal in FIG. 6 is as follows: DEVCLK 25kHz, Duty 12% → ON time 4.8usec TRPCLK 5kHz, Duty 3.6% → ON time 7.2usec PRCLK 16.7kHz, Duty 10% → ON time 6usec

[0040] Of these, TRPCLK has the longest ON time, so an ON time of 7.2 usec is selected, and DEVCLK has the highest frequency, so 25 kHz is selected. In other words, CommCLK is a pulse signal with a frequency of 25 kHz and an ON time of 7.2 usec. By using this as a common clock, each circuit will appropriately thin out CommCLK and switch each MOSFET Q101 so that the output voltage reaches the target value, making it possible to output different output voltages.

[0041] (CommCLK according to the operation of the printer 300) Here, it is possible to change CommCLK so that it becomes the optimal output condition for each high voltage in the print sequence. For example, suppose that during the preparation operation for printing (pre-rotation), it is desired to suppress the ripple of the output voltage of the charging power supply 100PR as much as possible. Conventionally, PRCLK was set to 16.7 kHz and duty 10%, so CommCLK is set to 16.7 kHz and duty 10% only during the pre-rotation. Also, during the operation after printing (post-rotation), for example, in order to clean the transfer roller 106, the transfer power supply 100TRP is prioritized, so CommCLK is set to 5 kHz, duty 3.6%, which is the original TRPCLK for transfer. Since charging and development are important during printing, the value with the highest frequency and the longest ON time is selected from both PRCLK 16.7 kHz, duty 10% and DEVCLK 25 kHz, duty 12%. In other words, CommCLK is set to 25 kHz and duty 12%. In this way, by changing the specifications of the CommCLK pulse signal over time, it is possible to achieve a configuration in which the ripple in the output voltage of each high voltage power supply during the print sequence is small and the supply capacity is not excessive.

[0042] FIG. 4 shows the print sequence and the CommCLK specifications (frequency, duty) selected during each sequence. In FIG. 4, the horizontal axis shows time, and the vertical axis shows the state of the printer 300 and the frequency and duty of the CommCLK during that state. When the printer 300 is on standby, the CPU 200 does not output the CommCLK (stopped). As described above, during the pre-rotation operation, the CPU 200 outputs the CommCLK with a frequency of 16.7 kHz and a duty of 10%. During the pre-rotation operation, in order to suppress the ripple of the charging voltage, the CPU 200 outputs the CommCLK with a frequency of 16.7 kHz and a duty of 10%. During printing, in order to suppress the ripple of the developing voltage, the CPU 200 outputs the CommCLK with a frequency of 25.7 kHz and a duty of 12%. During the post-rotation operation, in order to suppress the ripple of the transfer voltage, the CPU 200 outputs the CommCLK with a frequency of 5 kHz and a duty of 3.6%. In this way, the frequency and duty of the unified CommCLK may be changed depending on the operating status of the printer 300.

[0043] (environmental temperature) Also, if the printer 300 is equipped with an environment detection means such as a temperature sensor and detects that the environment is low and must output a fairly high voltage as the transfer voltage, the clock signal in the print sequence may be selected to prioritize transfer over charging. In other words, 5 kHz of TRPCLK and a duty of 3.6% may be selected as CommCLK.

[0044] If one of the voltages is to be prioritized and the ripple of the output voltage is to be kept small, the same control method as that described in the above-mentioned prior art 2 can be used. Specifically, if you want to suppress the ripple of the output voltage of the charging power supply 100PR in FIG. 3, you can do it as follows. That is, after inputting the target value of the output voltage to PRPWM, you can output CommCLK with a frequency according to the duty. As a result, within the charging voltage, CommCLK is hardly thinned out by the comparator CP101, and the MOSFET Q101 oscillates almost continuously instead of intermittently, and the ripple of the output voltage is minimized. The same applies to development and transfer. The frequency according to the duty of the target value of the output voltage is the threshold frequency (the limit value) at which the MOSFET Q101 can oscillate continuously and output the target voltage in a pulse signal.

[0045] As described above, according to the third embodiment, it is possible to reduce the cost of components and the area occupied by the entire power supply circuit on the board.

[0046] The disclosure of this embodiment includes the following configuration. (Configuration 1) a boost circuit comprising: a generating means having a switching element and a transformer which are turned on or off by a drive signal, and which generates a high voltage; a rectifying means for rectifying the high voltage generated by the generating means; a detecting means for detecting an output of the high voltage rectified by the rectifying means; a comparing means for comparing a detection result by the detecting means with a target voltage; and a controlling means for controlling the driving signal to be turned on or off based on a comparison result by the comparing means so that the high voltage becomes a constant output voltage; an output means for outputting the drive signal and outputting a PWM signal corresponding to the target voltage to the comparison means; A power supply device comprising: The boost circuit includes at least two boost circuits, The plurality of boost circuits are each capable of outputting a different high voltage; The power supply device according to claim 1, wherein the output means outputs the drive signal common to a plurality of the boost circuits. (Configuration 2) the switching element is a field effect transistor having a drain-source breakdown voltage exceeding 100 V; 2. The power supply device according to configuration 1, wherein the field effect transistor has an on-resistance guaranteed at a gate-source voltage of 4 V or more. (Configuration 3) the output means operates at a first voltage and has one port for outputting the drive signal; a conversion means for converting a level of the drive signal output from the one port, 3. The power supply device according to claim 2, wherein the conversion means converts the first voltage into a voltage having a level equal to or higher than a second voltage which is higher than the first voltage. (Configuration 4) the output means operates at a first voltage; the output means has one port for outputting the drive signal; a conversion means is provided between the one port and a switching element of each of the boost circuits, 3. The power supply device according to configuration 2, wherein each of the conversion means converts the first voltage to a voltage at a level equal to or higher than a second voltage that is higher than the first voltage. (Configuration 5) The power supply device according to configuration 3 or 4, wherein the conversion means is a logic IC. (Configuration 6) A charging means for charging the photoconductor; a developing means for developing the latent image on the photoreceptor with a developer; A transfer means for transferring the developer image onto a recording material; A power supply device according to any one of configurations 1 to 5; Equipped with The image forming apparatus according to the present invention is characterized in that the power supply device generates a charging voltage to be supplied to the charging means, a developing voltage to be supplied to the developing means, and a transfer voltage to be supplied to the transfer means. (Configuration 7) 7. The image forming apparatus according to configuration 6, wherein the output means successively changes a frequency and an ON time of the drive signal in accordance with a print sequence in an electrophotographic process. [Explanation of symbols]

[0047] 100DEV, 100TRP, 100PR boost circuit 200 CPU CP101 Comparator D101 Diode Q101 MOSFET T101 transformer

Claims

1. a boost circuit comprising: a generating means having a switching element and a transformer which are turned on or off by a drive signal, and which generates a high voltage; a rectifying means for rectifying the high voltage generated by the generating means; a detecting means for detecting an output of the high voltage rectified by the rectifying means; a comparing means for comparing a detection result by the detecting means with a target voltage; and a controlling means for controlling the driving signal to be turned on or off based on a comparison result by the comparing means so that the high voltage becomes a constant output voltage; an output means for outputting the drive signal and outputting a PWM signal corresponding to the target voltage to the comparison means; A power supply device comprising: The boost circuit includes at least two boost circuits, The plurality of boost circuits are each capable of outputting a different high voltage; The power supply device according to claim 1, wherein the output means outputs the drive signal common to a plurality of the boost circuits.

2. the switching element is a field effect transistor having a drain-source breakdown voltage exceeding 100 V; 2. The power supply device according to claim 1, wherein the on-resistance of the field effect transistor is guaranteed at a gate-source voltage of 4 V or more.

3. the output means operates at a first voltage and has one port for outputting the drive signal; a conversion means for converting a level of the drive signal output from the one port, 3. The power supply device according to claim 2, wherein the conversion means converts the first voltage into a voltage having a level equal to or higher than a second voltage which is higher than the first voltage.

4. the output means operates at a first voltage and has one port for outputting the drive signal; a conversion means is provided between the one port and a switching element of each of the boost circuits, 3. The power supply device according to claim 2, wherein each of said conversion means converts said first voltage to a voltage having a level equal to or higher than a second voltage which is higher than said first voltage.

5. 5. The power supply device according to claim 3, wherein the conversion means is a logic IC.

6. A charging means for charging the photoconductor; a developing means for developing the latent image on the photoreceptor with a developer; A transfer means for transferring the developer image onto a recording material; A power supply device according to any one of claims 1 to 4; Equipped with The image forming apparatus according to the present invention is characterized in that the power supply device generates a charging voltage to be supplied to the charging means, a developing voltage to be supplied to the developing means, or a transfer voltage to be supplied to the transfer means.

7. 7. The image forming apparatus according to claim 6, wherein said output means successively changes the frequency and ON time of said drive signal in accordance with a print sequence in an electrophotographic process.

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