Method and apparatus for performing acceleration operation on feature data, medium, and device

Abstract

To provide a method and an apparatus for performing acceleration operation on feature data, a medium, and a device.SOLUTION: A method includes the steps of: determining, from input feature data, an input point corresponding to an output point in to-be-calculated output feature data; determining a target region tag that matches the input point on the basis of the position parameter of the input point; determining existence information on a target feature value group mapped by the target region tag in an on-chip buffer, including feature values of a plurality of points matching each region tag in the input feature data; determining a target memory adapted to the existence information from the on-chip buffer and an on-chip main memory that stores the input feature data; calculating the feature value of the output point on the basis of the feature value of the input point in the target memory; and calculating the output feature data on the basis of the feature value of the output point.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to artificial intelligence technology, and in particular to a method, device, medium, and apparatus for performing high-speed calculations on feature data. [Background technology]

[0002] In the field of artificial intelligence technology, it is common to calculate the requirements of output feature data based on input feature data. In some scenes, an image can be subjected to a scaling process to obtain a scaled image, where the image before scaling can be the input feature data, and the image after scaling can be the output feature data. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure provides a method, device, medium and apparatus for performing high-speed calculations on feature data to ensure the calculation efficiency of output feature data. [Means for solving the problem]

[0004] A high-speed calculation method for feature data according to an embodiment of the present disclosure includes: determining, from the input feature data, input points corresponding to output points in the output feature data to be calculated; determining a target region tag matching the input point based on a position parameter of the input point; determining presence status information in an on-chip buffer of a set of target feature values ​​to which the target region tag is mapped, the set of feature values ​​to which any region tag is mapped including feature values ​​of a plurality of points in the input feature data that match the region tag; determining a target memory that matches the presence status information from the on-chip buffer and an on-chip main memory in which the input feature data is stored; calculating feature values ​​of the output points based on feature values ​​of the input points in the target memory; and calculating the output feature data based on feature values ​​of the output points.

[0005] A high-speed calculation device for feature data according to another aspect of the embodiment of the present disclosure includes: a first determination module for determining, from the input feature data, input points corresponding to output points in the output feature data to be calculated; a second determination module for determining a target area tag matching the input point based on the position parameters of the input point determined by the first determination module; a third determination module for determining information on the presence status in an on-chip buffer of a target feature value group to which the target area tag determined by the second determination module is mapped, the feature value group to which any area tag is mapped includes each feature value of a plurality of points in the input feature data that match the area tag; a fourth determination module for determining a target memory that matches the presence status information determined by the third determination module from the on-chip buffer and the on-chip main memory in which the input feature data is stored; a first calculation module for calculating feature values ​​of the output points based on the feature values ​​of the input points in the target memory determined by the fourth determination module; a second calculation module for calculating the output feature data based on the feature values ​​of the output points calculated by the first calculation module.

[0006] A computer-readable storage medium according to yet another aspect of the embodiment of the present disclosure stores a computer program for executing the high-speed calculation method for the feature data.

[0007] According to another aspect of the present disclosure, there is provided an electronic device comprising: A processor; a memory for storing instructions executable by the processor; The processor is for implementing the high speed computation method for the feature data by reading and executing the executable instructions from the memory.

[0008] A computer program product according to another aspect of the present disclosure includes instructions, when executed by a processor, that perform the high-speed calculation method for the feature data described above. Effect of the Invention

[0009] According to the method, device, medium, electronic device, and computer program product for high-speed computation on feature data according to the above-mentioned embodiments of the present disclosure, an input point corresponding to an output point in output feature data to be computed can be determined from the input feature data, a target area tag matching the input point can be determined based on a position parameter of the input point, an appropriate target memory can be determined from the on-chip buffer and the on-chip main memory in which the input feature data is stored by referring to information on the presence status in the on-chip buffer of the target feature value group to which the target area tag is mapped, a feature value of the output point can be calculated based on the feature value of the input point in the target memory, and output feature data can be calculated based on the feature value of the output point. In this way, by operating the tag policy, the feature value of the input point can be preferentially read from the on-chip buffer, and if the required feature value is not present in the on-chip buffer, the feature value of the input point can be read from the on-chip main memory, which is advantageous in improving the efficiency of reading the input feature data and realizing high-speed computation on the input feature data, thereby ensuring the efficiency of computing the output feature data. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic flowchart of a method for fast calculations on feature data according to some exemplary embodiments of the present disclosure. [Diagram 2]FIG. 2 is a schematic diagram of a memory hierarchy of an on-chip main memory in some example embodiments of the present disclosure. [Diagram 3] 1 is a schematic flow diagram of an aspect of obtaining feature values ​​of an input point in a target memory in some exemplary embodiments of the present disclosure; [Figure 4] 4 is a schematic flowchart of a method for determining first address information in some exemplary embodiments of the present disclosure. [Diagram 5] 1 is a schematic flowchart of an aspect of determining first information in some exemplary embodiments of the present disclosure. [Figure 6] 11 is a schematic flowchart of an aspect of determining second information in some exemplary embodiments of the present disclosure. [Figure 7] 11 is a schematic flowchart of an aspect of determining third information in some exemplary embodiments of the present disclosure. [Figure 8] 1 is a schematic flow diagram of an aspect of determining a target region tag in accordance with some exemplary embodiments of the present disclosure; [Figure 9] 11 is a schematic flow diagram of operations performed on an on-chip buffer in a situation where the on-chip buffer does not contain a set of target feature values ​​in accordance with some exemplary embodiments of the present disclosure. [Figure 10] 11 is a schematic flow diagram of an aspect of adding target feature values ​​to an on-chip buffer in accordance with some exemplary embodiments of the present disclosure. [Figure 11] 1 is a schematic flow chart of an aspect of calculating output feature data in some exemplary embodiments of the present disclosure. [Figure 12] 11 is a schematic flow diagram of an aspect of obtaining feature values ​​of an input point in a target memory in some alternative exemplary embodiments of the present disclosure; [Figure 13-1] FIG. 2 is a principle diagram of a method for calculating output feature data in some exemplary embodiments of the present disclosure. [Figure 13-2] FIG. 13 is a principle diagram of a method for calculating output feature data in some other exemplary embodiments of the present disclosure. [Figure 14] 11 is a schematic flowchart of an aspect of obtaining feature values ​​of an input point in a target memory in yet another exemplary embodiment of the present disclosure; [Figure 15] FIG. 1 is a schematic structural diagram of a high-speed calculation device for feature data according to some exemplary embodiments of the present disclosure. [Figure 16] FIG. 11 is a schematic structural diagram of a high-speed calculation device for feature data according to some other exemplary embodiments of the present disclosure. [Figure 17] FIG. 2 is a schematic diagram of modules involved in the calculation of output feature data in some exemplary embodiments of the present disclosure. [Figure 18] FIG. 1 is a structural diagram of an electronic device according to some example embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In order to interpret the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. Also, the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments, and the present disclosure is not limited to the exemplary embodiments.

[0012] It should be noted that the relative configurations of components and steps set forth in these examples, numerical expressions and values ​​do not limit the scope of the present disclosure unless specifically stated otherwise.

[0013] The scenes for computing the output feature data based on the input feature data may include, but are not limited to, the following scenes: Scene 1: Preprocessing is performed on an image to obtain a preprocessed image, where the preprocessing can include, but is not limited to, a scaling (resize) process, a rotation process, a projection process, a distortion removal process, etc., and the image before the preprocessing can be used as input feature data, and the image after the preprocessing can be used as output feature data. Scene 2: A pooling process is performed on the feature map to obtain a pooled feature map. Here, the pooling process can include, but is not limited to, a maximum pooling process, an average pooling process, etc., and the feature map before pooling can be used as input feature data, and the feature map after pooling can be used as output feature data.

[0014] In addition, fields such as image recognition, detection, and segmentation may all relate to scenes in which output feature data is calculated based on input feature data, and how to ensure the calculation efficiency of output feature data for scenes in which output feature data is calculated based on input feature data is a problem that requires attention from those skilled in the art.

[0015] 1 is a schematic flow chart of a method for fast computation of feature data according to some exemplary embodiments of the present disclosure. The method shown in FIG. 1 can be applied to electronic devices such as in-vehicle computing platforms. The method shown in FIG. 1 can include steps 110, 120, 130, 140, 150, and 160.

[0016] In step 110, an input point corresponding to an output point in the output feature data to be calculated (waiting for calculation) is determined from the input feature data.

[0017] Optionally, both the input feature data and the output feature data may be images or feature maps, and thus both the input feature data and the output feature data may include multiple pixel points, each of which may be an output point.

[0018] In step 110, an input point corresponding to an output point in the output feature data can be determined from a plurality of pixel points contained in the input feature data.

[0019] JPEG2025071069000002.jpg65157

[0020] Although the above describes a situation in which the number of input points corresponding to an output point is four, in some embodiments, the number of input points corresponding to an output point may be nine, sixteen, etc., and is not listed one by one here. For ease of understanding, the embodiments of the present disclosure will be described taking as an example a situation in which the number of input points corresponding to an output point is four.

[0021] In step 120, a target region tag that matches the input point is determined based on the position parameters of the input point.

[0022] Optionally, the position parameter of the input point may refer to the position coordinate of the input point. The position coordinate of the input point may be associated with the row and column in which the input point is located in the input feature data. For example, if the input point is located in the j-th row and the i-th column of the input feature data, the position coordinate of the input point may be (i-1, j-1) or (i, j).

[0023] Optionally, any region tag may be a tag that corresponds to a particular region in the input feature data, and each pixel point in that particular region may share that region tag, and all of these pixel points may be considered to match that region tag.

[0024] At step 130, presence information in an on-chip buffer of target feature values ​​to which a target region tag is mapped is determined, where the feature values ​​to which any region tag is mapped include respective feature values ​​of a number of points in the input feature data that match the region tag.

[0025] Optionally, the on-chip buffer may be a Cache.

[0026] Optionally, the feature value of a single point may be stored in RGB0 format, where the feature value of a single point may include an R channel pixel value, a G channel pixel value, a B channel pixel value, and a transparency, where R represents red, G represents green, and B represents blue, or may be stored in YUV0 format, where the feature value of a single point may include a Y component value, a U component value, a V component value, and a transparency, where Y represents luminance, and U and V represent chromaticity.

[0027] In step 130, presence status information can be obtained by querying the on-chip buffer using the target area tag as index information, and the presence status information can be for indicating whether the target feature value group to which the target area tag is mapped exists in the on-chip buffer.

[0028] In step 140, a target memory that matches the presence status information is determined from the on-chip buffer and the on-chip main memory in which the input feature data is stored.

[0029] Optionally, the on-chip main memory may include, but is not limited to, Static Random-Access Memory (SRAM), Synchronous Dynamic Random-Access Memory (SDRAM), and the like.

[0030] If the presence status information indicates that the target feature value set is present in the on-chip buffer, it can be determined that the target memory that matches the presence status information is the on-chip buffer.If the presence status information indicates that the target feature value set is not present in the on-chip buffer, it can be determined that the target memory that matches the presence status information is the on-chip main memory.

[0031] In step 150, feature values ​​for the output points are calculated based on feature values ​​for the input points in the target memory.

[0032] If the target memory is an on-chip buffer, it indicates that the feature value of the input point is present in the on-chip buffer, and then the feature value of the input point can be obtained by reading the on-chip buffer, and the feature value of the output point can be calculated based on the feature value of the input point.

[0033] If the target memory is an on-chip main memory, it indicates that the feature value of the input point does not exist in the on-chip buffer, and since the input feature data is stored in the on-chip main memory, the feature value of the input point exists in the on-chip main memory, so the feature value of the input point can be obtained by reading the on-chip main memory, and the feature value of the output point can be calculated based on the feature value of the input point.

[0034] Since the number of input points corresponding to the output point is four, in step 150, according to the specific scene where the output feature data needs to be calculated based on the input feature data, suitable arithmetic logic can be used to perform calculations on the feature values ​​of each of the four input points to obtain the feature value of the output point.

[0035] For example, if the specific scene that needs to calculate the output feature data based on the input feature data is the above scene 1, and the pre-processing related to scene 1 includes a scaling process, an interpolation operation can be performed on the feature values ​​of each of the four input points to obtain the feature value of the output point. Optionally, the interpolation operation here can be realized by a bilinear interpolation operator.

[0036] For example, if a specific scene that needs to calculate output feature data based on input feature data is the above scene 2 and the pooling process related to scene 2 includes a max pooling process, a maximum value can be calculated for each feature value of four input points to obtain a feature value of an output point. Optionally, the maximum value calculation here can be realized by a pooling operator.

[0037] Further, for example, if a specific scene that needs to calculate output feature data based on input feature data is the above scene 2, and the pooling process related to scene 2 includes an average pooling process, an average value operation can be performed on each feature value of four input points to obtain the feature value of an output point. Optionally, the average value operation here can be realized by a pooling operator.

[0038] JPEG2025071069000003.jpg46157

[0039] If the specific scene for which output feature data needs to be calculated based on input feature data is the above scene 1 and the pre-processing related to scene 1 includes a scaling process, the feature value of the output point can be calculated by the following formula:

[0040] Vtop = (1-x + Δx) × V topLeft +(x-Δx)×V topRight V bot =(1-x+Δx)×V botLeft +(x-Δx)×V botRight V(x,y)=(1-y+Δy)×V top +(y-Δy)×V bot

[0041] Here, V top V topLeft and V topRight are the linear interpolation results of both and bot V botLeft and V botRight and V(x,y) is the linear interpolation result of Vtop and V bot and are the linear interpolation results.

[0042] If the specific scene for which output feature data needs to be calculated based on input feature data is the above scene 2 and the pooling process for scene 2 includes a max pooling process, the feature value of the output point can be calculated by the following formula:

[0043] V(x,y) = MAX(V topLeft ,V topRight ,V botLeft ,V botRight )

[0044] In step 160, output feature data is calculated based on the feature values ​​of the output points.

[0045] In addition, the output feature data may include a plurality of output points, and for each output point in the plurality of output points, a corresponding feature value may be determined in the manner introduced above, and the output feature data may be calculated based on the determined feature values.

[0046] In an embodiment of the present disclosure, an input point corresponding to an output point in output feature data to be calculated can be determined from the input feature data, a target area tag matching the input point can be determined based on a position parameter of the input point, an appropriate target memory can be determined from the on-chip buffer and the on-chip main memory in which the input feature data is stored by referring to information on the presence status in the on-chip buffer of the target feature value group to which the target area tag is mapped, a feature value of the output point can be calculated based on the feature value of the input point in the target memory, and output feature data can be calculated based on the feature value of the output point. In this way, by operating the tag policy, the feature value of the input point can be preferentially read from the on-chip buffer, and if the required feature value is not present in the on-chip buffer, the feature value of the input point can be read from the on-chip main memory, which is advantageous in improving the reading efficiency of the input feature data and realizing high-speed calculation for the input feature data, thereby ensuring the calculation efficiency of the output feature data.

[0047] In some alternative examples, the on-chip main memory may include multiple banks, each of which may include multiple slices, each of which may include multiple storage locations for storing respective feature values ​​for each point in a dot matrix of a given size in the input feature data, i.e., the on-chip main memory may include three memory hierarchies: a bank hierarchy, a slice hierarchy, and a storage location hierarchy.

[0048] Optionally, the on-chip main memory may include R banks, and the R banks in the on-chip main memory may be numbered according to an arithmetic progression starting from 0 and with a common difference of 1.

[0049] Optionally, each bank may include S slices, and the S slices in each bank may be numbered according to an arithmetic progression starting at 0 and with a common difference of 1.

[0050] Optionally, each slice may include M×M storage locations for storing respective feature values ​​for each point in an M×M sized dot matrix in the input feature data, and the M×M storage locations in each slice may be numbered according to an arithmetic progression starting at 0 and with a common difference of 1.

[0051] In some embodiments, the R banks in the on-chip main memory may be numbered starting at 1, and / or the S slices in each bank may be numbered starting at 1, and / or the M×M storage locations in each slice may be numbered starting at 1.

[0052] Note that for all locations other than those locations described separately below, the R banks in the on-chip main memory are numbered starting at 0, the S slices in each bank are numbered starting at 0, and the M x M storage locations in each slice are numbered starting at 0.

[0053] Assuming that the value of M is 2 and the value of S is 16, the memory hierarchy of the on-chip main memory can be seen in FIG. 2. Taking slice 0 in bank 0 as an example, slice 0 can include four storage locations, where the storage location (0,0) is for storing the feature value of the point whose coordinates are (0,0) in the input feature data, the storage location (0,1) is for storing the feature value of the point whose coordinates are (0,1) in the input feature data, the storage location (1,0) is for storing the feature value of the point whose coordinates are (1,0) in the input feature data, and the storage location (1,1) is for storing the feature value of the point whose coordinates are (1,1) in the input feature data. Assuming that the feature value of each point is 4 bytes and each feature value of the four points is 16 bytes in total, each slice can store 16 bytes of data. As can be seen from FIG. 2, a single bank can store 16 consecutive 2×2 dot matrices.

[0054] In some alternative examples, when the target memory is an on-chip main memory, the method according to the embodiment of the present disclosure may include steps 310 and 320, as shown in Fig. 3. Optionally, steps 310 and 320 may be performed before step 150 of the present disclosure.

[0055] In step 310, first address information is determined based on the position parameter of the input point and the size of the input feature data to indicate which bank the input point belongs to, which slice it belongs to, and where it is located in the on-chip main memory.

[0056] As introduced in the previous paragraph, the position parameter of the input point may refer to the position coordinate of the input point. The position coordinate of the input point may include the abscissa and ordinate of the input point. The abscissa of the input point may be represented as w, and the ordinate of the input point may be represented as h. Furthermore, the size of the input feature data may include the width and height of the input feature data. The width of the input feature data may be represented as W, and the height of the input feature data may be represented as H.

[0057] Optionally, the first address information can include three components, where the first component is for indicating a bank to which the input point belongs in the on-chip main memory, the second component is for indicating a slice to which the input point belongs in the on-chip main memory, and the third component is for indicating a storage location to which the input point belongs in the on-chip main memory. Thus, the first address information can have an expression form of (bank a, slice b, storage location c).

[0058] In step 320, obtain the feature value of the input point in the on-chip main memory based on the first address information.

[0059] If the target feature value group is not present in the on-chip buffer, i.e., the feature value of the input point cannot be obtained from the on-chip buffer, step 310 can be executed to determine first address information, then search for the bank indicated by the first address information from among R banks contained in the on-chip main memory, search for the slice indicated by the first address information from among S slices contained in the bank, search for the storage location indicated by the first address information from among M×M storage locations contained in the slice, and then read the feature value of the input point from the storage location.

[0060] In an embodiment of the present disclosure, the on-chip main memory can store input feature data according to three memory hierarchies (bank hierarchy, slice hierarchy and storage location hierarchy). In this way, when the feature value of an input point cannot be obtained from the on-chip buffer, for an output point, it is only necessary to determine first address information indicating the bank to which the input point belongs, the slice to which it belongs and the storage location in which it is located, and then the required feature value can be quickly read from the on-chip main memory based on the first address information.

[0061] In some alternative examples, as shown in FIG. 4, step 310 may include step 3101, step 3103, step 3105, and step 3107.

[0062] In step 3101, a first piece of information is determined for indicating a bank to which the input point belongs in the on-chip main memory based on a position parameter of the input point and a size of the input feature data.

[0063] In some alternative embodiments of the present disclosure, as shown in FIG. 5, step 3101 may include step 31011, step 31013, and step 31015.

[0064] In step 31011, a first width and a first height of a pixel block that can be accommodated by a single bank are determined based on a first number of slices contained in a single bank and a second number of storage locations contained in a single slice.

[0065] Optionally, S in the preceding sentence can be a first number and M×M in the preceding sentence can be a second number, and then a first width of pixel blocks that a single bank can accommodate can be S×M and a first height can be M.

[0066] In step 31013, a second width of the input feature data is determined based on the size of the input feature data.

[0067] Optionally, W in the preceding sentence may be a second width.

[0068] In step 31015, first information is determined based on the position parameter of the input point, the first width, the first height, and the second width.

[0069] Optionally, the first information can be represented by the sorting value in the R banks of the bank to which the input point belongs. If the sorting value in the R banks of the bank to which the input point belongs is B, and the abscissa and ordinate of the position parameter of the input point are w and h, respectively, B can be calculated by the following formula:

[0070] B=floor{[floor(h / M)×W+w] / (S×M)} Here, floor represents a rounddown operation.

[0071] In this manner, the first information for indicating the bank to which the input point belongs can be determined efficiently and reliably by combining arithmetic logic such as division, rounding down, multiplication, and addition.

[0072] In step 3103, second information is determined based on the position parameter of the input point, the size of the input feature data and the first information to indicate the slice to which the input point belongs in the on-chip main memory.

[0073] In some alternative embodiments of the present disclosure, as shown in FIG. 6, step 3103 may include step 31031, step 31033, step 31035, and step 31037.

[0074] In step 31031, a first width and a first height of a pixel block that can be accommodated by a single bank are determined based on a first number of slices contained in a single bank and a second number of storage locations contained in a single slice.

[0075] Referring to the introduction to step 31011 in the preceding sentence, the first width can be expressed as S×M, and the first height can be expressed as M.

[0076] In step 31033, a first sum of the first widths of pixel blocks that can be accommodated by each bank that is sorted before the bank to which the input point belongs is determined based on the first information.

[0077] If the first information is B in the preceding sentence, the total number of banks sorted before the bank to which the input point belongs can be B, and since the first width of the pixel block that a single bank can accommodate is S×M, the first sum in step 31033 can be expressed as B×(S×M).

[0078] In step 31035, a second width of the input feature data is determined based on the size of the input feature data.

[0079] Optionally, W in the preceding sentence may be a second width.

[0080] In step 31037, second information is determined based on the position parameter of the input point, the first sum, the first height and the second width.

[0081] Optionally, the second information can be represented by a sorting value of the slice to which the input point belongs and the bank to which the input point belongs. If the sorting value of the slice to which the input point belongs and the bank to which the input point belongs is C, and the horizontal and vertical coordinates of the position parameters of the input point are w and h, respectively, C can be calculated by the following formula:

[0082] C=floor{[floor(h / M)×W+wB×S×M] / M}

[0083] In this manner, by combining arithmetic logic such as division, truncation, multiplication, addition, and subtraction, the second information for indicating the slice to which the input point belongs can be efficiently and reliably determined.

[0084] In step 3105, third information is determined based on the position parameter of the input point, the size of the input feature data, the first information and the second information to indicate a storage location where the input point is located in the on-chip main memory.

[0085] In some alternative embodiments of the present disclosure, as shown in FIG. 7, step 3105 may include step 31051, step 31053, step 31055, step 31057, and step 31059.

[0086] In step 31051, a first width and a first height of a pixel block that can be accommodated by a single bank are determined based on a first number of slices contained in a single bank and a second number of storage locations contained in a single slice.

[0087] Referring to the introduction to step 31011 in the preceding sentence, the first width can be expressed as S×M, and the first height can be expressed as M.

[0088] In step 31053, a first sum of the first widths of pixel blocks that can be accommodated by each bank that is sorted before the bank to which the input point belongs is determined based on the first information.

[0089] Referring to the introduction to step 31033 in the preceding sentence, the first sum can be expressed as B×(S×M).

[0090] In step 31055, based on the second information, a second sum of second heights of pixel blocks that can be accommodated by each slice that is sorted before the slice to which the input point belongs in the bank to which the input point belongs is determined.

[0091] If the second information is C as above, the total number of slices sorted before the slice to which the input point belongs in the bank to which the input point belongs can be C, and since the second height of the pixel block contained by a single slice is M, the second sum in step 31055 can be expressed as C×M.

[0092] In step 31057, a second width of the input feature data is determined based on the size of the input feature data.

[0093] Optionally, W in the preceding sentence may be a second width.

[0094] In step 31059, third information is determined based on the position parameter of the input point, the first sum, the second sum, the first height, and the second width.

[0095] Optionally, the third information can be represented by a sort value of the storage location where the input point is located in the slice to which the input point belongs. If the sort value of the storage location where the input point is located in the slice to which the input point belongs is O, and the horizontal and vertical coordinates of the position parameters of the input point are w and h, respectively, O can be calculated by the following formula:

[0096] O=[h-floor(h / M)]×M+floor(h / M)×W+wB×S×MC×M

[0097] In this manner, by performing arithmetic logic operations such as division, truncation, multiplication, addition, and subtraction, the third information for indicating the storage location where the input point is located can be efficiently and reliably determined.

[0098] In step 3107, the first address information is determined based on the first information, the second information, and the third information.

[0099] In step 3107, the first address information having an expression form of (bank a, slice b, storage location c) can be obtained by combining the first information, the second information, and the third information. For example, the first address information can specifically be in the form of (B, C, O).

[0100] It should be noted that the formulas for obtaining B, C, and O in the preceding sentence assume that the R banks are numbered starting from 0, the S slices in each bank are numbered starting from 0, and the M×M storage locations in each slice are numbered starting from 0. In a concrete implementation, the R banks can be numbered starting from 1 rather than starting from 0, the S slices in each bank are still numbered starting from 0, and the M×M storage locations contained in each slice are still numbered starting from 0, then the formula for obtaining C can be modified to C=floor{[floor(h / M)×W+w-(B-1)×S×M] / M}. Also, if the R banks are numbered starting at 1, and the S slices in each bank are also numbered starting at 1, and the M × M storage locations contained in each slice are also numbered starting at 1, then the formula for obtaining C can be modified to C = floor{[floor(h / M) × W + w-(B-1) × S × M] / M} + 1, and the formula for obtaining O can be modified to O = [h-floor(h / M)] × M + floor(h / M) × W + wB × S × M-(C-1) × M + 1.

[0101] In addition, the position parameters of the input point and the size of the input feature data can be regarded as basic reference information, and the basic reference information can provide a valid reference for determining the first information, the first information and the basic reference information together can provide a valid reference for determining the second information, and the first information, the second information and the basic reference information together can provide a valid reference for determining the third information, so that the determined first information, second information and third information all conform to both the position of the input point in the input feature data and the size of the input feature data, thereby ensuring the accuracy and reliability of the determined first information, second information and third information, and in this way, the accuracy and reliability of the first address information obtained by combining the first information, second information and third information can also be well guaranteed.

[0102] In some alternative examples, step 120 may include step 1201, step 1203, step 1205, and step 1207, as shown in FIG.

[0103] In step 1201, a target abscissa and a target ordinate of the input point are determined based on the position parameters of the input point.

[0104] Optionally, w in the preceding sentence may be taken as the target abscissa and h in the preceding sentence may be taken as the target ordinate.

[0105] In step 1203, a first tag parameter is determined based on the target abscissa and the first preset value.

[0106] Optionally, step 1203 includes rounding down a ratio between the target abscissa and the first preset value to obtain the first tag parameter. Since the target abscissa is represented as w, if the first preset value is 2, the ratio of the target abscissa to the first preset value can be represented as w / 2, and the first tag parameter obtained by rounding down the ratio of the target abscissa to the first preset value can be represented as floor(w / 2).

[0107] In this way, the first tag parameter can be obtained efficiently and reliably by performing division and truncation operations.

[0108] In step 1205, a second tag parameter is determined based on the target ordinate and the first preset value.

[0109] Optionally, step 1205 includes rounding down a ratio between the target ordinate and the first preset value to obtain the second tag parameter.

[0110] Since the target ordinate is represented as h, if the first preset value is 2, the ratio between the target ordinate and the first preset value can be expressed as h / 2, and the second tag parameter obtained by truncating the ratio between the target ordinate and the first preset value can be expressed as floor(h / 2).

[0111] In this way, the second tag parameter can be obtained efficiently and reliably by performing division and truncation operations.

[0112] In step 1207, a target area tag is determined based on the first tag parameter and the second tag parameter.

[0113] Optionally, the first tag parameter and the second tag parameter can be combined, and the combined result can be the target area tag. For example, the target area tag can be [floor(w / 2), floor(h / 2)]. Or, the first tag parameter and the second tag parameter can be concatenated using a preset symbol, and the concatenated result can be the target area tag. For example, the target area tag can be floor(w / 2)&floor(w / 2). In some embodiments, the target area tag can be tag[floor(w / 2), floor(h / 2)]. Or, the combined result or concatenated result can be encoded into binary data, and the binary data obtained by encoding can be the target area tag.

[0114] In this way, by determining the tag parameters corresponding to the target abscissa and the target ordinate of the input point, and integrating the tag parameters corresponding to the target abscissa and the target ordinate, the target region tag matching the input point can be obtained efficiently and reliably, and the target region tag can be shared by multiple points in the input feature data. For example, if the coordinates of the input point are (7,7), the target region tag can be (3,3), and obviously, the target region tag can be shared by the point with coordinates (6,6), the point with coordinates (6,7), and the point with coordinates (7,6), so the target feature value group can include the feature value of the input point, the feature value of the point with coordinates (6,6), the feature value of the point with coordinates (6,7), and the feature value of the point with coordinates (7,6).

[0115] In some alternative examples, as shown in Fig. 9, the method according to the embodiment of the present disclosure may further include step 910 and step 920. Optionally, step 910 may be performed in a situation where the target memory is an on-chip main memory.

[0116] In step 910, for the remaining points other than the input point among the multiple points matching the target area tag, second address information is determined to indicate the bank to which the remaining points belong, the slice to which they belong, and the storage location in the on-chip main memory based on the position parameters of the remaining points and the size of the input feature data.

[0117] Continuing with the example in the previous paragraph, the input point has coordinates (7,7), and the multiple points matching the target area tag (3,3) further include, in addition to the input point, a point with coordinates (6,6), a point with coordinates (6,7), and a point with coordinates (7,6). In this case, the second address information corresponding to the point with coordinates (6,6), the point with coordinates (6,7), and the point with coordinates (7,6) can be determined. For the specific determination method, refer to the introduction of the method for determining the first address information in the previous paragraph, and the explanation will be omitted here.

[0118] In step 920, based on the second address information, the feature values ​​of the remaining points in the on-chip main memory are obtained to obtain a target feature value set including the feature values ​​of the input point and the feature values ​​of the remaining points, and the target feature value set is added to the on-chip buffer.

[0119] In step 920, the feature values ​​of the point with coordinates (6,6), the point with coordinates (6,7), and the point with coordinates (7,6) in the on-chip main memory can be obtained based on the second address information corresponding to the point with coordinates (6,6), the point with coordinates (6,7), and the point with coordinates (7,6), respectively, and the specific obtaining method can be referred to the introduction of the obtaining method of the feature value of the input point in the on-chip main memory in the previous paragraph, and the description will be omitted here. Then, the target feature values ​​consisting of the feature values ​​of the input point, the point with coordinates (6,6), the point with coordinates (6,7), and the point with coordinates (7,6) can be added to the on-chip buffer.

[0120] By adding the group of target feature values ​​to the on-chip buffer, when it is necessary to subsequently obtain the feature values ​​of the remaining points that share the target area tag with the input point, there is no need to obtain them from the on-chip main memory, but rather the on-chip buffer can be read directly, thus improving the reading efficiency of the input feature data and further ensuring the calculation efficiency of the output feature data.

[0121] 10, the method according to the embodiment of the present disclosure may further include step 1010, step 1020, step 1030, and step 1040. Optionally, a combination of steps 1010 to 1040 may be an alternative embodiment of adding the set of target feature values ​​to the on-chip buffer in step 920 of the present disclosure.

[0122] In step 1010, a numerical relationship between the number of sets of feature values ​​present in the on-chip buffer and a preset number is established.

[0123] It should be noted that the preset number may be the maximum number of feature value groups that can be stored in the on-chip buffer. Optionally, the preset number may be 4, 6, etc., and is not listed one by one here. The numerical relationship in step 1010 may refer to the magnitude relationship between the number of feature value groups present in the on-chip buffer and the preset number.

[0124] In step 1020, if the numerical relationship satisfies a preset condition, the usage status information corresponding to each set of characteristic values ​​in the on-chip buffer is determined.

[0125] If the number of feature values ​​in the on-chip buffer is less than the preset number, it indicates that the number of feature values ​​in the on-chip buffer is not large and there is sufficient space in the on-chip buffer to store new feature values. In this case, it can be determined that the numerical relationship in step 1010 does not satisfy the preset condition, and in this case, the target feature value group can be directly added to the on-chip buffer.

[0126] If the number of feature value sets in the on-chip buffer is equal to the preset number, it indicates that the number of feature value sets in the on-chip buffer is large and the on-chip buffer does not have enough space to store new feature value sets, then it can be determined that the numerical relationship in step 1010 satisfies the preset condition, and then the usage status information corresponding to each feature value set in the on-chip buffer can be determined. The usage status information corresponding to any feature value set can be to indicate the number of times, frequency, etc. that the feature value set has been accessed in a recent period.

[0127] In some embodiments, the numerical relationship in step 1010 may be a ratio of the number of feature values ​​present in the on-chip buffer to a preset number, and in this situation, if the ratio is equal to the preset ratio (e.g., 1), it may be determined that the numerical relationship in step 1010 satisfies the preset condition.

[0128] In step 1030, a set of feature values ​​that meet a preset deletion condition is selected from the on-chip buffer based on the usage information.

[0129] In step 1030, the feature value group that has been least accessed in a recent period can be selected from the on-chip buffer as the feature value group that satisfies the preset deletion condition by referring to the usage status information corresponding to each of the feature value groups in the on-chip buffer. If the number of the feature value groups that have been least accessed in a recent period is one or more, one feature value group can be randomly selected from the one or more feature value groups as the feature value group that satisfies the preset deletion condition.

[0130] In step 1040, the set of feature values ​​in the on-chip buffer that satisfy a preset deletion condition is replaced with the set of target feature values.

[0131] In step 1040, the target feature values ​​can be added to the on-chip buffer by directly replacing the feature values ​​that satisfy the preset deletion condition with the target feature values.

[0132] In addition, the on-chip buffer usually has a limited storage space. For example, the on-chip buffer can store a maximum of a preset number of feature value groups. In view of this, in the embodiment of the present disclosure, the feature value groups can be replaced according to a least frequently used (LFU) policy, so as to ensure that the target feature value groups are successfully added, while ensuring that the on-chip buffer stores as many used feature values ​​as possible, and avoiding invalid storage.

[0133] In some optional examples, as shown in FIG. 11, the method according to the embodiment of the present disclosure may further include step 1110, step 1120, and step 1130.

[0134] In step 1110, a plurality of calculation tasks are determined, where each calculation task is for calculating feature values ​​of some output points in the output feature data to be calculated.

[0135] Optionally, the output feature data to be calculated can be partitioned into N pixel blocks, where N is an integer equal to or greater than 2. For example, N can be 8, 16, etc. The sizes of different pixel blocks can be the same or different. Each pixel block can correspond to one calculation task, and thus there can be a total of N calculation tasks. The calculation task corresponding to each pixel block can be a task for calculating a respective feature value of each output point in the pixel block.

[0136] In step 1120, different computational tasks are assigned to different computational components.

[0137] Optionally, the computation component may include an Arithmetic And Logic Unit (ALU).

[0138] In step 1120, the N computational tasks can be assigned to the N computational components, which may be assigned randomly or according to a set rule to ensure that the N computational tasks correspond one-to-one to the N computational components. Optionally, each of the N computational components can be provided with an independent on-chip buffer.

[0139] In step 1130, different computational components are controlled such that corresponding computational tasks are executed in parallel.

[0140] In step 1130, each of the N computing components can complete a corresponding computing task through an independent thread. For example, one of the N computing components can calculate a feature value of an output point in pixel block 1 through thread 1, while another of the N computing components can calculate a feature value of an output point in pixel block 2 through thread 2.

[0141] In the embodiments of the present disclosure, different calculation components can perform calculation tasks in parallel, thus further ensuring the calculation efficiency of the output feature data.

[0142] In some alternative examples, as shown in FIG. 12, step 320 may include step 3201 and step 3203.

[0143] In step 3201, a data bus corresponding to both the bank and slice designated by the first address information is determined.

[0144] As introduced in the previous paragraph, the on-chip main memory can include R banks, and each bank can include S slices. R×S data buses are provided for each of the N calculation components, and the calculation components can be connected to each slice in each bank via R×S data buses. If the output point is located in the pixel block corresponding to the calculation component, the data bus for connecting the calculation component and the slice indicated by the first address information can be the data bus in step 3201.

[0145] In step 3203, the feature value of the input point is obtained from the storage location specified by the first address information via a data bus corresponding to both the bank and slice specified by the first address information.

[0146] In step 3203, by reading data via the data bus determined in step 3201, the feature value at the storage location indicated by the first address information can be obtained, and this feature value is the feature value of the input point.

[0147] In the embodiments of the present disclosure, different computing components can execute corresponding computing tasks in parallel, and each computing component can select an appropriate data bus from multiple data buses provided for that computing component during the calculation process to use for acquiring feature values, thereby avoiding interference in reading and writing between different computing components.

[0148] In some selectable examples, as shown in FIG. 13-1, the input feature data can be an input image or a feature map, which is stored in a static random access memory (SRAM) 1310, and the output feature data can be an output image or a feature map. Each ALU (Arithmetic Logic Unit) 1320 as a calculation component can calculate a respective feature value of each output point in a pixel block with a width of 2, a height of 2, and a channel number of 4. Optionally, each ALU 1320 can obtain the feature value of a corresponding input point from the SRAM 1310 via a data bus 1330, and calculate the feature value of a corresponding output point according to the feature value of the input point, thereby completing a calculation task.

[0149] In some alternative examples, as shown in Figure 13-2, the coordinates of the output point may be (7.3,7.7) and the coordinates of the four input points corresponding to the output point may be (7,7), (7,8), (8,7), and (8,8), respectively. Then, the target region tags matching each of the four input points may be calculated, and the calculated target region tags may be tag(3,3), tag(3,4), tag(4,3), and tag(4,4), respectively.

[0150] If a task of calculating the feature value of an output point with coordinates (7.3,7.7) is assigned to a target ALU (which may be an ALU 1320 in FIG. 13-1), the target area tag matching the input point with coordinates (7,7) is tag(3,3), and in FIG. 13-2, the on-chip buffer 1340 of the target ALU has buffered feature values ​​corresponding to tag(4,3), tag(3,4), tag(3,3), and tag(2,4), respectively, so that the feature value of the input point with coordinates (7,7) can be directly obtained from the on-chip buffer 1340 of the target ALU. In some circumstances, if the on-chip buffer 1340 of the target ALU does not have buffered feature values ​​corresponding to tag(3,3), the feature value of the input point with coordinates (7,7) can be obtained from the SRAM 1310 and stored in the on-chip buffer 1340 of the target ALU, and thus the feature value of the input point with coordinates (7,7) can be determined. The feature values ​​of the other input points can be determined in a similar manner, and the description is omitted here. If the feature values ​​of the four input points are feature value 1, feature value 2, feature value 3, and feature value 4, respectively, the feature value of the output point can be obtained by performing double linear interpolation on feature value 1 to feature value 4 after the target ALU.

[0151] In some alternative examples, as shown in FIG. 14, an offset amount corresponding to the output point can be obtained, and four input points corresponding to the output point can be determined based on the coordinates of the output point and the offset amount corresponding to the output point. Next, an input point among the four input points can be set as an input point P, and a Cache can be queried for whether or not the input point P is hit (corresponding to determining the information on the presence status of the target feature values ​​in the on-chip buffer), and if the query result is a hit (corresponding to the target feature values ​​being buffered in the on-chip buffer), the feature value of the input point P can be obtained from the Cache, and if the query result is a miss-hit (corresponding to the target feature values ​​not being buffered in the on-chip buffer), the feature value of the input point P can be obtained from the SRAM via the data bus. Then, it can be determined whether or not the traversal of the input point P is completed (i.e., it is determined whether or not all of the four input points are set as the input point P), and if the traversal is not completed, the input point P can be updated to another input point among the four input points, and if the traversal is completed, the ALU can perform a double linear interpolation on the feature values ​​of each of the four input points. Optionally, the SRAM, ALU, and Cache may all be arranged for neural network acceleration (e.g., convolutional neural network acceleration).

[0152] As described above, in the embodiment of the present disclosure, in order to effectively guarantee the calculation efficiency of the output feature data, by providing multiple ALUs, it is possible to realize parallel calculation with single instruction multiple threads (SIMT) with low hardware area overhead and cost. By setting multiple data buses for each ALU and introducing an LFU policy, it is possible to avoid interference in reading and writing between different ALUs and save bandwidth.

[0153] FIG. 15 is a schematic structural diagram of a high-speed calculation device for feature data according to some exemplary embodiments of the present disclosure. The device shown in FIG. a first determination module 1510 for determining, from the input feature data, input points corresponding to output points in the output feature data to be calculated; a second determination module 1520 for determining a target area tag matching the input point based on the position parameters of the input point determined by the first determination module 1510; a third determination module 1530 for determining presence status information in an on-chip buffer of a set of target feature values ​​to which the target area tag determined by the second determination module 1520 is mapped, the set of feature values ​​to which any area tag is mapped includes respective feature values ​​of a plurality of points in the input feature data that match the area tag; a fourth determination module 1540 for determining a target memory that matches the presence status information determined by the third determination module 1530 from the on-chip buffer and the on-chip main memory in which the input feature data is stored; a first calculation module 1550 for calculating feature values ​​of output points based on the feature values ​​of the input points in the target memory determined by the fourth determination module 1540; and a second calculation module 1560 for calculating output feature data based on the feature values ​​of the output points calculated by the first calculation module 1550.

[0154] In some alternative examples, if the target memory is an on-chip main memory, as shown in FIG. 16, the apparatus according to the embodiment of the present disclosure may: a fifth determination module 1570 for determining first address information indicating which bank, which slice and where the input point is located in the on-chip main memory, based on the position parameter of the input point and the size of the input feature data determined by the first determination module 1510, before the first calculation module 1550 calculates the feature value of the output point based on the feature value of the input point in the target memory determined by the fourth determination module 1540; The fifth determining module 1570 further includes a first obtaining module 1580 for obtaining the feature value of the input point in the on-chip main memory based on the first address information determined by the fifth determining module 1570.

[0155] In some alternative examples, the fifth determination module 1570: a first determination submodule for determining first information indicating a bank to which the input point belongs in the on-chip main memory based on a position parameter of the input point and a size of the input feature data; a second determination sub-module for determining second information indicating a slice to which the input point belongs in the on-chip main memory based on the position parameters of the input point, the size of the input feature data, and the first information determined by the first determination sub-module; a third determination submodule for determining third information indicating a storage location where the input point is located in the on-chip main memory based on the position parameters of the input point, the size of the input feature data, the first information determined by the first determination submodule, and the second information determined by the second determination submodule; and a fourth determination submodule for determining the first address information based on the first information determined by the first determination submodule, the second information determined by the second determination submodule, and the third information determined by the third determination submodule.

[0156] In some alternative examples, the first determining submodule: a first determining unit for determining a first width and a first height of a pixel block that can be accommodated by a single bank based on a first number of slices included in the single bank and a second number of storage locations included in the single slice; a second determining unit for determining a second width of the input feature data according to a size of the input feature data; and a third determination unit for determining the first information based on the position parameter of the input point, the first width determined by the first determination unit, the first height determined by the first determination unit, and the second width determined by the second determination unit.

[0157] In some alternative examples, the second determination submodule: a fourth determining unit for determining a first width and a first height of a pixel block that can be accommodated by the single bank based on a first number of slices included in the single bank and a second number of storage locations included in the single slice; a fifth determination unit for determining, based on the first information determined by the first determination sub-module, a first sum of first widths of pixel blocks that can be accommodated by each bank sorted before the bank to which the input point belongs; a sixth determining unit for determining a second width of the input feature data according to a size of the input feature data; a seventh determination unit for determining second information according to the position parameter of the input point, the first sum determined by the fifth determination unit, the first height determined by the fourth determination unit, and the second width determined by the sixth determination unit.

[0158] In some alternative examples, the third determining submodule: an eighth determining unit for determining a first width and a first height of a pixel block that can be accommodated by the single bank based on a first number of slices included in the single bank and a second number of storage locations included in the single slice; a ninth determination unit for determining, based on the first information determined by the first determination submodule, a first sum of first widths of pixel blocks that can be accommodated by each bank sorted before the bank to which the input point belongs; a tenth determination unit for determining, based on the second information determined by the second determination sub-module, a second sum of second heights of pixel blocks that can be accommodated by each slice that is sorted before the slice to which the input point belongs in the bank to which the input point belongs; an eleventh determining unit for determining a second width of the input feature data according to a size of the input feature data; a twelfth determination unit for determining third information according to the position parameter of the input point, the first sum determined by the ninth determination unit, the second sum determined by the tenth determination unit, the first height determined by the eighth determination unit, and the second width determined by the eleventh determination unit.

[0159] In some alternative examples, as shown in FIG. 16, an apparatus according to an embodiment of the present disclosure may include: a sixth determination module 1585 for determining, for remaining points other than the input point among the plurality of points matching the target area tag determined by the second determination module 1520, second address information indicating a bank to which the remaining point belongs, a slice to which the remaining point belongs, and a storage location to which the remaining point is located in the on-chip main memory based on the position parameters of the remaining point and the size of the input feature data; The system further includes a second acquisition module 1590 for acquiring the feature values ​​of the remaining points in the on-chip main memory based on the second address information determined by the sixth determination module 1585, thereby acquiring a target feature value group including the feature values ​​of the input point and the feature values ​​of the remaining points, and adding the target feature value group to the on-chip buffer.

[0160] In some alternative examples, the second acquisition module 1590 a fifth determining submodule for determining a numerical relationship between the number of feature values ​​present in the on-chip buffer and a preset number; a sixth determination sub-module for determining usage status information corresponding to each of the feature value groups in the on-chip buffer when the numerical relationship determined by the fifth determination sub-module satisfies a preset condition; a selection submodule for selecting a set of feature values ​​that satisfy a preset deletion condition from the on-chip buffer based on the usage information determined by the sixth determination submodule; The on-chip buffer memory includes a replacement submodule for replacing a set of feature values ​​that satisfies a preset deletion condition in the on-chip buffer and that have been deleted by the selection submodule, among the set of target feature values.

[0161] In some alternative examples, the first acquisition module 1580: a seventh determination submodule for determining a data bus corresponding to both the bank and the slice indicated by the first address information determined by the fifth determination module 1570; and an acquisition sub-module for acquiring the feature value of the input point from the storage location indicated by the first address information determined by the fifth determination module 1570 via the data bus determined by the seventh determination sub-module.

[0162] In some alternative examples, the second determination module 1520: an eighth determination sub-module for determining a target abscissa and a target ordinate of the input point based on the position parameters of the input point determined by the first determination module 1510; a ninth determination sub-module for determining a first tag parameter according to the target abscissa determined by the eighth determination sub-module and the first preset value; a tenth determination sub-module for determining a second tag parameter according to the target ordinate determined by the eighth determination sub-module and the first preset value; and an eleventh determination sub-module for determining the target area tag based on the first tag parameter determined by the ninth determination sub-module and the second tag parameter determined by the tenth determination sub-module.

[0163] In some alternative examples, as shown in FIG. 17, an apparatus according to an embodiment of the present disclosure may include: a seventh determination module 1710 for determining a plurality of calculation tasks for calculating feature values ​​of some output points in the output feature data to be calculated; an allocation module 1720 for allocating the different computation tasks determined by the seventh determination module 1710 to different computation components; and a control module 1730 for controlling different computing components such that the corresponding computing tasks assigned by the allocation module 1720 are executed in parallel.

[0164] In the device of the present disclosure, the various selectable embodiments, selectable embodiments, and selectable examples described above can all be flexibly selected and combined as necessary to achieve corresponding functions and effects, and will not be recited one by one in this disclosure.

[0165] FIG. 18 illustrates a block diagram of an electronic device 1800 including one or more processors 1810 and a memory 1820 in accordance with an embodiment of the present disclosure.

[0166] The processor 1810 may be a central processing unit (CPU) or other type of processing unit having data processing and / or instruction execution capabilities and may control the other components of the electronic device 1800 to perform desired functions.

[0167] The memory 1820 may include one or more computer program products, which may include various forms of computer-readable storage media, such as, for example, volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache). The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored in the computer-readable storage media, and the processor 1810 may execute the one or more computer program instructions to realize the methods of the embodiments of the present disclosure described above and / or other desired functions.

[0168] In one example, the electronic device 1800 may further include an input device 1830 and an output device 1840 connected to each other via a bus system and / or other form of connection (not shown).

[0169] The input device 1830 may further include, for example, a keyboard, a mouse, and the like.

[0170] The output device 1840 can output various types of information to the outside, and can include, for example, a display, a speaker, a printer, a communication network, and a remote output device connected thereto.

[0171] For simplicity, Fig. 18 shows only some of the components related to the present disclosure in the electronic device 1800, and omits components such as buses, input / output interfaces, etc. In addition, the electronic device 1800 may further include any other appropriate components according to a specific application situation.

[0172] In addition to the methods and apparatus described above, embodiments of the present disclosure may provide a computer program product including computer program instructions that, when executed by a processor, can cause the processor to perform the steps of the methods of each type of embodiment of the present disclosure described in the "Exemplary Methods" section above of this specification.

[0173] The computer program product may be produced with program code for carrying out operations of embodiments of the present disclosure in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and traditional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partly on the user computing device and partly on a remote computing device, or entirely on the remote computing device or a server.

[0174] Moreover, an embodiment of the present disclosure further provides a computer-readable storage medium having stored thereon computer program instructions which, when executed by a processor, cause the processor to perform steps of the method of each type of embodiment of the present disclosure as described in the "Exemplary Method" section herein above.

[0175] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0176] Although the basic principles of the present disclosure have been described above with reference to specific examples, the advantages, merits, effects, etc. mentioned in the present disclosure are merely illustrative and not limiting, and these advantages, merits, effects, etc. are not necessarily possessed by each embodiment of the present disclosure. In addition, the specific details of the above disclosure are merely illustrative and easy-to-understand actions and are not limiting, and the above details do not necessarily limit the present disclosure to be realized by the above specific details.

[0177] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A high-speed calculation method for feature data, comprising: determining, from the input feature data, input points corresponding to output points in the output feature data to be calculated; determining a target region tag matching the input point based on a position parameter of the input point; determining presence status information in an on-chip buffer of a set of target feature values ​​to which the target region tag is mapped, the set of feature values ​​to which any region tag is mapped including feature values ​​of a plurality of points in the input feature data that match the region tag; determining a target memory that matches the presence status information from the on-chip buffer and an on-chip main memory in which the input feature data is stored; calculating feature values ​​of the output points based on feature values ​​of the input points in the target memory; and calculating the output feature data based on the feature values ​​of the output points.

2. When the target memory is the on-chip main memory, prior to the step of calculating feature values ​​of the output points based on feature values ​​of the input points in the target memory, The high-speed calculation method includes: determining first address information for indicating a bank, a slice and a storage location in the on-chip main memory to which the input point belongs based on a position parameter of the input point and a size of the input feature data; 2. The high-speed computing method according to claim 1, further comprising: acquiring a feature value of the input point in the on-chip main memory based on the first address information.

3. determining first address information for indicating a bank, a slice, and a storage location in the on-chip main memory to which the input point belongs based on a position parameter of the input point and a size of the input feature data, the step comprising: determining first information for indicating a bank to which the input point belongs in the on-chip main memory based on a position parameter of the input point and a size of the input feature data; determining second information for indicating a slice to which the input point belongs in the on-chip main memory based on a position parameter of the input point, a size of the input feature data and the first information; determining third information for indicating a storage location where the input point is located in the on-chip main memory based on a position parameter of the input point, a size of the input feature data, the first information, and the second information; 3. The high speed calculation method according to claim 2, further comprising the step of: determining said first address information based on said first information, said second information, and said third information.

4. determining first information for indicating a bank to which the input point belongs in the on-chip main memory based on a position parameter of the input point and a size of the input feature data, determining a first width and a first height of a pixel block that can be accommodated by a single bank based on a first number of slices included in the single bank and a second number of storage locations included in the single slice; determining a second width of the input feature data based on a size of the input feature data; and determining the first information based on a position parameter of the input point, the first width, the first height, and the second width.

5. determining second information for indicating a slice to which the input point belongs in the on-chip main memory based on a position parameter of the input point, a size of the input feature data, and the first information, comprising: determining a first width and a first height of a pixel block that can be accommodated by a single bank based on a first number of slices included in the single bank and a second number of storage locations included in the single slice; determining a first sum of a first width of pixel blocks that can be accommodated by each bank that is sorted before the bank to which the input point belongs based on the first information; determining a second width of the input feature data based on a size of the input feature data; determining the second information based on position parameters of the input points, the first sum, the first height, and the second width.

6. determining third information for indicating a storage location in the on-chip main memory where the input point is located based on a position parameter of the input point, a size of the input feature data, the first information, and the second information, the step of: determining a first width and a first height of a pixel block that can be accommodated by a single bank based on a first number of slices included in the single bank and a second number of storage locations included in the single slice; determining a first sum of a first width of pixel blocks that can be accommodated by each bank that is sorted before the bank to which the input point belongs based on the first information; determining a second sum of second heights of pixel blocks that can be accommodated by each slice that is sorted before the slice to which the input point belongs in the bank to which the input point belongs based on the second information; determining a second width of the input feature data based on a size of the input feature data; determining the third information based on position parameters of the input points, the first sum, the second sum, the first height, and the second width.

7. The high-speed calculation method includes: determining, for remaining points other than the input point among the plurality of points matching the target area tag, second address information for indicating a bank, a slice, and a storage location in the on-chip main memory to which the remaining points belong, based on position parameters of the remaining points and a size of the input feature data; 3. The high-speed computing method according to claim 2, further comprising the step of acquiring the feature values ​​of the remaining points in the on-chip main memory based on the second address information, thereby acquiring the target feature value group including the feature values ​​of the input point and the feature values ​​of the remaining points, and adding this target feature value group to the on-chip buffer.

8. The step of adding the set of target feature values ​​to the on-chip buffer comprises: determining a numerical relationship between the number of sets of feature values ​​present in the on-chip buffer and a preset number; determining usage status information corresponding to each of the feature value groups in the on-chip buffer when the numerical relationship satisfies a preset condition; selecting, from the on-chip buffer, a group of feature values ​​that satisfy a preset deletion condition based on the information on the usage state; 8. The high-speed computing method according to claim 7, further comprising the step of replacing a set of feature values ​​in the on-chip buffer that satisfies the preset deletion condition with the set of target feature values.

9. The step of obtaining the feature value of the input point in the on-chip main memory based on the first address information includes: determining a data bus corresponding to both the bank and the slice designated by the first address information; 3. The high-speed computing method according to claim 2, further comprising the step of: acquiring the feature value of the input point from a storage location designated by the first address information via the data bus.

10. determining a target region tag matching the input point based on a position parameter of the input point, determining a target abscissa and a target ordinate of the input point based on a position parameter of the input point; determining a first tag parameter based on the target abscissa and a first preset value; determining a second tag parameter based on the target ordinate and the first preset value; 10. The high speed calculation method according to claim 1, further comprising: determining the target area tag based on the first tag parameter and the second tag parameter.

11. A high-speed calculation device for feature data, a first determination module for determining, from the input feature data, input points corresponding to output points in the output feature data to be calculated; a second determination module for determining a target area tag matching the input point based on the position parameters of the input point determined by the first determination module; a third determination module for determining information on the presence status in an on-chip buffer of a target feature value group to which the target area tag determined by the second determination module is mapped, the feature value group to which any area tag is mapped includes each feature value of a plurality of points in the input feature data that match the area tag; a fourth determination module for determining a target memory that matches the presence status information determined by the third determination module from the on-chip buffer and the on-chip main memory in which the input feature data is stored; a first calculation module for calculating feature values ​​of the output points based on the feature values ​​of the input points in the target memory determined by the fourth determination module; a second calculation module for calculating the output feature data based on the feature values ​​of the output points calculated by the first calculation module.

12. 1. A computer-readable storage medium, comprising: A computer-readable storage medium storing a computer program for executing the high-speed calculation method for feature data according to any one of claims 1 to 9.

13. An electronic device, A processor; a memory for storing instructions executable by the processor; The electronic device, characterized in that the processor is configured to realize a high-speed calculation method for feature data according to any one of claims 1 to 9 by reading the executable instructions from the memory and executing them.

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