Array substrate, display panel and method for manufacturing array substrate

Abstract

To achieve both low wiring resistance and stabilization of TFT characteristics.SOLUTION: An array substrate 30 comprises a semiconductor film 33 arranged on an upper layer side of an insulating substrate 31, a gate insulating film 37 arranged on an upper layer of the semiconductor film 33, a gate electrode 32G arranged on an upper layer of the gate insulating film 37, an interlayer insulating film 38 arranged on an upper layer of the gate electrode 32G, a TFT 32 having a source electrode 32S and a drain electrode 32D, which are arranged on an upper layer side through the interlayer insulating film 38 with respect to the gate electrode 32G, and a gate wiring 36G connected to the gate electrode 32G. The gate electrode 32G and gate wiring 36G have an Al film 71 and a protective metal film 72 that covers the entire surface of the Al film 71, which is made of a metal material with a higher melting point than that of Al.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present technology relates to an array substrate, a display panel, and a method for manufacturing an array substrate. [Background technology]

[0002] It is known that TFTs (thin film transistors) are used as switching elements in display panels such as liquid crystal panels and organic EL (electro-luminescence) panels. TFTs are formed by laminating various thin films on an array substrate (active matrix substrate, TFT substrate) that constitutes the display panel. Patent Document 1 discloses an example of a method for manufacturing TFTs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-8027 A

[0004] The TFT described in Patent Document 1 is a so-called top-gate TFT, and the gate electrode and gate wiring have a three-layer structure with titanium (Ti) layers arranged above and below an aluminum (Al) layer. While the use of an aluminum layer can reduce wiring resistance, when the aluminum layer is subjected to heat treatment in the manufacturing process, defects (such as so-called hillocks) are likely to occur due to moisture diffusion from the gate insulating film and thermal reaction with the interlayer insulating film. Therefore, the TFT described in Patent Document 1 is said to be able to suppress the occurrence of defects in the aluminum layer even when heat treatment is performed at 400°C in the manufacturing process by sandwiching the aluminum layer between titanium layers with a high melting point. Summary of the Invention [Problem to be solved by the invention]

[0005] However, the heat treatment temperature in the manufacturing process of TFTs may be too low at 400°C. For example, to enlarge the screen of an in-vehicle liquid crystal panel with a touch panel function, high stability is required for the TFT characteristics, but if the heat treatment temperature is less than 450°C, the TFT characteristics may vary and become unstable. More specifically, when a polysilicon film (LTPS, Low Temperature Polycrystalline Silicon) is used as the semiconductor film of the TFT, if the heat treatment temperature is less than 450°C, the recovery of the crystallinity of the polysilicon film may be insufficient, and defects may remain. In reality, TFTs having semiconductor films containing defects have deteriorated and unstable TFT characteristics.

[0006] The technology described in this specification was completed based on the above-mentioned circumstances, and aims to achieve both low wiring resistance and stabilization of TFT characteristics. [Means for solving the problem]

[0007] (1) An array substrate related to the technology described in the present specification comprises a thin film transistor having a semiconductor film arranged on the upper layer side of an insulating substrate, a gate insulating film arranged on the semiconductor film, a gate electrode arranged on the gate insulating film, an interlayer insulating film arranged on the gate electrode, and a source electrode and a drain electrode arranged on the upper layer side of the gate electrode with the interlayer insulating film interposed therebetween, and a gate wiring continuous with the gate electrode, wherein the gate electrode and the gate wiring have an aluminum film and a protective metal film made of a metal material having a higher melting point than aluminum and covering the entire surface of the aluminum film.

[0008] (2) In addition to the above (1), the array substrate may be configured such that the protective metal film includes an overlapping portion that overlaps with the aluminum film and a protruding portion that protrudes from the overlapping portion and does not overlap with the aluminum film, the semiconductor film is an impurity semiconductor film, and the impurity concentration of the semiconductor film is different in a first region that overlaps with the overlapping portion of the protective metal film and a second region that overlaps with the protruding portion of the protective metal film.

[0009] (3) In addition to the above (2), the array substrate may have a structure in which the semiconductor film includes a channel region overlapping with the aluminum film of the gate electrode and the overlapping portion of the protective metal film, high-concentration impurity regions arranged on both sides of the channel region, each of which is connected to one of the source electrode or the drain electrode, and a low-concentration impurity region arranged at least either between the channel region and the source region or between the channel region and the drain region, overlapping with the protrusion portion of the protective metal film.

[0010] (4) In addition to any one of (1) to (3) above, the array substrate may be such that the semiconductor film is a polysilicon film.

[0011] (5) A display panel related to the technology described in this specification includes an array substrate as described in any one of (1) to (4) above, an opposing substrate arranged opposite the array substrate with an internal space between them, and a liquid crystal layer sealed in the internal space.

[0012] (6) A method for manufacturing an array substrate according to the technology described in the present specification includes forming a semiconductor film of a thin film transistor on an upper layer side of an insulating substrate, forming a gate insulating film of the thin film transistor on the semiconductor film, forming a first metal film on the gate insulating film, the first metal film being a part of the gate electrode of the thin film transistor and a part of the gate wiring connected to the gate electrode and made of a metal material having a higher melting point than aluminum, forming an aluminum film on the first metal film to be a part of the gate electrode and a part of the gate wiring, etching a base layer including the formed first metal film and the aluminum film to pattern it, forming a second metal film on the patterned base layer, the second metal film being a part of the gate electrode and a part of the gate wiring and made of a metal having a higher melting point than aluminum, etching and patterning the formed second metal film so as to have a planar size larger than that of the base layer, forming the gate electrode and the gate wiring having the base layer and the second metal film, and performing a heat treatment process of heating at 450° C. or more after the formation of the gate electrode and the gate wiring.

[0013] (7) In addition to the above (6), the method for manufacturing the array substrate may further include a step of introducing an impurity into the semiconductor film after the formation of the gate electrode and before the heat treatment step, in which an impurity is introduced into the semiconductor film at an accelerated rate, and in which surfaces of the gate electrode and the gate wiring are exposed and not covered by anything.

[0014] (8) In addition to the above (6) or (7), the method for manufacturing the array substrate may further include the step of: the semiconductor film is a polysilicon film; and the heat treatment step restores crystallinity of the polysilicon film deteriorated by the impurity introduction step. Effect of the Invention

[0015] According to the technology described in this specification, it is possible to achieve both low wiring resistance and stable TFT characteristics. [Brief description of the drawings]

[0016] [Figure 1] 1 is a schematic plan view of a liquid crystal panel according to a first embodiment; [Diagram 2] Cross-section of a liquid crystal panel [Diagram 3] Equivalent circuit diagram of a display pixel [Figure 4] Cross-sectional view of the TFT area in the GDM circuit section of the array substrate [Diagram 5] Cross-sectional view of the TFT area in the display area of ​​the array substrate [Figure 6A] 5A to 5C are diagrams showing a manufacturing process of the array substrate shown in FIG. [Figure 6B] FIG. 6B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 6A; [Figure 6C] FIG. 6B is a diagram showing a manufacturing process of the array substrate; [Figure 6D] FIG. 6C is a diagram showing a manufacturing process of the array substrate; [Figure 6E] FIG. 6C is a diagram showing a manufacturing process of the array substrate, subsequent to FIG. 6D. [Figure 6F] FIG. 6C is a diagram showing a manufacturing process of the array substrate, subsequent to FIG. 6E. [Figure 6G] FIG. 6F shows a manufacturing process of the array substrate. [Figure 6H] 6G, showing the manufacturing process of the array substrate (an enlarged cross-sectional view of the TFT area in FIG. 4) [Figure 7] Cross-sectional microscope photograph of the vicinity of the gate electrode of the array substrate according to Comparative Example 1 [Figure 8A] FIG. 1 is a diagram showing a manufacturing process of an array substrate according to Comparative Example 1. [Figure 8B] FIG. 8B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 8A; [Figure 8C] FIG. 8C is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 8B. [Figure 9] 1 is a cross-sectional view of a TFT and its surroundings on an array substrate according to a second embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] <Embodiment 1> A liquid crystal panel 10 (one example of a display panel) according to embodiment 1 will be described with reference to Fig. 1 to Fig. 6H. Note that some of the drawings show X-axis, Y-axis, and Z-axis, and each axis direction is drawn to be a common direction in each drawing. Also, the +Z-axis direction is the front side, and the -Z-axis direction is the back side.

[0018] As shown in Fig. 1, the liquid crystal panel 10 is divided into a display area (active area) AA that can display an image and is located at the center, and a non-display area (non-active area) NAA that is located on the outer periphery of the display area AA and has a frame-like (picture frame-like) shape in a plan view. In Fig. 1, the dashed line represents the outer shape of the display area AA, and the area outside the dashed line is the non-display area NAA. The planar shape of the liquid crystal panel 10 is not limited, but in this embodiment, the liquid crystal panel 10 has a vertically long rectangular shape as a whole, with the short side direction coinciding with the X-axis direction, the long side direction coinciding with the Y-axis direction in each drawing, and the plate thickness direction coinciding with the Z-axis direction.

[0019] In order to drive the liquid crystal panel 10, a source driver 12 and two GDM circuit (Gate Driver Monolithic circuit) units 14 are provided in the non-display area NAA of the liquid crystal panel 10. The source driver 12 is an LSI that incorporates a source drive circuit. The GDM circuit unit 14 is a gate drive circuit monolithically formed on the array substrate 30. The source driver 12 and the GDM circuit unit 14 are connected to a flexible substrate 13, one end of which is mounted on the non-display area NAA. The other end of the flexible substrate 13 is connected to an external control substrate that is a supply source of various signals.

[0020] As shown in Fig. 2, the liquid crystal panel 10 has two opposing substrates 20, 30 (one example of a display panel substrate), a liquid crystal layer 18, and a sealing section 50. The liquid crystal layer 18 is sandwiched between the two substrates 20, 30, and contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. The sealing section 50 is disposed in the non-display area NAA so as to surround the liquid crystal layer 18, and is interposed between the two substrates 20, 30 to seal the liquid crystal layer 18 while maintaining a cell gap of the thickness of the liquid crystal layer 18. A backlight device that irradiates light to the liquid crystal panel 10 is provided on the rear side of the liquid crystal panel 10 (the array substrate 30 side).

[0021] Of the two substrates 20, 30, the front side is an opposing substrate (color filter substrate, CF substrate) 20, and the back side is an array substrate 30. In the opposing substrate 20 and the array substrate 30, various films are laminated on the liquid crystal layer 18 side of a glass substrate 31 (an example of an insulating substrate). Polarizing plates 10C, 10D are attached to the outer surface sides (opposite the liquid crystal layer 18) of both substrates 20, 30, respectively.

[0022] A large number of color filters are arranged in a matrix in the display area AA of the counter substrate 20. The color filters are arranged in a predetermined order with three colored films of R (red), G (green), and B (blue). In the array substrate 30, pixel electrodes 34 (described later) are arranged at positions facing each of the colored films. Each of the R, G, and B colored films and a set of three pixel electrodes 34 facing each of them constitutes one display pixel PX, which is a display unit.

[0023] As shown in FIG. 3, in the display area AA of the array substrate 30, a large number of TFTs 32, which are switching elements, and pixel electrodes 34 are arranged in a matrix (rows and columns). Gate wiring (scanning lines) 36G and source wiring (data lines, signal lines) 36S are arranged in a lattice shape so as to surround the TFTs 32 and the pixel electrodes 34. As shown in FIG. 1, the left and right ends of the gate wiring 36G extend to the non-display area NAA and are connected to at least one of the two GDM circuit units 14. A gate voltage (scanning signal) is supplied to the gate wiring 36G from the GDM circuit unit 14. The source wiring 36S is connected to the source driver 12 via a first lead-out wiring 61 in the non-display area NAA. A data voltage (image signal) is supplied to the source wiring 36S from the source driver 12.

[0024] 3, the TFT 32 has a gate electrode 32G connected to a gate line 36G, a source electrode 32S connected to a source line 36S, and a drain electrode 32D connected to a pixel electrode 34. The TFT 32 also has a semiconductor film 33 having one end connected to the source electrode 32S and the other end connected to the drain electrode 32D. The TFT 32 is driven based on a gate signal supplied to the gate line 36G. When a source signal is supplied to the source line 36S during a gate writing period in which the gate signal is equal to or higher than a gate threshold voltage, a current flows between the source electrode 32S and the drain electrode 32D via a channel region 33C of the semiconductor film 33, and the pixel electrode 34 is charged to a potential according to the source signal.

[0025] When a potential difference occurs between the pixel electrode 34 and the common electrode 35 to which a reference potential is applied, a fringe electric field including a component along the plate surface (XY plane) of the array substrate 30 as well as a component in the normal direction (Z-axis direction) to the plate surface of the array substrate 30 is applied to the liquid crystal layer 18. This fringe electric field changes the alignment state of the liquid crystal molecules in the liquid crystal layer 18. As a result, the transmittance of light passing through the liquid crystal panel 10 changes, and the display state of the display pixel PX changes. Note that the driving method of the liquid crystal panel 10 is not limited to FFS (Fringe Field Switching) mode, and may be other methods such as IPS (In Plane Switching) mode.

[0026] The liquid crystal panel 10 also has a touch panel function that detects the position where the user inputs. The liquid crystal panel 10 is an in-cell type touch panel that has a built-in configuration for realizing the touch panel function. The liquid crystal panel 10 uses a self-capacitance method as a detection method, but a mutual capacitance method may also be used.

[0027] As shown in Fig. 1, the common electrode 35 is divided into rectangular shapes and arranged in a matrix in the display area AA, and also serves as a sensor electrode for detecting an input position. When a user brings a finger (a position input object that is a conductor) close to the surface (display surface) of the liquid crystal panel 10, a capacitance is formed between the finger and the common electrode 35, and the input position is detected based on the change in the capacitance. The common electrode (also sensor electrode) 35 is connected to a position detection circuit in the source driver 12 via a sensor wiring 40 extending along the Y-axis direction in the display area AA and a second lead wiring 62 in the non-display area NAA. The sensor wiring 40 supplies a reference potential signal related to the display function and a position detection signal related to the touch panel function to the common electrode 35 at different timings.

[0028] An example of a layer structure of the array substrate 30 described above will be described with reference to Fig. 4 and Fig. 5. In the array substrate 30, a base coat film 45, a semiconductor film 33, a gate insulating film 37, a gate electrode 32G, a first interlayer insulating film 38, a source electrode 32S and a drain electrode 32D, and a planarizing film 39 are laminated in this order on a glass substrate 31 in the vicinity of the TFT 32 of the GDM circuit section 14, as shown in Fig. 4. In addition, in the array substrate 30, a light-shielding film 44, a base coat film 45, a semiconductor film 33, a gate insulating film 37, a gate electrode 32G, a first interlayer insulating film 38, a source electrode 32S and a drain electrode 32D, a planarizing film 39, a second interlayer insulating film 41, a sensor wiring 40, a third interlayer insulating film 42, a common electrode 35, a fourth interlayer insulating film 43, and a pixel electrode 34 are laminated in this order on a glass substrate 31 in the vicinity of the TFT 32 of the display area AA, as shown in Fig. 5. Furthermore, an alignment film is applied to the uppermost layer of the array substrate 30 (the layer closest to the liquid crystal layer 18) so as to cover these various laminated films.

[0029] The base coat film 45, the gate insulating film 37, the first interlayer insulating film 38, the second interlayer insulating film 41, the third interlayer insulating film 42, and the fourth interlayer insulating film 43 are made of silicon nitride (SiN x The base coat film 45 is made of an inorganic insulating material such as silicon oxide (SiO2) or silicon dioxide (SiO2). x The gate insulating film 37 is, for example, a SiN x The first interlayer insulating film 38 is, for example, a SiN x The second interlayer insulating film 41 and the third interlayer insulating film 42 are, for example, a SiN x The fourth interlayer insulating film 43 is, for example, a 200 nm-thick SiN x It is called a membrane.

[0030] The planarization film 39 is made of a transparent organic insulating material such as an acrylic resin (PMMA, etc.) or a polyimide resin, and its thickness is greater than that of other insulating films (such as the first interlayer insulating film 38). The planarization film 39 planarizes the surface of the display area AA of the array substrate 30.

[0031] The light-shielding film 44 is made of a metal film, for example, a molybdenum (Mo) film with a thickness of about 50 nm. The light-shielding film 44 is disposed below the semiconductor film 33 via a base coat film 45, and overlaps with the semiconductor film 33. By providing the light-shielding film 44, it is possible to suppress fluctuations in the characteristics of the TFT 32 that may occur when the semiconductor film 33 is irradiated with light from a backlight device.

[0032] The semiconductor film 33 is disposed below the gate electrode 32G via the gate insulating film 37, and overlaps with the gate electrode 32G. The semiconductor film 33 is an impurity semiconductor film in which an intrinsic semiconductor film is doped with impurities, and is made of a polysilicon film in this embodiment. The semiconductor film 33 has a channel region 33C (an example of a first region), a source region 33S, a drain region 33D, and a low-concentration impurity region 33L (an example of a second region). The impurity concentrations of the semiconductor film 33 are formed to be different in the channel region 33C, the low-concentration impurity region 33L, and the high-concentration impurity regions (the source region 32S and the drain region 32D).

[0033] The channel region 33C of the semiconductor film 33 overlaps with an aluminum (Al) layer 71 (described later) of the gate electrode 32G, and is prevented from being doped with impurities during the manufacturing process. The source region 33S and the drain region 33D are disposed on both the left and right sides of the channel region 33C, and are doped with impurities at a high concentration during the manufacturing process. The source region 33S and the drain region 33D are connected to the source electrode 32S and the drain electrode 32D, respectively.

[0034] The low-concentration impurity region 33L of the semiconductor film 33 is formed between the channel region 33C and the source region 33S, and between the channel region 33C and the drain region 33D. The low-concentration impurity region 33L is doped with impurities at a lower concentration than the channel region 33C and the source region 33S during the manufacturing process. Therefore, the TFT 32 is an n-channel MOSFET having an LDD (Lightly Doped Drain) structure. The low-concentration impurity region 33L according to this embodiment overlaps with a protruding portion 72B of a protective metal film 72 of the gate electrode 32G, which will be described later.

[0035] The semiconductor film 33 may be made of an oxide semiconductor material (for example, IGZO (Indium Gallium Zinc Oxide)) or an amorphous silicon film. When a polysilicon film is used as in this embodiment, carrier mobility can be improved, so that the planar size of the TFT 32 can be reduced, and power consumption can be reduced by narrowing the frame and reducing the size of the non-display area NAA. In addition, the switching speed of the TFT 32 can be increased, so that display defects such as flicker and afterimages in the display area AA can be prevented from occurring.

[0036] The gate electrode 32G and the gate wiring 36G are disposed on the gate insulating film 37. As shown in an example of the gate electrode 32G in Figures 4 and 5, the gate electrode 32G and the gate wiring 36G have an Al film 71 and a protective metal film 72. The protective metal film 72 is made of a metal material (e.g., Mo or Ti) having a higher melting point than at least Al, and covers and protects the entire surface (all of the upper, lower, and side surfaces) of the Al film 71.

[0037] As shown in FIG. 4 and FIG. 5, the protective metal film 72 has an overlapping portion 72A and a protruding portion 72B. The overlapping portion 72A overlaps with the Al film 71 and the channel region 33C of the semiconductor film 33. The protruding portion 72B protrudes from the overlapping portion 72A along the plate surface direction (XY plane) and does not overlap with the Al film 71 and the channel region 33C of the semiconductor film 33. The protruding portion 72B according to this embodiment protrudes from the overlapping portion 72A to both the source electrode S32 side (left side of the paper) and the drain electrode 32D side (right side of the paper), but may protrude to only one of them as described in the second embodiment. The specific materials and film thicknesses of the gate electrode 32G and the gate wiring 36G will be described in detail in the manufacturing method described later.

[0038] The source electrode 32S, the drain electrode 32D, the source wiring 36S, and the sensor wiring 40 are made of metal films. The source electrode 32S, the drain electrode 32D, and the source wiring 36S are disposed on the upper layer side of the gate electrode 32G and the gate wiring 36G via the first interlayer insulating film 38. The source electrode 32S, the drain electrode 32D, and the source wiring 36S are, for example, a three-layer film in which a Ti film with a thickness of about 50 nm, an Al film with a thickness of about 350 nm, and a Ti film with a thickness of about 100 nm are laminated in this order from the lower layer side. The sensor wiring 40 is disposed on the upper layer of the second interlayer insulating film 41. The sensor wiring 40 is, for example, a three-layer film in which a Mo film with a thickness of about 100 nm, an Al film with a thickness of about 300 nm, and a Mo film with a thickness of about 30 nm are laminated in this order from the lower layer side.

[0039] The pixel electrode 34 and the common electrode 35 are made of a transparent electrode film (e.g., ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide)). As shown in FIG. 5, the pixel electrode 34 penetrates between the pixel electrode 34 and the drain electrode 32D (specifically, the planarization film 39, the second interlayer insulating film 41, the third interlayer insulating film 42, and the fourth interlayer insulating film 43) and is connected to the drain electrode 32D.

[0040] Next, a method for manufacturing the array substrate 30 will be described. The manufacturing process after the formation of the base coat film 45 and before the formation of the planarizing film 39 will be described in detail below with reference to FIGS. 6A to 6H, taking as an example the lamination process of the cross-sectional portion shown in FIG. 4.

[0041] A known manufacturing process can be used as a method for patterning and forming the semiconductor film 33 on the base coat film 45. More specifically, after an amorphous silicon film is formed on the base coat film 45 by a CVD method or the like, a heat treatment is performed at about 450°C in a nitrogen atmosphere. This dehydrogenation heat treatment reduces the hydrogen concentration contained in the amorphous silicon film. The amorphous silicon film with the reduced hydrogen concentration is crystallized by ELA (Excimer Laser Annealing) to form a polysilicon film. The polysilicon film is then patterned into a predetermined shape to form the semiconductor film 33 before impurity doping as shown in FIG. 6A.

[0042] A gate insulating film 37 is formed on the patterned semiconductor film 33. A lower first metal film L1, an Al film L2, and an upper first metal film L3 are formed in this order on the formed gate insulating film 37 (FIG. 6A). The first metal films L1 and L3 contact and protect the upper and lower surfaces of the Al film L2 (Al film 71 to be patterned in a later process). The Al film L2 has a thickness of about 300 nm, and the first metal films L1 and L3 are made of Mo having a thickness of about 20 nm, for example.

[0043] Next, the laminated first metal films L1, L3 and Al film L2 are patterned. The patterned three-layer film L1, L2, L3 becomes the base layer 32G1 of the gate electrode 32G (FIG. 6B). A second metal film L4 is formed on the base layer 32G1 of the formed gate electrode 32G (FIG. 6C). The second metal film L4 is made of Mo with a thickness of about 500 mm, for example. The formed second metal film L4 is patterned so that its planar size is larger than that of the base layer 32G1, forming a cover layer 32G2 that covers the base layer 32G1 from above (FIG. 6D).

[0044] 6D, when the gate electrode 32G is formed in this manner, the patterned Al film L2 of the base layer 32G1 becomes the Al film 71 of the gate electrode 32G. Moreover, the patterned first metal films L1 and L3 of the base layer 32G1 and the cover layer 32G2 (patterned second metal film L4) become the protective metal film 72 of the gate electrode 32G.

[0045] However, the method for forming the gate electrode 32G is not limited to the above-mentioned manufacturing process. For example, the first upper metal film L3 may not be formed, and the two-layer film of the first lower metal film L1 and the AL film L2 may be patterned to form the base layer 32G1, and the cover layer 32G2 may be formed to cover the base layer 32G1 from above.

[0046] Next, the semiconductor film 33 is doped with impurities by performing impurity ion implantation using the formed gate electrode 32G as a mask (FIG. 6E, impurity introduction step). In the impurity introduction step, the surface of the gate electrode 32G is not covered with anything and is exposed. The degree of impurity injection into the semiconductor film 33 by the impurity introduction step varies depending on the positional relationship with the gate electrode 32G. More specifically, ions are injected at a high concentration into the region of the semiconductor film 33 that does not overlap with the gate electrode 32G, and these become the source region 33S and the drain region 33D with the highest impurity concentration (FIG. 6F). In addition, the region of the semiconductor film 33 that overlaps with the base layer 32G1 (Al film 71) of the gate electrode 32G is covered with a thick metal film from above, so that the introduction of the impurity concentration is prevented and the channel region 33C with the lowest impurity concentration is formed. On the other hand, in the semiconductor film 33, the region overlapping with the protruding portion 72B of the protective metal film 72 of the gate electrode 32G becomes a low-concentration impurity region 33L into which impurities are introduced at a low concentration, since the thickness of the metal film covering it from above is thinner than that of the channel region 33C (Figure 6F).

[0047] After doping the semiconductor film 33 with impurities, a first interlayer insulating film 38 is formed on the gate electrode 32G (FIG. 6G). After forming the first interlayer insulating film 38, an activation heat treatment is performed (heat treatment step) to restore (activate) the crystallinity of the semiconductor film 33 (polysilicon film) that was destroyed by the impurity doping. In this activation heat treatment step, by heating at a high heat treatment temperature of 450° C. or higher, it is possible to prevent the crystallinity of the polysilicon film from being insufficiently restored, resulting in the remaining of defects.

[0048] After the activation heat treatment process, the source electrode 32S and the drain electrode 32D are patterned on the first interlayer insulating film 38 (FIG. 6H). The source electrode 32S and the drain electrode 32D can be patterned using a known manufacturing process. The source electrode 32S and the drain electrode 32D are connected to the source region 33S and the drain region 33D of the semiconductor film 33 by contact parts that penetrate between the layers.

[0049] Next, the effects of the array substrate 30 and the manufacturing method of the array substrate 30 will be described. The gate electrode 32G and the gate wiring 36G according to this embodiment have an Al film 71 with low resistance and a protective metal film 72 made of a high melting point material. The Al film 71 reduces the wiring resistance, thereby enabling high-speed signal transmission. Furthermore, by covering the entire surface of the Al film 71 with the protective metal film 72, the Al film 71 can be protected by the protective metal film 72 even when heated at 450°C or higher in the activation heat treatment process of the manufacturing process.

[0050] If the gate electrode 32G and the gate wiring 36G were made of only the base layer 32G1 as in the conventional case, and the side surface of the Al film 71 was not covered with the protective metal film 72, the side surface of the Al film 71 would thermally shrink or melt due to a thermal reaction with the first interlayer insulating film 38, as shown in the gate electrode 932G according to Comparative Example 1 in Fig. 7. As a result, hillocks (defective protrusions) would be formed in the Al film 71, causing unexpected leakage.

[0051] On the other hand, if the heating temperature of the activation heat treatment process is lowered to less than 450°C (e.g., 400°C) in order to prevent such problems from occurring in the Al film 71, the crystallinity of the semiconductor film 33 destroyed by impurity doping will not be fully restored, and the TFT characteristics will deteriorate and become unstable.

[0052] In contrast, according to this embodiment, since the side surfaces of the Al film 71 are covered with the protective metal film 72, even when the Al film 71 is heated at 450° C. or higher, it is possible to suppress the Al film 71 from thermally shrinking or from reacting thermally with the first interlayer insulating film 38 and melting. As a result, the activation heat treatment process for the semiconductor film 33 can be performed at 450° C. or higher without causing any problems in the Al film 71, and the TFT characteristics of the semiconductor film 33 can be stabilized. Therefore, according to the array substrate 30 and the manufacturing method for the array substrate 30, it is possible to achieve both low resistance of the wiring and stable TFT characteristics.

[0053] Furthermore, since the entire surface of the Al film 71 is covered with the protective metal film 72, it becomes easier to prevent foreign matter from being mixed into the Al film 71 during the manufacturing process and to prevent defects in pattern formation.

[0054] The protective metal film 72 includes an overlapping portion 72A that overlaps with the Al film 71, and a protruding portion 72B that protrudes from the overlapping portion 72A and does not overlap with the Al film 71. In the impurity doping in the manufacturing process, the protruding portion 72B of the protective metal film 72 is used as a mask, which makes it possible to easily form the low-concentration impurity region 33L of the semiconductor film 33. As a result, it is possible to easily form the TFT 32 with an LDD structure in which the impurity concentrations of the semiconductor film 33 are different between the channel region 33C, the low-concentration impurity region 33L, and the high-concentration impurity regions (the source region 32S and the drain region 32D).

[0055] If the gate electrode 932G is formed only from the base layer 32G1 as in the conventional case and the protruding portion 72B of the protective metal film 72 is not provided, it is necessary to perform two impurity ion implantations (doping) to form a TFT with an LDD structure. For example, the first impurity ion implantation is performed using the gate electrode 932G as a mask after the manufacturing process shown in FIG. 6C (FIG. 8A). At this time, the region of the semiconductor film 33 that overlaps with the base layer 32G1 (Al film 71) of the gate electrode 932G is covered from above with a thick metal film, so that the introduction of the impurity concentration is prevented, and the region becomes the channel region 33C with the lowest impurity concentration. On the other hand, the semiconductor film 33 other than the channel region 33C becomes a low-concentration impurity region 33L into which the impurity is introduced.

[0056] After the first impurity doping, a photoresist L9 is formed to cover the upper and side surfaces of the gate electrode 932G, and a second impurity ion implantation is performed using the photoresist L9 as a mask, thereby performing a second impurity doping into the semiconductor film 33 (FIG. 8B). The regions of the semiconductor film 33 that do not overlap with the photoresist L9 are again ion-implanted, and become the source region 33S and the drain region 33D with the highest impurity concentration. Thereafter, the photoresist L9 is removed (FIG. 8C), and the first interlayer insulating film 38 is formed as in FIG. 6G, and the source electrode 32S and the drain electrode 32D are formed as in FIG. 6H, resulting in a TFT with an LDD structure.

[0057] Therefore, if the protruding portion 72B of the protective metal film 72 is not provided, it is necessary to perform impurity doping twice and form and remove the photoresist L9 in order to form the low concentration impurity region 33L and the high concentration impurity region (the source region 33S and the drain region 33D) as described above. In this regard, according to the present embodiment, by utilizing the protruding portion B2 of the protective metal film 72 as a mask, it is possible to perform impurity doping only once and the process of forming and removing the photoresist L9 is also unnecessary.

[0058] Although the above example shows a case where a polysilicon film is used for the semiconductor film 33, this technology is also effective when performing impurity doping or heat treatment on an oxide semiconductor. In particular, the heat treatment temperature of an oxide semiconductor has a large effect on the TFT characteristics, and by covering the entire surface of the Al film 71 with the protective metal film 72, there is no restriction on the heat treatment temperature, making it easier to improve and stabilize the TFT characteristics.

[0059] <Embodiment 2> A TFT 132 of an array substrate 130 according to the second embodiment will be described with reference to Fig. 9. The TFT 132 differs from the first embodiment in that a protruding portion 172B of a protective metal film 172 of a gate electrode 132G protrudes from an overlapping portion 72A to only one side of the drain electrode 32D (the right side of the drawing). In the second embodiment, the same configurations, actions, and effects as those in the first embodiment are denoted by the same reference symbols, and duplicated descriptions will be omitted.

[0060] By providing the protruding portion 172B of the protective metal film 172 only on one side, the low concentration impurity region 33L of the semiconductor film 133 can be formed only on the side where the protruding portion 172B is provided. In the case of this embodiment, since the protruding portion 172B is provided only on the drain electrode 32D side, the low concentration impurity region 33L is formed only between the channel region 33C and the drain region 33D. This allows the TFT 132 to be space-saving. In particular, since the TFT 132 provided in the GDM circuit unit 14 has a regulated current direction, the low concentration impurity region 33L is formed on the drain region 33D side, where degradation in reliability is a concern, to ensure performance, while not forming the low concentration impurity region 33L on the source region 33S side to save space.

[0061] <Other embodiments> The technology described in this specification is not limited to the embodiments described above with reference to the drawings, and for example, the following embodiments are also included within the technical scope of the present invention.

[0062] (1) The layer structure and layout pattern of the array substrate 30 are not limited to those shown in the drawings. The TFTs 32 and 132 formed in the GDM circuit section 14 and the display area AA do not have to be of the same type, and may be formed by combining types of TFTs with different structures and semiconductor film materials. The TFTs 32 and 132 may also be of a CMOS type that combines n-channel and p-channel types.

[0063] (2) Depending on the driving method of the liquid crystal panel 10, the common electrode 35 may be provided on the counter substrate 20. [Explanation of symbols]

[0064] 10... liquid crystal panel (display panel), 18... liquid crystal layer, 20... opposing substrate, 30, 130... array substrate, 31... glass substrate (insulating substrate), 32, 132... TFT (thin film transistor), 32D... drain electrode, 32G, 132G... gate electrode, 32G1... base layer, 32S... source electrode, 33, 133... semiconductor film, 33C... channel region (first region), 33D... drain region, 33S... source region, 33L... low-concentration impurity region (second region), 36G... gate wiring, 37... gate insulating film, 38... first interlayer insulating film, 71... aluminum (Al) film, 72, 172... protective metal film, 72A... overlapping portion, 72B, 172B... protruding portion, L1... first metal film, L4... second metal film

Claims

1. A semiconductor film disposed on an upper layer side of an insulating substrate; a gate insulating film disposed on an upper layer of the semiconductor film; the gate electrode disposed on the gate insulating film; an interlayer insulating film disposed above the gate electrode; a thin film transistor having a source electrode and a drain electrode disposed on an upper layer side of the gate electrode with the interlayer insulating film interposed therebetween; a gate wiring connected to the gate electrode of the thin film transistor; The gate electrode and the gate wiring are formed on an array substrate having an aluminum film and a protective metal film made of a metal material having a higher melting point than aluminum and covering the entire surface of the aluminum film.

2. the protective metal film includes an overlapping portion overlapping the aluminum film and a protruding portion protruding from the overlapping portion and not overlapping the aluminum film, the semiconductor film is an impurity semiconductor film, 2 . The array substrate according to claim 1 , wherein an impurity concentration of the semiconductor film is different between a first region overlapping the overlapping portion of the protective metal film and a second region overlapping the protruding portion of the protective metal film.

3. The semiconductor film is a channel region overlapping the aluminum film of the gate electrode and the overlapping portion of the protective metal film; a source region and a drain region, each of which is connected to one of the source electrode and the drain electrode of the thin film transistor; 3. The array substrate according to claim 2, further comprising a low concentration impurity region disposed at least either between the channel region and the source region or between the channel region and the drain region, the low concentration impurity region overlapping the protruding portion of the protective metal film.

4. 3. The array substrate according to claim 1, wherein the semiconductor film is a polysilicon film.

5. An array substrate according to claim 1 or 2; an opposing substrate disposed opposite to the array substrate with an internal space therebetween; a liquid crystal layer sealed in the internal space.

6. A semiconductor film of a thin film transistor is formed on the upper layer side of an insulating substrate; forming a gate insulating film of the thin film transistor on the semiconductor film; forming a first metal film on the gate insulating film, the first metal film being a part of a gate electrode of the thin film transistor and a part of a gate wiring connected to the gate electrode, the first metal film being made of a metal material having a melting point higher than that of aluminum; forming an aluminum film on the first metal film to be a part of the gate electrode and a part of the gate wiring; patterning the base layer including the first metal film and the aluminum film formed by etching; forming a second metal film, which is to become a part of the gate electrode and a part of the gate wiring, on the patterned base layer and is made of a metal having a melting point higher than that of aluminum; The deposited second metal film is etched and patterned so as to have a planar size larger than that of the base layer, thereby forming the gate electrode and the gate wiring having the base layer and the second metal film; A method for manufacturing an array substrate, comprising a heat treatment process of heating at 450° C. or higher after forming the gate electrodes and the gate wiring.

7. the semiconductor film is an impurity semiconductor film, performing an impurity introduction step of accelerating and injecting ionized impurities into the semiconductor film after the formation of the gate electrode and before the heat treatment step; 7. The method for manufacturing an array substrate according to claim 6, wherein in the impurity introduction step, a surface of the gate electrode is not covered with anything and is left exposed.

8. the semiconductor film is a polysilicon film, 8. The method for manufacturing an array substrate according to claim 7, wherein the heat treatment step recovers the crystallinity of the polysilicon film deteriorated by the impurity introduction step.

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