Semiconductor device

Abstract

To provide a semiconductor device which keeps a breakdown voltage high.SOLUTION: A semiconductor device is composed of a semiconductor having an insulating surface; a device layer on which an active region 13A is defined is provided; a field-effect transistor 20 is formed on the device layer; and a first conductive type source region 20S and drain region 20D, and a second conductive type body region 20B and gate electrode 20G as opposed to the first conductive type are included. The field-effect transistor further includes a second conductive type body contact region 20BC that extends from a plurality of body contact joints 21 at the edge of the body region 20B on the side of the source region toward the source region side in planar view from the z direction. The source region is connected to the body region at a plurality of source-body joints 22 other than the plurality of body contact joints. The largest value of the length Wsb in the y direction of each of the plurality of source-body joints is equal to or smaller than eight times the size L of a gate electrode in the x direction orthogonal to the y direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] When a MOSFET is operated at high voltage, electron-hole pairs are generated in the body region directly below the gate electrode due to the impact ionization phenomenon. In order to extract the generated holes from the body region, a body contact region connected to the body region is provided (see Patent Document 1). The holes generated in the body region move through the body region to reach the body contact region, where they are extracted. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0348514 Summary of the Invention [Problem to be solved by the invention]

[0004] In the MOSFET described in Patent Document 1, it takes a long time to extract holes generated in the body region from the body region, which may result in a decrease in breakdown voltage.

[0005] An object of the present invention is to provide a semiconductor device capable of efficiently extracting holes from a body region of a MOSFET and suppressing a decrease in the breakdown voltage. [Means for solving the problem]

[0006] According to one aspect of the present invention, a device layer comprising a semiconductor disposed on an insulating surface; a field effect transistor including a source region of a first conductivity type formed in the device layer, a drain region of the first conductivity type, a body region of a second conductivity type opposite to the first conductivity type, and a gate electrode disposed on the device layer; Equipped with the body region is disposed directly below the gate electrode; When the insulating surface is viewed in a plan view, the gate electrode and the body region have a shape elongated in a first direction, the source region is disposed on one side of the gate electrode, and the drain region is disposed on the other side of the gate electrode; The field effect transistor is The body region further includes a body contact region of the second conductivity type extending from a plurality of body contact connection points at an edge of the body region on the side of the source region toward the side of the source region, the source region is connected to the body region at a plurality of source body connection points other than the plurality of body contact connection points; There is provided a semiconductor device in which the maximum length of each of the plurality of source body connecting portions in the first direction is equal to or less than eight times the dimension of the gate electrode in a second direction perpendicular to the first direction. Effect of the Invention

[0007] If the maximum value of the length in the first direction of each of the plurality of source body connecting parts is set to 8 times or less the dimension in the second direction of the gate electrode, it becomes possible to maintain a high breakdown voltage. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 2A and 2B are cross-sectional views taken along dashed lines 2A-2A and 2B-2B in FIG. 1, respectively. [Diagram 3] FIG. 3 is a plan view for explaining a process in which holes generated in the body region by impact ionization are extracted from the body region. [Figure 4] FIG. 4 is a graph showing the calculation results of the relationship between the length Wsb of the source body connection portion and the electrical resistance Rbody of the hole migration path. [Diagram 5] FIG. 5 is a graph showing the relationship between area efficiency and the length Wsb of the source body connection portion. [Figure 6] 1 is a graph showing the relationship between the breakdown voltage and the length Wsb of the source body connection portion. [Figure 7] FIG. 7 is a plan view of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [First Example] A semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 6. FIG. 1 is a plan view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment includes a field effect transistor, for example a MOSFET, provided on an SOI substrate.

[0010] An active region 13A is defined in a device layer of an SOI substrate (described later with reference to FIGS. 2A and 2B). A source region 20S of n-type conductivity, a drift region 20DR, a drain region 20D, and a body region 20B of p-type conductivity are formed in the active region 13A. A gate electrode 20G is disposed so as to substantially overlap the body region 20B.

[0011] The gate electrode 20G has a shape long in one direction in a plan view, and is disposed so as to intersect with the active region 13A. For example, the gate electrode 20G extends from one side of the rectangular active region 13A, passing through the active region 13A, and reaching the opposite side. An xyz Cartesian coordinate system is defined in which the longitudinal direction (gate width direction) of the gate electrode 20G is the y direction, the direction parallel to the surface of the device layer (the paper surface of FIG. 1) and perpendicular to the y direction (gate length direction) is the x direction, and the normal direction to the surface of the device layer is the z direction.

[0012] In a plan view, the source region 20S is disposed on one side of the gate electrode 20G, and the drift region 20DR is disposed on the other side of the gate electrode 20G. The drain region 20D is disposed at a position farther from the drift region 20DR as viewed from the gate electrode 20G so as to be in contact with the drift region 20DR.

[0013] The body contact regions 20BC of p-type conductivity extend from each of a plurality of points on the edge of the body region 20B on the side of the source region 20S toward the source region 20S. The connection points between the body contact regions 20BC and the body region 20B are referred to as body contact connection points 21. The body contact connection points 21 refer to points where the width in the y direction changes in the p-type conductivity region including the body region 20B and the body contact region 20BC. The source region 20S is composed of a plurality of parts separated in the y direction by the plurality of body contact regions 20BC. The source region 20S is connected to the body region at a plurality of points other than the plurality of body contact connection points 21. The connection points between the source region 20S and the body region 20B are referred to as source body connection points 22. The source body connection points 22 refer to points where n-type conductivity transitions to p-type conductivity in the x direction. The dimension (gate width) of the body region 20B in the y direction is denoted as Wu. The length in the y direction of each of the body contact connection points 21 is denoted as Wbc, and the length in the y direction of each of the source body connection points 22 is denoted as Wsb.

[0014] In a plan view, a plurality of source contact vias 28S are arranged in a location included in the source region 20S, and a plurality of drain contact vias 28D are arranged in a location included in the drain region 20D. The source contact vias 28S are electrically connected to the source region 20S and the body contact region 20BC, and the drain contact vias 28D are electrically connected to the drain region 20D.

[0015] 2A and 2B are cross-sectional views taken along dashed lines 2A-2A and 2B-2B in FIG. 1, respectively. An SOI substrate 10 includes a support substrate 11 made of silicon, an insulating layer (referred to as a buried oxide film 12), and a device layer 13. The device layer 13 is disposed on an insulating surface of the buried oxide film 12. An element isolation region (not shown) is formed in the device layer 13, and an active region 13A (FIG. 1) surrounded by the element isolation region is defined. A gate electrode 20G is disposed on the active region 13A of the device layer 13 via a gate insulating film 20GI. A sidewall spacer 20SW covers the side surface of the gate electrode 20G.

[0016] 2A, a p-type conductive body region 20B, and an n-type conductive source region 20S, a source extension region 20SE, a drift region 20DR, and a drain region 20D are arranged in the device layer 13. The body region 20B, the source region 20S, the source extension region 20SE, the drift region 20DR, and the drain region 20D reach from the upper surface of the device layer 13 to the interface between the device layer 13 and the buried oxide film 12.

[0017] The body region 20B is disposed immediately below the gate electrode 20G. For example, in a plan view, the body region 20B is included in the gate electrode 20G, and the dimension of the body region 20B in the x direction on the surface of the device layer 13 is smaller than the dimension of the gate electrode 20G in the x direction. The source extension region 20SE is disposed immediately below the sidewall spacer 20SW on one side of the gate electrode 20G. The tip portion of the drift region 20DR is disposed immediately below the sidewall spacer 20SW on the other side.

[0018] The source extension region 20SE and the drift region 20DR are in contact with the body region 20B via a pn junction interface. The source region 20S is connected to the body region 20B via the source extension region 20SE. In this specification, the source region 20S and the source extension region 20SE may be collectively referred to as the source region 20S. The drain region 20D is connected to the body region 20B via the drift region 20DR.

[0019] A silicide film 25 is disposed on the upper surface of the source region 20S, and a silicide film 26 is disposed on the upper surface of the drain region 20D. An interlayer insulating film 27 is disposed on the device layer 13 so as to cover the gate electrode 20G and the sidewall spacer 20SW. A source contact via 28S and a drain contact via 28D are disposed in the interlayer insulating film 27. The source contact via 28S is electrically connected to the source region 20S through the silicide film 25. The drain contact via 28D is electrically connected to the drain region 20D through the silicide film 26.

[0020] In the cross section shown in FIG. 2B, a body contact region 20BC is disposed in the device layer 13 so as to contact the body region 20B. Both the body region 20B and the body contact region 20BC have p-type conductivity and are electrically connected to each other. The silicide film 25 disposed on the upper surface of the source region 20S (FIG. 2A) continuously covers the upper surface of the body contact region 20BC. The source contact via 28S is also electrically connected to the body contact region 20BC through the silicide film 25. Therefore, the same potential as that of the source region 20S, typically the ground potential, is applied to the body contact region 20BC.

[0021] Next, an outline of a method for manufacturing a semiconductor device according to the first embodiment will be described. An SOI substrate 10 is prepared, which is composed of a support substrate 11, a buried oxide film 12, and a device layer 13. After an element isolation region (not shown) is formed in the device layer 13 to define an active region 13A (FIG. 1), a p-type dopant such as boron is implanted into the active region 13A to form a body region 20B and a body contact region 20BC.

[0022] Thereafter, an oxidation process is performed to form a silicon oxide film that will become the gate insulating film 20GI on the entire surface of the device layer 13. Furthermore, a polysilicon film that will become the gate electrode 20G is deposited, and an n-type dopant is implanted into the polysilicon film. The silicon oxide film and the polysilicon film are patterned to obtain the gate insulating film 20GI and the gate electrode 20G. If necessary, an insulating film may be formed on the polysilicon film. This insulating film has a function of preventing the injection of dopants into the gate electrode 20G when the gate electrode 20G is used as a mask in a later ion implantation process. Furthermore, a through oxide film may be formed before the ion implantation into the device layer 13, if necessary.

[0023] Using the gate electrode 20G as a mask, a p-type dopant is injected to form a halo region (not shown), and an n-type dopant is injected to form a source extension region 20SE. Next, using a resist pattern (not shown) and the gate electrode 20G as a mask, a p-type dopant is injected to form a body contact region 20BC. Furthermore, using another resist pattern (not shown) and the gate electrode 20G as a mask, an n-type dopant is injected to form a drift region 20DR. The dopant injected into the device layer 13 on the drain region 20D side during the injection of the dopant to form the source extension region 20SE is absorbed by the drift region 20DR. Then, a sidewall spacer 20SW is formed.

[0024] Next, using another resist pattern (not shown), the gate electrode 20G, and the sidewall spacer 20SW as a mask, an n-type dopant is implanted to form the source region 20S and the drain region 20D. A source extension region 20SE (FIG. 2A) formed by the n-type dopant remains directly below the sidewall spacer 20SW on the source region 20S side.

[0025] The activation annealing of the dopants implanted in the device layer 13 may be performed after each dopant implantation, or may be performed collectively after all the dopant implantation steps.

[0026] Next, a silicide film 25 is formed on the upper surfaces of the source region 20S and the body contact region 20BC, and a silicide film 26 is formed on the upper surface of the drain region 20D. The silicide films 25 and 26 can be formed by depositing a metal film such as cobalt or titanium, and then reacting it with silicon. Thereafter, an interlayer insulating film 27, a source contact via 28S, a drain contact via 28D, etc. are formed.

[0027] Next, with reference to FIG. 3, a process in which holes generated in the body region 20B by impact ionization are extracted from the body region 20B will be described.

[0028] 3 is a plan view for explaining a process in which holes generated in the body region 20B by impact ionization are extracted from the body region 20B. A source region 20S arranged on one side (left side in FIG. 3) of the body region 20B long in the y direction contacts the body region 20B at a source body connection point 22. A body contact region 20BC extends from a body contact connection point 21 of the body region 20B toward the side where the source region 20S is arranged. A drift region 20DR is arranged on the other side (right side in FIG. 3) of the body region 20B.

[0029] During high-voltage operation, electron-hole pairs are generated by impact ionization mainly near the interface between the body region 20B and the drift region 20DR. The generated electrons reach the drain region 20D (FIG. 1) through the n-type conductive drift region 20DR. The holes h move toward the source region 20S in the body region 20B, but do not reach the source region 20S due to a potential barrier generated at the pn junction interface between the source region 20S and the body region 20B.

[0030] The holes h reach the body contact region 20BC connected to the body region 20B. The holes h reach the region at ground potential through the body contact region 20BC, the silicide film 25 (FIG. 2B), and the source contact via 28S (FIG. 2A). In order for the holes h to reach the body contact region 20BC, they must move in the body region 20B in the y direction as well as the x direction. In order to efficiently extract the holes h from the body region 20B, it is desirable to reduce the electrical resistance of the path along which the holes h generated by impact ionization move.

[0031] In the y direction, the migration path of a hole h generated at the center of the source body connection part 22 to the body contact region 20BC is the longest. The electrical resistance of this migration path is denoted as Rbody. The dimension of the body region 20B in the x direction is approximately equal to the dimension of the gate electrode 20G in the x direction (gate length L). The dimension of the gate length L is determined by the frequency of the target high-frequency signal, and is, for example, 0.4 μm or less.

[0032] Next, the relationship between the length Wsb of the source body connection part 22 and the electric resistance Rbody of the movement path of the holes h will be described with reference to Fig. 4. Fig. 4 is a graph showing the calculation results of the relationship between the length Wsb of the source body connection part 22 and the electric resistance Rbody of the movement path of the holes h. The horizontal axis represents the length Wsb of the source body connection part 22 in units of μm, and the vertical axis represents the electric resistance Rbody in units of Ω. The gate length L is 0.25 μm, the gate width Wu is 5 μm, and the length Wbc of the body contact connection part 21 in the y direction is 0.2 μm.

[0033] The length Wbc in the y direction of the body contact connection parts 21 located at both ends in the y direction is set to 1 / 2 the length Wbc in the y direction of the body contact connection parts 21 other than the ends, that is, 0.1 μm. Therefore, the two body contact regions 20BC at both ends are counted as one. In addition, the sheet resistance of the body region 20B is set to 1×10 17 The ratio was set to Ω / □.

[0034] The numbers attached to the circle symbols in FIG. 4 represent the number n of the body contact regions 20BC. In a configuration in which the number n is 1, the body contact regions 20BC are arranged at both ends of the body region 20B in the y direction. In a configuration in which the number n of the body contact regions 20BC is 2 or more, the body contact regions 20BC are arranged so that the lengths Wsb of the multiple source body connection portions 22 are equal. For example, in a configuration in which the number n is 2, the body contact regions 20BC are arranged at both ends of the body region 20B in the y direction, and the body contact region 20BC is also arranged in the center of the body region 20B in the y direction. In this case, the length Wsb of each of the source body connection portions 22 is 2.3 μm.

[0035] When the length Wsb of the source body connection part 22 is longer, the distance traveled by the holes h to the body contact region 20BC becomes longer, and the electrical resistance Rbody becomes larger. When the length Wsb of the source body connection part 22 is shorter than 4L, the gate length L is more dominant than the length Wsb in terms of the length of the path traveled by the holes h. When the length Wsb of the source body connection part 22 is 4L or more, the length Wsb is more dominant in terms of the length of the path traveled by the holes h.

[0036] Therefore, when the length Wsb is longer than 4L, the slope of the increase in the electrical resistance Rbody relative to the increase in the length Wsb becomes steeper than when the length Wsb is shorter than 4L. From the viewpoint of suppressing the increase in the electrical resistance Rbody, it is preferable to set the length Wsb to 4L or less. When the lengths Wsb of the multiple source body connection parts 22 are not constant, it is preferable to set the maximum value of the length Wsb to 4L or less.

[0037] Next, the relationship between the area efficiency and the length Wsb of the source body connection portion 22 will be described with reference to Fig. 5. Fig. 5 is a graph showing the relationship between the area efficiency and the length Wsb of the source body connection portion 22. The horizontal axis represents the length Wsb in units of μm, and the vertical axis represents the area efficiency in units of %. Here, the area efficiency means the ratio of the total length Wsb of the source body connection portion 22 to the gate width Wu. The area efficiency can be considered as the ratio of the area of ​​the body region 20B that can be substantially used as a channel.

[0038] In Fig. 5, the gate length L is set to 0.25 μm and the gate width Wu is set to 5 μm, as in Fig. 4. The method of counting the length Wbc of the body contact connection portion 21 in the y direction and the number n of the body contact regions 20BC is the same as in Fig. 4. The numbers attached to the circle symbols shown in Fig. 5 represent the number n of the body contact regions 20BC.

[0039] As the length Wsb becomes shorter, the area efficiency decreases. In particular, the decrease in area efficiency becomes significant when the length Wsb is shorter than 3L. In order to avoid a significant decrease in area efficiency, it is preferable to set the length Wsb to 3L or more. When the lengths Wsb of the multiple source body connection portions 22 are not the same, it is preferable to set the minimum value of the length Wsb to 3L or more.

[0040] Next, the relationship between the breakdown voltage and the length Wsb will be described with reference to FIG. 6. The breakdown voltage is an actual measurement value. FIG. 6 is a graph showing the relationship between the breakdown voltage and the length Wsb of the source body connection part 22. The horizontal axis represents the length Wsb in units of μm, and the vertical axis represents the breakdown voltage in units of V. In FIG. 6, as in FIG. 4, the gate length L is set to 0.25 μm and the gate width Wu is set to 5 μm. The method of counting the length Wbc of the body contact connection part 21 in the y direction and the number n of the body contact regions 20BC is the same as in FIG. 4. The numbers attached to the circle symbols shown in FIG. 6 represent the number n of the body contact regions 20BC.

[0041] As the length Wsb becomes longer, the withstand voltage decreases. If the length Wsb exceeds 10L, the withstand voltage decreases significantly with increasing length Wsb. In order to maintain a high withstand voltage, it is preferable to set the length Wsb to 10L or less, for example.

[0042] Next, the preferred thickness of the device layer 13 will be described. In a configuration in which the source region 20S (FIG. 2A) does not reach the interface between the device layer 13 and the buried oxide film 12, a region of p-type conductivity identical to that of the body region 20B is secured between the source region 20S and the buried oxide film 12. In this configuration, even if the body contact region 20BC is disposed at a distance from the body region 20B, holes can be extracted from the body region 20B through the region of p-type conductivity between the source region 20S and the buried oxide film 12.

[0043] As shown in FIG. 2A, when the source region 20S reaches from the upper surface of the device layer 13 to the interface between the device layer 13 and the buried oxide film 12, if the body contact region 20BC is disposed at a distance from the body region 20B, the holes in the body region 20B cannot reach the body contact region 20BC. When the source region 20S reaches from the upper surface of the device layer 13 to the interface between the device layer 13 and the buried oxide film 12, a significant effect is obtained by adopting a configuration in which the body contact region 20BC is disposed so as to contact the body region 20B. When the thickness of the device layer 13 is 50 nm or less, it is difficult to secure a p-type conductive region between the source region 20S and the buried oxide film 12. Therefore, when the thickness of the device layer 13 is 50 nm or less, a significant effect is obtained by adopting the configuration of the first embodiment.

[0044] Next, a semiconductor device according to a modification of the first embodiment will be described. The semiconductor device according to the first embodiment includes an n-channel MOSFET. Alternatively, it may include a p-channel MOSFET. In the p-channel MOSFET, the preferable relationship between the length Wsb and the gate length L is the same as in the n-channel MOSFET.

[0045] In the first embodiment (FIG. 1), one gate electrode 20G is arranged so as to intersect with one active region 13A. The configuration according to the first embodiment can also be adopted for a multi-finger MOSFET in which multiple gate electrodes 20G are arranged so as to intersect with one active region 13A. In the case of a multi-finger MOSFET, the gate width Wu may be considered as the dimension in the gate width direction of each of the multiple fingers of the gate electrode 20G.

[0046] [Second Example] Next, a semiconductor device according to a second embodiment will be described with reference to Fig. 7. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 6 will be omitted.

[0047] FIG. 7 is a plan view of the semiconductor device according to the second embodiment. In the first embodiment (FIG. 1), each of the body contact regions 20BC extends from the body contact connection points 21 of the body region 20B toward the source region 20S and reaches the opposite edge of the source region 20S. In contrast, in the second embodiment, each of the body contact regions 20BC extending from the body contact connection points 21 does not reach the opposite edge of the source region 20S. Therefore, the source region 20S is not separated by the body contact regions 20BC, but is composed of one continuous region.

[0048] In the second embodiment, similarly to the first embodiment, holes generated in the body region 20B move within the body region 20B and reach the body contact region 20BC through the body contact connection part 21. Thus, in the second embodiment, the process of extracting holes within the body contact region 20BC is similar to that in the first embodiment.

[0049] Next, the advantageous effects of the second embodiment will be described. In the second embodiment as well, by making the relationship between the length Wsb of the source body connection portion 22 and the gate length L satisfy the same relationship as in the first embodiment, excellent effects similar to those of the first embodiment can be obtained.

[0050] [Third Example] Next, a semiconductor device according to a third embodiment will be described with reference to Fig. 8. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 6 will be omitted.

[0051] 8 is a plan view of a semiconductor device according to the third embodiment. In the third embodiment, the body contact region 20BC is composed of a first body contact region 20BC1 and a second body contact region 20BC2. The first body contact region 20BC1 extends from the body contact connection point 21 of the body region 20B toward the source region 20S, similar to the first embodiment (FIG. 1). The first body contact region 20BC1 does not reach the edge on the opposite side of the source region 20S, similar to the body contact region 20BC of the second embodiment (FIG. 7).

[0052] A gate electrode protrusion 20GP protruding from the gate electrode 20G toward the source region 20S overlaps with the first body contact region 20BC1 in a plan view. When an n-type dopant is implanted into the source region 20S, the gate electrode protrusion 20GP acts as a mask, so that the first body contact region 20BC1 directly below the gate electrode protrusion 20GP has p-type conductivity like the body region 20B, and the dopant concentration in the first body contact region 20BC1 is the same as the dopant concentration in the body region 20B.

[0053] A second body contact region 20BC2 having p-type conductivity is formed so as to surround the tip of the first body contact region 20BC1 from three sides. The concentration of p-type dopant in the second body contact region 20BC2 is higher than the concentration of p-type dopant in the first body contact region 20BC1. A silicide film is disposed on the top surface of the source region 20S and the second body contact region 20BC2, similar to the silicide film 25 (FIG. 2A) in the first embodiment. Holes that move through the body region 20B and reach the body contact connection point 21 reach the region of ground potential via the first body contact region 20BC1 and the second body contact region 20BC2.

[0054] Next, the excellent effects of the third embodiment will be described. In the third embodiment, the length Wbc of the body contact connection portion 21 is approximately equal to the dimension in the y direction of the gate electrode protrusion 20GP. In general, the processing accuracy of the gate electrode 20G is higher than that of other components. Therefore, it is possible to shorten the length Wbc of the body contact connection portion 21 without depending on the dimension of the second body contact region 20BC2. In other words, it is possible to lengthen the length Wsb of the source body connection portion 22. Therefore, it is possible to improve the area efficiency.

[0055] In the third embodiment as well, by making the relationship between the length Wsb of the source body connection portion 22 and the gate length L satisfy the same relationship as in the first embodiment, it is possible to obtain the same excellent effects as in the first embodiment.

[0056] The above-mentioned embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. Similar effects due to similar configurations of multiple embodiments are not mentioned in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible.

[0057] Based on the above examples described in this specification, the following invention is disclosed. <1> a device layer comprising a semiconductor disposed on an insulating surface; a field effect transistor including a source region of a first conductivity type formed in the device layer, a drain region of the first conductivity type, a body region of a second conductivity type opposite to the first conductivity type, and a gate electrode disposed on the device layer; Equipped with the body region is disposed directly below the gate electrode; When the insulating surface is viewed in a plan view, the gate electrode and the body region have a shape elongated in a first direction, the source region is disposed on one side of the gate electrode, and the drain region is disposed on the other side of the gate electrode; The field effect transistor is The body region further includes a body contact region of the second conductivity type extending from a plurality of body contact connection points at an edge of the body region on the side of the source region toward the side of the source region, the source region is connected to the body region at a plurality of source body connection points other than the plurality of body contact connection points; a maximum length of each of the plurality of source body connecting portions in the first direction is 10 times or less than a dimension of the gate electrode in a second direction perpendicular to the first direction;

[0058] <2> The maximum length of each of the plurality of source body connecting portions in the first direction is equal to or smaller than four times the dimension of the gate electrode in a second direction perpendicular to the first direction. <1> The semiconductor device according to claim 1 .

[0059] <3> The minimum length of each of the plurality of source body connecting portions in the first direction is equal to or greater than three times the dimension of the gate electrode in a second direction perpendicular to the first direction. <1> or <2> The semiconductor device according to claim 1 .

[0060] <4> The source region extends from the top surface of the device layer to the insulating surface. <1> ~ <3> 13. The semiconductor device according to claim 12,

[0061] <5> The thickness of the device layer is 50 nm or less. <1> ~ <4> 13. The semiconductor device according to claim 12,

[0062] <6> The semiconductor device further includes a drift region that is disposed between the body region and the drain region, has the first conductivity type, and has a lower impurity concentration than the drain region. <1> ~ <5> 13. The semiconductor device according to claim 12, [Explanation of symbols]

[0063] 10 SOI substrate 11 Support substrate 12 Buried oxide film 13 Device Layer 13A active area 20 Field-effect transistor (FET) 20B Body Region 20BC Body contact area 20BC1 First body contact region 20BC2 Second body contact region 20D drain region 20DR Drift Area 20G gate electrode 20GI Gate insulating film 20GP Gate electrode protrusion 20S Source Area 20SE Source Extension Area 20SW Sidewall Spacer 21 Body contact connection point 22 Source body connection 25, 26 Silicide film 27 Interlayer insulating film 28D Drain Contact Via 28S Source Contact Via

Claims

1. a device layer comprising a semiconductor disposed on an insulating surface; a field effect transistor including a source region of a first conductivity type formed in the device layer, a drain region of the first conductivity type, a body region of a second conductivity type opposite to the first conductivity type, and a gate electrode disposed on the device layer; Equipped with the body region is disposed directly below the gate electrode; When the insulating surface is viewed in a plan view, the gate electrode and the body region have a shape elongated in a first direction, the source region is disposed on one side of the gate electrode, and the drain region is disposed on the other side of the gate electrode, The field effect transistor is The body region further includes a body contact region of the second conductivity type extending from a plurality of body contact connection points at an edge of the body region on the side of the source region toward the side of the source region, the source region is connected to the body region at a plurality of source body connection points other than the plurality of body contact connection points; A semiconductor device in which the maximum length of each of the plurality of source body connection points in the first direction is 10 times or less than the dimension of the gate electrode in a second direction perpendicular to the first direction.

2. 2 . The semiconductor device according to claim 1 , wherein a maximum value of a length in the first direction of each of the plurality of source body connection points is four times or less a dimension in a second direction perpendicular to the first direction of the gate electrode.

3. 3. The semiconductor device according to claim 1, wherein the minimum length of each of the plurality of source body connection points in the first direction is three or more times the dimension of the gate electrode in a second direction perpendicular to the first direction.

4. 3. The semiconductor device according to claim 1, wherein the source region extends from the upper surface of the device layer to the insulating surface.

5. 3. The semiconductor device according to claim 1, wherein the device layer has a thickness of 50 nm or less.

6. 3. The semiconductor device according to claim 1, further comprising a drift region of the first conductivity type, the drift region being disposed between the body region and the drain region and having a lower impurity concentration than the drain region.

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