Surface modified depth controlled deposition for plasma based deposition

Abstract

To provide a method for performing gap filling of a feature on a substrate, and a gas supply system for supplying a process gas to a process chamber for an ALD process and plasma processing.SOLUTION: A method for performing gap fill of a feature on a substrate includes the following operations: (a) moving the substrate into a process chamber; (b) performing a plurality of cycles of an ALD process; (c) purging process gases from the ALD process from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine- containing gas into the process chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the process chamber; (e) purging process gases from the plasma treatment from the process chamber; (f) repeating the operations (b) through (e) until a predefined number of cycles are performed.SELECTED DRAWING: Figure 4

Description

[Background technology]

[0001] Deposition-etch-deposition (DED) has been demonstrated to fill high aspect ratio vias, holes, and trenches. When using DED to fill features with increasing reentrancy from the top of the structure downward, gap-fill limitations are encountered. In structures with predominantly reentrant features compared to the opening dimensions, or with any reentrant features large compared to the bulk opening, not enough material can grow within the field of view of the etching ions before the feature pinches off.

[0002] It is in this context that implementations of the present disclosure arise. Summary of the Invention

[0003] In some implementations, a method for performing gap filling of features on a substrate is provided, the method including: (a) moving the substrate into a process chamber; (b) performing multiple cycles of an ALD process; (c) purging process gas from the process chamber from the ALD process; (d) performing a plasma treatment on the substrate by introducing a fluorine-containing gas into the process chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the process chamber; (e) purging process gas from the plasma treatment from the process chamber; and (f) repeating operations (b) through (e) until a predetermined number of cycles have been performed.

[0004] In some implementations, the fluorine plasma passivates portions of features on the substrate, thereby inhibiting deposition from the ALD process on the portions of the passivated features.

[0005] In some implementations, the portion of the feature that is passivated extends from the top of the feature to a predetermined target level within the feature.

[0006] In some implementations, the pre-defined target level is controlled by one or more parameters of the plasma process.

[0007] In some implementations, the parameters of the plasma treatment include one or more of the duration of the plasma treatment, the temperature of the plasma treatment, the pressure of the fluorine-containing gas, and the RF power level.

[0008] In some implementations, the feature includes re-entrancy and the predetermined target level is defined at approximately the level of the re-entrancy such that the plasma treatment substantially inhibits deposition from the ALD process above the level of the re-entrancy.

[0009] In some implementations, the fluorine plasma passivates a portion of the feature by forming fluorine-terminated species along a surface of the portion of the feature.

[0010] In some implementations, the method further includes (g) performing one or more cycles of an ALD process.

[0011] In some implementations, the predetermined number of cycles of operation (e) is configured to perform gap filling to eliminate reentrancy in the feature.

[0012] In some implementations, the one or more cycles of the ALD process of operation (g) are configured to complete gap filling of the feature.

[0013] In some implementations, the ALD process is configured to deposit an oxide in a feature of a substrate.

[0014] In some implementations, the fluorine-containing gas is CH3F, CHF3, CF4, C2H4F2, C2H2F4, C3H2F6, C4H2F8, C4F8, NF3, or SF6.

[0015] In some implementations, a method for performing gap filling of a feature on a substrate is provided, the method including: (a) moving a substrate into a process chamber; (b) performing multiple cycles of an ALD process, the ALD process configured to deposit oxide in the feature of the substrate; (c) purging process gas from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine-containing gas into the process chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the process chamber; (e) purging process gas from the plasma treatment from the process chamber; (f) repeating operations (b) through (e) until a predetermined number of cycles have been performed; and (g) performing multiple cycles of the ALD process.

[0016] In some implementations, the fluorine plasma passivates portions of features on the substrate, thereby inhibiting deposition from the ALD process on the portions of the passivated features.

[0017] In some implementations, the portion of the feature that is passivated extends from the top of the feature to a predetermined target level within the feature.

[0018]

[0019] In some implementations, the pre-defined target level is controlled by one or more parameters of the plasma process.

[0020] In some implementations, the parameters of the plasma treatment include one or more of the duration of the plasma treatment, the temperature of the plasma treatment, the pressure of the fluorine-containing gas, and the RF power level.

[0021] In some implementations, a method for performing gap filling of features on a substrate is provided, the method including: (a) moving the substrate into a process chamber; (b) performing multiple cycles of an ALD process; (c) purging process gas from the ALD process from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine-containing gas into the process chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the process chamber, where the RF power is applied at a frequency in the range of about 200-600 kHz; (e) purging process gas from the plasma treatment from the process chamber; and (f) repeating operations (b) through (e) until a predetermined number of cycles have been performed.

[0022] In some implementations, the pressure of the plasma treatment is in the range of about 66.6612 to about 1066.58 Pascals (about 0.5 to 8 Torr).

[0023] In some implementations, the duration of the plasma treatment is in the range of about 0.1 to 3 seconds.

[0024] Other aspects and advantages of the present disclosure herein will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the disclosure. [Brief description of the drawings]

[0025] [Figure 1A] FIG. 1A conceptually illustrates a cross-sectional view of a feature exhibiting re-entrancy in accordance with an implementation of the present disclosure. [Figure 1B] FIG. 1B conceptually illustrates a cross-sectional view of a feature exhibiting re-entrancy in accordance with an implementation of the present disclosure. [Figure 1C] Fig. 1C conceptually illustrates a cross-sectional view of a feature exhibiting reentrancy in accordance with an implementation of the present disclosure. Fig. 18 is a simplified schematic diagram of a computer system for implementing an implementation of the present disclosure.

[0026] [Figure 2A] FIG. 2A illustrates the application of gap filling onto a multi-layer stack in accordance with an implementation of the present disclosure. [Figure 2B] FIG. 2B illustrates the application of gap filling onto a multi-layer stack in accordance with an implementation of the present disclosure.

[0027] [Figure 3A] FIG. 3A illustrates an inhibition-based technique for achieving gap-fill of re-entrant features. [Figure 3B] FIG. 3B illustrates an inhibition-based technique for achieving gap-fill of re-entrant features. [Figure 3C] FIG. 3C illustrates an inhibition-based technique for achieving gap-fill of re-entrant features. [Figure 3D] FIG. 3D illustrates an inhibition-based technique for achieving gap-fill of re-entrant features.

[0028] [Figure 4] FIG. 4 illustrates a method for performing a gap-fill process with fluorine plasma inhibition according to an implementation of the present disclosure.

[0029] [Figure 5A] FIG. 5A is a graph showing the effect of an inhibition treatment on subsequent deposition cycles, according to an implementation of the present disclosure.

[0030] [Figure 5B] FIG. 5B is a graph showing suppression depth versus suppression processing time, according to an implementation of the present disclosure.

[0031] [Figure 6A] FIG. 6A conceptually depicts a cross-section of a feature on a substrate, illustrating a gap-fill process according to an implementation of the present disclosure. [Figure 6B]FIG. 6B conceptually depicts a cross-section of a feature on a substrate, illustrating a gap-fill process according to an implementation of the present disclosure. [Figure 6C] FIG. 6C conceptually depicts a cross-section of a feature on a substrate, illustrating a gap-fill process according to an implementation of the present disclosure.

[0032] [Figure 7A] FIG. 7A shows a cross-section of a feature having multiple reentranties and illustrates a process for gap filling according to an implementation of the present disclosure. [Figure 7B] FIG. 7B shows a cross section of a feature having multiple reentranties, illustrating a process for gap filling according to an implementation of the present disclosure. [Figure 7C] FIG. 7C shows a cross section of a feature having multiple reentranties, illustrating a process for gap filling according to an implementation of the present disclosure. [Figure 7D] FIG. 7D shows a cross section of a feature having multiple reentrants, illustrating a process for gap filling according to an implementation of the present disclosure. [Figure 7E] FIG. 7E shows a cross section of a feature having multiple reentranties, illustrating a process for gap filling according to an implementation of the present disclosure. [Figure 7F] FIG. 7F shows a cross section of a feature having multiple reentranties, illustrating a process for gap filling according to an implementation of the present disclosure.

[0033] [Figure 8] FIG. 8 shows a gas delivery system for supplying process gas to a process chamber for an ALD process in accordance with an implementation of the present disclosure.

[0034] [Figure 9A] 9A and 9B show the difference between existing systems and systems with separate manifolds for delivery of inhibit / passivation gases and cleaning / etching gases in accordance with implementations of the present disclosure. [Figure 9B] 9A and 9B show the difference between existing systems and systems with separate manifolds for delivery of inhibit / passivation gases and cleaning / etching gases in accordance with implementations of the present disclosure.

[0035] [Figure 10A] FIG. 10A illustrates the improvement in gap-filling performance that is possible using techniques according to implementations of the present disclosure. [Figure 10B] FIG. 10B illustrates the improvement in gap-filling performance that is possible using techniques according to implementations of the present disclosure. [Figure 10C] FIG. 10C illustrates the improvement in gap-filling performance that is possible using techniques according to implementations of the present disclosure.

[0036] [Figure 11] FIG. 11 illustrates a cluster tool system 1100 for processing a substrate in accordance with an implementation of the present disclosure.

[0037] [Figure 12] FIG. 12 is a simplified schematic diagram of a computer system for implementing implementations of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] In the following description, numerous specific details are set forth to provide a thorough understanding of the exemplary implementations. However, it will be apparent to one skilled in the art that the exemplary implementations may be practiced without some of these specific details. In other cases, process operations and implementation details have not been described in detail if they are already well known.

[0039] As used herein, the terms "about" and "approximately" mean that the specified parameter can vary within a reasonable tolerance, for example, in some implementations, by ±10%, in some implementations, by ±15%, or in some implementations, by ±20%.

[0040] Broadly speaking, implementations of the present disclosure provide methods, systems, and apparatus that allow for dielectric gap-filling of high aspect ratio features with large reentrant structures inside holes or trenches. In some implementations, the disclosed techniques utilize fluorine modified surfaces through the use of low frequency (LF; e.g., 200-600 Hz) plasmas and high frequency (HF; e.g., 13-14 MHz) plasmas. The surface modification allows for control of deposition depth within the feature during the growth process. Fluorine surface treatment may be applied to gap-fill vias, holes, shallow trench isolation (STI) structures, and trenches on multilayer stacks (not just features made of a single material) including a variety of materials including, but not limited to, silicon / polysilicon, silicon dioxide, germanium, nitride, oxide, or multilayer stack materials. The modification allows for multiple plasma cycles to be performed before reapplication of the surface modification is required.

[0041] Generally speaking, a reentrant feature is one that exhibits a sidewall profile in which a portion of the sidewall is laterally etched / removed to a greater extent than another portion directly above it that is at a shallower depth. Thus, the first portion is said to be "shadowed" by the second portion that is at a shallower depth. Reentrant features are typically caused by the etching process deviating from a straight line, causing undercutting or shadowing, and the area where this occurs is the reentrant. This can occur anywhere within the feature. There can be various causes for reentrant features. For example, sidewall passivation may occur during the etching process, and if the passivation varies or is inconsistent, bowing may occur in some areas due to inconsistent etching along the sidewall. In some cases, there may be layers of different materials that are etched at different rates, causing the resulting sidewall etch profile to exhibit bulging due to the different etch rates of the materials.

[0042] 1A, 1B, and 1C conceptually illustrate cross-sectional views of features exhibiting re-entrancy, according to implementations of the present disclosure. For example, as shown in FIG. 1A, some re-entrancy is shown as a (large) feature 100 that is small at the top and widens at the bottom. This is sometimes described as sidewalls 102 having a negative slope or tapering. In some processes, there is a two-stage etch, which may create re-entrancy, for example, at the top of the feature and re-entrancy somewhere in the middle of the feature.

[0043] As shown in FIG. 1B, in some cases, reentrancy may occur due to bending of the line feature 104. For example, such bending may occur due to improper etching or stress in the film. The bending causes one side of the feature to become reentrant relative to the other side. It will be appreciated that in the illustrated implementation, bending the feature 104 back and forth creates a reentrancy 106 along one side of the top region of the feature 104 and another reentrancy 108 along the other side of the bottom region of the feature 104.

[0044] 1C, another example of re-entrancy is due to the sidewall topography of the feature 110. By way of non-limiting example, this may occur in NAND devices, FINFET devices, oxide / nitride (ONON) stacks, oxide / polysilicon (OPOP) stacks, etc. For example, the sidewalls may have fins 112 or other features that cause re-entrancy in the feature.

[0045] The ability of the etch process to remove reentrancy and sidewall profile that is not required for gap filling can depend on the structure of the inlet portion: structures with "necking" features or reentrant portions within the structure can cause pinching, pinching off the deposited material before the etch portion of the DED can remove it.

[0046] 2A and 2B show the application of gap filling on a multi-layer stack according to an implementation of the present disclosure. As a non-limiting example, the multi-layer stack can be an ONON or OPOP material stack. In the illustrated implementation, layers of a first material 202 alternate with layers of a second material 204 to form a multi-layer stack. Etching such a multi-layer stack is often accompanied by re-entrancy, which results in undercutting in multiple areas. For example, the first material 202 may be etched at a slower rate than the second material 204, which may cause the layers of the second material 204 to be recessed relative to the layers of the first material 202 along the sidewalls of the feature 200.

[0047] 2B shows gapfill 206 deposited within feature 200. In typical gapfill processes (such as, for example, atomic layer deposition (ALD)), reentrancy can lead to voids when deposition is performed in these regions.

[0048] 3A, 3B, 3C, and 3D illustrate inhibition-based techniques for achieving gapfill of reentrant features. As shown in FIG. 3A, feature 300 may have reentrancy 302. In the illustrated example, reentrancy 302 is shown at the top of feature 300, but in various features, reentrancy can occur anywhere from the top to the bottom of the feature. Wherever such reentrancy exists, it can become a void during gapfill.

[0049] Existing techniques can apply an inhibitor-fill process using an inhibitor such as nitrogen (N2) plasma. Such a process aims to inhibit growth and fill at a different rate, so that deposition at the bottom of the feature grows at a faster rate than at the top, thereby allowing faster growth in the reentrant before pinching off. That is, an inhibitor is applied in each ALD cycle such that the deposition rate decreases towards the top of the feature.

[0050] In some cases, the inhibitor fill process is performed over multiple cycles until a certain thickness is reached, producing a partial inhibitor fill layer 304, as shown in Figure 3A. Optionally, an etching step can then be performed to remove material, as shown in Figure 3C. A regular ALD (without inhibitor) fill process then follows to complete gapfill of the feature, as shown in Figure 3D.

[0051] However, a problem with the inhibitor fill process mentioned above is that the inhibitor must be applied for every ALD cycle of the flow. Every time material is deposited in a cycle, an inhibitor application is required, which is a long additional step, making it a very slow process. As a non-limiting example, for an inhibitor fill process using an inhibitor such as nitrogen (N2) plasma, the ALD cycle itself may be on the order of 1.5 seconds, but an additional 20 seconds may be required per cycle to perform the N2 plasma inhibition. Thus, the deposition cycle time may increase from a cycle time of 1.5 seconds to a cycle time of 21.5 seconds. The growth rate may typically be about 0.8 angstroms per second, and a typical desired thickness may be about 200 angstroms, so the number of cycles is typically on the order of about 200-300 cycles. Thus, the increase in cycle time is magnified, and the throughput loss due to the inhibition process may be quite large. The purpose of the etching step is to speed up the process by allowing the filling procedure to be reverted to normal ALD without the risk of pinch-off. Thus, existing procedures may entail performing an inhibitor fill process (e.g., 20-25 second cycles, which is a very slow fill) until the reentrant is filled to the point where shadowing is no longer present, then running a long etch (e.g., about 30 seconds), and then switching to regular ALD deposition to complete the fill. However, while the etch back and switch to regular ALD fill may help throughput, the overall process is still very significantly hindered by the inhibitor portion of the inhibitor fill process.

[0052] However, according to implementations of the present disclosure, an inhibitor is used such that the inhibitor effect can withstand multiple repetitions of ALD plasma cycles. This allows multiple ALD cycles to be performed consecutively without reapplication of the inhibitor. Previously applied inhibitors could not withstand multiple ALD cycles. However, implementations of the present disclosure provide an inhibitor that can provide an inhibitor effect that lasts over multiple ALD cycles.

[0053] In some implementations, a fluorinated gas is utilized to treat a substrate surface and provide an inhibitory effect. Broadly speaking, a process flow may entail performing multiple ALD cycles, then purging the ALD gas, and then applying a fluorinated gas to treat the surface. This process is repeated for multiple iterations. The fluorinated gas provides an inhibitory effect that persists over multiple ALD cycles, and therefore does not need to be reapplied for each ALD cycle.

[0054] It should be noted that fluorinated gases are not typically used in deposition processes, but rather tend to be used in etching processes. The use of fluorinated agents during chamber cleaning processes is known. However, in such cases, the purpose of the fluorine is to effect cleaning and removal. In contrast, according to implementations of the present disclosure, fluorine is used to selectively remain in certain areas of the substrate, thereby providing an inhibition effect during gap-fill deposition.

[0055] 4 illustrates a method for performing a gap-fill process with fluorine plasma inhibition according to an implementation of the present disclosure. In method operation 400, a wafer (substrate) is introduced into a process chamber. In method operation 402, optional heating or cooling of the wafer with a thermal soak step can be performed to bring the wafer to a desired temperature. In method operation 404, a gas pre-flow for ALD is introduced. For example, this may include flowing an inert gas into the process chamber and balancing the flow of gas into and out of the process chamber.

[0056] In method operation 406, one or more ALD cycles are performed. Each ALD cycle typically consists of a first reactant dose, a first purge, a second reactant dose, and a second purge. In some implementations, the first or second reactant dose can be a plasma process. Following completion of the ALD cycle, then in method operation 408, all process gas from the ALD is purged from the process chamber (e.g., using an inert gas). It will be understood that the number of specific ALD cycles performed in method operation 406 can vary depending on the application, the dimensions of the feature to be filled, and any reentrancy therein. In some implementations, the number of ALD cycles is in the range of about 5-25 cycles, in some implementations, in the range of about 10-20 cycles, and in some implementations, in the range of about 10-15 cycles.

[0057] In method operation 410, a fluorine-containing gas is introduced into the process chamber. In method operation 412, RF power is applied to the process chamber to generate a plasma from the fluorine-containing gas, thus performing a fluorine plasma treatment. Following the plasma treatment, the process chamber is then purged in method operation 414. In method operation 416, if the predefined number of cycles has not been reached, the method returns to method operation 406. Thus, cycles of ALD deposition and fluorine plasma treatment are repeated until the predefined number of cycles is reached.

[0058] Once the predefined number of cycles is completed, in method operation 420 the wafer exits the process tool.

[0059] Optionally, in some implementations, after the predetermined number of cycles is completed in method operation 416, an additional predetermined number of ALD cycles are performed (without performing the inhibit processing of method operations 410, 412, and 414). This may be useful when the ALD+inhibit processing cycles of method operations 406-416 are sufficient to achieve deposition up to a level of reentrancy such that the reentrancy is eliminated (or sufficiently reduced) so that regular ALD gap fill can then be used to fill the remainder of the feature.

[0060] The process parameters for fluorine plasma treatment may vary according to various implementations of the present disclosure. In some implementations, a dual frequency RF power is applied that combines a relatively low frequency (LF; e.g., generated by an LF generator) and a relatively high frequency (HF; e.g., generated by an HF generator) of RF power. In some implementations, the low frequency is in the range of about 400-430 kHz. In some implementations, the frequency is in the range of about 200-600 kHz. In some implementations, the high frequency is in the range of about 13-14 MHz. In some implementations, the high frequency range can extend to about 10-120 MHz. In some implementations, the high frequency is 13.56 MHz.

[0061] In some implementations, the power for the fluorine plasma treatment is in the range of about 500 to 2500 Watts. In some implementations, the power is in the range of about 50 Watts to 5 kW. Generally speaking, increasing the power is associated with an increased inhibition effect that extends deeper within the feature.

[0062] In some implementations, the temperature of the fluorine plasma treatment is in the range of about 75 degrees Celsius to 550 degrees Celsius. In some implementations, the temperature is in the range of about 20 degrees Celsius to 800 degrees Celsius. It will be appreciated that the optimum temperature may depend on the particular application, e.g., the circuitry already disposed on a given substrate / wafer. For example, to protect existing structures, higher temperatures may be utilized at lower levels, while lower temperatures may be utilized at higher levels.

[0063] In some implementations, the pressure of the fluorine plasma treatment is in the range of about 0.5 to 8 Torr. Roughly speaking, increasing the pressure is associated with a greater inhibition effect that extends deeper within the feature.

[0064] In some implementations, the duration of the fluorine plasma treatment is in the range of about 0.1 to 3 seconds. Generally speaking, increasing the duration is associated with an increased inhibition effect that extends deeper within the feature.

[0065] Additionally, increasing the flow rate of the fluorine-containing gas may increase the suppression effect.

[0066] In view of the above, it will be appreciated that the parameters of the ALD+plasma inhibition treatment cycles defined by method operations 406-416 may be varied from one cycle to the next, or from one set of cycles to the next, to optimize the amount and level of inhibition effect, taking into account the structure of the features, including the depth and severity of any re-entrancy, and changes in the profile or structure of the features as the fill process progresses.

[0067] For example, in some implementations, method operations 406-416 are performed for a first number of cycles using a first set of parameters with a goal of filling the feature up to a first level of reentrancy, and then method operations 406-416 are performed for a second number of cycles using a second set of parameters with a goal of filling the feature up to a second level of reentrancy. It will be appreciated that this concept can be extended to goal filling up to additional levels of reentrancy, optionally followed by an ALD fill without an inhibit process as described above.

[0068] In some implementations, the parameters of the fluorine plasma inhibition treatment can be gradually changed over multiple ALD+ inhibition treatment cycles, hi some implementations, the fluorine plasma inhibition treatment can be gradually tapered over a number of such cycles to gradually reduce the effectiveness and depth of inhibition.

[0069] FIG. 5A is a graph showing the effect of an inhibition treatment on subsequent deposition cycles according to an implementation of the present disclosure. The graph shown shows deposition thickness versus number of ALD cycles. Curve 500 shows the case without an inhibition treatment, and shows a nearly linear increase in deposition thickness with increasing number of ALD deposition cycles. Curve 502 shows the deposition thickness after a fluorine plasma inhibition treatment according to an implementation of the present disclosure. As shown by curve 502, the deposition thickness does not increase for a certain number of cycles after the inhibition treatment, and thus, ALD deposition is inhibited during these cycles. Following this, a further increase in the number of ALD cycles eventually leads to an increase in deposition thickness, indicating a weakening of the inhibition effect of the inhibition treatment.

[0070] As a non-limiting example, curve 502 may correspond to a 1 second application of inhibitor, and little to no growth may occur until about 15 cycles after inhibitor application, thus illustrating inhibition (e.g., at the top of the feature) over an extended number of cycles.

[0071] 5B is a graph showing inhibition depth versus inhibition treatment time, according to an implementation of the present disclosure. As the duration of the fluorine plasma inhibition treatment increases, the depth to which the inhibition effect extends within the feature also increases, as shown by curve 510. The graph shown illustrates a feature with straight walls, and as shown, for such features the effect is approximately linear, with inhibition depth increasing approximately linearly with fluorine plasma treatment time. It will be appreciated that for other types of feature contours the effect may not be linear.

[0072] As shown, by adjusting certain parameters such as the duration of the fluorine plasma suppression treatment, it is possible to adjust the amount and depth of suppression and thereby target where deposition growth is permitted within the feature. Thus, timing (or another adjustable parameter) can be used to target the reentrancy so that growth is suppressed to the lowest reentrancy level, but still below the level of reentrancy where normal ALD growth occurs. For reentrancy located at shallower depths, shorter suppression treatment times can be used. Conversely, for reentrancy located at deeper depths, longer times can be used to target the reentrancy and stop ALD growth to the lowest reentrancy level. Thus, depending on the depth of the reentrancy, the reentrancy can be targeted using shorter times for the upper reentrancy and longer times for the lower reentrancy.

[0073] It is noted that the inhibition effect provided by the fluorine plasma treatment provided according to the implementations of the present disclosure persists over multiple ALD cycles, unlike prior art inhibition techniques. Without being bound by theory, it is hypothesized that fluorine-containing gas is initially present in the plasma, and bonds may be homolyzed to generate fluorine-localized radicals. Also, since free radicals are highly reactive, the reactivity of the fluorine radicals with the substrate is enhanced. Therefore, it is theorized that there may be chemisorption by terminated fluorine species as well as physisorption. This results in a highly inert surface structure that can withstand multiple ALD cycles.

[0074] Additionally, it is noted that some etching may result from the fluorine plasma suppression treatment. It is therefore theorized that the plasma treatment may also achieve selective deposition by selectively etching to a particular depth within the feature.

[0075] It will be appreciated that the techniques disclosed herein are applicable to gap-fill applications in trenches (STI), holes, vias, etc. By way of non-limiting example, the deposited materials may include nitrides, oxides, polysilicon, silicon, etc. By way of non-limiting example, the techniques disclosed herein may be useful in processes for building NAND devices, DRAM, logic, STI, horizontal gap-fill, vertical gap-fill, etc.

[0076] Techniques according to implementations of the present disclosure provide significant improvements in throughput while allowing complete gap-fill of reentrant structures without pinch-off or void formation. To address reentrancy at the top of the feature, previous deposition techniques required performing a very long inhibitor fill (e.g., performing a 20-25 second cycle of inhibitor treatment for each ALD cycle), and then once the gap-fill reached a point where shadowing was no longer present in the feature, a long etch (e.g., 30 seconds) was performed, followed by a regular ALD deposition to complete the fill. However, in contrast to conventional methods, as a non-limiting example according to implementations of the present disclosure, the present method for gap-fill can proceed by performing about 10 cycles of ALD fill, followed by 0.1-0.3 seconds of inhibition, and then repeating the process about 60-100 times to achieve a fully filled structure.

[0077] As currently described, plasma suppression can be used to control deposition depth in holes and trenches. Plasma suppression continues over multiple ALD cycles without the need to re-treat the surface. Although fluorine plasma is described, it will be understood that any fluorine-containing precursor suitable for generating fluorine plasma can be used, including, by way of non-limiting example, CH3F, CHF3, CF4, C2H4F2, C2H2F4, C3H2F6, C4H2F8, C4F8, NF3, SF6, and the like. In addition, although fluorine plasma is specifically described, it will be understood that other suppressors can be used, including: NH3, ethylenediamine, methylamine, dimethylamine, trimethylamine, t-butylamine, ethylamine, bis-diethylamine, trimethylamine, methanol, ethanol, propanol, isopropanol, ethanediol, alcoholamine, ethanolamine, and the like.

[0078] 6A, 6B, and 6C conceptually show cross-sections of features on a substrate to illustrate a gap-fill process according to implementations of the present disclosure. As shown in FIG. 6A, a feature 600 is defined in a substrate. The feature 600 includes a re-entrancy 602. To fill the feature 600, it is desirable to minimize or reduce growth above the re-entrancy 602 while allowing growth up to and including the re-entrancy 602. Thus, broadly speaking, as one moves down the feature 600, as shown, the level at which the re-entrancy 602 begins defines a target inhibition level, whereby growth above the target inhibition level is inhibited and growth below the target inhibition level is permitted.

[0079] Accordingly, a gap-fill procedure according to implementations of the present disclosure can be used to fill feature 600, including gap-filling of re-entrancy 602, while avoiding pinch-off or void formation due to re-entrancy 602. That is, ALD+inhibition processing cycles can be adjusted such that ALD growth is inhibited above re-entrancy 602, while faster growth is permitted below re-entrancy 602 and up to re-entrancy 602, as shown in FIG. 6B. It will be appreciated that each cycle includes multiple ALD cycles combined with a single inhibition process. In some implementations, the gap-fill process fills above the re-entrancy more slowly, so that the re-entrancy is filled before the region above the re-entrancy is filled. This process allows for complete gap-filling of feature 600 without voids, as shown in FIG. 6C.

[0080] 7A-7F show cross-sections of a feature having multiple re-entranties illustrating a process for gap filling according to implementations of the present disclosure. As shown in FIG. 7A, the feature 700 includes a first re-entranty 702 located deep within the feature 700 and a second re-entranty 704 located toward the center of the feature 700. The first re-entranty 702 defines a first inhibition target level, and inhibition at this level is targeted to allow growth up to and including the first re-entranty 702 while inhibiting growth above this level.

[0081] Thus, as shown in Figure 7B, a first cycle of an ALD+ inhibition process is performed targeting a first inhibition target level. In response, as shown in Figure 7C, feature 700 is filled up to and including first re-entrancy 702 without forming voids.

[0082] Similar to that described with respect to the first re-entrancy 702, the second re-entrancy 704 also defines a second suppression target level, with suppression at this level targeted to allow growth up to and including the second re-entrancy 704, while suppressing growth above this level.

[0083] Thus, as shown in Figure 7D, a second cycle of the ALD+ inhibition process is performed targeting a second inhibition target level. In response, as shown in Figure 7E, feature 700 is filled up to and including second re-entrancy 704 without forming voids.

[0084] After the first and second reentrant fill is accomplished, in some implementations, regular ALD is then performed (without an inhibit process) to complete the gap fill of feature 700, as shown in FIG. 7F.

[0085] Deposition-etch-deposition (DED) (e.g., ALD oxide → etch → repeat) and inhibition (e.g., fluorine inhibition as described above) based deposition processes have been demonstrated to fill high aspect ratio vias, holes, and trenches, as described above. However, DED / inhibition methods encounter throughput limitations due to existing hardware configurations when compared to standard ALD-based growth techniques.

[0086] Thus, according to implementations of the present disclosure, hardware enhancements are combined with DED / inhibition techniques for filling high aspect ratio structures with reentrant features to provide throughput comparable to or greater than standard ALD fill processes. The overall throughput of ALD films grown under standard ALD process conditions is also improved. To achieve higher throughput, a combination of new growth techniques and new hardware is utilized. More specifically, in terms of hardware, a new set of manifolds is used to enable fast cycle times of etch / inhibit / passivate gases. Etch / inhibit / passivate gases are utilized to reshape / treat the surface to enable gap-free growth.

[0087] 8 shows a gas supply system for supplying process gases to a process chamber for an ALD process according to an implementation of the present disclosure. A central gas supply 800 is configured to deliver the system's process gases to a showerhead 856. The central gas supply 800 is defined by several segments and manifolds to allow various gases to be supplied to the showerhead 856 and thereby into the process chamber.

[0088] As shown, the central gas supply 800 includes a supply line 806 through which an inert gas 802 is supplied to the central gas supply 800. The flow of the inert gas 802 into the central gas supply 800 may be controlled by a valve 804.

[0089] The central gas supply 800 further includes a manifold 808 configured to enable delivery of an oxidant 812 into the central gas supply 800. The oxidant 812 is delivered through a supply line 810 that connects to the manifold 808. Further, the flow of the oxidant into the manifold 808 may be controlled by a valve 814. Additionally, in some implementations, the oxidant may be diverted through a valve 816, as shown.

[0090] Segments 818 connect between manifold 808 and manifold 820. Manifold 820 is configured to allow delivery of suppression or passivation gas 824 into central gas supply 800. The suppression / passivation gas 824 is delivered through a supply line 822 that connects to manifold 820. The delivery of suppression / passivation gas 824 is controlled by a valve 826. In the illustrated implementation, an actuator 828 is configured to control the opening / closing of valve 826.

[0091] Segment 830 connects between manifold 820 and manifold 832. Manifold 832 is configured to allow delivery of cleaning or etching gas 836 into central gas supply 800. Cleaning / etching gas 836 is delivered through supply line 834 that connects to manifold 832. Delivery of cleaning / etching gas 836 is controlled by valve 838. In the illustrated implementation, actuator 840 is configured to control the opening / closing of valve 838.

[0092] Segment 842 connects between manifold 832 and manifold 844. Manifold 844 is configured to allow delivery of ALD precursor gases 848 into central gas supply 800. ALD precursor gases 848 are delivered through supply lines 846 that connect to manifold 844. Delivery of ALD precursor gases 848 is controlled by valves 850. In the illustrated implementation, an inert gas 802 can also be delivered through supply lines 846, controlled by valve 852. Such an inert gas can be used to purge supply lines 846 of any precursor remaining after a dose of ALD precursor.

[0093] A segment 854 connects to the manifold 844 and directs gases to a showerhead 856 that is configured to deliver process gases into the process chamber.

[0094] As shown, the inhibiting / passivating gas and the cleaning / etching gas are supplied through separate manifolds, both of which are entirely independent from the delivery of the ALD precursor gases 848 and the oxidizer 812.

[0095] 9A and 9B show the difference between existing systems and a system that includes separate manifolds for delivering inhibit / passivation gases and cleaning / etching gases.

[0096] FIG. 9A shows the configuration of an existing system. As shown, gases are delivered to the process chamber in two manifolds. The oxidizer (e.g., for the second dose step of the ALD process) is delivered through one manifold. However, the deposition (ALD precursor) gas and the etch / clean (e.g., fluorine-containing) gas are delivered through another manifold. Because the deposition and cleaning / etch gases share a manifold, the precursor / cleaning-etch manifold needs to be flushed when switching between the deposition and etch-clean processes, resulting in processing delays. For example, switching between the ALD precursor and fluorine-containing gases may require a long purge, taking a total time on the order of 100-300 seconds.

[0097] 9B shows a configuration of a system with separate manifolds for various process gases in accordance with an implementation of the present disclosure. To overcome the requirement for purging, separate inhibit, cleaning-etch, oxidizer, and precursor manifolds are utilized to increase throughput. Long purge times (e.g., minutes) can be reduced to seconds, allowing ALD-like deposition-etch-inhibit / passivate cycle times.

[0098] For example, in the case of fluorine-containing suppression gases as described above, the fluorine-containing gases can be delivered through a cleaning-etching manifold that is separate from the ALD precursor manifold, and thus the long purges previously required are no longer necessary. In addition, the system can accommodate the use of other suppression gases, which also have separate suppression / passivation manifolds for delivery.

[0099] Both the cleaning-etching manifold and the inhibit / passivation manifold are separate from the ALD precursor manifold, and therefore the entire ALD process is independent in terms of gas delivery from the inhibit or fluorine treatment gases. This allows for faster switching times for the various processes, allowing combinations of ALD, etching, and inhibit / passivation processes to be run in rapid succession with minimal switching times, thereby improving system throughput.

[0100] 10A, 10B, and 10C show the improvement in gap-filling performance possible using the techniques according to the implementations of the present disclosure. FIG. 10A conceptually shows a cross-section of a feature 1000 after a gap-filling process using a standard ALD process according to best known methods. The resulting gap-filling 1002 may contain voids 1004. In general, it is desirable to minimize such voids so that they are as deep as possible, but also so that the gap-filling deposition is performed as fast as possible. FIG. 10B shows the gap-filling of the feature 1000 using a high-throughput ALD process, for example, with a process time reduced by 0.3 times that of the standard ALD process. However, as shown, the gap-filling 1006 shows a worse result, with the voids 1008 extending higher and wider than those of the standard ALD process. Although the throughput is improved, the gap-filling performance is compromised.

[0101] 10C, however, illustrates gap-filling of a feature using a DED process utilizing techniques and hardware according to implementations of the present disclosure, followed by a high-throughput ALD process (e.g., DED to overcome reentrancy, followed by high-throughput ALD to complete the fill). Minimal or no voids 1012 are observed in the resulting gap-filling 1010, and throughput is improved to 0.5 times the process time of standard ALD.

[0102] FIG. 11 illustrates a cluster tool system 1100 for processing substrates according to an implementation of the present disclosure. The cluster tool system is typically installed in a manufacturing facility. A transport container 1102 (e.g., a front-opening integrated pod (FOUP)) is utilized to move substrates (e.g., wafers) to and from the cluster tool system. The equipment front-end module (EFEM) 1104 includes a robot 1106 configured to transfer wafers between the transport module 1102 and a load lock 1108. The transfer module 1110 includes a robot 1112 configured to transfer wafers between the load lock 1108 and one of several process tools 1114. In the illustrated implementation, each of the process tools 1114 is a multi-station process tool having multiple process stations 1116 and capable of processing multiple wafers simultaneously. For example, in the illustrated implementation, each multi-station process tool 1114 has four process stations 1116 and is capable of processing four wafers simultaneously (e.g., performing an ALD process as described in accordance with an implementation of the present disclosure).

[0103] In some implementations, the controller is part of a system that may be part of the examples described above. Such systems may include semiconductor processing equipment, including processing tool(s), chamber(s), processing platform(s), and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems may be integrated with electronics for controlling pre-, during, and post-processing operations of semiconductor wafers or substrates. The electronics may be referred to as a "controller" and may control various components or subparts of the system(s). The controller may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer to and from tools and other transport tools and / or load locks connected or interfaced with the particular system, depending on the processing requirements and / or type of system.

[0104] Broadly speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software to receive instructions, issue instructions, control operations, enable cleaning operations, and enable endpoint measurements. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. In some implementations, the operational parameters may be part of a recipe defined by a process engineer to achieve one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0105] The controller, in some implementations, may be part of or connected to a computer that is integrated or connected to the system or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a fab host computer system, which may enable remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance indicators from multiple manufacturing operations, modify parameters of a current process, set processing steps following a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step that is performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more individual controllers networked together and operating toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes may be one or more integrated circuits on the chamber in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the process in the chamber.

[0106] Without being limited thereto, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0107] As described above, depending on the process steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from tool locations and / or load ports in a semiconductor manufacturing factory to transport wafer containers in and out of the tool locations.

[0108] 12 is a simplified schematic diagram of a computer system for carrying out an implementation of the present disclosure. It should be understood that the methods described herein may be carried out on a digital processing system, such as a conventional general-purpose computer system. In the alternative, a special-purpose computer designed or programmed to perform only one function may be used. The computer system 1800 includes a central processing unit (CPU) 1804 coupled to a random access memory (RAM) 1828, a read-only memory (ROM) 1812, and a mass storage device 1814 via a bus 1810. A system controller program 1808 resides in the random access memory (RAM) 1828, but may also reside in the mass storage device 1814.

[0109] Mass storage device 1814 represents a persistent data storage device, such as a floppy disk drive or fixed disk drive, which may be local or remote. Network interface 1830 provides a connection over network 1832 to allow communication with other devices. It should be understood that CPU 1804 may be embodied with a general purpose processor, a special purpose processor, or a specially programmed logic device. Input / output (I / O) interface 1820 provides communication with various peripherals and is connected to CPU 1804, RAM 1828, ROM 1812, and mass storage device 1814 via bus 1810. Exemplary peripherals include a display 1818, a keyboard 1822, a cursor control 1824, a removable media device 1834, and the like.

[0110] The display 1818 is configured to display the user interface described herein. A keyboard 1822, a cursor control (mouse) 1824, a removable media device 1834, and other peripherals are coupled to the I / O interface 1820 for communicating information in command selection to the CPU 1804. It should be understood that data to and from external devices may be communicated via the I / O interface 1820. Implementations may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a wired or wireless network.

[0111] Implementations may be practiced with a variety of computer system configurations, including handheld devices, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. Implementations may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a network.

[0112] With the above implementations in mind, it should be understood that the implementations employ various computer-implemented operations involving data stored in computer systems. These operations are operations requiring physical manipulation of physical quantities. Any operations described herein that form part of the implementations are useful machine operations. The implementations also relate to devices or apparatus for performing these operations. An apparatus may be specially constructed for the required purpose, such as a special purpose computer. When defined as a special purpose computer, the computer may also perform other processes, program execution, or routines that are not part of the special purpose while being capable of operating for the special purpose. Alternatively, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or retrieved over a network. If the data is retrieved over a network, the data may be processed by other computers on the network, for example, a cloud of computing resources.

[0113] One or more implementations can also be made as computer readable code on a computer readable medium. The computer readable medium is any data storage device that can store data that can be read later by a computer system. Examples of computer readable media include hard drives, network attached storage (NAS), read-only memory, random access memory, CD-ROM, CD-R, CD-RW, magnetic tape, and other optical and non-optical data storage devices. The computer readable medium can include computer readable tangible media distributed across computer systems coupled to a network, such that the computer readable code is stored and executed in a distributed manner.

[0114] Although the method operations are described in a particular order, it should be understood that other housekeeping operations may be performed between operations, or operations may be coordinated so that they occur at slightly different times, or may be distributed within the system to allow processing operations to occur at various time intervals associated with the processing, so long as the processing of the overlay operation is performed in the desired manner.

[0115] Accordingly, the disclosure of the exemplary implementations is intended to illustrate, but not limit, the scope of the disclosure, which is set forth in the following claims and their equivalents. Although the exemplary implementations of the present disclosure have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the following claims. In the following claims, the elements and / or steps do not imply any particular order of operations unless expressly recited in the claims or implicitly required by the disclosure.

Claims

1. 1. A method for performing gap filling of features on a substrate, comprising: (a) moving the substrate into a process chamber; (b) performing multiple cycles of an ALD process; (c) purging process gas from the ALD process from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine containing gas into the process chamber and applying RF power to the fluorine containing gas to generate a fluorine plasma in the process chamber; (e) purging process gas from the plasma treatment from the process chamber; (f) repeating operations (b) through (e) until a predetermined number of cycles have been performed.

2. 2. The method of claim 1, wherein the fluorine plasma passivates a portion of the feature on the substrate, thereby inhibiting deposition by the ALD process on the portion of the feature that has been passivated.

3. 3. The method of claim 2, wherein the portion of the feature that is passivated extends from a top of the feature to a predetermined target level within the feature.

4. The method of claim 3 , wherein the predetermined target level is controlled by one or more parameters of the plasma process.

5. 5. The method of claim 4, wherein the parameters of the plasma treatment include one or more of a duration of the plasma treatment, a temperature of the plasma treatment, a pressure of the fluorine-containing gas, and a level of the RF power.

6. 4. The method of claim 3 , wherein the feature includes a reentrancy and the predetermined target level is defined at approximately the level of the reentrancy, such that the plasma treatment substantially inhibits deposition by the ALD process above the level of the reentrancy.

7. 3. The method of claim 2, wherein the fluorine plasma passivates the portion of the feature by forming fluorine-terminated species along a surface of the portion of the feature.

8. 2. The method of claim 1 , (g) performing one or more cycles of said ALD process.

9. 10. The method of claim 8, wherein the predetermined number of cycles of operation (e) is configured to perform gap filling to eliminate reentrancy in the feature.

10. 10. The method of claim 9, wherein one or more cycles of the ALD process of operation (g) are configured to complete the gap filling of the feature.

11. 2. The method of claim 1, wherein the ALD process is configured to deposit an oxide in the feature of the substrate.

12. 2. The method of claim 1, wherein the fluorine-containing gas is CH 3 F, C.H.F. 3 , C.F. 4 , C 2 H 4 F 2 , C 2 H 2 F 4 , C 3 H 2 F 6 , C 4 H 2 F 8 , C 4 F 8 , N.F. 3 , or Sci-Fi 6 That is, the method.

13. 1. A method for performing gap filling of features on a substrate, comprising: (a) moving the substrate into a process chamber; (b) performing a plurality of cycles of an ALD process, the ALD process configured to deposit an oxide in the feature of the substrate; and (c) purging process gas from the ALD process from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine containing gas into the process chamber and applying RF power to the fluorine containing gas to generate a fluorine plasma in the process chamber; (e) purging process gas from the plasma treatment from the process chamber; (f) repeating operations (b) through (e) until a predetermined number of cycles have been performed; and (g) performing multiple cycles of said ALD process.

14. 14. The method of claim 13, wherein the fluorine plasma passivates a portion of the feature on the substrate, thereby inhibiting deposition by the ALD process on the portion of the feature that is passivated.

15. 15. The method of claim 14, wherein the portion of the feature that is passivated extends from a top of the feature to a predetermined target level within the feature.

16. 16. The method of claim 15, wherein the predetermined target level is controlled by one or more parameters of the plasma process.

17. 17. The method of claim 16, wherein the parameters of the plasma treatment include one or more of a duration of the plasma treatment, a temperature of the plasma treatment, a pressure of the fluorine-containing gas, and a level of the RF power.

18. 1. A method for performing gap filling of features on a substrate, comprising: (a) moving the substrate into a process chamber; (b) performing multiple cycles of an ALD process; (c) purging process gas from the ALD process from the process chamber; (d) performing a plasma treatment on the substrate by introducing a fluorine-containing gas into the process chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the process chamber, the RF power being applied at a frequency in the range of about 200-600 kHz; (e) purging process gas from the plasma treatment from the process chamber; (f) repeating operations (b) through (e) until a predetermined number of cycles have been performed.

19. 20. The method of claim 18, wherein the plasma treatment pressure is in the range of about 0.5 to 8 Torr.

20. The method of claim 18, wherein the duration of the plasma treatment is in the range of about 0.1 to 3 seconds.

21. 1. A gas delivery system for delivering process gas to a process chamber for ALD processes and plasma processing, comprising: a central gas supply having a first end for receiving an inert gas, the central gas supply having a second end for connecting to a showerhead, the showerhead delivering process gas to the process chamber; the central gas supply includes a first manifold for receiving and delivering an ALD precursor gas into the central gas supply, the ALD precursor gas being used for a first dose step of the ALD process; the central gas supply includes a second manifold that receives and delivers an oxidizer gas into the central gas supply, the oxidizer gas being used for a second dose step of the ALD process; A gas delivery system, wherein the central gas supply includes a third manifold that receives and delivers a fluorine-containing gas into the central gas supply, the fluorine-containing gas being used to generate a plasma in the process chamber for the plasma treatment.

22. 22. The gas supply system of claim 21 , wherein the first manifold, the second manifold, and the third manifold are independent and separately deliver the ALD precursor gas, the oxidizer gas, and the fluorine-containing gas into the central gas supply.

23. 22. The gas supply system of claim 21, wherein the first manifold is disposed along the central gas supply downstream of the second manifold and the third manifold.

24. 24. The gas supply system of claim 23, wherein the second manifold is disposed along the central gas supply upstream of the third manifold.

25. 22. The gas supply system of claim 21, a supply line connected to the first manifold; and a valve controlling the flow of the ALD precursor gas to the supply line.

26. 26. The gas supply system of claim 25, The gas supply system further comprising a second valve controlling the flow of the inert gas into the supply line.

27. 22. The gas supply system of claim 21, a supply line connected to the second manifold; a valve controlling the flow of the oxidant gas to the supply line.

28. 22. The gas supply system of claim 21, a supply line connected to the third manifold; a valve controlling the flow of the fluorine-containing gas into the supply line.

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