Display substrate and display device

Abstract

To provide a display substrate and a display device.SOLUTION: A display substrate includes a sub-pixel, the sub-pixel includes a pixel circuit, the pixel circuit includes a data writing sub-circuit, a storage sub-circuit, and a driving sub-circuit. The display substrate further includes a first connection electrode, and the storage sub-circuit includes a storage capacitor. The first connection electrode is arranged at the same layer as one capacitor electrode of the storage capacitor in an insulating manner, and electrically connects another one capacitor electrode of the storage capacitor and the data writing sub-circuit. The display substrate is useful for optimizing a process.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] This application is a divisional application of an invention patent application having application number 2022-503870 and title of the invention "Display substrate and display device." The embodiments of the present disclosure relate to a display substrate and a display device. [Background technology]

[0002] Micro OLED displays involve the combination of organic light-emitting diode (OLED) technology and CMOS technology, and are associated with the mutual integration of the optoelectronics industry and the microelectronics industry. They are promoting the development of next-generation micro display technology, and are also promoting the research and development of organic electronics on silicon and even molecular electronics on silicon.

[0003] Micro OLED displays have excellent display characteristics such as high resolution, high brightness, rich colors, low driving voltage, high response speed, and low power consumption, and are expected to be a promising display device. Summary of the Invention [Means for solving the problem]

[0004] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate and sub-pixels on the base substrate. the sub-pixel includes a pixel circuit including a data writing sub-circuit, a recording sub-circuit, and a driving sub-circuit, the recording sub-circuit includes a storage capacitor, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode are respectively a first terminal and a second terminal of the recording sub-circuit, the data writing sub-circuit is electrically connected to the first terminal of the recording sub-circuit and configured to transmit a data signal to the first terminal of the recording sub-circuit in response to a control signal, the driving sub-circuit includes a control electrode, a first electrode and a second electrode, the control electrode of the driving sub-circuit is electrically connected to the first terminal of the recording sub-circuit, the driving sub-circuit is configured to control a driving current flowing from the first electrode to the second electrode in response to a voltage of the first terminal of the recording sub-circuit and driving the light emitting element to emit light, the display substrate further includes a first connecting electrode, the first connecting electrode is insulated and installed in the same layer as the second capacitor, and electrically connects the first capacitor electrode and the data writing sub-circuit.

[0005] In some examples, the first electrode includes a first portion extending along a first direction and a second portion extending along a second direction, the first portion and the second portion being an integral structure, the first direction and the second direction being perpendicular to each other, the first portion being electrically connected to the data writing sub-circuit, and the second portion being electrically connected to the first capacitor electrode.

[0006] In some examples, an orthogonal projection of the first portion of the first connection electrode onto the base substrate does not overlap with an orthogonal projection of the storage capacitor onto the base substrate.

[0007] In some examples, the drive subcircuit includes a drive transistor, the gate, first pole and second pole of the drive transistor being the control electrode, first electrode and second electrode of the drive subcircuit, respectively, and the first connection electrode does not overlap with the channel region of the transistor in a direction perpendicular to the base substrate.

[0008] In some examples, the semiconductor device further includes a polysilicon layer located on the base substrate, the control electrode of the drive subcircuit being located on the polysilicon layer, and the first connection electrode being located on a side of the polysilicon layer away from the base substrate.

[0009] In some examples, a current path of the driving current flowing from a first electrode of the driving sub-circuit to the light emitting element includes, in order, a first straight current path, a second folded line current path, and a third U-shaped current path.

[0010] In some examples, the second fold line current path and the first straight current path are located in different layer structures of the display substrate.

[0011] In some examples, the first straight current path is located within the base substrate, and the second folded line current path is located within a layer structure in which the first connection electrode is located.

[0012] In some examples, the semiconductor device further includes a second connecting electrode, the second folding line current path being located in the second connecting electrode, and a first terminal of the second connecting electrode being electrically connected to a second electrode of the driving sub-circuit.

[0013] In some examples, the first connection electrode and the second connection electrode do not overlap in a direction perpendicular to the base substrate.

[0014] In some examples, the second connection electrode is insulated from the first connection electrode on the same layer.

[0015] In some examples, the base substrate further includes a U-shaped resistor, one end of the U-shaped resistor configured to be electrically connected to a second terminal of the second connection electrode and the other end of the U-shaped resistor configured to be electrically connected to the light-emitting element, and the third U-shaped current path is located in the U-shaped resistor.

[0016] In some examples, the U-shaped resistor and the control electrode are located in a polysilicon layer, and the resistivity of the U-shaped resistor is higher than the resistivity of the control electrode of the drive sub-circuit.

[0017] In some examples, the second connection electrode and the first capacitor electrode at least partially overlap in a direction perpendicular to the base substrate.

[0018] In some examples, the opening of the third U-shaped current path faces towards the drive sub-circuit.

[0019] In some examples, the recording sub-circuit further includes a third capacitor electrode located on a side of the first capacitor electrode remote from the second capacitor electrode and configured to be electrically connected to the second capacitor electrode.

[0020] In some examples, the third capacitor electrode is located on the base substrate.

[0021] In some examples, the display substrate includes a plurality of the sub-pixels, the plurality of sub-pixels being arranged as an array along a first direction and a second direction, the data writing sub-circuit, the first connection electrode and the driving sub-circuit being arranged in sequence along the second direction, which is different from the first direction and the second direction.

[0022] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate and the light-emitting element on the display substrate.

[0023] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below, and it is obvious that the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure. [Brief description of the drawings]

[0024] [Figure 1A]FIG. 1A is a schematic diagram 1 of a display substrate according to at least one embodiment of the present disclosure. [Figure 1B] FIG. 1B is a pixel circuit diagram 1 according to at least one embodiment of the present disclosure. [Figure 1C] FIG. 1C is a schematic diagram showing the structure of a pixel circuit. [Figure 2A] FIG. 2A is a pixel circuit diagram 2 according to at least one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a pixel circuit diagram 3 according to at least one embodiment of the present disclosure. [Figure 2C] FIG. 2C is a signal timing diagram of a pixel circuit in accordance with at least one embodiment of the present disclosure. [Figure 3A] FIG. 3A is a schematic diagram 2 of a display substrate according to at least one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic diagram of the cross-section of the display substrate shown in FIG. 3A taken along line II'. [Figure 4A] FIG. 4A is a schematic diagram 3 of a display substrate according to at least one embodiment of the present disclosure. [Figure 4B] FIG. 4B is an enlarged schematic diagram of one sub-pixel of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] FIG. 5A shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5B] FIG. 5B shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5C] FIG. 5C shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5D] FIG. 5D shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 5E] FIG. 5E shows a diagram of the fabrication steps of the display substrate shown in FIG. 4A. [Figure 6A] FIG. 6A is a schematic diagram of a first conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 6B] FIG. 6B is a schematic diagram of a first conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 6C]FIG. 6C shows a cross-sectional view along the section line IV-IV' of FIG. 6B. [Figure 7A] FIG. 7A is a schematic diagram of a second conductive layer of a display substrate in accordance with at least one embodiment of the present disclosure. [Figure 7B] FIG. 7B is a schematic diagram of a second conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 8A] FIG. 8A is a schematic diagram of a third conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 8B] FIG. 8B is a schematic diagram of a third conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 9A] FIG. 9A is a schematic diagram of a fourth conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 9B] FIG. 9B is a schematic diagram of a fourth conductive layer of a display substrate according to at least one embodiment of the present disclosure. [Figure 10A] FIG. 10A is a schematic diagram 4 of a display substrate according to at least one embodiment of the present disclosure. [Figure 10B] FIG. 10B is an enlarged schematic diagram of the area of ​​the display substrate shown by the dashed line in FIG. 10A. [Figure 10C] FIG. 10C is a cross-sectional view taken along the cross-sectional line VV' of FIG. 10B. [Figure 11A] FIG. 11A is a schematic diagram 5 of a display substrate according to at least one embodiment of the present disclosure. [Figure 11B] FIG. 11B is a schematic diagram 6 of a display substrate according to at least one embodiment of the present disclosure. [Figure 11C] FIG. 11C is a cross-sectional view taken along line II-II' of the display substrate shown in FIG. 11B. [Figure 11D] FIG. 11D is a cross-sectional view taken along line III-III' of the display substrate shown in FIG. 11B. [Figure 12] FIG. 12 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Of course, the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments that a person skilled in the art can obtain without inventive work belong to the protection scope of the present disclosure.

[0026] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning understood by those skilled in the art. The words "first", "second" and similar words used in this disclosure do not indicate order, number, or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not limit the quantity, but mean that there is at least one. Similar words such as "comprise" or "comprise" mean that the element or part shown before the word includes the element or part listed after the word and its equivalents, but does not exclude other elements or parts. Similar words such as "connect" or "couple" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. "Top", "bottom", "left", "right", etc. are used only to indicate relative positional relationships, and when the absolute position of the objects being described changes, the relative positional relationships may change accordingly.

[0027] In the field of OLED (Organic Light-Emitting Diode) displays, with the rapid development of high-resolution products, the requirements for the structural design of the display substrate, such as the arrangement of pixels and signal lines, are increasing. For example, compared with an OLED display device with a resolution of 4K, a large OLED display device with a resolution of 8K requires twice as many sub-pixel units to be installed, and accordingly the pixel density is doubled. On the one hand, the line width of the signal line is correspondingly smaller, resulting in a higher resistance of the signal line itself, and on the other hand, the signal lines are more likely to overlap with each other, resulting in a higher parasitic capacitance of the signal line, which leads to a higher resistive-capacitive load on the signal line. Accordingly, phenomena such as signal delay (RC delay), voltage drop (IR drop), and voltage rise (IR rise) caused by the resistive-capacitive load become serious. These phenomena seriously impair the display quality of the display product.

[0028] Micro OLED displays generally have a size smaller than 100 micrometers, such as a size smaller than 50 micrometers, and involve the combination of organic light emitting diode (OLED) technology with CMOS technology, where an OLED array is fabricated on a silicon-based substrate that contains the CMOS circuitry.

[0029] Micro OLED is widely applied in the fields of AR and VR. With the continuous development of technology, higher resolution is required, which increases the requirements for the structural design of the display substrate, such as the arrangement of pixels and signal lines.

[0030] A display substrate according to at least one embodiment of the present disclosure can achieve a sub-pixel area of ​​5.45um x 13.6um through optimized layout and wiring design processing in the design, thereby achieving high resolution (PPI) and optimized arrangement of the pixel circuit array, while having a relatively good display effect.

[0031] FIG. 1A is a block diagram of a display substrate according to at least one embodiment of the present disclosure. As shown in FIG. 1A, the display substrate 10 includes a plurality of sub-pixels 100, a plurality of scan lines 11, and a plurality of data lines 12 distributed in an array. Each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element. The plurality of scan lines 11 and the plurality of data lines 12 cross each other to define a plurality of pixel regions distributed in an array in the display region, and the pixel circuit of one sub-pixel 100 is installed in each pixel region. The pixel circuit is, for example, a normal pixel circuit, for example, a 2T1C (i.e., two transistors and one capacitor) pixel circuit, an nTmC (n, m are positive integers) pixel circuit such as 4T2C, 5T1C, 7T1C, etc., and in different embodiments, the pixel circuit may further include a compensation sub-circuit, including an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include a transistor, a capacitor, etc. For example, the pixel circuit may further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc., as necessary. For example, the display substrate may further include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in a non-display area. The gate driving sub-circuit 13 is connected to the pixel circuits via the scan lines 11 to provide various scanning signals, and the data driving sub-circuit 14 is connected to the pixel circuits via the data lines 12 to provide data signals. The positional relationship between the gate driving sub-circuit 13 and the data driving sub-circuit 14 on the display substrate, and the positional relationship between the scan lines 11 and the data lines 12 on the display substrate shown in Fig. 1A are merely examples, and the actual arrangement positions can be designed as needed.

[0032] For example, the display substrate 10 may further include a control circuit (not shown). For example, the control circuit may be configured to control the data driving sub-circuit 14 to apply the data signals and to control the gate driving sub-circuit to apply the scan signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and a memory, the memory including executable code, and the processor executing the executable code to perform the detection method.

[0033] For example, a processor may be a central processing unit (CPU) or other form of processing device having data processing capabilities and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), and the like.

[0034] For example, a recording device may include one or more computer program products, which may include various forms of computer-readable recording media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. The computer-readable recording media may store one or more computer program instructions, and the processor may execute the functions desired by the program instructions. The computer-readable recording media may further store various application programs and various data.

[0035] The pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a recording sub-circuit as required, and may further include a light emission control sub-circuit, a reset circuit, etc. as required.

[0036] 1B shows a schematic diagram of a pixel circuit. As shown in FIG. 1B, the pixel circuit includes a data writing sub-circuit 111, a driving sub-circuit 112 and a recording sub-circuit 113.

[0037] The data writing sub-circuit 111 is electrically connected to a first terminal of the recording sub-circuit 113 and configured to transmit a data signal Vd to the first terminal of the recording sub-circuit 113 in response to a control signal (first control signal SEL). A second terminal of the recording sub-circuit 113 is configured to receive, for example, a second power supply voltage VSS.

[0038] The driving sub-circuit 112 includes a control electrode (control terminal) 150, a first electrode (first terminal) 151 and a second electrode (second terminal) 152, where the control electrode 150 of the driving sub-circuit is electrically connected to the first terminal of the recording sub-circuit, the first electrode 151 of the driving sub-circuit 112 is configured to receive a first power supply voltage VDD, and the second electrode 152 of the driving sub-circuit 112 is electrically connected to a first node S and connected to a first electrode 121 of the light-emitting element 120. The driving sub-circuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage of the first terminal of the recording sub-circuit. The second electrode 122 of the light-emitting element 120 is configured to receive, for example, a first common voltage Vcom1.

[0039] In at least some embodiments of the present disclosure, as shown in FIG. 1B, the pixel circuit further includes a bias sub-circuit 114. The bias sub-circuit 114 includes a control terminal, a first terminal and a second terminal, the control terminal of the bias sub-circuit 114 is configured to receive a bias signal, the first terminal of the bias sub-circuit 114 is configured to receive, for example, a second power supply voltage VSS, and the second terminal of the bias sub-circuit 114 is electrically connected to a first node S. For example, the bias signal is a second common voltage Vcom2. For example, the bias signal Vcom2 is a constant voltage signal, for example, 0.8V-1V, and the bias sub-circuit 114 is in a normally open state under the action of the bias signal and is configured to provide a constant current, so that the voltage applied to the light-emitting element 120 and the data signal have a linear relationship, which contributes to controlling the gray scale with high precision, thereby improving the display effect. Hereinafter, the description will be further given with reference to a specific circuit.

[0040] For example, when the data signal (voltage) Vd changes from high to low, the grayscale voltage of the first electrode 121 of the write light-emitting element 120 needs to change quickly, and the bias sub-circuit 114 can also allow the first electrode 121 of the light-emitting element 120 to release charge quickly, thereby achieving good dynamic contrast.

[0041] The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or switching devices with the same characteristics, and in the embodiments of the present disclosure, a metal-oxide semiconductor field effect transistor is taken as an example for description. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain do not need to be structurally distinguished. In the embodiments of the present disclosure, in order to distinguish between the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole as the second pole. In addition, according to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the on voltage is a low level voltage (e.g., 0V, -5V, -10V or other suitable voltage), and the off voltage is a high level voltage (e.g., 5V, 10V or other suitable voltage), and when the transistor is an N-type transistor, the on voltage is a high level voltage (e.g., 5V, 10V or other suitable voltage), and the off voltage is a low level voltage (e.g., 0V, -5V, -10V or other suitable voltage).

[0042] The display substrate according to the embodiment of the present disclosure may be a rigid substrate such as a glass substrate, a silicon substrate, or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC), etc. All the embodiments of the present disclosure are described using a silicon substrate as an example, that is, the pixel structure is fabricated on a silicon substrate, but the embodiments of the present disclosure are not limited thereto.

[0043] For example, the pixel circuit includes a complementary metal oxide semiconductor circuit (CMOS circuit), i.e., the pixel circuit is fabricated on a single crystal silicon-based substrate. Due to the mature CMOS integrated circuit technology, silicon-based processes can achieve high precision (e.g., PPI can reach 6500 or even 10000 or more).

[0044] For example, due to process variations in the display substrate, a short circuit may occur between the first electrode 121 and the second electrode 122 of the light-emitting element 120 in a sub-pixel, causing the voltage of the first electrode 121 of the light-emitting element 120 to be too high (e.g., the first common voltage Vcom1 is at a high potential) or too low (e.g., the first common voltage Vcom1 is at a low potential), causing the PN junction formed between the second electrode of the driving sub-circuit and the base substrate to turn on, resulting in a failure of the CMOS circuit and causing defects such as dark lines on the display substrate.

[0045] In some examples, for example, the data write sub-circuit includes a first data write transistor P1, and the driving sub-circuit includes a driving transistor N2. For example, the first data write transistor is a P-type metal-oxide semiconductor field effect transistor (PMOS), the driving transistor N2 is an N-type metal-oxide semiconductor field effect transistor (NMOS), and the gate, the first pole, and the second pole of the driving transistor N2 are the control electrode 150, the first electrode 151, and the second electrode 152 of the driving sub-circuit 112, respectively. In this case, for example, when the first common voltage Vcom1 provided to the second electrode 122 of the light-emitting element 120 is at a low potential, and the first electrode 121 and the second electrode 122 of the light-emitting element 120 are short-circuited, this causes the potential of the second pole of the driving transistor directly connected to the first electrode 121 to be too low.

[0046] 1C shows a schematic diagram of a transistor failure in the pixel circuit. The N-type active region (e.g., second pole) of the driving transistor N2, the P-type silicon-based base, the N-type well region in which the first data write transistor P1 is located, and the P-type active region (e.g., first pole) of the first data write transistor P1 form two parasitic transistors Q1 and Q2 connected together to form an NPNP structure. Because the potential of the second pole (i.e., the first node S) of the driving transistor N2 is too low, it will cause a forward bias of the PN junction (emitter junction) between the second pole (N-type high-concentration doped region) of the driving transistor N2 and the P-type base, so that Q1 will be conductive and provide enough current to make the parasitic transistor Q2 conductive, and in turn, feed back the current to the parasitic transistor Q1, forming a vicious circle. Finally, most of the current will not be controlled by the gate voltage of the transistor, but will directly pass from VDD through the parasitic transistor to VSS, resulting in the failure of the CMOS pixel circuit. When the circuit fails, the parasitic transistor Q2 will constantly draw current from the emitter, i.e., the data line, causing the failure of a column of sub-pixels connected to the data line, resulting in defects such as dark lines appearing on the display substrate, and greatly impairing the display effect.

[0047] In at least some embodiments of the present disclosure, at least one subpixel further includes a resistor connected between the second electrode 152 of the driving subcircuit 112 and the first electrode 121 of the light-emitting element 120 to increase or decrease the potential of the first node S, thereby reducing or avoiding circuit failure, improving the reliability of the circuit, and improving the display effect.

[0048] 2A is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. As shown in FIG. 2A, the pixel circuit further includes a resistor 130, a first terminal 131 of the resistor 130 is electrically connected to the second electrode 152 of the driving sub-circuit 112, and a second terminal 132 of the resistor 130 is electrically connected to the first electrode 121 of the light-emitting element 120. That is, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 by the resistor 130.

[0049] For example, the resistor 130 may be a fixed resistor or a variable resistor, or may have an equivalent resistor formed with other devices (eg, transistors).

[0050] For example, the resistor 130 is insulated from the same layer as the control electrode 150 of the drive subcircuit 112, and the resistivity of the resistor is higher than the resistivity of the control electrode of the drive subcircuit. That is, the conductivity of the control electrode of the drive subcircuit is higher than the conductivity of the resistor. For example, the resistivity of the resistor is 10 times or more higher than the resistivity of the control electrode.

[0051] In addition, "disposed in the same layer" referred to in the present disclosure means that two (or more) types of structures are formed by the same deposition process and patterned by the same patterning process, and the materials may be the same or different. For example, the precursor materials forming the structures disposed in the same layer are the same, and the materials finally formed may be the same or different. In the present disclosure, "integral structure" means that two (or more) types of structures are formed by the same deposition process and patterned by the same patterning process, and are connected to each other, and the materials may be the same or different.

[0052] Such placement allows the control electrodes and resistors of the drive sub-circuits to be formed in the same patterning process, thereby providing process savings.

[0053] For example, the material of the resistor and the control electrode of the drive sub-circuit are both polysilicon materials, and the doping concentration of the resistor is lower than the doping concentration of the control electrode, so the resistor has a higher resistivity than the control electrode. For example, the resistor may be intrinsic polysilicon or lightly doped polysilicon, and the control electrode is heavily doped polysilicon.

[0054] In some other examples, the materials of the control electrode and the resistor may be different. For example, the materials of the control electrode and the resistor may each include a metal and a metal oxide corresponding to the metal. For example, the metal may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials combining these.

[0055] In at least one embodiment of the present disclosure, the data writing sub-circuit 111 may include a transmission gate circuit configured by connecting two complementary transistors in parallel with each other, and the control signal includes two control signals having opposite phases. The data writing sub-circuit 111 can contribute to transmitting the data signal to the first terminal of the recording sub-circuit 113 without loss by using a circuit having a transmission gate structure.

[0056] For example, the data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal and a second terminal, the first control electrode and the second control electrode of the data writing sub-circuit are configured to receive a first control signal and a second control signal, respectively, the first terminal of the data writing sub-circuit is configured to receive a data signal, and the second terminal of the data writing sub-circuit is electrically connected to the first terminal of the recording sub-circuit and configured to transmit the data signal to the first terminal of the recording sub-circuit in response to the first control signal and the second control signal.

[0057] However, in the description of the embodiments of the present disclosure, the first node S does not necessarily represent an actually existing component, but represents a junction that connects related circuits in a circuit diagram.

[0058] In the description of the embodiments of the present disclosure, the symbol Vd can indicate both the data signal terminal and the level of the data signal, the symbol SEL can indicate both the control signal and the control signal terminal, the symbols Vcom1 and Vcom2 can indicate the first common voltage and the second common voltage, and can also indicate the first common voltage terminal and the second common voltage terminal, the symbol VDD can indicate both the first voltage terminal and the first power supply voltage, and the symbol VSS can indicate both the second voltage terminal and the second power supply voltage. The following embodiments are the same as this, and the description will be omitted.

[0059] 2B shows a circuit diagram of a specific implementation of the pixel circuit shown in FIG. 2A. As shown in FIG. 2B, the data write sub-circuit 111 includes a first data write transistor P1 and a second data write transistor N1 connected in parallel with each other. The first data write transistor P1 and the second data write transistor N1 are P-type metal-oxide semiconductor field effect transistors (PMOS) and N-type metal-oxide semiconductor field effect transistors (NMOS), respectively. The control signals include a first control signal SEL and a second control signal SEL_B that are in opposite phases to each other, and the gate of the first data write transistor P1 is configured to receive the first control signal SEL as a first control electrode of the data write sub-circuit, and the gate of the second data write transistor N1 is configured to receive the second control signal SEL_B as a second control electrode of the data write sub-circuit. The first pole of the second data write transistor N1 and the first pole of the first data write transistor P1 are electrically connected to receive a data signal Vd as a first terminal of the data write sub-circuit, and the second pole of the second data write transistor N1 and the second pole of the first data write transistor P1 are electrically connected to a control electrode 150 of the driving sub-circuit 112 as a second terminal of the data write sub-circuit.

[0060] For example, the first data write transistor P1 and the second data write transistor N1 are the same size and have the same channel aspect ratio.

[0061] The data writing sub-circuit 111 utilizes the complementary electrical properties of transistors and has low on-state resistance whether it is high-level transmission or low-level transmission, thereby having the advantage of transmitting electrical signals perfectly, and the data signal Vd can be transmitted to the first terminal of the recording sub-circuit 113 without loss.

[0062] 2B, the driving sub-circuit 112 includes a driving transistor N2, for example, the driving transistor N2 is an NMOS. The gate, the first electrode and the second electrode of the driving transistor N2 are respectively the control electrode, the first electrode and the second electrode of the driving sub-circuit 112.

[0063] For example, the recording sub-circuit 113 includes a storage capacitor Cst, which includes a first capacitor electrode 141 (an example of a first capacitor electrode in the present disclosure) and a second capacitor electrode 142 (an example of a third capacitor electrode in the present disclosure), and the first capacitor electrode 141 and the second capacitor electrode 142 are respectively a first terminal and a second terminal of the recording sub-circuit 113.

[0064] For example, the resistor 130 includes a resistor R. For example, a PN junction is formed between the second electrode 152 of the driving sub-circuit 112 and the base substrate, and the resistance value of the resistor 130 is set so that the PN junction is turned off when the driving transistor N2 operates in a saturation region, that is, when the pixel circuit operates to drive the light-emitting element 120 to emit light. In this case, even if a short circuit occurs between the two electrodes of the light-emitting element 120, a voltage drop exists in the resistor 130, so that the potential of the second electrode 152 can be protected, thereby avoiding circuit failure.

[0065] For example, the resistance of resistor 130 is

number

number

[0066] For example, the light emitting element 120 is specifically realized as an organic light emitting diode (OLED). For example, the light emitting element 120 may be an OLED with a top emission structure, and may emit red light, green light, blue light, or white light, etc. For example, the light emitting element 120 is a micro OLED. The embodiments of the present disclosure do not limit the specific structure of the light emitting element. For example, the first electrode 121 of the light emitting element 120 is an anode of the OLED, and the second electrode 122 is a cathode of the OLED, that is, the pixel circuit is a common cathode structure. However, the embodiments of the present disclosure are not limited thereto, and the pixel circuit may be a common anode structure according to the change of the circuit structure.

[0067] For example, the bias sub-circuit 114 includes a bias transistor N3, the gate, the first pole and the second pole of which are the control terminal, the first terminal and the second terminal of the bias sub-circuit 114, respectively.

[0068] Figure 2C shows a signal timing diagram of the pixel circuit shown in Figure 2B, and the operation principle of the pixel circuit shown in Figure 2C will be described below with reference to the signal timing diagram shown in Figure 2B. For example, the second data write transistor, the driving transistor, and the bias transistor are all N-type transistors, and the first data write transistor is a P-type transistor, but the embodiments of the present disclosure are not limited thereto.

[0069] FIG. 2C shows waveform diagrams of each signal in two consecutive display periods T1 and T2, for example, the data signal Vd is a high gray-scale voltage in the display period T1 and a low gray-scale voltage in the display period T2.

[0070] For example, as shown in Fig. 2C, a process of displaying an image of each frame includes a data writing step 1 and an emission step 2. An operation process of the pixel circuit includes a data writing step 1 in which the first control signal SEL and the second control signal SEL_B are both on signals, the first data writing transistor P1 and the second data writing transistor N1 are conductive, and a data signal Vd is transmitted to the gate of the driving transistor N2 via the first data writing transistor P1 and the second data writing transistor N1, and an emission step 2 in which the first control signal SEL and the second control signal SEL_B are both off signals, and due to a bootstrap phenomenon of the storage capacitor Cst, the voltage across the storage capacitor Cst does not change, the driving transistor N2 operates in a saturated state, the current does not change, and the light emitting element 120 is driven to emit light. When the pixel circuit enters the display period T2 from the display period T1, the data signal Vd becomes a low gray-scale voltage from a high gray-scale voltage, and the bias transistor N3 generates a stable drain current under the control of the second common voltage Vcom2, which can quickly discharge the charge stored in the OLED anode when the display gray scale of the OLED needs to change quickly. For example, the discharge process occurs in the data writing stage 1 of the display period T2, so that in the light emission stage 2 of the display period T2, the voltage of the OLED anode drops quickly, thereby realizing a high dynamic contrast and improving the display effect.

[0071] As shown in FIG. 2B, for example, in the light emitting stage, the light emitting current when the light emitting element OLED writes gray scale data is on the order of nanoamperes (e.g., several nanoamperes), but the bias transistor N3 is controlled by the bias signal, i.e., the second common voltage Vcom2, to operate in the saturation region, and the generated current is on the order of microamperes (e.g., 1 microampere). Therefore, most of the current flowing through the driving transistor N2 flows into the bias transistor N3, and both can be treated in the same way, that is,

number

number

number

number

number

[0072] For example, the bias transistor N3 is controlled by the bias signal Vcom2 to operate in the saturation region, and the voltage difference between the gate and source of the bias transistor N3 is

number

[0073] For example, when the first node S is directly electrically connected to the light emitting element 120, the voltage V0 is directly applied to the first electrode 121 of the light emitting element 120, for example, the anode voltage of an OLED. When the first node S is electrically connected to the light emitting element 120 through a resistor 130, the current flowing through the light emitting element 120 is very small, so that the voltage of the first node S may be approximately equal to the voltage of the first electrode 121 of the light emitting element 120. That is, the voltage of the first electrode 121 of the light emitting element 120 and the data signal (data voltage) Vd are linearly related, thereby realizing high-precision control of the gray scale and improving the display effect.

[0074] For example, the first control signal SEL and the second control signal SEL_B are differential complementary signals, with the same amplitude and opposite phase, thus contributing to improving the anti-interference performance of the circuit, for example, the first control signal SEL and the second control signal SEL_B can be output from the same gate driving circuit unit (e.g., GOA unit), thus simplifying the circuit.

[0075] For example, as shown in Fig. 1A, the display substrate 10 may further include a data driving circuit 13 and a scan driving circuit 14. The data driving circuit 13 is configured to transmit a data signal, for example, the above-mentioned data signal Vd, as needed (for example, an image signal input to a display device). The scan driving circuit 14 is configured to output various scan signals, for example, including the above-mentioned first control signal SEL and second control signal SEL_B, and is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly fabricated on the display substrate.

[0076] For example, the display substrate can use a silicon substrate as the base substrate 101, and the pixel circuit, the data driving circuit 13 and the scan driving circuit 14 can be integrated on the silicon substrate. In this case, since the silicon-based circuit can achieve high precision, the data driving circuit 13 and the scan driving circuit 14 are not necessarily located in the non-display area, and can be formed, for example, in an area corresponding to the display area of ​​the display substrate.

[0077] For example, the display substrate 10 further includes a control circuit (not shown). For example, the control circuit is configured to control the data driving circuit 13 to apply the data signal Vd and to control the gate driving circuit 13 to apply various scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may take various forms, for example, including a processor and a memory, the memory including executable code, and the processor executing the executable code to perform the detection method.

[0078] For example, a processor may be a central processing unit (CPU) or other form of processing device having data processing and / or instruction execution capabilities, and may include, for example, a microprocessor, a programmable logic controller (PLC), and the like.

[0079] For example, the recording device may include one or more computer program products, which may include various forms of computer-readable recording media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be recorded on the computer-readable recording media, and the processor 121 may execute the functions desired by the program instructions. Various application programs and various data, such as electrical characteristic parameters obtained by the above detection method, may also be recorded on the computer-readable recording media.

[0080] Hereinafter, a display substrate according to at least one embodiment of the present disclosure will be described by taking the pixel circuit shown in FIG. 2B as an example, but the embodiments of the present disclosure are not limited thereto.

[0081] Fig. 3A is a schematic diagram of a display substrate 10 according to at least one embodiment of the present disclosure. For example, as shown in Fig. 3A, the display substrate 10 includes a base substrate 101, and a plurality of sub-pixels 100 are located on the base substrate 101. The plurality of sub-pixels 100 are arranged as a sub-pixel array, in which the row direction of the sub-pixel array is a first direction D1, the column direction of the sub-pixel array is a second direction D2, and the first direction D1 and the second direction D2 cross, for example, perpendicular to each other. Fig. 3A exemplarily illustrates two rows and six columns of sub-pixels, i.e., two pixel rows 20 and six pixel columns 30, and each of the regions of the three pixel columns spaced apart from each other is indicated by a dashed frame.

[0082] For example, the base substrate 101 may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or may be formed of a flexible material having excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cycloolefin polymer (COP), and cycloolefin copolymer (COC), etc. Although the embodiments of the present disclosure are described as an example in which the base substrate 101 is a silicon substrate, the embodiments of the present disclosure are not limited thereto.

[0083] For example, the base substrate 101 includes single crystal silicon or high purity silicon. The pixel circuit is formed on the base substrate 10 by a CMOS semiconductor process, for example, by forming an active region of a transistor (including a channel region, a first pole, and a second pole of the transistor) in the base substrate 101 by a doping process, forming each insulating layer by a silicon oxidation process or a chemical vapor deposition process (CVD), and forming a wiring structure by forming a plurality of conductive layers by a sputtering process. The active region of each transistor is located inside the base substrate 101.

[0084] Figure 3B shows a cross-sectional view taken along line II' in Figure 3A. For clarity, Figure 3B omits wiring or electrode structures that have no direct connection relationship.

[0085] For example, as shown in Fig. 3B, the display substrate 10 includes a base substrate 101, a first insulating layer 201, a polycrystalline silicon layer 102, a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205 and a fourth conductive layer 304, which are arranged in this order on the base substrate 10. The structure of the display substrate 10 will be described below layer by layer, and will be described with reference to Fig. 3B.

[0086] For clarity and convenience of explanation, Fig. 4A shows the part of the display substrate 10 located under the first conductive layer 301, i.e., the base substrate 101 and the first insulating layer 201 and the polysilicon layer 102 thereon, including the transistors (P1, N1-N3), the storage capacitor Cst and the resistor 130, Fig. 4B is an enlarged schematic diagram of one sub-pixel 100 in Fig. 4A, and for clarity, Fig. 4A also shows the corresponding cross-sectional line I-I' in Fig. 3A. Figs. 5A-5E show the process of forming the substrate structure shown in Fig. 4A.

[0087] As shown in FIG. 4B, for example, in a direction parallel to the substrate surface of the base substrate 101, the first data write transistor P1 and the driving transistor N2 are located on opposite sides of the storage capacitor Cst, and for example, are located on opposite sides of the storage capacitor Cst in the second direction D2.

[0088] As shown in conjunction with FIG. 1C, such placement contributes to increasing the distance between the first data write transistor P1 and the drive transistor N2, thereby increasing the resistance of the parasitic circuit and further reducing the risk of circuit failure in the CMOS circuit.

[0089] For example, the material of the second capacitor electrode 142 of the storage capacitor 140 is a conductor or a semiconductor. For example, as shown in FIG. 3B and FIG. 4B, the second capacitor electrode 142 of the storage capacitor 140 is the first region 401 of the base substrate 101, for example, the base substrate 101 is a P-type silicon-based base, and the material of the second capacitor electrode 142 is P-type single crystal silicon. When a voltage is applied to the first capacitor electrode 141, the first region 401, which is a semiconductor located below the first capacitor electrode 141 in the base substrate 101, forms an inversion region and becomes a conductor, and is electrically connected to the contact hole regions (contact hole regions 145a, 145b shown in FIG. 4B) on both sides of the first region 401. In such a case, no separate process such as doping is performed on the first region 401.

[0090] In another example, the first region 401 may be a conductive region, such as a highly doped region, in the base substrate 101, such that the second capacitor electrode 142 can have a stable and high electrical conductivity.

[0091] For example, the base substrate 101 further includes a second region 402 which is an N-type well region in the base substrate 101. As shown in Fig. 4B, for example, the first data write transistor P1 and the resistor 130 are arranged in parallel in the second region 402 in the second direction D2. The resistor 130 made of polysilicon material is arranged in the N-type base, which contributes to reducing parasitic phenomena and improving the characteristics of the circuit.

[0092] For example, in a direction parallel to the substrate surface of the base substrate 101, the resistor (R) 130 and the first data write transistor P1 are located on the same side of the second capacitor electrode 142. For example, in a direction parallel to the substrate surface of the base substrate 101, the drive transistor N2 and the bias transistor N3 are located on the same side of the second capacitor electrode 142.

[0093] 4B, the first data write transistor P1 and the second data write transistor P1 are arranged in parallel in the first direction D1 and are symmetrical with respect to a symmetry axis along the second direction D2. For example, the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor N1 are arranged in parallel in the first direction D1 and are symmetrical with respect to a symmetry axis along the second direction D2.

[0094] For example, resistor 130 has a U-shaped structure, e.g., an asymmetric U-shaped structure, e.g., the lengths of the two branches of the U-shaped structure are not equal. For example, as shown in FIG. 4B, the second terminal 132 of resistor 130 is closer to drive transistor N2.

[0095] The resistor 130 is configured as a U-shaped structure, which can help save the layout area occupied by the resistor, thereby improving the space utilization rate of the layout and the resolution of the display substrate. For example, in the same space, the resistor with the U-shaped structure can increase the length of the resistor, thereby achieving a desired resistance value.

[0096] In addition, the resistor 130 is designed as an asymmetric structure to make reasonable use of the layout space, for example, as shown in FIG. 4B, a contact hole region 411a is provided above the shorter branch of the U-shaped resistor, and the contact hole region 411a is parallel to the second terminal 132 of the resistor 130 in the first direction D1. For example, the contact hole region 411a is an N-type high concentration doping region (N+). For example, the contact hole region 411 is for biasing the well region 401 in which the first data write transistor P1 is located, thereby avoiding threshold voltage changes caused by parasitic phenomena such as base bias phenomenon, and improving circuit stability. For example, as shown in FIG. 3B, a low voltage bias is applied to the P-type base 101 and a high voltage bias is applied to the N-type well region 402, thereby reverse biasing the parasitic PN junction between them, electrically isolating the devices, and reducing the parasitic phenomena between the devices, thereby improving circuit stability.

[0097] For example, the opening of the U-shaped structure faces the first capacitor electrode 141, and the first terminal 131 and the second terminal 132 of the resistor 130 are respectively located at two ends of the U-shaped structure. As shown in the figure, the first terminal 131 of the resistor 130 is provided with a contact hole region 133 for electrically connecting to the gate 150 of the driving transistor N2, and the second terminal 132 of the resistor 130 is provided with a contact hole region 134 for electrically connecting to the first electrode 121 of the light-emitting element 120.

[0098] For example, the material of the resistor 130 includes a polycrystalline silicon material, the contact hole regions 133, 134 are doped regions for reducing contact resistance, and the body region of the resistor 130 other than the contact hole regions is, for example, an intrinsic region or a lightly doped region, thereby obtaining a desired resistance value.

[0099] For example, the first capacitor electrode 141 of the storage capacitor 140 and the resistor 130 are insulated from one another in the same layer and both include polysilicon material, and the doping concentration of the first capacitor electrode 141 of the storage capacitor 140 is higher than the doping concentration of the body region of the resistor 130. For example, the body region of the resistor 130 is an intrinsic polysilicon material.

[0100] For example, the gates 160, 170, 150, 180 of each of the transistors P1, N1-N3 and the first capacitor electrode 141 of the storage capacitor 140 are disposed in the same layer and all include polysilicon material. For example, as shown in FIG 4B, the gate 150 and the first capacitor electrode 141 of the driving transistor N2 are interconnected to form an integral structure.

[0101] FIG. 4B further shows the active areas P1a, N1a, N2a and N3a of each transistor P1, N1-N3, respectively, and also shows the first pole 161 and the second pole 162 of the first data write transistor P1, the first pole 171 and the second pole 172 of the second data write transistor N1, the first pole 151 and the second pole 152 of the drive transistor N2, and the first pole 181 and the second pole 182 of the bias transistor N3.

[0102] 4B further shows a gate contact region 165, a first contact region 163, and a second pole contact region 164 of the first data write transistor P1, a gate contact region 175, a first contact region 173, and a second pole contact region 174 of the second data write transistor N1, a gate contact region 155, a first contact region 153, and a second pole contact region 154 of the drive transistor N2, and a gate contact region 185, a first contact region 183, and a second pole contact region 184 of the bias transistor N3. For example, each first pole contact region is an area for making an electrical contact to a corresponding first pole, each second pole contact region is an area for making an electrical contact to a corresponding second pole, and each gate contact region is an area for making an electrical contact to a corresponding gate.

[0103] For example, the active region P1a of the first data write transistor P1 and the active region N1a of the second data write transistor N1 are arranged in parallel in the first direction D1 and are symmetrical with respect to a symmetry axis along the second direction D2.

[0104] As shown in FIG. 4B, the area of ​​the active area N2a of the driving transistor N2 is larger than the areas of the active areas of the other transistors, so that a large aspect ratio can be obtained, which contributes to improving the driving capability of the driving transistor N2, and thereby improving the display effect.

[0105] As shown in FIG. 4B, transistors with large active areas, such as the driving transistor N2 and the bias transistor N3, have enough space to provide at least two contact hole areas on their first and second poles, respectively, so that they can make sufficient contact with the structure to be connected and form a parallel connection structure, thereby reducing the contact resistance.

[0106] 4B further illustrates the contact hole area 144 in the first capacitor electrode 141 and the contact hole areas 145a, 145b configured to be electrically connected to the second capacitor electrode 142. As shown in FIG 4B, the first capacitor electrode 141 and the second capacitor electrode 142 each have at least two contact hole areas correspondingly disposed therebetween to reduce contact resistance.

[0107] 4A , the distribution of transistors (e.g., including the shape, size, etc. of each transistor), storage capacitors, and resistors in two subpixels 100 adjacent to each other in the first direction D1 is symmetrical about an axis of symmetry along the second direction D2, i.e., corresponding structures in the two subpixels are symmetrical about an axis of symmetry along the second direction D2. The distribution of transistors in two subpixels 100 adjacent to each other in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1.

[0108] Such symmetrical arrangement can minimize the uniformity of process errors, thereby improving the uniformity of the display substrate, and also allows several structures that are disposed on the same layer of the substrate and can be connected to each other to be integrally formed, which can make the pixel arrangement more compact than if they were disposed separately, thereby improving the space utilization rate and thereby improving the resolution of the display substrate.

[0109] 4A , the second regions 402 of two sub-pixels 100 adjacent to each other in the first direction D1 are integral with each other, and the second regions 402 of two sub-pixels 100 adjacent to each other in the second direction D2 are integral with each other, that is, the first data write transistors N1 and the resistors 130 in the four adjacent sub-pixels 100 are located in the same well region. Compared with separately providing independent well regions, such an arrangement can make the pixel arrangement more compact in meeting the design rules, which contributes to improving the resolution of the display substrate.

[0110] For example, as shown in FIG. 4A, the active areas P1a of the first data writing transistors P1 of two subpixels adjacent in the second direction D2 are connected to each other to form an integral structure, i.e., the active areas P1a of the two first data writing transistors P1 are located in the same doping region A1 (P well) of the same second region 402, and the first poles of the two first data transistors P1 are connected to each other to form an integral structure so as to receive the same data signal Vd.

[0111] For example, as shown in FIG. 4A , the active regions N1a of the second data write transistors N1 of two subpixels adjacent to each other in the second direction D2 are connected to each other to form an integral structure, i.e., the active regions N1a of the two second data write transistors N1 are located in the same doping region A2 (N-well) of the base substrate 101, and the first electrodes of the two second data write transistors N1 are connected to each other to form an integral structure so as to receive the same data signal Vd.

[0112] For example, as shown in FIG. 4A, the gates of the first data write transistor P1 or the gates of the second data write transistor N2 of two sub-pixels 100 adjacent to each other in the first direction D1 are connected to each other to form an integral structure.

[0113] In each row of pixels, the gates of the first data write transistors P1 are configured to receive the same first control signal SEL, and the gates of the second data write transistors N1 are configured to receive the same second control signal SEL_B. In addition, the transistors of two subpixels adjacent in the first direction D1 are mirror symmetrical, and the first write transistors P1 and the second write transistors N1 of the two subpixels are alternately adjacent in the first direction D1. Therefore, the gates of the two adjacent first data write transistors P1 can be directly connected to form an integral structure to form the first control electrode group 191, and the gates of the adjacent second data write transistors N1 can be directly connected to form an integral structure to form the second control electrode group 192. This arrangement can make the pixel arrangement more compact while satisfying the design rules, and contribute to improving the resolution of the display substrate.

[0114] As shown in FIG. 4A, in two subpixels 100 adjacent in the first direction D1, when the driving transistors N2 are adjacent, the active regions N2a of the two driving transistors N2 are connected to each other to form an integral structure, that is, the active regions N2a of the two driving transistors N2 are located in the same doping region B (N well) of the base substrate 101, and the first electrodes of the two driving transistors N2 are connected to each other to form an integral structure so as to receive the same first power supply voltage VDD, thereby forming the third control electrode group 193. When the bias transistors N3 are adjacent, the gates of the two bias transistors N3 are connected to each other to form an integral structure so as to receive the same second common voltage Vcom2, and the active regions N3a of the two bias transistors N3 are connected to each other to form an integral structure, i.e., the active regions N3a of the two bias transistors N3 are located in the same doping region C (N well) of the base substrate 101, and the first poles of the two bias transistors N3 are connected to each other to form an integral structure so as to receive the same second power supply voltage VSS.

[0115] Such an arrangement allows the pixels to be arranged more compactly while still satisfying design rules, which contributes to improving the resolution of the display substrate.

[0116] 5A-5D show a process of forming the substrate structure shown in FIG. 4A, and for clarity, the figures only show two rows and two columns of sub-pixels, i.e., four adjacent sub-pixels 100, which constitute one pixel unit group. FIG. 4A shows the pixel unit group 420 in a dashed frame. For example, the display substrate includes a plurality of pixel unit groups arranged along a first direction D1 and a second direction D2.

[0117] Hereinafter, a process for forming a display substrate according to an embodiment of the present disclosure will be described with reference to FIGS. 5A-5D as an example, but is not intended to limit the present disclosure.

[0118] For example, a silicon-based base substrate is provided, for example the material is P-type single crystal silicon, and an N-type transistor (for example a driving transistor) can be directly fabricated on the P-type silicon base, i.e. the P-type base is the channel region of the N-type transistor, which is advantageous to realize the high speed advantage of NMOS devices and improve the performance of the circuit.

[0119] As shown in FIG. 5A, for example, a P-type silicon base substrate is N-type doped to form an N-type well region, ie, a second region 402, which serves as the base of the first data write transistor P1 and the resistor 130.

[0120] For example, the second regions 402 of two sub-pixels adjacent in the first direction D1 may be connected to each other, and the second regions 402 of two sub-pixels adjacent in the second direction D2 may be connected to each other. For example, when the N-type doping is performed, the undoped regions of the base substrate 101 are blocked.

[0121] As shown in FIG. 4B and FIG. 5B, for example, a first insulating layer 201 is formed on the base substrate 101, and then a polycrystalline silicon layer 102 is formed on the first insulating layer 201.

[0122] The first insulating layer 201 includes the gate insulating layers of each transistor, and further includes the dielectric layer 104 of the storage capacitor Cst. The polysilicon layer 102 includes the first capacitor electrode 141, the resistor 130, and the gates 150, 160, 170, 180 of each transistor (P1, N1-N3).

[0123] The gate of the first data write transistor P1 is located in the second region 402, and the N-type well region is the channel region of the P-type transistor. The resistor 130 is also formed in the second region 402, i.e., the orthogonal projection of the resistor 130 on the base substrate is located in the second region. The resistor 130 made of polysilicon material is formed on the N-type base, which helps to reduce parasitic phenomena and improve the characteristics of the circuit. Each N-type transistor is directly formed on the P-type base outside the N-type well region.

[0124] 5B , the orthogonal projections of the first capacitor electrodes 141 of the four sub-pixels in each pixel unit group on the base substrate are located outside the second region 402 and surround the second region 402. For example, the second region 402 is rectangular, and the orthogonal projections of the first capacitor electrodes 141 of each sub-pixel on the base substrate surround one corner of the rectangle, for example, each first capacitor electrode 141 includes a recessed structure with an L-shaped outline, and one corner of the rectangle extends into the orthogonal projection of the recessed structure to match the outline of the L-shape.

[0125] As shown in Fig. 5B, the patterns of the polysilicon layers in two subpixels adjacent in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D2, and the patterns of the polysilicon layers in two subpixels adjacent in the second direction D2 are symmetrical with respect to an axis of symmetry along the first direction D1, i.e., the patterns of the polysilicon layers are symmetrical patterns. For example, as shown in Fig. 5B, the resistors of the subpixels adjacent in the first direction are symmetrical with respect to an axis of symmetry along the second direction, and the resistors of the subpixels adjacent in the second direction are symmetrical with respect to an axis of symmetry along the first direction. For example, the first capacitor electrodes of the subpixels adjacent in the first direction are symmetrical with respect to an axis of symmetry along the second direction, and the first capacitor electrodes of the subpixels adjacent in the second direction are symmetrical with respect to an axis of symmetry along the first direction.

[0126] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two subpixels adjacent to each other in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D1, For example, the gates of the first data write transistor P1 or the second data write transistor N1 of two subpixels adjacent to each other in the first direction D1 are integrally formed.

[0127] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two sub-pixels adjacent to each other in the second direction D2 are symmetrical with respect to a symmetry axis along the first direction.

[0128] For example, the first insulating layer is formed on the base substrate by thermal oxidation, and the material of the first insulating layer is, for example, silicon nitride, silicon oxide or silicon oxynitride.

[0129] For example, a polysilicon material layer is formed on the first insulating layer by a chemical vapor deposition process (PVD), and then a lithography process is performed on the polysilicon material layer to form the polysilicon layer 102 .

[0130] FIG. 5C shows a doping window region 103 (left) of the base substrate, and the doping window region (right) in the substrate structure shown in FIG. 5B. For example, the doping is high concentration doping, so as to form contact hole regions for electrical connection to the base substrate. For example, the doping window region includes the source region and drain region of each transistor. For example, the doping window region further includes each contact hole region in the base and the contact hole region in the resistor 130, such as the contact hole regions 400a, 400b, 411a, 411b, 145a, 145b, 133, 134 shown in FIG. 4B. For example, the gate of the transistor is made of polysilicon material, so it is also necessary to dope the polysilicon gate. When doping, it is necessary to form a barrier layer to block the non-doped region, so as to expose only the corresponding doping window region and the amorphous silicon region.

[0131] 5C only shows each doping window region, and in the actual doping process, a corresponding barrier layer / mask layer is provided to expose the corresponding doping window region and polysilicon region for doping. For example, the material of the barrier layer / mask layer can be photoresist or oxide material.

[0132] 5D, a barrier layer 135 is formed corresponding to the resistor 130. In order to protect the resistance value of the resistor 130, the resistor 130 needs to be shielded during the doping process to avoid the resistor 130 being damaged by the doping. The barrier layer 135 shields the body of the resistor 130 and only exposes the contact hole regions 133, 134 at both ends of the resistor 130.

[0133] For example, the barrier layer 135 may be a silicon nitride, oxide, or oxynitride, or may be a photoresist material. After the doping process is completed, the barrier layer 135 may remain on the display substrate or may be removed.

[0134] In some other examples, the barrier layer 135 of the resistor 130 may be formed together with the barrier layer / mask layer of other regions when doping, and the embodiments of the present disclosure are not limited thereto.

[0135] For example, in the doping process, it is necessary to perform N-type doping and P-type doping, respectively, such as forming the source region and drain region of an N-type transistor and the source region and drain region of a P-type transistor. When performing the N-type doping process, it is necessary to form a barrier layer that blocks the region that is not N-type doped, and when performing the P-type doping process, it is necessary to form a barrier layer that blocks the region that is not P-type doped.

[0136] Figure 5E shows the N-type doped region SN and the P-type doped region SP in different shading patterns (left) and in the substrate shown in Figure 5D (right), which are also shown in Figure 4B and may be referenced thereto.

[0137] For example, performing an N-type doping process includes forming a barrier layer covering the P-type doping region SP and the region of the N-type doping region SN other than the doping window region and the polysilicon region, leaving only the doping window region and the polysilicon region of the N-type doping region SN, i.e., the overlap region of the SN region and the doping window region 103 and the polysilicon region shown in Fig. 5C, and performing an N-type doping process. In contrast to Fig. 4B, the gates and the first and second poles of the transistors N1-N3, as well as the contact hole regions 411a, 411b, 145a, 145b can be formed by the N-type doping process. The N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, a boron element.

[0138] For example, performing a P-type doping process includes forming a barrier layer covering the N-type doping region SN and the region of the P-type doping region SP other than the doping window region and the polysilicon region, leaving only the doping window region and the polysilicon region of the P-type doping region SP, i.e., the overlap region of the SP region and the doping window region 103 and the polysilicon region shown in Fig. 5C, and then performing a P-type doping process. In contrast to Fig. 4B, the gate, the first pole and the second pole, and the contact holes 400a, 400b, 133, 134 of the transistor P1 can be formed by the P-type doping process. The P-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, a phosphorus element.

[0139] In the doping process, for example, an ion implantation process is used, and the polysilicon pattern is used as a mask, so that the ions are implanted into the silicon-based base on both sides of the polysilicon, thereby forming the first pole and the second pole of each transistor, and realizing self-alignment. In addition, the resistivity of the polysilicon, which has originally high resistance, is reduced by the doping process, so that the gate of each transistor and the first capacitor electrode can be formed. Therefore, using the polysilicon material as the material of the resistor and the gate has multiple beneficial effects and saves process costs.

[0140] In this way, the structure of the display substrate including the transistors P1, N1-N3, the resistor 130, and the storage capacitor Cst shown in FIG. 4A is formed.

[0141] For example, corresponding transistors, resistors and storage capacitors Cst in two adjacent subpixels in the first direction D1 are each symmetrical with respect to an axis of symmetry along the second direction D2, and corresponding transistors, resistors and storage capacitors Cst in two adjacent subpixels in the second direction D2 are each symmetrical with respect to an axis of symmetry along the first direction D1.

[0142] In this embodiment, the storage capacitor Cst is a capacitor formed by the field effect, and after a voltage is applied to the first capacitor electrode 141, an inversion charge is generated in the region located below the first capacitor electrode 141 in the base substrate 101, making the lower plate of the storage capacitor Cst, i.e., the second capacitor electrode 142, a conductor.

[0143] In some other embodiments, a conductive process (e.g., a doping process) may be performed in advance on a region of the base substrate 101 located below the first capacitor electrode 141 in order to form the second capacitor electrode 142. The embodiments of the present disclosure are not limited thereto.

[0144] The display substrate shown in FIG. 3A is formed by sequentially forming the second insulating layer 202, the first conductive layer 301, the third insulating layer 203, the second conductive layer 302, the fourth insulating layer 204, the third conductive layer 303, the fifth insulating layer 205 and the fourth conductive layer 304 on the substrate shown in FIG. 4A.

[0145] 6A and 6B respectively show a pattern of the first conductive layer 301 and the first conductive layer 301 disposed on the substrate structure shown in FIG 4A, FIG 6C shows a cross-sectional view taken along the section line IV-IV' in FIG 6B, and FIG 6B also shows vias in the second insulating layer 202, which correspond one-to-one with each contact area in FIG 4B and are used to electrically connect each contact hole area to the pattern in the first conductive layer 301. For clarity, the figures only show 2 rows and 6 columns of sub-pixels, and the area of ​​one sub-pixel 100 is indicated by a dashed frame, and FIG 6B also shows the corresponding position of the section line I-I' in FIG 3A.

[0146] 6A, the patterns of the first conductive layers in two subpixels adjacent in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D2, and the patterns of the first conductive layers in two subpixels adjacent in the second direction D2 are symmetrical with respect to the axis of symmetry along the first direction D1. Hereinafter, the pattern of the first conductive layer will be illustratively described using one subpixel as an example.

[0147] As shown in FIG. 6A, the first conductive layer 301 includes a connection electrode 313 (an example of a second connection electrode in this disclosure) for electrically connecting the first terminal 131 of the resistor 130 to the second electrode 152 of the driving subcircuit 112.

[0148] For example, as referred to in conjunction with FIG. 6B, a first terminal of the connection electrode 313 is electrically connected to the first terminal 131 of the resistor 130 by a via 225 in the second insulating layer 202, and a second terminal of the connection electrode 313 includes a first branch portion 331 and a second branch portion 332, and as referred to in conjunction with FIG. 3B, the first branch portion 331 is electrically connected to the first pole 151 of the driving transistor N2 by a via 226a in the second insulating layer 202, and the second branch portion 332 is electrically connected to the first pole 181 of the bias transistor N3 by a via 226b in the second insulating layer 202.

[0149] For example, as shown in FIG. 6B, in the second direction D2, the via 225 and the via 226a are respectively located on opposite sides of the first capacitor electrode 141, i.e., the orthogonal projection of the connection electrode 313 on the base substrate 101 passes through the orthogonal projection of the first capacitor electrode 141 on the base substrate 101 in the second direction D2.

[0150] For example, in order to reduce the contact resistance, at least two of the vias 226a and the vias 226b may be provided.

[0151] For example, as referred to in conjunction with Figures 6A and 6B, the first conductive layer 301 further includes a connection electrode 314, which is electrically connected to the second terminal 132 of the resistor 130 by a via 229 in the second insulating layer 202, and the connection electrode 314 is used to electrically connect to the first electrode 121 of the light-emitting element 120.

[0152] For example, the connecting electrode 314 is L-shaped, one branch of which is electrically connected to the second terminal 132 of the resistor 130 , and the other branch of which is electrically connected to the first electrode 121 of the light emitting element 120 .

[0153] 6B and 6C, the first conductive layer 301 further includes a third capacitor electrode 315 (one example of a second capacitor electrode in the present disclosure) overlapping the first capacitor electrode 141 in a direction perpendicular to the base substrate. The third capacitor electrode 315 is located on a side of the first capacitor electrode 141 away from the second capacitor electrode 142 and is configured to be electrically connected to the second capacitor electrode 142. That is, in a direction perpendicular to the base substrate, the second capacitor electrode 142 and the third capacitor electrode 315 are located on both sides of the first capacitor electrode 141, respectively, and are electrically connected to each other, thereby forming a structure of parallel-connected capacitors and increasing the capacitance value of the storage capacitor Cst.

[0154] 6B and 6C, the third capacitor electrode 315 includes a first portion 315a and a second portion 315b, and the first portion 315a and the second portion 315b are spaced apart from each other in a first direction D1. For example, the third capacitor electrode 315 of the first portion 315a is electrically connected to the contact hole region 145b by a via 228 in the second insulating layer 202 to be electrically connected to the second capacitor electrode 142, and the second portion 315b is electrically connected to the contact hole region 145a by a via 227 in the second insulating layer 202 to be electrically connected to the second capacitor electrode 142.

[0155] For example, the first portion 315a and the second portion 315b of the third capacitor electrode 315 are located on both sides of the connection electrode 313 in the first direction D1, and are spaced apart from the connection electrode 313, respectively.

[0156] For example, the third capacitor electrodes 315 of two subpixels adjacent in the first direction D1 are symmetrical with respect to an axis of symmetry along the second direction D2, and the third capacitor electrodes 315 of two subpixels adjacent in the second direction D2 are symmetrical with respect to an axis of symmetry along the first direction D1.

[0157] For example, as shown in FIG. 6B, the first portion 315a or the second portion 315b of the third capacitor electrode 135 of two subpixels adjacent to each other in the first direction D1 are integrally formed.

[0158] For example, as shown in FIG. 6B, for each pixel unit group 420, the first portions 315a of the third capacitor electrodes 315 of two sub-pixels adjacent to each other in the first direction D1 are connected to each other to form an integral structure.

[0159] For example, as shown in FIG. 6B , the second portion 315b of the third capacitor electrode 315 of the subpixel in each pixel unit group 420 is interconnected to the second portion 315b of the third capacitor electrode 315 of the subpixel adjacent to the subpixel in the pixel unit group adjacent to the pixel unit group 420 to form an integral structure.

[0160] For example, as shown in FIG. 6A, adjacent third capacitor electrodes 315 in two subpixels adjacent in the first direction D1 may be integrally formed so as to receive the same second power supply voltage VSS, and adjacent third capacitor electrodes 315 in two subpixels adjacent in the first direction D1 may be integrally formed so as to receive the same second power supply voltage VSS.

[0161] For example, in order to reduce the contact resistance, at least two of the vias 227 and at least two of the vias 228 may be provided. For example, the at least two vias 227 are arranged along the second direction D2, and the at least two vias 228 are arranged along the second direction D2.

[0162] For example, the first conductive layer 301 further includes a connecting electrode 317 (an example of a first connecting electrode in the present disclosure), which is used to electrically connect the second terminal of the data writing sub-circuit to the first terminal of the recording sub-circuit, i.e., to electrically connect the second pole 161 of the first data writing transistor P1, the second pole 171 of the second data writing transistor N1, and the first capacitor electrode 141.

[0163] 6A and 6B, the connection electrode 317 includes three ends, for example a T-shaped structure. As shown in FIG. 3B, a first terminal of the connection electrode 317 is electrically connected to the second pole of the first data write transistor P1 by a via 261a in the second insulating layer 202, a second terminal of the connection electrode 317 is electrically connected to the second pole of the second data write transistor N1 by a via 261b in the second insulating layer 202, and a third terminal of the connection electrode 317 is electrically connected to the first capacitor electrode 141 by a via 261c in the second insulating layer 202.

[0164] 6B, in the second direction D2, the connecting electrode 314 at least partially overlaps with the third terminal of the connecting electrode 317. This arrangement makes the pixel arrangement more compact, thereby improving the space utilization rate of the display substrate and enhancing the resolution of the display substrate.

[0165] 6A and 6B, the first conductive layer 301 further includes a first scan line connecting part 311 and a second scan line connecting part 312, the first scan line connecting part 311 is used for electrically connecting the gate of the first data write transistor P1 to a first scan line to receive a first control signal SEL, and the second scan line connecting part 312 is used for electrically connecting the gate of the second data write transistor N1 to a second scan line to receive a first control signal SEL_B.

[0166] For example, the first scanning line connection portion 311 is electrically connected to the gate of the first data write transistor P1 by a via 221 in the second insulating layer 202, and the second scanning line connection portion 312 is electrically connected to the gate of the second data write transistor N1 by a via 222 in the second insulating layer 202.

[0167] For example, as shown in FIG. 6A, sub-pixels adjacent in the first direction D1 share the first scan line connecting portion 311 or the second scan line connecting portion 312.

[0168] For a detailed description of the first and second scan line connecting portions, please refer to the description of FIGS. 10A-10B below.

[0169] As shown in FIG. 6A, the first conductive layer 301 further includes a data line connection portion 245, which is used to electrically connect to a data line, so that a first electrode of the first data write transistor P1 and a first electrode of the second data write transistor N1 receive a data signal Vd transmitted through the data line.

[0170] As shown in FIG. 6B, the data line connection portion 245 is electrically connected to the first pole 161 of the first data write transistor P1 by a via 223 in the second insulating layer 202, and is electrically connected to the first pole 171 of the second data write transistor N1 by a via 224 in the second insulating layer 202.

[0171] 6A, the data line connection parts 245 are spaced apart in the first direction D1, for example, at the boundaries of two subpixel rows, and for example, two subpixels adjacent in the second direction D2 share one data line connection part 245.

[0172] For a detailed description of the data line connection portion, please refer to the description of the second data line connection portion in the following FIGS. 8A-8D.

[0173] 6A and 6B, the first conductive layer 301 further includes a connection electrode 318, which is electrically connected to the first electrode of the driving transistor N2 by a via 230 in the second insulating layer 202.

[0174] As shown in Figures 4A and 6B, the first conductive layer 301 further includes connection electrodes 319a, 319b, and 319c, which are all set to bias the base of the transistor, for example, used to connect the N-type base to a first power supply voltage terminal to receive a first power supply voltage VDD (high voltage), or used to connect the P-type base to a second power supply voltage terminal to receive a second power supply voltage VSS (low voltage), thereby avoiding parasitic phenomena such as base bias phenomenon and improving circuit stability.

[0175] 4B, the connection electrodes 319a, 319b are electrically connected to the contact hole regions 411a, 411b in the second region (N-well region) 402 of the base substrate 101 by the vias 262a, 262b in the second insulating layer 202, respectively, and the connection electrodes 319a and 319b are used to connect to the first voltage terminal VDD so as to bias the N-type base of the first data write transistor P1. The connection electrode 319c is electrically connected to the contact hole region 400a in the base substrate 101 by the via 262c in the second insulating layer 202, and the connection electrode 319c is used to connect to the second voltage terminal VSS so as to bias the P-type base where the second data write transistor N1 is located.

[0176] 6A-6B, the first conductive layer 301 further includes a bias voltage line 250 extending along a first direction D1 to provide a second common voltage Vcom2 and electrically connected to the gate of the bias transistor N3 by a via 263 in the second insulating layer 202.

[0177] 4B and 6A-6B, the first conductive layer 301 further includes a power line 260, which extends along a first direction D1 and is used for transmitting a second power supply voltage VSS. The power line 260 is electrically connected to a first pole of the bias transistor N3 by a via 264a in the second insulating layer 202 to provide the second power supply voltage VSS, and is electrically connected to a contact hole region 400b in the base substrate 101 by a via 264b in the second insulating layer 202 to bias a P-type base on which the second data write transistor N1 is located.

[0178] 7A shows a schematic diagram of the second conductive layer 302, and FIG. 7B shows the second conductive layer 302 based on the first conductive layer 301, and FIG. 7B also shows a via in the third insulating layer 203, which is used to connect the pattern in the first conductive layer 301 with the pattern in the second conductive layer 302. For clarity, the figure only shows 4 rows and 6 columns of sub-pixels, and dashed lines indicate the boundaries between two sub-pixel rows, and FIG. 7B also correspondingly indicates the location of the cross-sectional line I-I' in FIG. 3A.

[0179] 7A, the patterns of the second conductive layer in two subpixels adjacent in the first direction D1 are symmetrical with respect to a symmetry axis along the second direction D2, and the patterns of the second conductive layer in two subpixels adjacent in the second direction D2 are symmetrical with respect to the symmetry axis along the first direction D1. Hereinafter, the pattern of the second conductive layer will be illustratively described using one subpixel as an example.

[0180] 7A, the second conductive layer 302 includes power lines 270a, 270b, 280a, 280b extending along a first direction D1, the power lines 270a, 270b are used to transmit a second power voltage VSS, and the power lines 280a, 280b are used to transmit a first power voltage VDD, and the power lines 270a, 280a, 270b, 280b are arranged alternately in a second direction D2.

[0181] 3B, 7A, and 7B, the power line 270a is electrically connected to the power line 260 in the first conductive layer 301 by a plurality of vias 235 arranged in the third insulating layer 203 along the first direction D1, thereby forming a parallel connection structure and effectively reducing the resistance of the wiring. For example, the power line 270b is electrically connected to the third capacitor electrode 315 by vias 236 arranged in the third insulating layer 203 along the second direction D2 to provide the second power supply voltage VSS. For example, the power line 270b is further electrically connected to the third capacitor electrode 315 (315b) by vias 267 arranged in the third insulating layer 203 along the second direction D2 to provide the second power supply voltage VSS.

[0182] For example, the width of the power line 270b is greater than that of the power line 270a in the second direction D2 because the first and second portions of the third capacitor electrode 315 electrically connected to the power line 270b both have large areas. The power line 270b is arranged to have a large width, which contributes to forming a plurality of connection holes 236, 267 between the power line 270b and the third capacitor electrode 315, thereby effectively reducing the contact resistance.

[0183] 7A and 7B, the power supply line 280a is electrically connected to a connection electrode 318 in the first conductive layer 301 by a via 237 in the third insulating layer 203 to provide a first power supply voltage VDD, and is connected to a first electrode of the driving transistor N2. The power supply line 280b is electrically connected to a connection electrode 319a in the first conductive layer 301 by a via 238 in the third insulating layer 203 to bias a second region (N-well region) 402 in the base substrate 101 to a high voltage, and for example, a plurality of vias 238 are arranged along the second direction D2.

[0184] For example, the width of the power line 280b is larger than that of the power line 280a in the second direction D2 because the connection electrode 319a electrically connected to the power line 280b has a relatively large size in the second direction D2. The power line 280b is arranged to have a relatively large width, which contributes to forming a plurality of connection holes 238 between the power line 280b and the connection electrode 319a, thereby increasing the contact area with the connection electrode 319a and effectively reducing the contact resistance.

[0185] For example, the second conductive layer 302 further includes a plurality of first scan lines 210 and a plurality of second scan lines 220 extending along a first direction D1. For example, the scan line 11 shown in FIG.

[0186] As shown in conjunction with Figures 6A and 6B, the first scanning line 210 is electrically connected to the first scanning line connection portion 311 by a via 231 in the third insulating layer 203, and the second scanning line 220 is electrically connected to the second scanning line connection portion 312 by a via 232 in the third insulating layer 203.

[0187] For a detailed description of the first and second scan lines, please refer to the description of FIGS. 10A-10B below.

[0188] For example, as shown in Figures 3B, 7A and 7B, the second conductive layer 302 further includes a connection electrode 323, which is electrically connected to the connection electrode 314 of the first conductive layer 301 by a via 239 in the third insulating layer 203, and is connected to the second terminal 132 of the resistor 130. The connection electrode 323 is used to electrically connect to the first electrode 121 of the light emitting element 120. For example, the number of the vias 239 is at least two.

[0189] For example, as referred to in conjunction with Figures 7A and 7B, the second conductive layer 302 further includes a connection electrode 324, which is electrically connected to a connection electrode 319b in the first conductive layer 301 by a via 265 in the third insulating layer 203 so as to be electrically connected to a contact hole region 411b of the second region (N-well region) 402 in the base substrate 101.

[0190] For example, as referred to in conjunction with Figures 7A and 7B, the second conductive layer 302 further includes a connection electrode 325, which is electrically connected to a connection electrode 319c in the first conductive layer 301 by a via 266 in the third insulating layer 203 so as to be electrically connected to a contact hole region 400a in the base substrate 101.

[0191] For example, the connecting electrode 325 has a cross structure, for example, the connecting electrodes 324 and the connecting electrodes 325 are alternately distributed in the first direction D1 and located at the boundaries of two sub-pixel rows.

[0192] For example, as shown in Figure 7A, the second conductive layer 302 further includes a data line connection portion 244. As shown in Figure 7B, the data line connection portion 244 is electrically connected to a data line connection portion 245 in the first conductive layer 301 by a via 233.

[0193] For example, as shown in FIG. 7A, the data line connecting portions 244 are spaced apart in the first direction D1, and one connecting electrode 324 or one connecting electrode 325 is provided between every two adjacent data line connecting portions 244.

[0194] For example, the data line connection portion 244 is located at the boundary between two sub-pixel rows, for example, two sub-pixels adjacent to each other in the second direction D2 share one data line connection portion 244.

[0195] For example, as shown in FIG. 7A and FIG. 7B, in the second direction D2, the data line connection portions 244 in the sub-pixels of each column are alternately located on both sides of the data line connection portion 245 and are electrically connected to the first terminal and the second terminal of the data line connection portion 245 by vias 233, 234, respectively, thereby connecting the data line connection portion 245 to different data lines.

[0196] For a detailed description of the data line connection portion, reference can be made to the description of the first data line connection portion in the following FIGS. 11A-11D.

[0197] Fig. 8A shows a schematic diagram of the third conductive layer 303, Fig. 8B shows the third conductive layer 303 based on the second conductive layer 302, and Fig. 8B also shows a via in the fourth insulating layer 204, which is used to connect the pattern in the second conductive layer 302 and the pattern in the third conductive layer 303. For clarity, the figure only shows the conductive patterns corresponding to the sub-pixels of 4 rows and 6 columns, and Fig. 8A shows the boundaries of the sub-pixels of two rows with dashed lines, and Fig. 8B also shows the corresponding position of the cross-sectional line I-I' in Fig. 3A.

[0198] For example, the third conductive layer 303 includes a plurality of data lines extending along the second direction D2, which are used to connect to first terminals of data writing sub-circuits in the sub-pixels to provide data signals Vd. For example, as shown in Fig. 8A, the plurality of data lines includes a plurality of first data lines 241 and a plurality of second data lines 242 arranged alternately one by one in the first direction D1. For example, the data line 12 shown in Fig. 1A may be the first data line 241 or the second data line 242.

[0199] For example, the data lines are divided into a plurality of data line groups, each of which includes one first data line 241 and one second data line 242. For example, each subpixel column is connected to a corresponding data line group, i.e., connected to one first data line 241 and one second data line 242, i.e., one column of subpixels is driven by two data lines. In this way, it is conducive to reducing the load on each data line, thereby improving the driving ability of the data line, reducing the signal delay, and improving the display effect.

[0200] 8B, the first data line 241 is electrically connected to a data line connection portion 244 located between the subpixels of the first row and the subpixels of the second row in the second conductive layer 302 shown in FIG. 7B by a via 403 in the fourth insulating layer 204, thereby providing data signals to the subpixels of the first and second rows, and the second data line 242 is electrically connected to a data line connection portion 244 located between the subpixels of the third row and the subpixels of the fourth row in the second conductive layer 302 shown in FIG. 7B by a via 404 in the fourth insulating layer 204, thereby providing data signals to the subpixels of the third and fourth rows.

[0201] For a detailed description of the first and second data lines, please refer to the description of Figures 11A-11D below. For ease of comparison, Figure 8B shows positions corresponding to the cross-sectional lines II-II' and III-III' in Figure 11B.

[0202] For example, the third conductive layer 303 includes power lines 330 and 340 extending along the second direction D2. The power line 330 is used to transmit a first power voltage VDD, and the power line 340 is used to transmit a second power voltage VSS. As shown in FIG 8A, the power lines 330 and the power lines 340 are alternately arranged in the first direction D1.

[0203] As shown in FIG. 8B, the power line 330 is electrically connected to the power lines 280a and 280b in the second conductive layer 302 by vias 405 and 406 in the fourth insulating layer 204, respectively, to form a mesh-like power line structure for transmitting the first power supply voltage. Such a structure contributes to reducing the resistance in the power line, thereby reducing the voltage drop in the power line, and contributing to uniformly transmitting the first power supply voltage VDD to each sub-pixel of the display substrate. The power line 330 is further electrically connected to the connection electrode 324 (see FIG. 7A) in the second conductive layer 302 by a via 407 in the fourth insulating layer, and electrically connected to the contact hole region 411b in the second region (N-well region) 402 in the base substrate 101, so as to bias the N-type base on which the first data write transistor P1 and the resistor 130 are located.

[0204] As shown in FIG. 8B, the power line 340 is electrically connected to the power lines 270a, 270b in the second conductive layer 302 by vias 408, 409 in the fourth insulating layer 204, respectively, to form a mesh-like power line structure for transmitting the second power voltage. Such a structure contributes to reducing the resistance in the power line, thereby reducing the voltage rise in the power line, and contributes to uniformly transmitting the second power voltage VSS to each sub-pixel of the display substrate. The power line 340 is further electrically connected to the connection electrode 325 (see FIG. 3B and FIG. 6A) in the second conductive layer 302 by vias 412 in the fourth insulating layer, and electrically connected to the contact hole region 400a in the base substrate 101, so as to bias the P-type bases on which the transistors N1-N3 are located.

[0205] As shown in Fig. 8A, the third conductive layer 303 further includes a connection electrode 333 located between the first data line 241 and the second data line 242 in one data line group. As shown in Fig. 7B, the connection electrode 333 is electrically connected to the power line 270b in the second conductive layer by the via 413 in the fourth insulating layer, for example, the number of the vias 413 is at least two, so that the connection electrode 333 can be in sufficient contact with the power line 270b and reduce the contact resistance. The connection electrode 333 is arranged in parallel with the power line 270b, which can contribute to reducing the resistance of the power line 270b, thereby reducing the voltage rise in the power line, and contributing to uniformly transmitting the second power supply voltage VSS to each sub-pixel of the display substrate.

[0206] 3B, 8A and 8B, the third conductive layer 303 further includes a connection electrode 334, which is electrically connected to the connection electrode 323 of the second conductive layer 302 by a via 414 in the fourth insulating layer, and is connected to the second terminal 132 of the resistor 130. The connection electrode 334 is used to electrically connect to the first electrode 121 of the light emitting element 120. For example, the number of the vias 414 is at least two.

[0207] 8A and 8B, the third conductive layer 303 further includes a shielding electrode 341, for example, the shielding electrode 341 extends along the second direction D2 and is located between the first data line 241 and the second data line 242 in one data line group, for example, the first data line 241 and the second data line 242 are symmetrically disposed on both sides of the shielding electrode 341 of the second data line. The shielding electrode 341 is disposed between the two data lines and performs a shielding function to prevent signals on the two data lines from interfering with each other. For example, the shielding electrode 341 receives a constant voltage to improve the shielding ability. In this embodiment, the shielding electrode 341 is used to receive the second power supply voltage VSS.

[0208] For example, the display substrate includes a plurality of shielding electrodes 341 arranged in one-to-one correspondence with the plurality of data line groups, and each shielding electrode is located between a first data line and a second data line in a corresponding data line group.

[0209] 8A, the connection electrode 333, the connection electrode 334, and the shielding electrode 341 are arranged in the second direction D2, and are located between the first data line 241 and the second data line 242. The connection electrode 333, the connection electrode 334, and the shielding electrode 341 form a shielding wall, which performs a shielding function within the entire range in which the first data line 241 and the second data line 242 extend, to prevent signals from interfering with each other in the two data lines.

[0210] 8A, the connection electrode 333 and the shielding electrode 341 are located on both sides of the connection electrode 334, and are spaced apart from the connection electrode 334. One end of the connection electrode 333 close to the connection electrode 334 has a protrusion 333a, which is L-shaped, with a first branch extending along a first direction D1 and connected to the body of the connection electrode 333, and a second branch extending along a second direction D2 close to the connection electrode 334 and overlapping with the gap between the connection electrode 333 and the connection electrode 334 in the first direction D1, thereby improving the shielding ability and thus avoiding signal interference between two data lines.

[0211] Similarly, one end of the shielding electrode 341 adjacent to the connecting electrode 334 has an L-shaped protrusion 341a for further blocking the gap between the shielding electrode 341 and the connecting electrode 334 and improving the shielding ability.

[0212] In this way, the shielding wall achieves complete shielding in the second direction D2, and the first data line 241 and the second data line 242 have no directly facing areas in the first direction D1, thereby achieving excellent signal shielding function, so that the display data has good stability and the display effect is improved.

[0213] 9A shows a schematic diagram of the fourth conductive layer 304, and FIG. 9B shows the fourth conductive layer 304 based on the third conductive layer 303, and FIG. 9B also shows a via in the fifth insulating layer 205, which is used to connect the pattern in the third conductive layer 303 with the pattern in the fourth conductive layer 304. For clarity, the figure only shows sub-pixels with 4 rows and 6 columns, and the dashed lines indicate the boundaries of the sub-pixels in two rows, and FIG. 9B also correspondingly shows the position of the cross-sectional line I-I' in FIG. 3A.

[0214] For example, the fourth conductive layer 304 includes power lines 350 and 360 extending along the second direction D2. The power line 350 is used to transmit a first power voltage VDD, and the power line 360 ​​is used to transmit a second power voltage VSS. As shown in FIG. 9A, the power lines 350 and the power lines 360 are alternately arranged in the first direction D1.

[0215] For example, the multiple power lines 350 and the multiple power lines 330 are installed in one-to-one correspondence, the multiple power lines 360 and the multiple power lines 340 are installed in one-to-one correspondence, and in the direction perpendicular to the base substrate 101, each power line 350 overlaps and is electrically connected (for example, connected in parallel) to the corresponding power line 330, and each power line 360 ​​overlaps and is electrically connected (for example, connected in parallel) to the corresponding power line 340. This reduces the resistance in the power lines and improves the uniformity of the display.

[0216] 9B, the power line 350 is electrically connected to the corresponding power line 330 by a via 251 in the fifth insulating layer 205, and the power line 360 ​​is electrically connected to the corresponding power line 340 by a via 252 in the fifth insulating layer. For example, the number of the vias 251 and 252 is at least two.

[0217] 9A and 9B, the fourth conductive layer 304 further includes a connection electrode 342, which is electrically connected to the connection electrode 333 in the third conductive layer 303 by the vias 253 in the fifth insulating layer, for example, the number of the vias 253 is at least two, so that the connection electrode 342 can be in full contact with the connection electrode 333 and reduce the contact resistance. The provision of the connection electrode 342 contributes to further reducing the resistance in the power line 270b, reducing the voltage rise in the power line, and contributing to uniformly transmitting the second power supply voltage VSS to each sub-pixel of the display substrate.

[0218] 3B, 9A and 9B, the fourth conductive layer 304 further includes a connection electrode 343, which is electrically connected to the connection electrode 334 in the third conductive layer 303 by a via 254 in the fifth insulating layer, and is connected to the second terminal 132 of the resistor 130. The connection electrode 343 is used to electrically connect to the first electrode 121 of the light emitting element 120. For example, the number of the vias 254 is at least two.

[0219] 9A and 9B, the fourth conductive layer 304 further includes a connection electrode 344 that is electrically connected to the shielding electrode 341 in the third conductive layer 303 by a via 255 in the fifth insulating layer. As shown in FIG. 9A, the fourth conductive layer 304 further includes a connection portion 345 that connects the connection electrode 344 to a power line 360 ​​that is directly adjacent to the connection electrode 344.

[0220] 9A, the connection electrodes 344 located on both sides of the power line 360 ​​are symmetrically arranged with respect to the power line 360. The power line 360, the connection electrodes 344 located on both sides thereof, and the connection parts 345 corresponding to the connection electrodes are connected to each other to form an integral structure. In this way, the power line 360 ​​can provide the second power supply voltage VSS to the shielding electrode 341, so as to improve the shielding ability of the shielding electrode.

[0221] For example, each via may be further filled with a conductive material (eg, tungsten) to make it conductive.

[0222] FIG. 9B also shows a contact hole area 256 of the connection electrode 343 , which is used to electrically connect to the first electrode 121 of the light emitting device 120 .

[0223] It should be noted that along the cross-sectional line I-I', the portion of the connection electrode 343 located at the contact hole region 256 is not continuous with the portion of the connection electrode 343 corresponding to the via 254 (area F shown in FIG. 9B), but for the sake of simplicity, the cross-sectional view shown in FIG. 3B shows the contact hole region 256 and the via 254 in the continuous connection electrode 343, that is, consistent with the actual situation. For example, as shown in FIG. 3B, the display substrate 10 further includes a sixth insulating layer 206, in which a via 257 is formed corresponding to the contact hole region 256 of the connection electrode 343, and the via 257 is filled with a conductive material (e.g., tungsten), and a flat surface is formed by a polishing process (e.g., chemical mechanical polishing) to form the light-emitting element 120.

[0224] For example, the number of vias 257 is at least two.

[0225] For example, as shown in FIG. 3B, the number of contact hole areas for electrical connection in the connection electrodes 314, 323, 334, 343 connected to the first electrode 121 of the light-emitting element 120 is at least two, thereby reducing the contact resistance between the connection electrodes and ultimately reducing the connection resistance between the resistor 130 and the first electrode 121 of the light-emitting element 120. As a result, the voltage drop in the transmission path through which the data signal is transmitted from the resistor 130 to the first electrode 121 is reduced, and problems such as color cast and display unevenness caused by anode potential loss (grayscale loss) due to the voltage drop are alleviated, thereby improving the display effect.

[0226] 3B, the vias 257, 254, and 414 corresponding to the first electrodes 121 of the light-emitting elements 120 do not overlap with each other in the direction perpendicular to the base substrate 101. Since stacking of the vias in the direction perpendicular to the substrate can easily cause connection failure, disconnection, or unevenness at the points where the vias are located, the above-mentioned installation improves the quality of the electrical connection of the first electrodes 121 of the light-emitting elements 120 and improves the display effect.

[0227] 3B, the light emitting element 120 includes a first electrode 121, a light emitting layer 123 and a second electrode 122 disposed in sequence on the sixth insulating layer 206. For example, the first electrode 121 and the second electrode 122 are respectively an anode and a cathode of an OLED. For example, a plurality of first electrodes 121 are disposed at intervals in the same layer, and correspond one-to-one to a plurality of sub-pixels. For example, the second electrode 122 is a common electrode, and its entire surface is disposed within the display substrate 10.

[0228] For example, as shown in FIG. 3B, the display substrate further includes a first package layer 124 located on the side of the light emitting element 120 away from the base substrate 101, a color filter layer 125, and a cover plate 126, etc.

[0229] For example, the first package layer 124 is configured to seal the light emitting element to prevent the light emitting element and pixel circuit from being damaged by external moisture and oxygen. For example, the package layer 124 includes an organic thin film or a structure in which organic thin films and inorganic films are alternately laminated. For example, a water absorbing layer configured to absorb water vapor or sol remaining in the light emitting element during a previous manufacturing process may be further installed between the package layer 124 and the light emitting element. The cover plate 126 is, for example, a glass cover plate.

[0230] For example, as shown in FIG. 3B , the display substrate may further include a second package layer 127 located between the color filter layer 125 and the cover plate 126 , where the second package layer 127 can protect the color filter layer 125 .

[0231] For example, the light emitting element 120 may be configured to emit white light and in combination with a color filter layer 124 provide a full color display.

[0232] In some other examples, the light emitting element 120 is configured to emit light of three primary colors, in which case the color filter layer 124 is not required. The embodiments of the present disclosure do not limit the manner in which the display substrate 10 realizes a full color display.

[0233] The following Table A exemplarily shows thickness ranges and exemplary values ​​of the first to sixth insulating layers, Table B exemplarily shows thickness ranges and exemplary values ​​of the first to fourth conductive layers, Table C exemplarily shows sizes and exemplary values ​​of via VIA2 in the second insulating layer, via VIA3 in the third insulating layer, via VIA4 in the fourth insulating layer, via VIA5 in the fifth insulating layer, and via VIA6 in the sixth insulating layer, and Table D exemplarily shows exemplary values ​​of the channel width, length, and aspect ratio of each transistor (N1-N4, P1), but this is not intended to limit the present disclosure.

[0234] [Table 1]

[0235] [Table 2]

[0236] [Table 3]

[0237] [Table 4]

[0238] For example, as shown in Table A, among the first to sixth insulating layers, the first insulating layer 201 has the smallest thickness, and the second insulating layer 202 has the largest thickness. This is because the first insulating layer 201 includes the gate insulating layer of each transistor and further includes the dielectric layer 104 of the storage capacitor Cst, and setting the thickness of the first insulating layer 201 to be small contributes to improving the gate controllability of the transistor and to obtaining a large storage capacity. In addition, the second insulating layer 202 serves as a field oxide layer, and setting it to be thick contributes to electrical isolation between each transistor. For example, the thicknesses of the third insulating layer 203, the fourth insulating layer 204, the fifth insulating layer 205, and the sixth insulating layer 206 are the same or close to each other. For example, the thickness of the second insulating layer 202 is 1.5-2 times the thicknesses of the third insulating layer 203 / fourth insulating layer 204 / fifth insulating layer 205 / sixth insulating layer 206.

[0239] For example, the planar shape of the via may be rectangular (e.g., square) or circular, and the sizes in Table C indicate the average side length or hole diameter of the rectangle. For example, as shown in Table C, the size of the multiple vias in each insulating layer is the same. For example, among the second to sixth insulating layers, the size of the via in the sixth insulating layer 206 is the largest. This is because the sixth insulating layer 206 is closest to the light emitting element, and in the driving process of the light emitting element, the current converges from the transistor in the lowest layer upward to the light emitting element, so the size of the via in the sixth insulating layer 206 is made the largest to transmit a large convergent current.

[0240] For example, the distance between the first data write transistor P1 and the second data write transistor N1 is in the range of 0.4-0.45 micrometers, e.g., 0.42 micrometers, thereby contributing to improving pixel density. As shown in FIG. 4B, the distance D0 is the distance between the closest sides of the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor N1.

[0241] For example, as shown in FIG. 4B, resistor 130 has an equivalent length of 4.4 micrometers and an average width of 0.42 micrometers.

[0242] For example, as shown in FIG. 4B, the effective capacitance area of ​​the storage capacitor Cst is 20 μm2, that is, the effective area of ​​the polysilicon layer 102 for forming the storage capacitor Cst is 20 μm2. For example, the area ratio of the storage capacitor Cst for each subpixel is 20%-35%, e.g., 27%. Through a reasonable arrangement, the display substrate according to the embodiment of the present disclosure can effectively increase the area ratio of the storage capacitor, thereby improving the capacitance value.

[0243] For example, the polysilicon layer 102 has a thickness of 200 nanometers.

[0244] At least one embodiment of the present disclosure further provides a pixel structure, the pixel structure including a base substrate, a pixel row located on the base substrate, a first scan line, and a second scan line, the pixel row includes a plurality of sub-pixels located on the base substrate and arranged along a first direction, the first scan line and the second scan line extend along the first direction, each sub-pixel includes a pixel circuit including a data writing sub-circuit, a recording sub-circuit, and a driving sub-circuit, the data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal, and a second electrode, the first control electrode and the second control electrode of the data writing circuit are respectively configured to receive a first control signal and a second control signal, the first terminal of the data writing sub-circuit is configured to receive a data signal, the second terminal of the data writing circuit is electrically connected to the first terminal of the recording sub-circuit, and is configured to transmit the data signal to the first terminal of the recording sub-circuit in response to the first control signal and the second control signal, the driving sub-circuit includes a control terminal, a first terminal, and a second terminal, the control terminal of the driving sub-circuit is electrically connected to the first terminal of the recording sub-circuit a first terminal of the driving subcircuit configured to receive a first power supply voltage and a second terminal of the driving subcircuit configured to be connected to a light-emitting element, the driving subcircuit configured to drive the light-emitting element to emit light in response to a voltage at the first terminal of the recording subcircuit; the first scanning line electrically connected to a first control electrode of a data writing circuit of the plurality of subpixels to provide the first control signal, and the second scanning line electrically connected to a second control electrode of a data writing circuit of the plurality of subpixels to provide the second control signal, the first scanning line and the second scanning line having the same resistance and the same area of ​​orthogonal projection on the base substrate.

[0245] In some instances, for example, the first and second scan lines are portions of wiring in the display area that transmit corresponding control signals from the scan drive circuit to each subpixel, and therefore, when comparing resistance values ​​and areas, portions of the wiring that are outside the display area are not taken into account.

[0246] In some other examples, for example, the first and second scan lines may refer to all parts of wiring that transmit corresponding control signals from a scan driving circuit to each subpixel, i.e., may include parts of the wiring located in the display area and non-display area, such as the S part shown in Fig. 1A. For example, the first control signal SEL and the second control signal SEL_B can be output from the same gate driving circuit unit (e.g., GOA unit).

[0247] This arrangement can ensure that the loads of the resistance capacitance (RC) in the first and second scan lines are the same. As shown in FIG. 1A, in the process of transmitting the control signal from the scan driving circuit 14 to each sub-pixel, the ratio of the portion of the scan line 11 (e.g., the first and second scan lines) located outside the display area (shown in the broken line frame) is small, so that the loads of the resistance capacitance in the portion of the scan line 11 located in the display area are set to the same, which can improve the synchronization of the first control signal SEL and the second control signal SEL_B. As shown in FIG. 2C, for example, when going from the data writing stage 1 to the light emitting stage 2, this arrangement allows the rising edge of the first control signal SEL and the falling edge of the second control signal SEL_B to occur at the same time. Therefore, the anti-interference performance of the pixel circuit is improved.

[0248] The present disclosure further provides a display substrate, including a plurality of pixel structures, where a plurality of pixel rows in the plurality of pixel structures are arranged along a second direction, and the first direction and the second direction intersect, whereby a plurality of sub-pixels in the plurality of pixel rows are arranged as a plurality of pixel columns.

[0249] It should be noted that the pixel structure according to the embodiment of the present disclosure can be applied to any one of the display substrates 10 according to the above embodiments. However, the pixel structure according to the embodiment of the present disclosure is not limited to a silicon-based display substrate, and can also be applied to, for example, a glass substrate or a flexible substrate, in which case the light-emitting element can have, for example, a bottom-emitting or double-sided emitting structure.

[0250] FIG. 10A shows a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. For clarity, the figure shows 2 rows and 6 columns of sub-pixels, i.e., only includes two of the above pixel structures. Compared with the display substrate shown in FIG. 3A, the display substrate omits the third and fourth conductive layers. In the following, the arrangement of the first and second scan lines in the display substrate and pixel structure according to the embodiment of the present disclosure will be exemplarily described with reference to FIG. 10A, but the embodiment of the present disclosure is not limited thereto.

[0251] For example, as shown in FIG. 10A, each sub-pixel row is respectively connected to one first scan line 210 and one second scan line 220, but this is not a limitation of the present disclosure.

[0252] For example, the display substrate 10 further includes a plurality of first scanning line connection parts 311 electrically connected to the first scanning line 210 and a plurality of second scanning line connection parts 312 electrically connected to the second scanning lines 220, and the first scanning line 210 is electrically connected to a first control electrode (i.e., the gate of the first data writing transistor) of the data writing circuit of the sub-pixels of a row by the plurality of first scanning line connection parts 311, and the second scanning line 220 is electrically connected to a second control electrode (i.e., the gate of the second data writing transistor) of the data writing circuit of the sub-pixels of the row by the plurality of second scanning line connection parts 312.

[0253] For example, the first scan line 210 and the second scan line 220 are insulated from the same layer and made of the same material.

[0254] For example, the plurality of first scan line connecting parts 311 and the plurality of second scan line connecting parts 312 are spaced apart in the same layer, are made of the same material, and are located in a different conductive layer than the first scan lines 210 and the second scan lines 220.

[0255] FIG 10B shows an enlarged schematic diagram of the dashed frame region E in FIG 10A, and for clarity, the figure only shows the gates of the first data write transistor P1 and the second data write transistor N1, the first scan line 210, the second scan line 220, and the first scan line connection part 311 and the second scan line connection part 312. For ease of comparison, FIG 7B also shows the corresponding position of the E region. FIG 10C shows a cross-sectional view along the cross-sectional line V-V' in FIG 10B.

[0256] For example, the first scan line 210 and the second scan line 220 have the same length and line width.

[0257] For example, the first scanning line connection portion 311 and the second scanning line connection portion 312 are alternately arranged in the first direction D1, and the extending direction is different from the first direction D1, the first scanning line connection portion 311 intersects with both the orthogonal projections of the first scanning line 210 and the second scanning line 220 on the base substrate, and the second scanning line connection portion 312 intersects with both the orthogonal projections of the first scanning line 210 and the second scanning line 220 on the base substrate. For example, both the first scanning line connection portion 311 and the second scanning line connection portion 312 have a linear structure and extend along the second direction D2.

[0258] For example, the total area of ​​the orthogonal projection of the first scanning line connection parts 311 on the base substrate is the same as the total area of ​​the orthogonal projection of the second scanning line connection parts 312 on the base substrate. Therefore, the parasitic capacitances of the first scanning line connection parts 311 and the second scanning line connection parts 312 are the same.

[0259] With this arrangement, the parasitic capacitance loads on the wiring (including the corresponding scanning lines and connection parts) when the first control signal and the second control signal are transmitted from the first scanning line and the second scanning line, respectively, to the data writing sub-circuit are made the same, thereby further improving the synchronism of the first control signal and the second control signal.

[0260] For example, the sizes of the first data write transistor P1 and the second data write circuit N1 electrically connected to the first scan line and the second scan line, respectively, are also the same, and therefore the loads caused by the scan lines connected to them are also the same, which further improves the synchronization of the first control signal and the second control signal, thereby improving the anti-interference performance of the circuit.

[0261] For example, each of the first scanning line connection portions 311 has the same length along the second direction D2, and each of the first scanning line connection portions 311 has the same line width. Each of the second scanning line connection portions 312 has the same length along the second direction D2, and each of the second scanning line connection portions 312 has the same line width.

[0262] For example, the first scan line 210 is electrically connected to the first scan line connection portion 311 by a via 231, and the second scan line 220 is connected to the second scan line connection portion 312 by a via 232, both of which are located in the third insulating layer 203.

[0263] For example, as shown in FIG. 10B, a first control electrode group 191 consisting of first control electrodes of two subpixels adjacent to each other in the first direction D1 is arranged alternately with a second control electrode group 192 consisting of two adjacent subpixels in the first direction D1.

[0264] 10B, the first scanning line connection portion 311 is electrically connected to the first control electrode group 191 or the first control electrode by a via 221, and the second scanning line connection portion 312 is electrically connected to the second control electrode group 192 or the second control electrode by a via 222. For example, the multiple first scanning line connection portions 311 and the multiple first control electrode groups 191 are electrically connected in one-to-one correspondence, and the multiple second scanning line connection portions 312 and the multiple second control electrode groups 192 are electrically connected in one-to-one correspondence.

[0265] For example, the first scanning line 210313 and the second scanning line 220 are located on the same side of the plurality of first control electrode groups 191 and the plurality of second control electrode groups 192, and the first scanning line 210 is closer to the plurality of first control electrode groups 191 and the second control electrode groups 192.

[0266] 10B, in a direction perpendicular to the base substrate, the first scanning line 210 intersects with both the first scanning line connection portion 311 and the second scanning line connection portion 312, and the second scanning line 220 intersects with both the first scanning line connection portion 311 and the second scanning line connection portion 312. The via 231 is located at the intersection of the first scanning line 210 and the first scanning line connection portion 311, and the via 232 is located at the intersection of the second scanning line 220 and the second scanning line connection portion 312.

[0267] For example, as shown in FIG. 10B, vias 231 and vias 232 are arranged alternately in a first direction D1 and staggered in a second direction D1, and via 231 is closer to the plurality of first control electrode groups 191 and second control electrode groups 192 than via 232.

[0268] 10B, one end of the second scanning line connection portion 312 is electrically connected to the second scanning line 220 by a via 232, and the other end is electrically connected to the second control electrode or second control electrode group to be connected by a via 222. The first scanning line 210 passes between the via 232 and the via 222.

[0269] 10B, the first scanning line connection portion 311 includes a main body portion 321 and an extension portion 322, and the extension portion 322 is a portion of the main body portion 321 that extends away from the first scanning line 20 along the second direction. The main body portion 321 is used to electrically connect the first scanning line connection portion 311 to the first control electrode or the first control electrode group, and is located between the first scanning line 210 and the first control electrode or the first control electrode group connected thereto in the second direction D2, and the extension portion 322 is located on the side away from the first control electrode or the first control electrode group connected to the first scanning line 210 in the second direction D2.

[0270] Here, since the extension portion 322 is a virtual structure, it cannot actually perform the function of electrical connection. By installing the extension portion 322, the first scanning line connection portion 311 and the second scanning line connection portion 312 have the same length, the same area, and form the same capacitive load.

[0271] 10B, the via 221 is located in the middle of the first control electrode group 191, and the via 222 is located in the middle of the second control electrode group 192. The two first control electrodes in the first control electrode group 191 are axially symmetrical with respect to the first scanning line connection portion 311 connected to the first control electrode group and its extension line, and the two second control electrodes in the second control electrode group 192 are axially symmetrical with respect to the second scanning line connection portion 312 connected to the second control electrode group and its extension line.

[0272] As shown in FIG. 10A, the first scanning line 210 connected to correspond to two adjacent pixel rows is symmetrical with respect to an axis of symmetry along the first direction D1, and the second scanning line 220 connected to correspond to two adjacent pixel rows is symmetrical with respect to an axis of symmetry along the first direction D1.

[0273] The display substrate 10 includes a plurality of data lines extending along a second direction D2, which are adapted to be connected to first terminals of data writing sub-circuits in the sub-pixels to provide data signals Vd.

[0274] FIG. 11A illustrates a schematic diagram of a display substrate according to some further embodiments of the present disclosure, and the diagram illustrates a schematic diagram of a data line of a display substrate according to at least one embodiment of the present disclosure, although the embodiments of the present disclosure are not limited thereto.

[0275] 8A, the data lines are divided into a plurality of data line groups, each of which includes one first data line 241 and one second data line 242. The plurality of data line groups are electrically connected to a plurality of pixel columns in one-to-one correspondence to provide the data signal Vd. Each sub-pixel column is electrically connected to one first data line 241 and one second data line 242, respectively, that is, the sub-pixels in one column are driven by two data lines.

[0276] For example, as shown in FIG. 11A, each sub-pixel column is correspondingly connected to two data lines, i.e., a first data line 241 and a second data line 242. For each column of sub-pixels, two sub-pixels located in adjacent n-th pixel row and n+1-th pixel row constitute one pixel group 240 and share one data line, where n is an odd or even number greater than 0. For each column of sub-pixels, in the second direction D2, the N-th pixel group 240 is connected to the first data line 241, and the N+1-th pixel group 240 is connected to the second data line 242, where N is a natural number, that is, in the second direction D2, the pixel groups 240 are alternately connected to the first data line 241 and the second data line 242, where the odd-numbered pixel groups share one data line, and the even-numbered pixel groups share the other data line.

[0277] By providing two data lines to drive one sub-pixel column, the load on each data line can be reduced, thereby improving the driving capability of the data lines, reducing signal delay, and improving the display effect.

[0278] Since the display substrate according to the embodiment of the present disclosure has a symmetrical structure, the layout of the signal lines can be matched with the driving manner of the data lines, thereby achieving the effect of design optimization.

[0279] For example, as shown in FIG. 4A, the first poles of two first data writing transistors P1 in one pixel group 240 are connected to each other to form an integral structure (see the A1 region), and the first poles of two second data writing transistors N1 are connected to each other to form an integral structure (see the A2 region), and therefore, in combination with the above-mentioned data line driving method, the data line can be electrically connected to the two first data writing transistors P1 or the two second data writing transistors N2 in the pixel group 240 by installing a connection via for connecting to the data line in the first pole of the integral structure within a limited contact area without installing a connection via for connecting to the data line in each of the two transistors. This not only saves processes, but also makes the layout design more compact even when limited by the design rule, thereby improving the resolution of the display substrate.

[0280] FIG. 11B shows the connection structure of the data lines in two adjacent pixel groups 240, and for clarity, only partial views where the first and second data lines are connected to the sub-pixels in each pixel group are selectively shown, and the partial views corresponding to the two pixel groups are connected to represent the continuous relationship of the signal lines, and the dashed line indicates the boundary between the two pixel groups.

[0281] As shown in FIG. 11B, in a direction perpendicular to the base substrate, the first data line 241 overlaps the first data write transistor P1 and is electrically connected to the first poles of two adjacent first data write transistors P1 in one pixel row 240, and the second data line 242 overlaps the second data write transistor N1 and is electrically connected to the first poles of two adjacent second data write transistors N1 in one pixel group 240.

[0282] For example, as shown in FIG. 11B, in a direction perpendicular to the base substrate, the first data line 241 overlaps with the gate 160 of the first data write transistor P1, and the second data line 242 overlaps with the gate 170 of the second data write transistor N1, i.e., both the first data line 241 and the second data line 242 pass through the pixel area, thereby improving space utilization without occupying additional pixel space.

[0283] 11C and 11D show cross-sectional views along the cross-sectional lines II-II' and III-III' of FIG. 11B, respectively, which are along the first direction D1, for example. For clarity, the figures only show the structures electrically connected to the data lines, and omit other structures. As shown in FIGS. 11C and 11D, the first data line 241 and the second data line 242 are located in the third conductive layer 303, and are electrically connected to the corresponding first data line connection portion 244 in the second conductive layer 302 by the vias 403, 404 in the fourth insulating layer 204, respectively. In the direction perpendicular to the base substrate, the first data line connection portion 244 overlaps with the corresponding first data line 241 or second data line 242, respectively. The first data line connection portion 244 is electrically connected to the second data line connection portion 245 in the first conductive layer 301 by vias 233, 234 in the third insulating layer 203, and the second data line connection portion 245 is electrically connected to the first pole 161 of the first data write transistor P1 and the first pole 171 of the second data write transistor N1 by vias 223 and 224 in the second insulating layer 202, respectively, thereby transmitting data signals to the transistors.

[0284] The first poles of two adjacent first data write transistors P1 and the first poles of two adjacent second data write transistors N1 in one pixel row are respectively connected to form an integral structure, and the second data line connection part 245 electrically connects the first pole of the first data write transistor P1 and the first pole of the second data write transistor N1 in one subpixel, so that the second data line connection part 245 electrically connects the first poles 161 of the two first data write transistors P1 and the first poles 171 of the two second data write transistors N1 of two adjacent subpixels in the second direction D2 in one subpixel group to each other, and is connected to the corresponding first data line 241 or second data line 242 by the corresponding first data line connection part 244. As can be seen from this, the first poles of the four transistors can be electrically connected to the data lines by only providing one via in the third insulating layer and the fourth insulating layer, respectively, which greatly saves the layout space and improves the space utilization rate.

[0285] As shown in FIGS. 11B-11D, for example, the first data line 241 and the second data line 242 are symmetrically disposed on both sides of the second data line connection part 245. As shown in FIG.

[0286] 11C and 11D, the third conductive layer further includes a shielding electrode 341 located between the first data line 241 and the second data line 242, for example, the first data line 241 and the second data line 242 are symmetrically disposed on both sides of the shielding electrode 341 of the second data line. The shielding electrode 341 is disposed between the two data lines, and performs a shielding function to prevent signals on the two data lines from crossing each other. For example, the shielding electrode 341 is configured to receive a constant voltage, for example, the shielding electrode 341 is configured to receive a second power supply voltage, so as to improve the shielding ability.

[0287] For example, as shown in FIG. 4A , the first poles 161 of the first data writing transistors P1 of two adjacent subpixels 100 in the second direction D2 are connected to each other to form an integral structure, and the first poles 171 of the second data writing transistors N1 of two adjacent subpixels 100 in the second direction D2 are connected to each other to form an integral structure.

[0288] For example, the materials of the first to fourth conductive layers are metal materials such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials combining the above metals. For example, the materials of the first to fourth conductive layers may be conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO).

[0289] For example, the materials of the first insulating layer to the sixth insulating layer are, for example, inorganic insulating layers, and are, for example, insulating materials containing oxides of silicon such as silicon oxide, silicon nitride, and silicon oxynitride, nitrides of silicon, or nitrogen oxides of silicon, or metal nitrogen oxides such as aluminum oxide and titanium nitride.

[0290] For example, the light emitting element 120 has a top emission structure, the first electrode 121 is reflective, and the second electrode 122 is transparent or semi-transparent. For example, the first electrode 121 is a high work function material, such as an ITO / Ag / ITO stacked structure, to serve as an anode, and the second electrode 122 is a low work function material, such as a semi-transparent metal or metal alloy material, such as an Ag / Mg alloy material, to serve as a cathode.

[0291] At least one embodiment of the present disclosure further provides a display panel, any of which includes a display substrate 10. It should be noted that the display substrate 10 according to at least one embodiment of the present disclosure may include a light emitting element 120, or may not include a light emitting element 120, that is, the light emitting element 120 can be formed in a panel factory after the display substrate 10 is completed. If the display substrate 10 itself does not include a light emitting element 120, the display panel according to the embodiment of the present disclosure further includes a light emitting element 120 in addition to the display substrate 10.

[0292] At least one embodiment of the present disclosure further provides a display device 40, which includes any one of the display substrates 10 or display panels described above, as shown in FIG. 12 , and the display device in this embodiment may be any product or component having a display function, such as a display, an OLED panel, an OLED TV, electronic paper, a mobile phone, a tablet PC, a notebook computer, a digital photo frame, a navigator, etc.

[0293] The above description is merely a specific embodiment of the present disclosure, but does not limit the scope of protection of the present disclosure, which should be governed by the claims.

Claims

1. A display substrate, a base substrate and a sub-pixel on the base substrate, the sub-pixel including a pixel circuit including a data writing sub-circuit, a recording sub-circuit, and a driving sub-circuit; the recording sub-circuit includes a storage capacitor, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the second capacitor electrode being a first terminal and a second terminal of the recording sub-circuit, respectively; the data writing subcircuit is electrically connected to a first terminal of the recording subcircuit and configured to transmit a data signal to the first terminal of the recording subcircuit in response to a control signal; the driving sub-circuit includes a control electrode, a first electrode and a second electrode, the control electrode of the driving sub-circuit being electrically connected to a first terminal of the recording sub-circuit; the driving subcircuit is configured to control a driving current flowing from the first electrode to the second electrode in response to a voltage at a first terminal of the recording subcircuit and driving the light emitting element to emit light; The display substrate further includes a first connection electrode, the first connection electrode being insulated from the second capacitor on the same layer as the second capacitor, and electrically connecting the first capacitor electrode to the data writing sub-circuit.

2. the first electrode includes a first portion extending along a first direction and a second portion extending along a second direction, the first portion and the second portion have an integral structure, and the first direction and the second direction are perpendicular to each other; The display substrate of claim 1 , wherein the first portion is electrically connected to the data writing sub-circuit, and the second portion is electrically connected to the first capacitor electrode.

3. The display substrate of claim 2 , wherein an orthogonal projection of the first portion of the first connection electrode on the base substrate does not overlap with an orthogonal projection of the storage capacitor on the base substrate.

4. the drive subcircuit includes a drive transistor, the gate, the first pole, and the second pole of the drive transistor being the control electrode, the first electrode, and the second electrode of the drive subcircuit, respectively; The display substrate according to claim 1 , wherein the first connection electrode does not overlap a channel region of the transistor in a direction perpendicular to the base substrate.

5. further comprising a polysilicon layer disposed on the base substrate; a control electrode of the drive sub-circuit located in the polysilicon layer; The display substrate according to claim 1 , wherein the first connection electrode is located on a side of the polysilicon layer away from the base substrate.

6. 2 . The display substrate as claimed in claim 1 , wherein a current path of the driving current flowing from the first electrode of the driving sub-circuit to the light emitting element includes a first straight current path, a second folded line current path and a third U-shaped current path, in that order.

7. The display substrate according to claim 6 , wherein the second folding line current path and the first straight current path are located in different layer structures of the display substrate.

8. The display substrate according to claim 6 , wherein the first straight current path is located within the base substrate, and the second folded current path is located within a layer structure in which the first connection electrode is located.

9. Further including a second connection electrode; The second folding line current path is located in the second connection electrode, The display substrate according to claim 6 , wherein a first terminal of the second connection electrode is electrically connected to a second electrode of the driving sub-circuit.

10. The display substrate of claim 9 , wherein the first connection electrode and the second connection electrode do not overlap in a direction perpendicular to the base substrate.

11. The display substrate of claim 9 , wherein the second connection electrode is disposed in the same layer as the first connection electrode and is insulated from the first connection electrode.

12. further comprising a U-shaped resistor on the base substrate; One end of the U-shaped resistor is electrically connected to the second terminal of the second connection electrode, and the other end of the U-shaped resistor is electrically connected to the light-emitting element, The display substrate of claim 9 , wherein the third U-shaped current path is located in the U-shaped resistor.

13. The display substrate of claim 12 , wherein the U-shaped resistor and the control electrode are located in a polysilicon layer, and the resistivity of the U-shaped resistor is higher than the resistivity of the control electrode of the driving sub-circuit.

14. The display substrate according to claim 9 , wherein the second connection electrode and the first capacitor electrode at least partially overlap in a direction perpendicular to the base substrate.

15. The display substrate according to claim 6 , wherein an opening of the third U-shaped current path faces the driving sub-circuit.

16. 2. The display substrate of claim 1, wherein the recording sub-circuit further includes a third capacitor electrode, the third capacitor electrode being located on a side of the first capacitor electrode away from the second capacitor electrode and configured to be electrically connected to the second capacitor electrode.

17. The display substrate of claim 16 , wherein the third capacitor electrode is located on the base substrate.

18. The display substrate includes a plurality of the sub-pixels, the plurality of sub-pixels being arranged as an array along a first direction and a second direction, the first direction being different from the second direction, The display substrate of claim 1 , wherein the data writing sub-circuit, the first connecting electrode, and the driving sub-circuit are arranged in sequence along the second direction.

19. A display device, comprising: A display device comprising the display substrate according to any one of claims 1 to 18 and the light emitting element.

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