Wiring board and display device

Abstract

To reduce the adverse influence of an electric field from a first wire.SOLUTION: A wiring board 21 includes: a first wire 27 extending along a first direction; a second wire 40 extending along the first direction; a first electrode 29 connected to the second wire 40; a third wire 42 extending along a second direction intersecting with the first direction; and a signal supply unit 12 connected to the first wire 27 and not connected to the second wire 40 and the third wire 42. Two of the first wires 27 are provided with a space therebetween in the second direction. Two of the second wires 40 are provided with a space therebetween in the second direction, overlapping with the two first wires 27 through insulating films 35 and 36. The signal supply unit 12 supplies a first signal to a first wire 27α corresponding to one of the two first wires 27, and supplies to a second signal with the polarity inverted from the first signal to a first wire 27β corresponding to the other of the two first wires 27. The third wire 42 is connected to the two second wires 40.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present specification relates to a wiring board and a display device. [Background technology]

[0002] Conventionally, the one described in the following Patent Document 1 is known as an example of a wiring substrate provided in a display device. Patent Document 1 describes an array substrate of a built-in touch panel of a display device as a wiring substrate. This built-in touch panel includes an array substrate having a plurality of subpixels, a plurality of gate lines and data lines provided on the array substrate and intersecting and insulated from each other, a plurality of self-capacitance electrodes provided in the same layer and independent from each other, and a plurality of touch control lines connecting each of the self-capacitance electrodes to a touch detection chip, the plurality of gate lines and the data lines intersecting each other to define the plurality of subpixels, each subpixel having a long side and a short side, including a pixel electrode, and the touch control line is provided to extend along the short side direction of the subpixel. This built-in touch panel is designed with a new pixel structure, so that the position of the touch control line is optimized, the aperture ratio can be improved, and power consumption can be reduced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-509662 Summary of the Invention [Problem to be solved by the invention]

[0004] In the built-in touch panel described in the above-mentioned Patent Document 1, a plurality of metal lines are formed in the same layer as the touch control lines and are insulated from each other. These metal lines are electrically connected to the self-capacitance electrode through via holes, so that the resistance of the self-capacitance electrode, which has a high resistance value, can be reduced. However, for example, if the metal lines are not properly connected to the self-capacitance electrode, the connection resistance between the self-capacitance electrode and the metal lines becomes high. For this reason, the electric field from the data lines may adversely affect the switching elements located near the metal lines through the metal lines.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to reduce the adverse effects of the electric field from the first wiring. [Means for solving the problem]

[0006] (1) A wiring board related to the technology described in this specification includes a first wiring extending along a first direction, a second wiring extending along the first direction, a first electrode connected to the second wiring, a third wiring extending along a second direction intersecting the first direction, and a signal supply unit connected to the first wiring and not connected to the second wiring and the third wiring, wherein two of the first wirings are arranged at intervals in the second direction, and two of the second wirings are arranged overlapping the two first wirings via an insulating film at positions spaced apart in the second direction, the signal supply unit supplies a first signal to one of the two first wirings and a second signal having a polarity opposite to that of the first signal to the other of the two first wirings, and the third wiring is connected to the two second wirings.

[0007] (2) In addition to the above (1), the above may further include a fourth wiring extending along the first direction and connected to a wiring board connected to the first electrode, and a fifth wiring extending along the second direction, wherein two of the fourth wirings are arranged at intervals in the second direction, and two of the first wirings are arranged overlapping the two fourth wirings via an insulating film at positions spaced apart in the second direction, and the signal supply unit supplies a third signal to the two fourth wirings, a fourth signal to one of the two first wirings overlapping with the two fourth wirings, and a fifth signal having a polarity opposite to that of the fourth signal to the other of the two first wirings overlapping with the two fourth wirings, and the fifth wiring may be connected to the two fourth wirings.

[0008] (3) In addition to the above (1) or (2), the wiring board may further include a second electrode and a switching element connected to the first wiring and the second electrode, and a portion of the second wiring may be arranged to overlap at least a portion of the switching element via an insulating film.

[0009] (4) In addition to any one of (1) to (3) above, the wiring board may further include a plurality of the third wirings arranged at spaced apart positions in the first direction, and the plurality of third wirings may be connected to each of the two second wirings.

[0010] (5) A display device according to the technology described in this specification includes a wiring substrate according to any one of (1) to (4) above, and a counter substrate arranged opposite the wiring substrate with a gap therebetween. Effect of the Invention

[0011] According to the technique described in this specification, it is possible to reduce the adverse effects of the electric field from the first wiring. [Brief description of the drawings]

[0012] [Figure 1]FIG. 1 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and the like that constitute a liquid crystal display device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, a flexible substrate, and the like according to the first embodiment; [Diagram 3] FIG. 1 is a circuit diagram showing an electrical configuration of an array substrate that constitutes a liquid crystal panel according to a first embodiment. [Figure 4] FIG. 2 is a cross-sectional view showing a cross-sectional configuration of the source wiring, the touch wiring, the first connection wiring, and the pixel electrode of the liquid crystal panel according to the first embodiment; [Diagram 5] FIG. 1 is a cross-sectional view showing a cross-sectional configuration of a TFT and a touch wiring area of ​​an array substrate according to a first embodiment. [Figure 6] FIG. 2 is a plan view showing a schematic relationship between the touch electrode according to the first embodiment, the gate wiring, the source wiring, the touch wiring, each connection wiring, and each short-circuit wiring; [Figure 7] FIG. 2 is a cross-sectional view showing a cross-sectional configuration in the vicinity of a TFT and a first connection line in the array substrate according to the first embodiment. [Figure 8] FIG. 2 is a cross-sectional view showing a cross-sectional configuration of a first short-circuit line and a gate line in the array substrate according to the first embodiment; [Figure 9] FIG. 11 is a plan view showing a schematic relationship between a touch electrode according to a second embodiment, a gate line, a source line, a touch line, each connection line, and each short-circuit line; [Figure 10] FIG. 11 is a plan view showing a schematic relationship between a touch electrode according to a third embodiment, a gate line, a source line, a touch line, each connection line, and each short-circuit line; [Figure 11] FIG. 11 is a plan view showing a schematic relationship between a touch electrode according to a fourth embodiment, a gate line, a source line, a touch line, each connection line, and each short-circuit line. [Figure 12] FIG. 13 is a plan view showing a schematic relationship between a touch electrode according to a fifth embodiment, a gate line, a source line, a touch line, each connection line, and each short-circuit line. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] <Embodiment 1> A first embodiment will be described with reference to Fig. 1 to Fig. 8. In this embodiment, a liquid crystal display device 10 having a display function and a touch panel function (position input function) is illustrated. Note that the X-axis, Y-axis, and Z-axis are shown in a part of each drawing, and each axis direction is drawn to be the direction shown in each drawing. Also, the upper side of Fig. 2, Fig. 4, Fig. 5, Fig. 7, and Fig. 8 is the front side, and the lower side of the drawings is the back side.

[0014] 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) which is an external light source that irradiates the liquid crystal panel 11 with light to be used for display. The backlight device is disposed on the rear side (back side) of the liquid crystal panel 11, and includes a light source (e.g., an LED) that emits white light and an optical member that converts the light from the light source into planar light by applying an optical effect. The central portion of the screen of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, a frame-shaped outer peripheral portion surrounding the display area AA on the screen of the liquid crystal panel 11 is a non-display area NAA where no image is displayed.

[0015] As shown in Fig. 1, a circuit section (peripheral circuit section, gate circuit section) 14 is provided in the non-display area NAA of the liquid crystal panel 11. A pair of circuit sections 14 are arranged to sandwich the display area AA from both sides in the X-axis direction. The circuit sections 14 are provided in a strip-shaped range extending along the Y-axis direction. The circuit section 14 is for supplying scanning signals to gate wiring 26 described later, and is monolithically provided on an array substrate 21 described later. The circuit section 14 is a GDM (Gate Driver Monolithic) circuit. The circuit section 14 includes a shift register circuit that outputs scanning signals at a predetermined timing, a buffer circuit that amplifies the scanning signals, and the like.

[0016] The liquid crystal panel 11 will be described in detail with reference to FIG. 1 and FIG. 2. As shown in FIG. 1 and FIG. 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. The front side (front side) of the pair of substrates 20 and 21 is an opposing substrate (CF substrate) 20, and the back side (rear side) is an array substrate (wiring substrate) 21. The opposing substrate 20 and the array substrate 21 are each formed by laminating various films on the inner side of glass substrates (substrates) 20GS and 21GS. A liquid crystal layer (medium layer) 22 containing liquid crystal molecules, which are a substance whose optical properties change with the application of an electric field, is disposed between the pair of substrates 20 and 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral ends of the pair of substrates 20 and 21. The seal portion 23 is formed in a rectangular frame shape (endless ring shape) so as to surround the liquid crystal layer 22. A polarizing plate 15 is attached to the outer surface of each of the substrates 20 and 21.

[0017] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 in such a manner that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally and is exposed from the counter substrate 20. The entire exposed portion 21A is a non-display area NAA, and is equipped with a driver (signal supply unit) 12 and a flexible substrate 13 for supplying various signals related to the display function and touch panel function described below.

[0018] The driver 12 shown in FIG. 1 and FIG. 2 is composed of an LSI chip having a driving circuit therein. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 by COG (Chip On Glass). The driver 12 processes various signals transmitted by the flexible substrate 13. The driver 12 supplies various signals (e.g., image signals, touch signals, etc.) to wiring in the display area AA (specifically, source wiring 27 and touch wiring 30 described later). The flexible substrate 13 is configured by forming a number of wiring patterns on a base material made of a synthetic resin material (e.g., polyimide resin, etc.) having insulating properties and flexibility. As shown in FIG. 1 and FIG. 2, one end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit substrate (e.g., a control substrate). The flexible substrate 13 is connected to an end of the exposed portion 21A on the opposite side to the display area AA side in the Y-axis direction with respect to the driver 12.

[0019] The liquid crystal panel 11 according to this embodiment has both a display function for displaying an image and a touch panel function for detecting a position (input position) input by a user based on the displayed image. A touch panel pattern for exerting the touch panel function is integrated (in-cell) in the liquid crystal panel 11. This touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitive type. As shown in FIG. 1, the touch panel pattern is composed of a plurality of touch electrodes (first electrodes, position detection electrodes) 29 arranged in a matrix on the plate surface of the liquid crystal panel 11. The touch electrodes 29 are arranged in a display area AA of the liquid crystal panel 11. Therefore, the display area AA of the liquid crystal panel 11 is approximately coincident with a touch area (position input area) where an input position can be detected, and the non-display area NAA is approximately coincident with a non-touch area (non-position input area) where an input position cannot be detected. When a user approaches a conductive finger (position input object) to the surface (display surface) of the liquid crystal panel 11 to input a position based on an image of the display area AA of the liquid crystal panel 11 that the user is viewing, a capacitance is formed between the finger and the touch electrode 29. As a result, the capacitance detected at the touch electrode 29 near the finger changes as the finger approaches, and becomes different from that of the touch electrode 29 far from the finger, so that it is possible to detect the input position based on the change. Note that the specific number of touch electrodes 29 installed can be changed as appropriate, in addition to the illustration in FIG. 1. The touch electrode 29 has an approximately rectangular shape in a plan view, and the dimension of one side is about several mm. Therefore, the size of the touch electrode 29 in a plan view is much larger than a pixel described later, and is arranged in a range that spans multiple pixels in the X-axis direction and the Y-axis direction.

[0020] As shown in FIG. 1, a plurality of touch wirings (fourth wirings, position detection wirings) 30 provided on the liquid crystal panel 11 are selectively connected to the plurality of touch electrodes 29. The touch wirings 30 extend roughly along the Y-axis direction, with one end connected to the driver 12 in the non-display area NAA and the other end connected to a specific touch electrode 29 among the plurality of touch electrodes 29 arranged along the Y-axis direction in the display area AA. The touch wirings 30 are further connected to a detection circuit. The detection circuit may be provided in the driver 12, or may be provided outside the liquid crystal panel 11 via the flexible substrate 13. A detailed configuration of the touch wirings 30 will be described later.

[0021] Next, the configuration of the display area AA in the array substrate 21 will be described with reference to FIG. 3. As shown in FIG. 3, at least TFTs (switching elements, transistors) 24 and pixel electrodes (second electrodes) 25 are provided on the inner surface side of the display area AA of the array substrate 21. The TFTs 24 and pixel electrodes 25 are arranged in a matrix shape (row and column shape) with a space between them along the X-axis direction and the Y-axis direction. Gate wiring (sixth wiring, scanning wiring) 26 and source wiring (first wiring, image wiring, signal wiring) 27 that are perpendicular (intersecting) to each other are arranged around the TFTs 24 and pixel electrodes 25. The gate wiring 26 extends along the X-axis direction, and a plurality of the source wirings 27 are arranged with a space between them along the Y-axis direction. The source wirings 27 extend along the Y-axis direction (first direction), and a plurality of the source wirings 27 are arranged with a space between them along the X-axis direction (second direction intersecting the first direction). The TFT 24 has a gate electrode 24A connected to the gate wiring 26, a source electrode 24B connected to the source wiring 27, a drain electrode 24C connected to the pixel electrode 25, and a semiconductor portion 24D connected to the source electrode 24B and the drain electrode 24C. The TFT 24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate wiring 26. Then, a potential related to the image signal (first signal, second signal, fourth signal, fifth signal) supplied from the driver 12 to the source electrode 24B by the source wiring 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to a potential related to the image signal. The pixel electrode 25 is disposed in an area surrounded by the gate wiring 26 and the source wiring 27, and has a planar shape of, for example, a substantially rectangular shape. In addition, slits are formed in each of the pixel electrodes 25. Note that the slits are not shown in FIG. 3.

[0022] Next, a cross-sectional configuration of the pixel electrode 25 in the liquid crystal panel 11 near the center thereof will be described with reference to FIG. 4. As shown in FIG. 4, in the display area AA on the inner surface side of the counter substrate 20 constituting the liquid crystal panel 11, three color filters 31 exhibiting blue (B), green (G) and red (R) are provided. The color filters 31 exhibiting different colors are arranged side by side so as to be adjacent to each other in the extending direction (X-axis direction) of the gate wiring 26. The color filters 31 exhibiting different colors extend along the extending direction (approximately Y-axis direction) of the source wiring 27. In this manner, the color filters 31 exhibiting different colors are arranged in a stripe pattern as a whole. These color filters 31 are arranged so as to overlap with each pixel electrode 25 on the array substrate 21 side in a plan view, and together with the pixel electrode 25, form a pixel, which is a display unit. The color filters 31 exhibiting different colors are arranged so that their boundaries (color boundaries) overlap with the source wiring 27. The inner surface of the counter substrate 20 is provided with a light-shielding portion (light-shielding portion between pixels, black matrix) 32 located below the color filter 31. The light-shielding portion 32 is made of a light-shielding material having excellent light-shielding properties. The light-shielding portion 32 can block light emitted from a backlight device or the like. In the display area AA, the light-shielding portion 32 has a substantially lattice-like planar shape and separates adjacent pixel electrodes 25 (pixels). The light-shielding portion 32 is arranged to overlap at least the gate wiring 26 and the source wiring 27 on the array substrate 21 side in a planar view. In addition, an overcoat film 33 is provided on the upper layer side (liquid crystal layer 22 side) of the color filter 31, which is arranged in a solid shape over almost the entire area of ​​the counter substrate 20 for flattening. In addition, an alignment film for aligning liquid crystal molecules contained in the liquid crystal layer 22 is formed on the innermost surface (uppermost layer) of both substrates 20 and 21 that contacts the liquid crystal layer 22.

[0023] As shown in FIG. 4, a common electrode 28 is formed on the inner surface of the display area AA of the array substrate 21 so as to overlap all the pixel electrodes 25. The common electrode 28 extends over almost the entire display area AA. The common electrode 28 is disposed on the lower layer side (glass substrate 21GS side) of the pixel electrodes 25 via a third interlayer insulating film 38 described later. A common potential signal that is a common potential (reference potential) is supplied to the common electrode 28. When the pixel electrodes 25 are charged to a potential based on an image signal transmitted to the source wiring 27 in response to the driving of the TFT 24, a potential difference is generated between the pixel electrodes 25 and the common electrode 28. Then, a fringe electric field (oblique electric field) including a component along the plate surface of the array substrate 21 as well as a component in the normal direction to the plate surface of the array substrate 21 is generated between the opening edge of the slit in the pixel electrode 25 and the common electrode 28. Therefore, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by utilizing this fringe electric field, and a predetermined display is performed based on the orientation state of the liquid crystal molecules. That is, the liquid crystal panel 11 according to this embodiment operates in a FFS (Fringe Field Switching) mode.

[0024] As shown in FIG. 1, the common electrode 28 constitutes the touch electrode 29 described above. The common electrode 28 has partition openings (partition slits) 28A that separate the adjacent touch electrodes 29. The partition openings 28A are composed of a first partition opening 28A1 that crosses the entire length of the common electrode 28 approximately along the X-axis direction, and a second partition opening 28A2 that crosses the entire length of the common electrode 28 approximately along the Y-axis direction, and generally form a substantially lattice shape in a plan view. The common electrode 28 is composed of a plurality of touch electrodes 29 that are electrically independent from each other and are divided into a substantially grid shape in a plan view by the partition openings 28A. The touch electrodes 29 aligned along the Y-axis direction are partitioned by the first partition openings 28A1, whereas the touch electrodes 29 aligned along the X-axis direction are partitioned by the second partition openings 28A2. A common potential signal (third signal) related to the image display function and a touch signal (third signal, position detection signal) related to the touch panel function are supplied from the driver 12 in a time-division manner to the touch wiring 30 connected to such a touch electrode 29. The timing when the common potential signal is supplied from the driver 12 to the touch wiring 30 is the display period, and the timing when the touch signal is supplied from the driver 12 to the touch wiring 30 is the sensing period (position detection period). This common potential signal is transmitted to all the touch wirings 30 at the same timing (display period), so that all the touch electrodes 29 become a reference potential based on the common potential signal and function as the common electrode 28.

[0025] 4, the touch wiring 30 is arranged to overlap the source wiring 27 in a plan view. As shown in FIG. 1, the touch wiring 30 is arranged across a first partition opening 28A1 that separates the touch electrodes 29 adjacent to each other in the Y-axis direction.

[0026] Here, various films laminated on the inner surface side of the array substrate 21 will be described with reference to Fig. 5. Fig. 5 shows a cross-sectional configuration of the TFT 24 and the touch wiring 30 of the array substrate 21. As shown in Fig. 5, the glass substrate (substrate) 21GS of the array substrate 21 has a first metal film, a gate insulating film 34, a semiconductor film, a second metal film (first conductive film), a first interlayer insulating film (insulating film) 35, a planarizing film (insulating film) 36, a third metal film (second conductive film), a second interlayer insulating film (insulating film) 37, a first transparent electrode film, a third interlayer insulating film (insulating film) 38, a second transparent electrode film, and an alignment film laminated thereon in this order from the lower layer side (glass substrate 21GS side).

[0027] The first metal film, the second metal film, and the third metal film are each a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and thus have electrical conductivity and light blocking properties. The first metal film constitutes the gate wiring 26, the gate electrode 24A of the TFT 24, etc. The second metal film constitutes the source wiring 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc. The third metal film constitutes the touch wiring 30, etc. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material (for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), etc.). The first transparent electrode film constitutes the common electrode 28 (touch electrode 29), etc. The second transparent electrode film constitutes the pixel electrode 25, etc. The alignment film is as described above.

[0028] The semiconductor film is made of an oxide semiconductor material and constitutes the semiconductor portion 24D of the TFT 24. The semiconductor film may contain at least one metal element selected from In, Ga, and Zn, and may be, for example, an In-Ga-Zn-O-based semiconductor (for example, indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. The In-Ga-Zn-O-based semiconductor used in the semiconductor film may be amorphous or crystalline. The semiconductor film may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, it may contain an In-Sn-Zn-O-based semiconductor (for example, In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In-W-Zn-O-based semiconductor containing W (tungsten), an In-W-Sn-Zn-O-based semiconductor, an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, a CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, or the like. The oxide semiconductor material of the semiconductor film has a higher resistance value when no voltage is applied (off state) than the polysilicon semiconductor material, and has a higher electron mobility than the amorphous silicon semiconductor material.

[0029] The gate insulating film 34, the first interlayer insulating film 35, the second interlayer insulating film 37, and the third interlayer insulating film 38 are each made of silicon nitride (SiN x), silicon oxide (SiO2), or other inorganic material. The thicknesses of the gate insulating film 34, the first interlayer insulating film 35, the second interlayer insulating film 37, and the third interlayer insulating film 38 are greater than the thicknesses of the first transparent electrode film and the second transparent electrode film. The planarizing film 36 is made of an organic material, for example, PMMA (acrylic resin). The thickness of the planarizing film 36 is much greater than the thicknesses of the gate insulating film 34, the first interlayer insulating film 35, the second interlayer insulating film 37, and the third interlayer insulating film 38. The planarizing film 36 planarizes the inner surface (surface on the liquid crystal layer 22 side) of the array substrate 21. The gate insulating film 34 keeps the first metal film on the lower layer side and the semiconductor film and second metal film on the upper layer side in an insulating state. For example, the intersection of the gate wiring 26 made of the first metal film and the source wiring 27 made of the second metal film is kept in an insulating state by the gate insulating film 34. In the TFT 24, the overlapping portion of the gate electrode 24A made of the first metal film and the semiconductor portion 24D made of the semiconductor film is kept in an insulated state by the gate insulating film 34. The first interlayer insulating film 35 and the planarizing film 36 keep the semiconductor film and the second metal film on the lower layer side and the third metal film on the upper layer side in an insulated state. For example, the overlapping portion of the source wiring 27 made of the second metal film and the touch wiring 30 made of the third metal film is kept in an insulated state by the first interlayer insulating film 35 and the planarizing film 36. The second interlayer insulating film 37 keeps the third metal film on the lower layer side and the first transparent electrode film on the upper layer side in an insulated state. For example, the overlapping portion of the touch wiring 30 made of the third metal film and the common electrode 28 (touch electrode 29) made of the first transparent electrode film is kept in an insulated state by the second interlayer insulating film 37. The third interlayer insulating film 38 keeps the first transparent electrode film on the lower layer side and the second transparent electrode film on the upper layer side in an insulated state. For example, the overlapping portion of the common electrode 28 (touch electrode 29) made of the first transparent electrode film and the pixel electrode 25 made of the second transparent electrode film is kept insulated by the third interlayer insulating film 38.

[0030] The structure of the TFT 24 will be described in detail. As shown in FIG. 5, the gate electrode 24A made of a first metal film is located on the lower layer side of the semiconductor portion 24D made of a semiconductor film via a gate insulating film 34. In other words, the TFT 24 can be said to be a bottom-gate type transistor. The gate electrode 24A is formed by partially widening the gate wiring 26 extending along the X-axis direction. The source electrode 24B and the drain electrode 24C made of a second metal film are arranged at positions spaced apart in the X-axis direction, and each of them is connected to the upper layer side of the semiconductor portion 24D in a manner that directly contacts the semiconductor portion 24D. The source electrode 24B is formed by partially widening the source wiring 27 extending along the Y-axis direction. An intermediate electrode 39 made of a third metal film is arranged to overlap the end of the drain electrode 24C on the opposite side to the semiconductor portion 24D. A first pixel contact hole CH1 is formed in the first interlayer insulating film 35 and the planarization film 36 interposed between the drain electrode 24C and the intermediate electrode 39 so as to communicate with each other. The drain electrode 24C and the intermediate electrode 39 are connected through a first pixel contact hole CH1. The intermediate electrode 39 is disposed so as to overlap a part of the pixel electrode 25 made of a second transparent electrode film. A second pixel contact hole CH2 is formed in the second interlayer insulating film 37 and the third interlayer insulating film 38 interposed between the intermediate electrode 39 and a part of the pixel electrode 25, and communicates with the second pixel contact hole CH2. The intermediate electrode 39 and the pixel electrode 25 are connected through the second pixel contact hole CH2. In addition, an opening is formed in the part of the common electrode 28 that overlaps with the second pixel contact hole CH2 to pass the pixel electrode 25 through.

[0031] A connection structure between the touch electrode 29 (common electrode 28) and the touch wiring 30 will be described. As shown in FIG. 5, a second interlayer insulating film 37 is interposed between the touch wiring 30 made of the third metal film and the touch electrode 29 made of the first transparent electrode film. A first contact hole CH3 for connecting the touch wiring 30 and the touch electrode 29 is opened and formed in the second interlayer insulating film 37. The first contact hole CH3 is arranged at a position overlapping both the touch wiring 30 and the touch electrode 29 to which the touch wiring 30 is to be connected. In detail, the first contact hole CH3 is arranged overlapping each of a part of the source electrode 24B and the semiconductor part 24D provided in a predetermined TFT 24 included in a plurality of TFTs 24 overlapping both the touch wiring 30 and the touch electrode 29. A plurality of first contact holes CH3 (eight in FIG. 6) are arranged at positions spaced apart from the touch electrode 29 and the touch wiring 30 connected to each other in the Y-axis direction. The touch wiring 30, like the source wiring 27, is partially widened, and the widened portions are arranged to overlap parts of the source electrode 24B and the semiconductor portion 24D, and the first contact hole CH3.

[0032] As shown in Fig. 6, the array substrate 21 is provided with a plurality of first connection wirings (second wirings) 40 connected to the touch electrodes 29, and second connection wirings 41 connected to some of the first connection wirings 40. In Fig. 6, one touch electrode 29 is selected from the plurality of touch electrodes 29 and illustrated, and the gate wiring 26, source wiring 27, touch wiring 30, first connection wiring 40, second connection wiring 41, etc. related to the touch electrode 29 are illustrated. Note that in Fig. 6, the source wiring 27 overlapping the touch wiring 30 is illustrated adjacent to the touch wiring 30 on the left side of Fig. 6.

[0033] As shown in FIG. 6, the first connection wiring 40 extends generally along the Y-axis direction, similar to the touch wiring 30. The first connection wiring 40 is arranged overlapping the touch electrode 29 to be connected, and the formation range in the Y-axis direction is limited to the same formation range of the touch electrode 29 to be connected. The first connection wiring 40 is connected to the touch electrode 29 to be connected at multiple points (two points in FIG. 6). The resistance distribution of the touch electrode 29 is reduced by such first connection wiring 40. The first connection wiring 40 is not connected to the driver 12. The first connection wiring 40 is located in the same layer as the touch wiring 30, and is arranged overlapping the source wiring 27 in a plan view. Note that in FIG. 6, the source wiring 27 overlapping the first connection wiring 40 is illustrated adjacent to the first connection wiring 40 on the left side of FIG. 6. The first connection wiring 40 extends along the Y-axis direction, similar to the source wiring 27 and the touch wiring 30. The first connection wiring 40 does not cross the first partition opening 28A1 that separates the touch electrode 29 to be connected from the touch electrode 29 adjacent to the touch electrode 29 in the Y-axis direction.

[0034] As shown in FIG. 6, the first connection wirings 40 are arranged in a group at positions offset in the X-axis direction in the touch electrode 29 to be connected. Specifically, the multiple first connection wirings 40 are arranged to be biased in the right region of the touch electrode 29 to be connected in FIG. 6. FIG. 6 illustrates a case where 12 first connection wirings 40 are arranged in a group in the right region of the touch electrode 29 to be connected in FIG. 6. In contrast, the multiple touch wirings 30 are arranged to be biased in the left region of the touch electrode 29 in FIG. 6. FIG. 6 illustrates a case where four touch wirings 30 are arranged in a group in the left region of the touch electrode 29 in FIG. 6. Of the four touch wirings 30 illustrated in FIG. 6, the two touch wirings 30 on the right side are mainly connected to the touch electrode 29 illustrated, while the two touch wirings 30 on the left side are connected to a touch electrode 29 other than the touch electrode 29 illustrated. The multiple first connection wirings 40 include one first connection wiring 40 that is located at the left end of the touch electrodes 29 to be connected in FIG. 6 and is sandwiched between the touch wiring 30 and a second connection wiring 41 described later.

[0035] The connection structure between the touch electrode 29 and the first connection wiring 40 will be described. As shown in FIG. 7, the first connection wiring 40 is made of the same third metal film as the touch wiring 30. FIG. 7 shows a cross-sectional configuration of the array substrate 21 near the TFT 24 and the first connection wiring 40. A second interlayer insulating film 37 is interposed between the first connection wiring 40 made of the third metal film and the touch electrode 29 to be connected. A second contact hole CH4 for connecting the touch electrode 29 and the first connection wiring 40 is opened and formed in the second interlayer insulating film 37. The second contact hole CH4 is disposed at a position overlapping both the first connection wiring 40 and the touch electrode 29 to which the first connection wiring 40 is to be connected. In detail, the second contact hole CH4 is disposed overlapping a part of each of the source electrode 24B and the semiconductor portion 24D provided in a predetermined TFT 24 included in the plurality of TFTs 24 overlapping both the touch electrode 29 and the first connection wiring 40. A plurality of second contact holes CH4 (two in FIG. 6) are arranged at positions spaced apart from each other in the Y-axis direction for one first connection wiring 40. The first connection wiring 40 is partially widened, similar to the source wiring 27 and the touch wiring 30, and the widened portions are arranged to overlap the second contact hole CH4 and parts of the source electrode 24B and the semiconductor portion 24D. A first interlayer insulating film 35 and a planarizing film 36 are interposed between the first connection wiring 40 made of the third metal film and the source wiring 27 overlapping the first connection wiring 40, thereby maintaining an insulating state.

[0036] As shown in FIG. 6, the second connection wiring 41 is arranged so as to overlap the second partition opening 28A2 that separates the adjacent touch electrodes 29 in the X-axis direction. In other words, the second connection wiring 41 is arranged so as not to overlap the touch electrode 29. The second connection wiring 41 does not cross the first partition opening 28A1 that separates the adjacent touch electrodes 29 in the Y-axis direction. The second connection wiring 41 is made of the same third metal film as the touch wiring 30 and the first connection wiring 40, and is arranged so as to overlap the source wiring 27 in a plan view. The source wiring 27 that overlaps the second connection wiring 41 is arranged so as to overlap the second partition opening 28A2. Note that in FIG. 6, the source wiring 27 that overlaps the second connection wiring 41 is illustrated so as to be adjacent to the second connection wiring 41 on the left side of FIG. 6. The second connection wiring 41 extends along the Y-axis direction, similar to the source wiring 27, the touch wiring 30, and the first connection wiring 40. The second connection wiring 41 is connected to a predetermined first connection wiring 40 via a third short-circuit wiring 44 described later. In other words, the second connection wiring 41 is indirectly connected to the touch electrode 29 via the third short-circuit wiring 44 and the first connection wiring 40. The formation range of the second connection wiring 41 in the Y-axis direction is limited to the same formation range of the first connection wiring 40 and the touch electrode 29 to be connected.

[0037] As described above, the first connection wiring 40 is connected to the touch electrode 29, so that the resistance distribution of the touch electrode 29 can be reduced. On the other hand, for example, if the first connection wiring 40 is not normally connected to the touch electrode 29, the connection resistance between the touch electrode 29 and the first connection wiring 40 increases. Therefore, the electric field from the source wiring 27 overlapping the first connection wiring 40 via the first interlayer insulating film 35 and the planarization film 36 may adversely affect the TFT 24 (other element) located near the first connection wiring 40 via the first connection wiring 40. In order to reduce the resistance distribution of the touch electrode 29, a method of increasing the number of connection points (second contact holes CH4) of the first connection wiring 40 to the touch electrode 29 may also be adopted. However, at the connection points of the first connection wiring 40 to the touch electrode 29, local recesses are generated on the inner surface of the array substrate 21 due to the second contact holes CH4 formed in communication with the first interlayer insulating film 35 and the planarization film 36. The concave portion easily disturbs the alignment of the liquid crystal molecules contained in the liquid crystal layer 22, and light leakage easily occurs, so that it is difficult to secure many connection points of the first connection wiring 40 to the touch electrode 29. In this embodiment, the number of connection points of the touch wiring 30 to the touch electrode 29 is set to be greater than the number of connection points of the first connection wiring 40 to the touch electrode 29. The reason for this is that a priority is given to ensuring the reliability of supplying the common potential signal and the touch signal transmitted by the touch wiring 30 to the touch electrode 29.

[0038] Therefore, in the array substrate 21 according to the present embodiment, as shown in FIG. 6, a first short-circuit wiring (third wiring) 42 that short-circuits a plurality of first connection wirings 40 is provided. The first short-circuit wiring 42 extends along the X-axis direction (second direction) that intersects with the extension direction (Y-axis direction) of the first connection wiring 40. The first short-circuit wiring 42 is arranged so as to overlap the touch electrode 29 to which the first connection wiring 40 to be short-circuited is to be connected in a plan view. The first short-circuit wiring 42 is arranged in the right region of the touch electrode 29 to which the first connection wiring 40 to be short-circuited is to be connected in FIG. 6, that is, in the arrangement region of the first connection wiring 40 to be short-circuited. The first short-circuit wiring 42 is connected to all the first connection wirings 40 (12 first connection wirings 40) arranged in the right region of the touch electrode 29 in FIG. 6. Therefore, the plurality of first connection wirings 40 arranged in the right region of the touch electrode 29 in FIG. 6 are short-circuited to each other by one first short-circuit wiring 42. The first short-circuit wiring 42 is arranged so as to be connected to the lower end of the plurality of first connection wirings 40 in FIG. 6. That is, the first short-circuit wiring 42 is arranged near the lower end of the touch electrode 29 in FIG. 6. The first short-circuit wiring 42 is arranged so as to overlap the gate wiring 26 in a plan view. Note that in FIG. 6, the first short-circuit wiring 42 overlapping the gate wiring 26 is illustrated so as to be adjacent to the gate wiring 26 on the lower side of FIG. 6. Note that in FIG. 6, only three gate wirings 26 overlapping the first short-circuit wiring 42 and a second short-circuit wiring 43, a third short-circuit wiring 44, and a fourth short-circuit wiring 45, which will be described later, are illustrated among the plurality of gate wirings 26. The first short-circuit wiring 42 is not connected to the driver 12.

[0039] As shown in FIG. 8, the first short-circuit wiring 42 is made of the same third metal film as the touch wiring 30 and the first connection wiring 40. Therefore, the first short-circuit wiring 42 is connected to the first connection wiring 40 to be connected by being directly connected to it. FIG. 8 shows a cross-sectional configuration of the array substrate 21 cut along the X-axis direction near the first short-circuit wiring 42 and the gate wiring 26. Between the first short-circuit wiring 42 made of the third metal film and the gate wiring 26 overlapping with the first short-circuit wiring 42, the gate insulating film 34, the first interlayer insulating film 35, and the planarizing film 36 are interposed to keep them in an insulated state. Between the first short-circuit wiring 42 made of the third metal film and the source wiring 27 intersecting with the first short-circuit wiring 42, the first interlayer insulating film 35 and the planarizing film 36 are interposed to keep them in an insulated state. A third interlayer insulating film 38 is interposed between the first short-circuit wiring 42 made of the third metal film and the touch electrode 29 overlapping the first short-circuit wiring 42, and they are kept in an insulated state.

[0040] Here, among the multiple source wirings 27 overlapping with the multiple first connection wirings 40 shown in FIG. 6, two predetermined source wirings 27 adjacent to each other with a gap (a gap of about the width dimension of one pixel electrode 25) in the X-axis direction are distinguished as a first source wiring (one first wiring) 27α and a second source wiring (the other first wiring) 27β. As shown in FIG. 6, the first source wiring 27α is one of the two source wirings 27 adjacent to each other with a gap in the X-axis direction. The second source wiring 27β is the other source wiring 27 adjacent to the one source wiring 27 in the X-axis direction among the two source wirings 27 described above. The driver 12 supplies a first image signal (first signal) to the first source wiring 27α of the two source wirings 27α and 27β, and supplies a second image signal (second signal) having a polarity inverted from that of the first image signal to the second source wiring 27β. In FIG. 6, the positive and negative polarities of the image signals supplied to the illustrated source wirings 27 are shown as signs of "+" and "-" below each source wiring 27. Specifically, when the polarity of the first image signal supplied to the first source wiring 27α is "+", the polarity of the second image signal supplied to the second source wiring 27β is "-". Conversely, when the polarity of the first image signal supplied to the first source wiring 27α is "-", the polarity of the second image signal supplied to the second source wiring 27β is "+". In other words, the driver 12 performs inversion driving to periodically invert the polarities of the image signals supplied to the odd-numbered source wirings 27 and the even-numbered source wirings 27 counting from one end side in the X-axis direction among the multiple source wirings 27 arranged along the X-axis direction.

[0041] As in the present embodiment, the multiple first connection wirings 40 arranged in the right region of the touch electrode 29 in FIG. 6 are short-circuited to each other by one first short-circuit wiring 42, so that the connection resistance between the multiple first connection wirings 40 and the touch electrode 29 can be reduced. Moreover, the first image signal and the second image signal, which are inverted in polarity to each other, are respectively supplied from the driver 12 to the two source wirings 27α, 27β that overlap the two first connection wirings 40 included in the multiple first connection wirings 40 via the first interlayer insulating film 35 and the planarization film 36, so that the electric field acting on the overlapping first connection wiring 40 from the first source wiring 27α to which the first image signal is supplied and the electric field acting on the overlapping first connection wiring 40 from the second source wiring 27β to which the second image signal is supplied can be offset. By canceling out the electric fields acting on the two first connection wirings 40 overlapping the two source wirings 27α, 27β, a difference is unlikely to occur in the electric field of the back channel that may occur in each of the semiconductor portions 24D of the two TFTs 24 that are partially overlapping the two first connection wirings 40. This makes it difficult for the transistor characteristics of the two TFTs 24 to vary (shift) over time, thereby suppressing deterioration in display quality caused by the variation in the transistor characteristics.

[0042] As shown in FIG. 6, the array substrate 21 is provided with a second short-circuiting line (fifth line) 43 that short-circuits two adjacent touch wirings 30 with a gap (a gap of about the width dimension of one pixel electrode 25) in the X-axis direction. The second short-circuiting line 43 extends along the X-axis direction intersecting with the extension direction (Y-axis direction) of the touch wirings 30. The second short-circuiting line 43 is connected to two touch wirings 30 connected to the same touch electrode 29. The second short-circuiting line 43 is arranged so that the touch wiring 30 to be short-circuited overlaps the touch electrode 29 to be connected in a plan view. The second short-circuiting line 43 is arranged in the left region of the touch electrode 29 overlapping the touch wiring 30 to be short-circuited in FIG. 6, that is, in the arrangement region of the touch wiring 30 to be short-circuited. Two second short-circuiting lines 43 are arranged so as to be connected to two of the four touch wirings 30 arranged in the left region of the touch electrode 29 in FIG. 6. Further, the second short-circuit wiring 43 is arranged so as to overlap with the gate wiring 26 in a plan view. Note that in Fig. 6, the second short-circuit wiring 43 overlapping with the gate wiring 26 is illustrated so as to be adjacent to the gate wiring 26 on the lower side of Fig. 6. The second short-circuit wiring 43 is indirectly connected to the driver 12 via the touch wiring 30.

[0043] The second short-circuit wiring 43 is made of the same third metal film as the touch wiring 30, the first connection wiring 40, and the first short-circuit wiring 42 (see FIG. 8). Therefore, the second short-circuit wiring 43 is connected to the touch wiring 30 to be connected by being directly connected to it. That is, the relationship between the second short-circuit wiring 43 and the touch wiring 30 is the same as the relationship between the first short-circuit wiring 42 and the first connection wiring 40. The relationship between the second short-circuit wiring 43 and the gate wiring 26, the source wiring 27, and the touch electrode 29 is the same as the relationship between the first short-circuit wiring 42 and the gate wiring 26, the source wiring 27, and the touch electrode 29. Between the second short-circuit wiring 43 made of the third metal film and the gate wiring 26 overlapping the second short-circuit wiring 43, the gate insulating film 34, the first interlayer insulating film 35, and the planarization film 36 are interposed to maintain an insulating state. A first interlayer insulating film 35 and a planarizing film 36 are interposed between the second short-circuit wiring 43 made of the third metal film and the source wiring 27 intersecting the second short-circuit wiring 43, and are kept in an insulated state. A third interlayer insulating film 38 is interposed between the second short-circuit wiring 43 made of the third metal film and the touch electrode 29 overlapping the second short-circuit wiring 43, and are kept in an insulated state.

[0044] Here, among the multiple source wirings 27 that are overlapped with the multiple touch wirings 30 shown in FIG. 6, two predetermined source wirings 27 that are connected to the same touch electrode 29 and overlap with two touch wirings 30 that are connected to the same second short-circuit wiring 43 are distinguished as a third source wiring (one first wiring) 27γ and a fourth source wiring (the other first wiring) 27δ. As shown in FIG. 6, the third source wiring 27γ and the fourth source wiring 27δ are arranged adjacent to each other with a gap (a gap of about the width dimension of one pixel electrode 25) in the X-axis direction. The third source wiring 27γ is one of the two source wirings 27 that are adjacent to each other with a gap in the X-axis direction. The fourth source wiring 27δ is the other source wiring 27 that is adjacent to one of the two source wirings 27 in the X-axis direction. The driver 12 supplies a third image signal (third signal) to the third source line 27γ of the two source lines 27γ and 27δ, and supplies a fourth image signal (fourth signal) whose polarity is inverted from that of the third image signal to the fourth source line 27δ. Specifically, when the polarity of the third image signal supplied to the third source line 27γ is set to "+", the polarity of the fourth image signal supplied to the fourth source line 27δ is set to "-". Conversely, when the polarity of the third image signal supplied to the third source line 27γ is set to "-", the polarity of the fourth image signal supplied to the fourth source line 27δ is set to "+".

[0045] As in the present embodiment, since the two touch wirings 30 are short-circuited to each other by one second short-circuit wiring 43, it is possible to reduce the connection resistance between the two touch wirings 30 and the touch electrode 29. Moreover, since the driver 12 supplies the third image signal and the fourth image signal, which are inverted in polarity to each other, to the two source wirings 27γ, 27δ that overlap the two touch wirings 30 included in the plurality of touch wirings 30 via the first interlayer insulating film 35 and the planarization film 36, respectively, it is possible to cancel out the electric field acting on the overlapping touch wiring 30 from the third source wiring 27γ to which the third image signal is supplied and the electric field acting on the overlapping touch wiring 30 from the fourth source wiring 27δ to which the fourth image signal is supplied. By canceling out the electric fields acting on the two touch wirings 30 overlapping the two source wirings 27γ, 27δ, a difference in the electric field of the back channel that may occur in each of the semiconductor parts 24D of the two TFTs 24 that are partially overlapping the two touch wirings 30 is unlikely to occur. As a result, the transistor characteristics of the two TFTs 24 described above are unlikely to fluctuate (shift) over time, so that a decrease in display quality due to the fluctuation of the transistor characteristics can be suppressed. In this way, the electric field from the source wirings 27α to 27δ that overlap the first connection wiring 40 and the touch wiring 30, respectively, is unlikely to fluctuate the transistor characteristics of each TFT 24 via the first connection wiring 40 and the touch wiring 30.

[0046] Further, as shown in FIG. 6, the array substrate 21 is provided with a third short-circuit wiring 44 that shorts two specific first connection wirings 40 out of the plurality of first connection wirings 40. Specifically, the third short-circuit wiring 44 is connected to two first connection wirings 40 located at the right end in FIG. 6 out of the touch electrodes 29 to which the plurality of first connection wirings 40 are to be connected. The third short-circuit wiring 44 extends along the X-axis direction. A plurality of third short-circuit wirings 44 (three in FIG. 6) are arranged at positions spaced apart in the Y-axis direction. The third short-circuit wiring 44 is arranged so as to overlap the gate wiring 26 in a plan view. The third short-circuit wiring 44 is not connected to the driver 12. The third short-circuit wiring 44 is made of the same third metal film as the touch wiring 30, the first connection wiring 40, the first short-circuit wiring 42, and the second short-circuit wiring 43 (see FIG. 8). Therefore, the second short-circuit wiring 43 is connected by being directly connected to the first connection wiring 40 to be connected. The relationship between the third short-circuit wiring 44 and the first connection wiring 40 is similar to the relationship between the first short-circuit wiring 42 and the first connection wiring 40. In addition, the relationship between the third short-circuit wiring 44 and the gate wiring 26, the source wiring 27, and the touch electrode 29 is similar to the relationship between the first short-circuit wiring 42 and the gate wiring 26, the source wiring 27, and the touch electrode 29.

[0047] 6, the array substrate 21 is provided with a fourth short-circuit wiring 45 that shorts a specific first connection wiring 40 and a second connection wiring 41 among the multiple first connection wirings 40. Specifically, the fourth short-circuit wiring 45 is connected to one first connection wiring 40 located at the left end of FIG. 6 among the touch electrodes 29 to which the multiple first connection wirings 40 are to be connected, and to a second connection wiring 41 adjacent to the first connection wiring 40 in the X-axis direction. The fourth short-circuit wiring 45 extends along the X-axis direction. A plurality of the fourth short-circuit wirings 45 (three in FIG. 6) are arranged at positions spaced apart from each other in the Y-axis direction. The fourth short-circuit wiring 45 is arranged so as to overlap the gate wiring 26 in a plan view. The fourth short-circuit wiring 45 is not connected to the driver 12. The fourth short-circuit wiring 45 is made of the same third metal film as the touch wiring 30, the first connection wiring 40, the first short-circuit wiring 42, the second short-circuit wiring 43, and the third short-circuit wiring 44 (see FIG. 8). Therefore, the fourth short-circuit wiring 45 is connected to the first connection wiring 40 and the second connection wiring 41 to be connected by being directly connected to them. The relationship between the fourth short-circuit wiring 45 and the first connection wiring 40 and the second connection wiring 41 is the same as the relationship between the first short-circuit wiring 42 and the first connection wiring 40. In addition, the relationship between the fourth short-circuit wiring 45 and the gate wiring 26, the source wiring 27, and the touch electrode 29 is the same as the relationship between the first short-circuit wiring 42 and the gate wiring 26, the source wiring 27, and the touch electrode 29.

[0048] As described above, the array substrate (wiring substrate) 21 of the present embodiment includes the source wiring (first wiring) 27 extending along the first direction, the first connection wiring (second wiring) 40 extending along the first direction, the touch electrode (first electrode) 29 connected to the first connection wiring 40, the first short-circuit wiring (third wiring) 42 extending along the second direction intersecting the first direction, and the driver (signal supply unit) 12 connected to the source wiring 27 and not connected to the first connection wiring 40 and the first short-circuit wiring 42. Two source wirings 27 are arranged at an interval in the second direction, and the first connection wiring (second wiring) 40 is connected to the first short-circuit wiring 42. The wiring 40 is arranged in two overlapping positions spaced apart in the second direction on the two source wirings 27 via an insulating film, a first interlayer insulating film 35 and a planarizing film 36, and the driver 12 supplies a first image signal (first signal) to the first source wiring 27α, which is one of the two source wirings 27, and supplies a second image signal (second signal) having an inverted polarity to the first image signal to the second source wiring 27β, which is the other of the two source wirings 27. The first short-circuit wiring 42 is connected to the two first connection wirings 40.

[0049] Since two first connection wirings 40 are connected to the touch electrode 29, the resistance distribution of the touch electrode 29 can be reduced. On the other hand, for example, if the first connection wirings 40 are not normally connected to the touch electrode 29, the connection resistance between the touch electrode 29 and the first connection wirings 40 increases. For this reason, the electric field from the source wiring 27 overlapping the first connection wiring 40 via the first interlayer insulating film 35 and the planarizing film 36, which are insulating films, may adversely affect other elements present near the first connection wiring 40 via the first connection wiring 40.

[0050] In this respect, since the two first connection wirings 40 are connected by the first short-circuit wiring 42 extending along the second direction, the connection resistance between the two first connection wirings 40 and the touch electrode 29 can be reduced. Moreover, the first image signal and the second image signal, which are inverted in polarity, are respectively supplied from the driver 12 to the two source wirings 27 overlapping the two first connection wirings 40 via the first interlayer insulating film 35 and the planarizing film 36, which are insulating films. Therefore, the electric field acting on the overlapping first connection wiring 40 from the first source wiring 27α, which is one of the source wirings 27 to which the first image signal is supplied, and the electric field acting on the overlapping first connection wiring 40 from the second source wiring 27β, which is the other source wiring 27 to which the second image signal is supplied, can be offset. As a result, it is possible to prevent a situation in which the electric field from the source wiring 27 adversely affects other elements present near the first connection wiring 40 via the first connection wiring 40.

[0051] The display device further includes a touch wiring (fourth wiring) 30 extending along the first direction and connected to the touch electrode 29, and a second short-circuit wiring (fifth wiring) 43 extending along the second direction. The touch wirings 30 are arranged in pairs at intervals in the second direction. The source wirings 27 are arranged in pairs at intervals in the second direction, overlapping the two touch wirings 30 via a first interlayer insulating film 35 and a planarizing film 36, which are insulating films. The driver 12 connects the two touch wirings 30 to a third short-circuit wiring 43. A third image signal (fourth signal) is supplied to the third source wiring 27γ, which is one of the two source wirings 27 overlapping the two touch wirings 30, and a fourth image signal (fifth signal) having a polarity inverted from that of the third image signal is supplied to the fourth source wiring 27δ, which is the other of the two source wirings 27 overlapping the two touch wirings 30, and the second short-circuit wiring 43 is connected to the two touch wirings 30. The common potential signal and the touch signal, which are the third signal output from the driver 12, are supplied to the touch electrode 29 via the two touch wirings 30. The two touch wirings 30 are connected by the second short-circuit wiring 43 extending along the second direction, so that the connection resistance between the two touch wirings 30 and the touch electrode 29 can be reduced. Moreover, the driver 12 supplies the third image signal and the fourth image signal, which are inverse in polarity to each other, to the two source wirings 27 that overlap the two touch wirings 30 via the first interlayer insulating film 35 and the planarizing film 36, respectively, so that the electric field acting on the overlapping touch wiring 30 from the third source wiring 27γ, which is one of the source wirings 27 to which the third image signal is supplied, and the electric field acting on the overlapping touch wiring 30 from the fourth source wiring 27δ, which is the other source wiring 27 to which the fourth image signal is supplied, can be offset. As a result, it is possible to prevent a situation in which the electric field from the source wiring 27 adversely affects other elements present near the touch wiring 30 via the touch wiring 30. In this way, the adverse effects of the electric field from the source wiring 27 that overlaps the first connection wiring 40 and the touch wiring 30 can be suitably reduced.

[0052] The pixel electrode (second electrode) 25 and the TFT (switching element) 24 connected to the source wiring 27 and the pixel electrode 25 are also included, and the first connection wiring 40 is arranged so that a part of it overlaps with at least a part of the TFT 24 via a first interlayer insulating film 35 and a planarizing film 36, which are insulating films. A first image signal output from the driver 12 is supplied to the pixel electrode 25 to be connected via a first source wiring 27α, which is one of the two source wirings 27, and a TFT 24 connected to the first source wiring 27α, which is one of the source wirings 27. A second image signal output from the driver 12 is supplied to the pixel electrode 25 to be connected via a second source wiring 27β, which is the other of the two source wirings 27, and a TFT 24 connected to the second source wiring 27β, which is the other of the two source wirings 27. By connecting the two first connection wirings 40 to the first short-circuit wiring 42, it is possible to prevent a situation in which an electric field from the source wiring 27 adversely affects the TFT 24 that overlaps with the first connection wiring 40 via the first connection wiring 40.

[0053] Moreover, the liquid crystal panel (display device) 11 of this embodiment includes the above-described array substrate 21 and a counter substrate 20 disposed opposite to and spaced apart from the array substrate 21. The liquid crystal panel 11 configured in this manner can reduce the occurrence of a situation in which the display quality is degraded due to an electric field from the source wiring 27.

[0054] <Embodiment 2> A second embodiment will be described with reference to Fig. 9. In this second embodiment, a case where the configuration of the first short-circuit wiring 142 is changed is shown. Note that a duplicated description of the structure, action, and effects similar to those of the first embodiment will be omitted.

[0055] As shown in Fig. 9, the first short-circuit wiring 142 according to the present embodiment is arranged so as to be connected to the upper end portions of all the first connection wirings 140 arranged in the right region of the touch electrode 129 in Fig. 9, as shown in Fig. 6. In other words, the first short-circuit wiring 142 is arranged near the upper end portion of the touch electrode 129 in Fig. 6.

[0056] <Embodiment 3> A third embodiment will be described with reference to Fig. 10. In this third embodiment, a configuration of the first short-circuit wiring 242 is changed from that of the first embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0057] As shown in Fig. 10, the first short-circuit wiring 242 according to the present embodiment is arranged so as to be connected to the center, in the up-down direction of Fig. 6, of all the first connection wirings 240 arranged in the right region of the touch electrode 229 in Fig. 10. In other words, the first short-circuit wiring 242 is arranged near the center, in the up-down direction of Fig. 6, of the touch electrode 229.

[0058] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 11. In this fourth embodiment, a configuration of the first short-circuit wiring 342 is changed from that of the first embodiment. Note that a duplicated description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0059] As shown in FIG. 11, a plurality of first short-circuit wirings 342 according to the present embodiment (three in FIG. 11) are arranged at positions spaced apart in the Y-axis direction. Specifically, the plurality of first short-circuit wirings 342 include a first short-circuit wiring 342 connected to a lower end of the first connection wiring 340 in FIG. 11, a first short-circuit wiring 342 connected to an upper end of the first connection wiring 340 in FIG. 11, and a first short-circuit wiring 342 connected to a center of the first connection wiring 340 in the up-down direction in FIG. 11. All of the plurality of first short-circuit wirings 342 are respectively connected to all of the first connection wirings 340 arranged in the right region of the touch electrode 329 in FIG. 11. In this way, by connecting each first connection wiring 340 to each of the plurality of first short-circuit wirings 342, the connection resistance between each first connection wiring 340 and the touch electrode 329 can be further reduced.

[0060] As described above, according to the present embodiment, the first short-circuit wirings 342 are arranged at positions spaced apart in the first direction, and the multiple first short-circuit wirings 342 are connected to the two first connection wirings 340, respectively. In this manner, the two first connection wirings 340 are connected to the multiple first short-circuit wirings 342, respectively, so that the connection resistance between the two first connection wirings 340 and the touch electrode 329 can be further reduced.

[0061] <Embodiment 5> A fifth embodiment will be described with reference to Fig. 12. In the fifth embodiment, the configuration of the first short-circuit wiring 442 is changed from that of the first embodiment. Note that a duplicated description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0062] As shown in FIG. 12, the first short-circuit wirings 442 according to this embodiment are arranged at intervals in the X-axis direction so that each of them is connected to two first connection wirings 440. The length dimension of the first short-circuit wirings 442 in the X-axis direction is approximately the interval between two adjacent first connection wirings 440 (source wirings 427) in the X-axis direction, and is also approximately the width dimension of one pixel electrode 25 (see FIG. 4). The interval between two adjacent first short-circuit wirings 442 in the X-axis direction is approximately the width dimension of one pixel electrode 25. Image signals with inverted polarity are supplied from the driver 412 to the two source wirings 427 that are overlapped with the two first connection wirings 440 shorted by the first short-circuit wirings 442. Therefore, in this embodiment as well, as in the first embodiment, the electric field acting on each overlapping first connection wiring 440 from each source wiring 427 can be offset. 12. Moreover, each of the multiple first short-circuit wirings 442 is connected to the center of the first connection wiring 440 in the up-down direction in FIG.

[0063] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0064] (1) The connection positions in the Y-axis direction of the first short-circuit wirings 42, 142, 242, 342, 442 to the first connection wirings 40, 140, 240, 340, 440 can be changed as appropriate to positions other than those shown in the drawings.

[0065] (2) In the configuration described in the fourth embodiment, the number of first short-circuit wirings 342 can be changed to two or four or more.

[0066] (3) The number of first connection wirings 40, 140, 240, 340, 440 shorted by the first short-circuit wirings 42, 142, 242, 342, 442 can be changed as appropriate to a number other than those shown in the drawings.

[0067] (4) The number of touch wirings 30 short-circuited by the second short-circuiting wiring 43 can be changed as appropriate to a number other than those shown in the drawings.

[0068] (5) The number of the third short-circuit wirings 44 and the fourth short-circuit wirings 45 may be changed as appropriate to a number other than that shown in the figure.

[0069] (6) The third short-circuit wiring 44 may be omitted.

[0070] (7) It is also possible to omit the fourth short-circuit wiring 45. In that case, a configuration in which the second connection wiring 41 is connected to the touch electrodes 29, 129, 229, and 329 can also be adopted.

[0071] (8) The short-circuit lines 42 to 45, 142, 242, 342, and 442 may be arranged so as not to overlap with the gate line 26.

[0072] (9) The number of connection points of the touch wiring 30 to the touch electrodes 29, 129, 229, and 329 can be changed as appropriate to other numbers than those shown in the drawings.

[0073] (10) The number of connection points of the first connection wirings 40, 140, 240, 340, 440 to the touch electrodes 29, 129, 229, 329 can be changed as appropriate to be different from the numbers shown in the drawings.

[0074] (11) The source wiring 27, 427, the touch wiring 30, and the first connection wiring 40, 140, 240, 340, 440 may be configured so as not to be partially widened.

[0075] (12) The relationship of which parts of the TFT 24 overlap with the touch wiring 30 can be changed as appropriate to other than that shown in the drawings. Similarly, the relationship of which parts of the TFT 24 overlap with the first connection wirings 40, 140, 240, 340, and 440 can be changed as appropriate to other than that shown in the drawings.

[0076] (13) In the TFT 24, the intermediate electrode 39 located between the drain electrode 24C and the pixel electrode 25 can be omitted.

[0077] (14) It is also possible to omit the circuit unit 14. In that case, a gate driver having the same function as the circuit unit 14 may be attached to the array substrate 21. Also, it is possible to provide the circuit unit 14 only on one side of the array substrate 21.

[0078] (15) The material of the semiconductor film that constitutes the semiconductor portion 24D may be polysilicon (LTPS), amorphous silicon, or the like.

[0079] (16) The structure of the TFT 24 may be a top gate type or a double gate type other than a bottom gate type.

[0080] (17) Of the pixel electrode 25 and the common electrode 28, the "upper layer electrode" that is the electrode located on the upper layer side may be the common electrode 28, and the "lower layer electrode" that is the electrode located on the lower layer side may be the pixel electrode 25. In this case, a slit is provided in the common electrode 28 that is the "upper layer electrode."

[0081] (18) The touch panel pattern may be a mutual capacitance type other than a self-capacitance type.

[0082] (19) The liquid crystal panel 11 may not have a touch panel pattern (touch panel function). In this case, the common electrode (first electrode) 28 has a non-divided structure, and the touch electrodes 29, 129, 229, and 329 are not formed. Also, instead of the touch wiring 30, a common wiring (third wiring) that is connected to the common electrode 28 and supplies a common potential signal (third signal) is provided using a third metal film.

[0083] (20) The color filter 31 may be provided on the array substrate 21. In other words, the liquid crystal panel 11 may have a COA (Color Filter On Array) structure.

[0084] (21) The number of colors of the color filter 31 may be four or more. The additional color filter 31 may be a yellow color filter that exhibits yellow color, a transparent color filter that transmits light in the entire wavelength range, or the like.

[0085] (22) The display mode of the liquid crystal panel 11 may be VA mode, IPS mode, or the like other than FFS mode.

[0086] (23) The liquid crystal panel 11 may be a reflective or semi-transmissive type instead of a transmissive type. If the liquid crystal panel 11 is a reflective type, the backlight device can be omitted.

[0087] (24) A display panel other than the liquid crystal panel 11 (such as an organic electroluminescence (EL) display panel) may be used. [Explanation of symbols]

[0088] 11... liquid crystal panel (display device), 12,412... driver (signal supply unit), 20... opposing substrate, 21... array substrate (wiring substrate), 24... TFT (switching element), 25... pixel electrode (second electrode), 27,427... source wiring (first wiring), 27α... first source wiring (one of the first wirings), 27β... second source wiring (the other of the first wirings), 27γ... third source wiring (one of the first wirings), 27δ...fourth source wiring (the other first wiring), 29, 129, 229, 329...touch electrode (first electrode), 30...touch wiring (fourth wiring), 35...first interlayer insulating film (insulating film), 36...planarization film (insulating film), 40, 140, 240, 340, 440...first connection wiring (second wiring), 42, 142, 242, 342, 442...first short-circuit wiring (third wiring), 43...second short-circuit wiring (fifth wiring)

Claims

1. A first wiring extending along a first direction; A second wiring extending along the first direction; A first electrode connected to the second wiring; a third wiring extending along a second direction intersecting the first direction; a signal supply unit connected to the first wiring and not connected to the second wiring and the third wiring; The first wiring is arranged in two pieces at an interval in the second direction, the second wirings are arranged in pairs at intervals in the second direction, overlapping the two first wirings with an insulating film interposed therebetween; the signal supply unit supplies a first signal to one of the two first wirings and a second signal having a polarity inverted from that of the first signal to the other of the two first wirings; The third wiring is connected to two of the second wirings.

2. a fourth wiring extending along the first direction and connected to the first electrode; a fifth wiring extending along the second direction, The fourth wiring is provided in two pieces with a gap therebetween in the second direction, the first wirings are arranged in pairs at intervals in the second direction and overlap two of the fourth wirings via an insulating film; the signal supply unit supplies a third signal to two of the fourth wirings, a fourth signal to one of the two first wirings overlapping with the two fourth wirings, and a fifth signal having a polarity inverted from that of the fourth signal to the other of the two first wirings overlapping with the two fourth wirings, The wiring board according to claim 1 , wherein the fifth wiring is connected to two of the fourth wirings.

3. A second electrode; a switching element connected to the first wiring and the second electrode, 3. The wiring board according to claim 1, wherein a portion of the second wiring is arranged to overlap at least a portion of the switching element via an insulating film.

4. the third wiring is arranged in a plurality of positions spaced apart from one another in the first direction; 3. The wiring board according to claim 1, wherein the third wirings are connected to two of the second wirings, respectively.

5. The wiring board according to claim 1 or 2, a counter substrate disposed opposite the wiring substrate with a gap therebetween.

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