Semiconductor device and manufacturing method thereof

Abstract

To cause a solder not to reach a triple point formed by a first electrode, a protective film, and a plating layer.SOLUTION: A semiconductor device includes a semiconductor substrate having an upper surface, a first electrode provided above the upper surface of the semiconductor substrate, a protective film provided above the first electrode, a plating layer provided above the first electrode and having a non-overlapping portion that does not overlap with the protective film in a top view, and a nitride film provided continuously from between the protective film and the first electrode to between the non-overlapping portion and the first electrode, and the thickness of the plating layer above the nitride film is greater than the thickness of the nitride film.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, a semiconductor device is known in which an intermediate layer is provided between an aluminum electrode and an organic protective film (see Patent Document 1). Also, a semiconductor device is known in which there is no triple point where the ends of the protective film, the plating layer, and the emitter electrode overlap (see Patent Document 2). Patent Document 1: WO2017 / 103978 Patent Document 2: JP2017-168659 Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable that the solder does not reach the triple point formed by the first electrode, the protective film, and the plating layer. [Means for solving the problem]

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device including a semiconductor substrate having an upper surface. The semiconductor device may include a first electrode provided above the upper surface of the semiconductor substrate. Any of the semiconductor devices may include a protective film provided above the first electrode. Any of the semiconductor devices may include a plating layer provided above the first electrode and having a non-overlapping portion that does not overlap with the protective film in a top view. Any of the semiconductor devices may include a nitride film provided continuously from between the protective film and the first electrode to between the non-overlapping portion and the first electrode. In any of the semiconductor devices, the thickness of the plating layer above the nitride film may be greater than the thickness of the nitride film.

[0005] In any of the above semiconductor devices, the nitride film may be in contact with the plating layer.

[0006] In any of the above semiconductor devices, the nitride film may be in contact with the first electrode.

[0007] In any of the above semiconductor devices, the protective film and the plating layer may be in contact with each other.

[0008] In any of the above semiconductor devices, the protective film and the plating layer may be spaced apart.

[0009] In a top view of any of the above semiconductor devices, a portion where the nitride film and the plating layer overlap may have a first length in a direction perpendicular to an end side of the plating layer of 1 μm or more.

[0010] In any of the above semiconductor devices, the first length may be 2 μm or more when viewed from above.

[0011] In any of the above semiconductor devices, the first length may be 4 μm or less when viewed from above.

[0012] In any of the above semiconductor devices, a portion of the nitride film that protrudes toward the plating layer side beyond the protective film may be 3 μm or more and 7 μm or less.

[0013] In any of the above semiconductor devices, the plating layer may have a thickness greater than a thickness of the protective film.

[0014] Any of the above semiconductor devices may further include a second plating layer provided between the protective film and the nitride film and having a lower density than the plating layer. In any of the above semiconductor devices, a length of the second plating layer in a direction connecting the protective film and the plating layer in a plane parallel to a top surface of the semiconductor substrate may be equal to or less than half the thickness of the plating layer.

[0015] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a semiconductor substrate having a first electrode above an upper surface thereof. In the above method for manufacturing a semiconductor device, a nitride film may be formed above a portion of the first electrode. In any of the above methods for manufacturing a semiconductor device, a protective film may be formed above the portion of the nitride film. In any of the above methods for manufacturing a semiconductor device, the nitride film and the protective film may be annealed. In any of the above methods for manufacturing a semiconductor device, after the annealing, a plating layer may be formed above the first electrode not covered with the nitride film and above the portion of the nitride film.

[0016] In any of the above methods for manufacturing a semiconductor device, the annealing temperature may be 300° C. or higher and 400° C. or lower.

[0017] In any of the above methods for manufacturing a semiconductor device, the annealing treatment may be performed for a period of time ranging from 30 minutes to 1 hour. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a diagram showing an example of a-a cross section in FIG. [Figure 2B] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. [Figure 3A] FIG. 2 is a diagram showing an example of aa cross section in a comparative example. [Figure 3B] FIG. 11 is a diagram showing another example of the aa cross section in the comparative example. [Figure 4] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. [Diagram 5] 2A to 2C are diagrams illustrating a part of the manufacturing process of the semiconductor device 100. [Figure 6] 1. FIG. 4 is a diagram showing another example of the a-a cross section in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0021] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0022] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0023] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0024] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0025] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type.

[0026] 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10, a protective film 70, a plating layer 72, and a nitride film 76. The semiconductor device 100 may further include a plating layer 73 and a nitride film 77. The semiconductor substrate 10 has an upper surface and a lower surface. FIG. 1 shows a view of the semiconductor device 100 viewed from above the upper surface of the semiconductor substrate 10, which is referred to as a top view in this specification.

[0027] The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 102 when viewed from above. The semiconductor substrate 10 of this example has two pairs of edges 102 facing each other when viewed from above. In FIG. 1, the X-axis and the Y-axis are parallel to either of the edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0028] The semiconductor substrate 10 is provided with at least one of a transistor section or a diode section, which will be described later. A first electrode, which will be described later, is provided above the upper surface of the semiconductor substrate 10. The first electrode may be an Al-Si alloy, for example. The first electrode is an electrode through which a main current flows, such as an emitter electrode or a source electrode. In this example, the protective film 70, the plating layer 72, and the nitride film 76 are provided above the first electrode. Solder is provided above the protective film 70, the plating layer 72, and the nitride film 76, and is connected to an external power supply or the like via a lead frame bonded to the solder, but is omitted in FIG. 1.

[0029] A control electrode such as a gate pad may be provided above the upper surface of the semiconductor substrate 10. The protective film 70 of this example is also provided above the control electrode. The plating layer 73 and the nitride film 77 are provided above the control electrode. The arrangement and structure of the protective film 70, the plating layer 73, and the nitride film 77 above the control electrode are similar to the arrangement and structure of the protective film 70, the plating layer 72, and the nitride film 76 above the first electrode. In this specification, the arrangement and structure of the protective film 70, the plating layer 72, and the nitride film 76 above the first electrode will be described, and the arrangement and structure of the protective film 70, the plating layer 73, and the nitride film 77 above the control electrode will be omitted. The nitride film 77 may be connected to the nitride film 76. That is, the nitride film 77 may be a part of the nitride film 76.

[0030] Electrodes other than the first electrode and the control electrode may be further provided above the semiconductor substrate 10. For each electrode above the semiconductor substrate 10, a structure similar to the protective film 70, the plating layer 72, and the nitride film 76 may be provided.

[0031] The protective film 70 is provided from the edge 102 of the semiconductor substrate 10 toward the inside of the semiconductor substrate 10 in a top view. In FIG. 1, the portion where the protective film 70 is provided is hatched. The protective film 70 is an insulating organic film, and is, for example, polyimide. An opening is provided inside the protective film 70 above the first electrode. A plating layer 72 and a nitride film 76 are provided above the first electrode in the opening, and are exposed upward from the opening of the protective film 70.

[0032] The plating layer 72 is provided on the inside of the semiconductor substrate 10 relative to the protective film 70. That is, the plating layer 72 is provided in an opening of the protective film 70. However, the protective film 70 and the plating layer 72 may overlap. A portion that does not overlap with the protective film 70 in a top view is referred to as a non-overlapping portion. That is, the plating layer 72 has a non-overlapping portion. The plating layer 72 is electrically connected to the first electrode. The plating layer 72 may be nickel, or may have a structure in which gold for oxidation prevention is laminated on nickel.

[0033] The nitride film 76 is provided continuously from between the protective film 70 and the first electrode to between the non-overlapping portion of the plating layer 72 and the first electrode. The nitride film 76 may overlap the entire protective film 70. The nitride film 76 in this example has a portion that does not overlap with the protective film 70. The nitride film 76 may be provided over a range larger than the protective film 70 when viewed from above. Since the protective film 70 and the plating layer 72 in this example do not overlap, the nitride film 76 is exposed upward from between the protective film 70 and the plating layer 72. The nitride film 76 may be silicon nitride, which has good adhesion to Al-Si.

[0034] Fig. 2A is a diagram showing an example of the aa cross section in Fig. 1. The aa cross section in this example is an XZ cross section passing through the semiconductor substrate 10, the emitter electrode 52, the collector electrode 24, the interlayer insulating film 38, the protective film 70, the plating layer 72, and the nitride film 76. The semiconductor device 100 in this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the collector electrode 24, the protective film 70, the plating layer 72, and the nitride film 76 in this cross section.

[0035] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The semiconductor substrate 10 in this example will be described as an RC-IGBT having a transistor portion 90 and a diode portion 80, but is not limited thereto. The transistor portion 90 may be a MOSFET. The semiconductor substrate 10 may have only the transistor portion 90, or may have only the diode portion 80. The aa cross section may be a cross section in which a pad portion, such as a gate pad for applying a gate voltage to a gate trench portion described later, is formed.

[0036] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with a contact hole 54. The inside of the contact hole 54 is filled with a contact plug 56 made of tungsten or the like.

[0037] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 via a contact plug 56. The emitter electrode 52 is an example of a first electrode. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0038] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in each of the transistor section 90 and the diode section 80.

[0039] Each of the transistor section 90 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction (X-axis direction). In the transistor section 90 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0040] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided on the upper surface 21 of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench portion. In this example, the transistor portion 90 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, when the term "mesa portion" is simply used, it refers to each of the mesa portion 60 and the mesa portion 61.

[0041] In the mesa portion 60 of the transistor portion 90, an N+ type emitter region 12, a P+ type contact region 15, and a P type base region 14 are provided on the upper surface 21 side of the semiconductor substrate 10. An N type drift region 18 is provided below the base region 14. An N+ type accumulation region 16 is provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0042] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10, and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0043] The contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10 at a position closer to the center of the mesa portion 60 than the emitter region 12. The contact region 15 may be provided deeper than the emitter region 12.

[0044] The base region 14 is provided below the emitter region 12 and the contact region 15. The base region 14 is provided in contact with the emitter region 12 and the contact region 15. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0045] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0046] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0047] In each of the transistor section 90 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0048] In the transistor portion 90, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0049] In the diode section 80, an N+ type cathode region 82 is provided under the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. The elements serving as the donor and acceptor of each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this example, the boundary between the diode section 80 and the transistor section 90 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0050] Each trench portion penetrates from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doped regions to reach the drift region 18. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the trench portion is formed and then the doped region is formed between the trench portions is also included in the case where the trench portion penetrates the doped region.

[0051] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0052] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring in another cross section. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0053] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 may be electrically connected to the emitter electrode 52 in another cross section. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0054] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0055] A protective film 70, a plating layer 72, and a nitride film 76 are provided above the emitter electrode 52. Solder is formed above the plating layer 72, but is omitted in FIG. 2A. Solder may also be formed above the protective film 70 and the nitride film 76. The plating layer 72 has a non-overlapping portion 74 that does not overlap with the protective film 70 in the depth direction (Z-axis direction). In this example, the protective film 70 and the plating layer 72 are separated from each other, so the entire plating layer 72 becomes the non-overlapping portion 74.

[0056] The nitride film 76 is provided between the protective film 70 and the emitter electrode 52. In this example, the nitride film 76 is in contact with the emitter electrode 52. The nitride film 76 is provided continuously from between the protective film 70 and the emitter electrode 52 to between the non-overlapping portion 74 of the plating layer 72 and the emitter electrode 52. By providing the nitride film 76, it is possible to prevent solder from reaching a triple point of the emitter electrode 52, the protective film 70, and the plating layer 72, which will be described later.

[0057] The thickness of the nitride film 76 in the depth direction is defined as t1. The thickness t1 of the nitride film 76 may be the average value of the thickness of the entire nitride film 76, or may be the average value of the thickness of the portion of the nitride film 76 that overlaps with the protective film 70. The thickness of the plating layer 72 located above the nitride film 76 in the depth direction is defined as t2. The thickness t2 may be greater than the thickness t1. By making the thickness t1 relatively small, it is possible to reduce the unevenness of the plating layer 72 caused by the provision of the nitride film 76. The thickness t2 may be 1.5 times or more, 2 times or more, 3 times or more, or 5 times or more of the thickness t1. The thickness t2 may be 10 times or less than the thickness t1. The plating layer 72 located above the nitride film 76 also includes a portion that does not overlap with the nitride film 76 in the depth direction. In this case, the thickness t2 may be the thickness of the plating layer 72 located above the position obtained by extending the upper end of the nitride film 76 into a plane parallel to the upper surface 21. The thickness t2 may be the value at the center of the plating layer 72, the average value of the thickness of the entire plating layer 72, or the average or maximum value of the thickness of the portion overlapping with the nitride film 76.

[0058] The nitride film 76 may be in contact with the plating layer 72. The nitride film 76 may overlap the plating layer 72. In a top view, the length of the portion where the nitride film 76 and the plating layer 72 overlap in a direction perpendicular to the edge 75 of the plating layer 72 is defined as t3. The edge 75 shown in FIG. 2A extends in the Y-axis direction. In FIG. 2A, the length t3 is the length in the X-axis direction, but in the portion where the edge of the plating layer 72 extends in the X-axis direction, the length t3 is the length in the Y-axis direction. The length t3 may be 1 μm or more. This can prevent the solder from reaching the emitter electrode 52.

[0059] When solder is formed on the plating layer 72, about 2 μm from the surface of the plating layer 72 may react with the solder, which is called solder erosion. Therefore, the length t3 may be 2 μm or more, or may be 2.5 μm or more. This makes it possible to prevent the solder from reaching the emitter electrode 52. The length t3 may be 5 μm or less, 4 μm or less, or 3.5 μm or less. In addition, the length t3 may be smaller than the thickness t6 of the plating layer 72, or may be equal to the thickness t6 of the plating layer 72.

[0060] The length of the portion of the nitride film 76 that protrudes toward the plating layer 72 side beyond the protective film 70 is defined as t4. As in the case of length t3, in FIG. 2A, length t4 is the length in the X-axis direction, but in the portion where the end edge of the protective film 70 extends in the X-axis direction, length t4 is the length in the Y-axis direction. Length t4 may be the length in the direction perpendicular to the end edge of the protective film 70 in a top view. Length t4 may be 3 μm or more, or may be 4 μm or more. Length t4 may be 5 μm or less, or may be 7 μm or less.

[0061] Fig. 2B is a diagram showing another example of the aa cross section in Fig. 1. The aa cross section of this example differs from the aa cross section shown in Fig. 2A in the arrangement of the protective film 70 and the plating layer 72. Other points are similar to Fig. 2A, so the description will be omitted.

[0062] In this example, the protective film 70 and the plating layer 72 are in contact with each other. An end of the plating layer 72 may be disposed above an end of the protective film 70. As described below, the protective film 70 and the plating layer 72 do not have high adhesion, so there is a possibility that solder may penetrate between the protective film 70 and the plating layer 72. In this example, the nitride film 76 is provided, so that it is possible to prevent the solder that has penetrated between the protective film 70 and the plating layer 72 from reaching the emitter electrode 52 (i.e., the triple point).

[0063] FIG. 3A is a diagram showing an example of aa cross section in a comparative example. The semiconductor device 100 of this example does not include a nitride film 76. Other parts are the same as those in FIG. 2A, so the description will be omitted. Residues of organic matter generated during patterning and etching of the protective film 70 tend to remain near the edge of the opening of the protective film 70. If a plating process for forming the plating layer 72 is performed in this state, plating may not grow easily near the edge of the opening of the protective film 70, and the plating layer 72 may not be formed. Therefore, a triple point of the emitter electrode 52, the protective film 70, and the plating layer 72 is formed and exposed upward. In this specification, the triple point is a position where the emitter electrode 52, the protective film 70, and the plating layer 72 coexist. If the process proceeds to a later step in this state and solder is formed, the solder will reach the triple point.

[0064] When the semiconductor device 100 is used for a long time with the solder having reached the triple point, the crack will progress in the order of the emitter electrode 52 and the semiconductor substrate 10. The progress of the crack will reduce the reliability of the semiconductor device 100 against breakdowns, etc. Since the progress of the crack progresses gradually with long-term use, it is difficult to detect it in an inspection before shipment.

[0065] 2A and 2B, the semiconductor device 100 of this embodiment has the nitride film 76 that is continuously provided from between the protective film 70 and the emitter electrode 52 to between the non-overlapping portion 74 of the plating layer 72 and the emitter electrode 52, so that the triple point is not formed. Also, it is possible to prevent the solder from reaching the emitter electrode 52.

[0066] FIG. 3B is a diagram showing another example of the aa cross section in the comparative example. The semiconductor device 100 of this example does not have the nitride film 76. Other parts are the same as those of FIG. 2A, so the description is omitted. This example shows a case where no organic residue remains near the edge of the opening of the protective film 70, and plating grows even near the edge of the opening of the protective film 70. In this case, the triple point is formed, but is not exposed upward. However, since the adhesion between the protective film 70 and the plating layer 72 is not high, there is a concern that the solder will penetrate between the protective film 70 and the plating layer 72 and reach the triple point. In the semiconductor device 100 of this embodiment, the triple point is not formed by the nitride film 76, so even if plating grows near the edge of the opening of the protective film 70, the reliability of the semiconductor device 100 can be suppressed from decreasing.

[0067] Fig. 4 is a diagram showing another example of the aa cross section in Fig. 1. The aa cross section of this example differs from the aa cross section shown in Fig. 2A in the thicknesses of the protective film 70 and the plating layer 72. Other points are similar to Fig. 2A, so the description will be omitted.

[0068] The thickness of the protective film 70 in the depth direction is t5. The thickness of the plating layer 72 in the depth direction is t6. In the semiconductor device 100 of this example, the thickness t6 is greater than the thickness t5. By making the plating layer 72 thicker, it is possible to reduce the unevenness of the plating layer 72 caused by providing the nitride film 76. However, as shown in FIG. 2A and other figures, the thickness t5 may be greater than the thickness t6. Also in this example, the protective film 70 and the plating layer 72 may be in contact with each other as shown in FIG. 2B.

[0069] 5 is a diagram showing a part of the manufacturing process of the semiconductor device 100. The manufacturing process of this example includes a first electrode forming step S1000, a first electrode patterning and etching step S1002, a nitride film forming step S1004, a nitride film patterning and etching step S1006, a protective film coating step S1008, a protective film patterning and etching step S1010, an annealing treatment step S1012, and a plating layer forming step S1014.

[0070] In the first electrode deposition step S1000, a first electrode is deposited above the upper surface 21 of the semiconductor substrate 10. An element structure as shown in FIG. 2A, for example, is formed on the semiconductor substrate 10. The first electrode is, for example, an emitter electrode 52, which may be an Al-Si alloy. In the first electrode patterning / etching step S1002, the deposited first electrode is patterned and etched into a desired shape.

[0071] In the nitride film deposition step S1004, a nitride film 76 is deposited above a portion of the first electrode. The nitride film 76 is, for example, silicon nitride, and is deposited by a method such as sputtering. In the nitride film patterning and etching step S1006, the deposited nitride film 76 is patterned and etched to form an opening.

[0072] In the protective film application step S1008, the protective film 70 is formed above a portion of the nitride film 76. The protective film 70 may be an insulating organic film, for example, polyimide. In the protective film patterning and etching step S1010, the protective film 70 is patterned and etched to form an opening. At this time, by making the opening of the protective film 70 larger than the opening of the nitride film 76, the nitride film 76 can be provided continuously between the non-overlapping portion 74 of the plating layer 72 to be formed later and the first electrode, as shown in FIG. 2A and the like.

[0073] In the annealing step S1012, the nitride film 76 and the protective film 70 are annealed. This improves the adhesion between the protective film 70 and the nitride film 76, and suppresses the growth of a second plating layer, which will be described later. The temperature of the annealing is, for example, 300° C. or more and 400° C. or less. The time of the annealing is, for example, 30 minutes or more and 1 hour or less. The time of the annealing may be 40 minutes or more and 50 minutes or less.

[0074] In plating layer formation step S1014, after annealing step S1012, plating layer 72 is formed on the first electrode not covered with nitride film 76 and on a part of nitride film 76. The plating layer 72 may be nickel and is formed by a method such as electroless plating. Gold for oxidation prevention may be formed on the nickel. Then, solder is formed on protective film 70, nitride film 76 and plating layer 72.

[0075] Fig. 6 is a diagram showing another example of the aa cross section in Fig. 1. The aa cross section of this example differs from the aa cross section shown in Fig. 2A in that a second plating layer 78 is formed between the protective film 70 and the nitride film 76. Other points are similar to Fig. 2A, so their explanation will be omitted.

[0076] The semiconductor device 100 of this embodiment further includes a second plating layer 78 provided between the protective film 70 and the nitride film 76 and having a lower density than the plating layer 72. The density is weight per unit volume. In FIG. 6, the second plating layer is indicated by coarse hatching. In the plating layer forming step S1014, if the adhesion between the protective film 70 and the nitride film 76 is low, the plating solution will seep between the protective film 70 and the nitride film 76, and the second plating layer 78 having a lower density than the plating layer 72 will be formed.

[0077] By performing the annealing treatment in the annealing treatment step S1012, the adhesion between the protective film 70 and the nitride film 76 is improved and the penetration of the plating solution is reduced, so that the growth of the second plating layer 78 can be suppressed. It is considered that the longer the plating treatment time in the plating layer forming step S1014, the larger the thickness t6 of the plating layer 72 becomes, and similarly, the second plating layer 78 also grows. Therefore, the ratio of the thickness of the plating layer 72 to the length of the second plating layer 78 may be used as the degree of growth suppression. That is, the length of the second plating layer 78 in the direction connecting the protective film 70 and the plating layer 72 in a plane parallel to the upper surface 21 of the semiconductor substrate 10 (the X-axis direction in the aa cross section) is defined as t7. The thickness t7 may be half or less of the thickness t6. The thickness t7 may be 30% or less of the thickness t6, 20% or less, or 10% or less.

[0078] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0079] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0080] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 30 dummy trench portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 42 gate insulating film, 4 DESCRIPTION OF THE PREFERRED EMBODIMENTS 4 Gate conductive portion, 52 Emitter electrode, 54 Contact hole, 56 Contact plug, 60, 61 Mesa portion, 70 Protective film, 72 Plating layer, 73 Plating layer, 74 Non-overlapping portion, 75 Edge, 76 Nitride film, 77 Nitride film, 78 Second plating layer, 80 Diode portion, 82 Cathode region, 90 Transistor portion, 100 Semiconductor device, 102 Edge

Claims

1. a semiconductor substrate having an upper surface; a first electrode provided above the top surface of the semiconductor substrate; A protective film provided above the first electrode; a plating layer provided above the first electrode and having a non-overlapping portion that does not overlap the protective film in a top view; a nitride film provided continuously from between the protective film and the first electrode to between the non-overlapping portion and the first electrode; Equipped with The thickness of the plating layer above the nitride film is greater than the thickness of the nitride film. Semiconductor device.

2. The nitride film is in contact with the plating layer. The semiconductor device according to claim 1 .

3. The nitride film is in contact with the first electrode. The semiconductor device according to claim 1 .

4. The protective film and the plating layer are in contact with each other. The semiconductor device according to claim 1 .

5. The protective film and the plating layer are separated from each other. The semiconductor device according to claim 1 .

6. When viewed from above, a first length in a direction perpendicular to an edge of the plating layer of a portion where the nitride film and the plating layer overlap is 1 μm or more. The semiconductor device according to claim 1 .

7. When viewed from above, the first length is 2 μm or more. The semiconductor device according to claim 6.

8. When viewed from above, the first length is 4 μm or less. The semiconductor device according to claim 7.

9. The portion of the nitride film that protrudes from the protective film to the plating layer side is 3 μm or more and 7 μm or less. The semiconductor device according to claim 1 .

10. The thickness of the plating layer is greater than the thickness of the protective film. The semiconductor device according to claim 1 .

11. a second plating layer having a lower density than the plating layer and provided between the protective film and the nitride film; The length of the second plating layer in a direction connecting the protective film and the plating layer in a plane parallel to the top surface of the semiconductor substrate is equal to or less than half the thickness of the plating layer. The semiconductor device according to claim 1 .

12. 1. A method for manufacturing a semiconductor device comprising: a semiconductor substrate having a first electrode above a top surface thereof, forming a nitride film above a portion of the first electrode; forming a protective film above a portion of the nitride film; annealing the nitride film and the protective film; After the annealing process, a plating layer is formed on the first electrode not covered with the nitride film and on a portion of the nitride film. A method for manufacturing a semiconductor device.

13. The annealing temperature is 300° C. or more and 400° C. or less. The method for manufacturing a semiconductor device according to claim 12 .

14. The annealing time is 30 minutes or more and 1 hour or less. The method for manufacturing a semiconductor device according to claim 12 .

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