Display device and display panel

Abstract

To provide a display device capable of controlling the viewing angle of a specific area of a display panel.SOLUTION: An exemplary embodiment of the present disclosure relates to a display device. Specifically, the display device comprises a first narrow angle control line electrically connected to a first viewing angle control circuit, a first wide angle control line electrically connected to the first viewing angle control circuit, and a first sub-pixel electrically connected to the first viewing angle control circuit, so as to control the viewing angle of a specific area of a display panel.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments of the present disclosure relate to a display device and a display panel. [Background technology]

[0002] 2. Description of the Related Art With the development of an information society, the demand for display devices for displaying images is increasing in various forms, and in recent years, various display devices such as liquid crystal display devices and organic light emitting display devices have been utilized.

[0003] An image can be displayed via the display panel, and the image has a predetermined viewing angle and can be displayed from the display panel.

[0004] Depending on the viewing angle adjustment, the image can be displayed at a wide or narrow angle. Summary of the Invention [Problem to be solved by the invention]

[0005] However, there is a technical problem in that it is difficult to freely adjust the viewing angle of a partial area of ​​the display panel.

[0006] Therefore, an embodiment of the present disclosure provides a display device that can control the viewing angle of a specific region of a display panel.

[0007] An embodiment of the present disclosure provides a display device in which the viewing angles in the left-right and up-down directions can be controlled simultaneously.

[0008] The embodiments of the present disclosure provide a display device capable of low power consumption through flexible viewing angle control. [Means for solving the problem]

[0009] An embodiment of the present disclosure provides a display device including a first viewing angle control circuit, a first narrow angle control line electrically connected to the first viewing angle control circuit, a first wide angle control line electrically connected to the first viewing angle control circuit, and a first subpixel electrically connected to the first viewing angle control circuit.

[0010] An embodiment of the present disclosure provides a display panel including a first pixel circuit electrically connected to a first narrow-angle control line and a first wide-angle control line, a second pixel circuit electrically connected to the first narrow-angle control line and the first wide-angle control line, and a third pixel circuit electrically connected to the second narrow-angle control line and the second wide-angle control line, wherein the viewing angle of light output from the second pixel circuit and the third pixel circuit is a wide angle, and the viewing angle of light output from the first pixel circuit is a narrow angle. Effect of the Invention

[0011] According to an embodiment of the present disclosure, a display device capable of controlling the viewing angle of a specific region of a display panel can be provided.

[0012] According to the embodiment of the present disclosure, it is possible to provide a display device capable of simultaneously controlling the viewing angles in the left-right direction and the up-down direction.

[0013] According to the embodiment of the present disclosure, it is possible to provide a display device capable of consuming low power through flexible viewing angle control. [Brief description of the drawings]

[0014] [Figure 1] 1 is a system configuration diagram of a display device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram of a display panel in which multiple sub-pixels emitting light at narrow or wide angles are arranged according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a diagram of a display panel in which multiple sub-pixels emitting light at narrow or wide angles are arranged according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram of a display panel in which multiple sub-pixels emitting light at narrow or wide angles are arranged according to an embodiment of the present disclosure. [Diagram 5] 1 is an exemplary diagram of a display panel including a wide-angle region and a narrow-angle region according to an embodiment of the present disclosure. [Figure 6] 1 is an exemplary diagram of a display panel including a wide-angle region and a narrow-angle region according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is an exemplary diagram of a display panel controlled by local narrow-angle area driving according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a diagram of a display panel including a number of pixel circuits according to an embodiment of the present disclosure. [Figure 9] FIG. 1 is a diagram showing a partial configuration of a subpixel and a viewing angle control circuit according to an embodiment of the present disclosure. [Figure 10] FIG. 1 is a diagram showing a partial configuration of a subpixel and a viewing angle control circuit according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram of a first subpixel and a first viewing angle control circuit according to an embodiment of the present disclosure. [Figure 12] FIG. 11 is an operation timing diagram of the first subpixel and the first viewing angle control circuit according to an embodiment of the present disclosure. [Figure 13] FIG. 11 is an operation timing diagram of the first subpixel and the first viewing angle control circuit according to an embodiment of the present disclosure. [Figure 14] FIG. 11 is a diagram of a first subpixel and a first viewing angle control circuit according to an embodiment of the present disclosure. [Figure 15] FIG. 11 is a diagram of a first subpixel and a first viewing angle control circuit according to an embodiment of the present disclosure. [Figure 16] FIG. 11 is a diagram of a first subpixel and a first viewing angle control circuit according to an embodiment of the present disclosure. [Figure 17] FIG. 2 is a diagram of a number of sub-pixels and a first viewing angle control circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Some embodiments of the present disclosure will be described in detail below with reference to the exemplary drawings. When adding reference symbols to components in each drawing, the same symbols can be attached to the same components as much as possible even if they are displayed on different drawings. In describing the present disclosure, if a specific description of a related publicly known configuration or function is determined to make the gist of the present disclosure unclear, the detailed description may be omitted. When "includes," "has," "performed," and the like are used in this specification, other parts may be added unless "only" is used. When a component is expressed as a singular number, it may include a case where a plurality is included unless otherwise explicitly stated.

[0016] In addition, in describing components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. are used. These terms are used to distinguish the components from other components, and do not limit the essence, order, procedure, number, etc. of the components.

[0017] In describing the positional relationship of components, when two or more components are described as being "coupled," "coupled," or "connected," it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be "coupled," "coupled," or "connected" through an additional "intervening" component. Here, the additional component may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0018] In describing a temporal sequence of components, methods of operation, methods of production, etc., when the temporal or chronological sequence is described using, for example, "after," "following," "after," or "before," this can include cases where the sequence is not consecutive, unless "immediately" or "directly" is used.

[0019] On the other hand, when referring to numerical values ​​or corresponding information (e.g., levels, etc.) for components, even if there is no explicit mention otherwise, the numerical values ​​or corresponding information can be interpreted as including an error range that may arise due to various factors (e.g., process factors, internal or external impacts, noise, etc.).

[0020] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0021] FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present invention.

[0022] Referring to FIG. 1, the display device 100 according to the present embodiment may include a display panel 110 on which a number of data lines DL and a number of gate lines GL are arranged and a number of sub-pixels SP connected to the number of data lines DL and the number of gate lines GL are arranged, and a driving circuit for driving the display panel 110.

[0023] From a functional perspective, the driving circuit may include a data driving circuit 120 that drives a number of data lines DL, a gate driving circuit 130 that drives a number of gate lines GL, and a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

[0024] In the display panel 110, a number of data lines DL and a number of gate lines GL may be arranged crossing each other. For example, a number of data lines DL may be arranged in rows or columns, and a number of gate lines GL may be arranged in columns or rows. In the following, for convenience of explanation, it is assumed that a number of data lines DL are arranged in rows, and a number of gate lines GL are arranged in columns.

[0025] The controller 140 supplies various control signals DCS and GCS required for the driving operations of the data driving circuit 120 and the gate driving circuit 130 to control them.

[0026] The controller 140 starts scanning according to the timing to be implemented in each frame, outputs image data DATA converted from input image data input from the outside according to the data signal format used in the data driving circuit 120, and controls data driving at an appropriate timing according to the scan.

[0027] The controller 140 described above receives various timing signals including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable (DE) signal, a clock signal CLK, and the like, together with input video data from an external source (eg, a host system).

[0028] The controller 140 outputs image data DATA that has been converted from externally input image data to match the data signal format used in the data driving circuit 120. In addition, in order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input DE signal, and a clock signal, generates various control signals, and outputs them to the data driving circuit 120 and the gate driving circuit 130.

[0029] Such a controller 140 may be a timing controller used in conventional display technology, or may be a control device that includes a timing controller and can further perform other control functions.

[0030] The controller 140 may be configured as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 to form an integrated circuit.

[0031] The data driving circuit 120 receives image data DATA from the controller 140 and supplies data voltages to the data lines DL, thereby driving the data lines DL. Here, the data driving circuit 120 is also called a source driving circuit.

[0032] The data driving circuit 120 may include at least one source driver integrated circuit (S-DIC: Source-Driver Integrated Circuit). Each source driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC: Digital to Analog Converter), an output buffer, etc. Each source driver integrated circuit (S-DIC) may further include an analog-to-digital converter (ADC: Analog to Digital Converter) in some cases.

[0033] Each source driver integrated circuit (S-DIC) may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method, or may be directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110 in some cases. Also, each source driver integrated circuit (S-DIC) may be configured in a chip on film (COF) method in which it is connected to the display panel 110 and mounted on a source-circuit film.

[0034] The gate driving circuit 130 sequentially drives the gate lines GL by sequentially supplying scan signals to the gate lines GL. Here, the gate driving circuit 130 is also called a scan driving circuit.

[0035] The gate driving circuit 130 may include a shift register, a level shifter, and the like.

[0036] The gate driving circuit 130 may be connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method, a chip on glass (COG) method, or a chip on panel (COP) method, or may be configured as a GIP (Gate In Panel) type and directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110. The gate driving circuit 130 may be configured as a chip on film (COF) method in which a number of gate driver integrated circuits (G-DICs) are mounted on a gate-circuit film connected to the display panel 110.

[0037] The gate driving circuit 130, under the control of the controller 140, sequentially supplies a scan signal of an on voltage or an off voltage to a number of gate lines GL.

[0038] When a particular gate line is opened by the gate driving circuit 130, the data driving circuit 120 converts the image data DATA received from the controller 140 into an analog data voltage and supplies it to a number of data lines DL.

[0039] The data driving circuit 120 may be located on only one side (e.g., the upper or lower side) of the display panel 110, or in some cases, on both sides (e.g., the upper and lower sides) of the display panel 110 depending on the driving method, panel design method, etc.

[0040] The gate driving circuit 130 may be located on only one side (e.g., the left or right side) of the display panel 110, or in some cases, on both sides (e.g., the left and right sides) of the display panel 110 depending on the driving method, panel design method, etc.

[0041] The multiple gate lines GL arranged on the display panel 110 may include multiple scan lines SCL, multiple sense lines SENL, and multiple emission control lines EML. The scan lines SCL, the sense lines SENL, and the emission control lines EML are wirings that transmit different types of gate signals (scan signals, sense signals, emission control signals) to gate nodes of different types of transistors (scan transistors, sense transistors, emission control transistors). Hereinafter, a description will be given with reference to FIG. 2.

[0042] The display device 100 according to this embodiment may be a self-luminous display such as an OLED (Organic Light Emitting Diode) display, a quantum dot display, or a micro LED (Micro Light Emitting Diode) display.

[0043] When the display device 100 according to the present embodiment is an OLED display, each subpixel SP may include an organic light emitting diode (OLED) that emits light by itself as a light emitting element. When the display device 100 according to the present embodiment is a quantum dot display, each subpixel SP may include a light emitting element made of a quantum dot, which is a semiconductor crystal that emits light by itself. When the display device 100 according to the present embodiment is a micro LED display, each subpixel SP may include a micro LED (Micro Light Emitting Diode) that emits light by itself and is made based on an inorganic material as a light emitting element.

[0044] Meanwhile, light output through the display panel 110 may be output from the display panel 110 at a predetermined viewing angle. One frame image may be displayed on the display panel 110 as each of a number of sub-pixels SP emits light. When one sub-pixel SP emits light, the light is output at a predetermined angle. For example, each of a number of sub-pixels SP may emit light in a predetermined viewing angle range, such as 30 degrees, 60 degrees, 120 degrees, and 150 degrees. If the viewing angle is n degrees (n is a natural number of 1 or more), the left side may be n / 2 degrees and the right side may be n / 2 degrees based on the front from which the light is output. When the viewing angle is relatively large, it may be called a "wide angle, wide viewing angle, wide viewing angle", and when the viewing angle is relatively small, it may be called a "narrow angle, narrow viewing angle, narrow viewing angle".

[0045] The viewing angle of the display panel 110 may be fixed. Also, the viewing angle of the display panel 110 may be variable. For example, the viewing angle of the display panel 110 may be controlled via a light control film (LCF), a lens layer, other viewing angle control structures, etc.

[0046] As an example of a method for adjusting the viewing angle of the display panel 110, one subpixel SP may include two light emitting elements. The two light emitting elements may be a first light emitting element and a second light emitting element. The first light emitting element may be a light emitting element for narrow angle driving, and the second light emitting element may be a light emitting element for wide angle driving. By selectively driving the first light emitting element and the second light emitting element, a frame image may be displayed on the display panel 110 at a narrow angle or a wide angle.

[0047] A method for driving the display device 100 that is switchable between a narrow angle and a wide angle will be specifically described below.

[0048] 2, 3 and 4 are diagrams of a display panel 110 in which multiple sub-pixels emitting light at narrow or wide angles are arranged according to an embodiment of the present disclosure.

[0049] Referring to FIG. 2, a display panel 110 in which a number of sub-pixels are arranged can be seen.

[0050] A large number of sub-pixels SP can be arranged in a matrix.

[0051] A number of sub-pixels SP may be grouped in the column direction of the display panel 110. That is, the display panel 110 may include a number of sub-pixel groups SPG.

[0052] 2, for convenience of explanation, it is assumed that 20 sub-pixels SP are arranged in the display panel 110. Five sub-pixel groups SPG may be arranged in the display panel 110. Each of the sub-pixel groups SPG may include four sub-pixels.

[0053] 2, a first subpixel group SPG1 may be disposed on the leftmost side of the display panel 110, and a fifth subpixel group SPG5 may be disposed on the rightmost side of the display panel 110. A second subpixel group SPG2, a third subpixel group SPG3, and a fourth subpixel group SPG4 may be disposed between the first subpixel group SPG1 and the fifth subpixel group SPG5.

[0054] The first sub-pixel group SPG1 may be electrically connected to the first narrow-angle control line P1 and the first wide-angle control line S1. The first narrow-angle control line P1 and the first wide-angle control line S1 may be electrically connected to the sub-pixels included in the first sub-pixel group SPG1.

[0055] The second subpixel group SPG2 may be electrically connected to the second narrow angle control line P2 and the second wide angle control line S2. The second narrow angle control line P2 and the second wide angle control line S2 may be electrically connected to the subpixels included in the second subpixel group SPG2.

[0056] The third subpixel group SPG3 may be electrically connected to the third narrow angle control line P3 and the third wide angle control line S3. The third narrow angle control line P3 and the third wide angle control line S3 may be electrically connected to the subpixels included in the third subpixel group SPG3.

[0057] The fourth sub-pixel group SPG4 may be electrically connected to a fourth narrow angle control line P4 and a fourth wide angle control line S4. The fourth narrow angle control line P4 and the fourth wide angle control line S4 may be electrically connected to sub-pixels included in the fourth sub-pixel group SPG4.

[0058] The fifth subpixel group SPG5 may be electrically connected to the fifth narrow angle control line P5 and the fifth wide angle control line S5. The fifth narrow angle control line P5 and the fifth wide angle control line S5 may be electrically connected to the subpixels included in the fifth subpixel group SPG5.

[0059] The multiple sub-pixel groups SPG can emit light at a wide angle or a narrow angle depending on the control signals supplied to the narrow angle control line P and the wide angle control line S.

[0060] Referring to FIG. 2, the sub-pixel groups SPG are grouped in the column direction, but depending on the arrangement of the narrow-angle control lines P and wide-angle control lines S, the sub-pixel groups SPG can also be grouped in the row direction.

[0061] Each of the multiple sub-pixels SP may include multiple transistors, capacitors, one or more light emitting elements, and the like.

[0062] Each of the sub-pixels SP may include one driving transistor TDR and one or more light-emitting elements ED, and may be designed in various ways, such as 2T1C, 3T1C, 6T1C, etc. Each of the sub-pixels SP may be a sub-pixel that does not require compensation for characteristic values, or may be a sub-pixel to which an internal compensation method is applied, or a sub-pixel to which an external compensation method is applied. That is, since the specific structure of the sub-pixel SP can be designed in various ways, the following description will focus on the driving transistor TDR and the light-emitting element ED included in the sub-pixel SP, and descriptions of other elements may be omitted.

[0063] Referring to FIG. 2, a portion of an equivalent circuit of one sub-pixel SP_a included in the first sub-pixel group SPG1 can be seen.

[0064] The sub-pixel SP_a may include a driving transistor TDR, a first emission control transistor Ts, a second emission control transistor Tp, a first light-emitting element ED_S, a second light-emitting element ED_P, and the like.

[0065] A driving current Id may flow through the driving transistor TDR in response to a voltage supplied to the gate node of the driving transistor TDR. The driving current Id may be supplied to the first light-emitting element ED_S or the second light-emitting element ED_P. The first light-emitting element ED_S and the second light-emitting element ED_P may emit light at a luminance corresponding to the driving current Id.

[0066] The first emission control transistor Ts may be electrically connected between the driving transistor TDR and the first light emitting element ED_S. A gate node of the first emission control transistor Ts may be supplied with a wide-angle control signal S_sel. The first emission control transistor Ts may control an electrical connection relationship between the driving transistor TDR and the first light emitting element ED_S in response to the wide-angle control signal S_sel. The wide-angle control signal S_sel may be a voltage of a predetermined size and may be expressed as a high-level signal or a low-level signal.

[0067] The second emission control transistor Tp may be electrically connected between the driving transistor TDR and the second light emitting element ED_P. A gate node of the second emission control transistor Tp may be supplied with a narrow angle control signal P_sel. The second emission control transistor Tp may control the electrical connection relationship between the driving transistor TDR and the second light emitting element ED_P in response to the narrow angle control signal P_sel. The narrow angle control signal P_sel may be a voltage of a predetermined magnitude and may be expressed as a high level signal or a low level signal.

[0068] 3, when the first emission control transistor Ts is turned on and the second emission control transistor Tp is turned off, the first light emitting element ED_S may be supplied with a driving current Id, and when the first light emitting element ED_S emits light, the sub-pixel SP_a may emit light while maintaining a wide angle WA.

[0069] 4, when the second emission control transistor Tp is turned on and the first emission control transistor Ts is turned off, the second light emitting element ED_P may be supplied with a driving current Id, and when the second light emitting element ED_P emits light, the sub-pixel SP_a may emit light while maintaining a narrow angle NA.

[0070] When the sub-pixel SP_a emits light at a wide angle WA, the viewing angle may be wider than when the sub-pixel SP_a emits light at a narrow angle NA. In this case, not only users in front of the display panel 110 but also users on the sides of the display panel 110 can see the image displayed on the display panel 110. When the viewing angle is wide, all users positioned within the wide viewing angle can see the image, which may be referred to as a "shared mode," "shared mode," or "shared drive."

[0071] When the sub-pixel SP_a emits light at a narrow angle NA, the viewing angle may be narrower than when the sub-pixel SP_a emits light at a wide angle WA. In this case, only users in front of or close to the front of the display panel 110 can see the image displayed on the display panel 110. When the viewing angle is narrow, only users located within the narrow viewing angle can see the image, which may be referred to as a "private life mode," "privacy mode," or "privacy drive."

[0072] When the first light-emitting element ED_S included in the subpixel SP emits light, the subpixel SP may be disposed in the wide-angle region SA. That is, the region of the display panel 110 where the first light-emitting element ED_S emits light may be the wide-angle region SA.

[0073] When the second light-emitting element ED_P included in the subpixel SP emits light, the subpixel SP may be disposed in the narrow-angle region PA. That is, the region of the display panel 110 where the second light-emitting element ED_P emits light may be the narrow-angle region PA.

[0074] In the case of the wide-angle region SA, the first light-emitting element ED_S may emit light at a wide viewing angle, so that an image may be displayed at a wide viewing angle in the wide-angle region SA. Alternatively, the viewing angle may be adjusted through a light refraction structure, such as a lens or a viewing angle adjusting layer, disposed on the first light-emitting element ED_S.

[0075] In the case of the narrow-angle region PA, the second light-emitting element ED_P may emit light at a narrow viewing angle, so that an image may be displayed at a narrow viewing angle in the narrow-angle region PA. Alternatively, the viewing angle may be adjusted through a light refraction structure, such as a lens or a viewing angle adjusting layer, disposed on the second light-emitting element ED_P.

[0076] 5 and 6 are exemplary diagrams of a display panel 110 including a wide angle area SA and a narrow angle area PA according to an embodiment of the present disclosure.

[0077] FIG. 7 is an exemplary diagram of a display panel 110 controlled by local narrow-angle area driving according to an embodiment of the present disclosure.

[0078] 5, a portion of the display panel 110 may be a wide-angle region SA, and the other portion of the display panel 110 may be a narrow-angle region PA. A first subpixel group SPG1, a second subpixel group SPG2, a third subpixel group SPG3, and a fourth subpixel group SPG4 may be arranged in the wide-angle region SA of the display panel 110. A fifth subpixel group SPG5 may be arranged in the narrow-angle region PA of the display panel 110. That is, the first subpixel group SPG1 to the fourth subpixel group SPG4 may emit light at a wide angle, and the fifth subpixel group SPG5 may emit light at a narrow angle.

[0079] 6, a portion of the display panel 110 may be a wide-angle region SA, and the other portion of the display panel 110 may be a narrow-angle region PA. A first subpixel group SPG1 and a second subpixel group SPG2 may be arranged in the wide-angle region SA of the display panel 110. A third subpixel group SPG3, a fourth subpixel group SPG4, and a fifth subpixel group SPG5 may be arranged in the narrow-angle region PA of the display panel 110. That is, the first subpixel group SPG1 and the second subpixel group SPG2 may emit light at a wide angle, and the third to fifth subpixel groups SPG3 to SPG5 may emit light at narrow angles.

[0080] Referring to Figures 5 and 6, the narrow-angle control line P and the wide-angle control line S can be arranged in the column direction of the display panel 110, and the narrow-angle control line P and the wide-angle control line S can be electrically connected to a number of sub-pixel groups SPG.

[0081] The narrow-angle control lines P and wide-angle control lines S arranged in the column direction are electrically connected to the subpixel groups SPG grouped in the column direction, so that the wide-angle area SA or narrow-angle area PA can be controlled only in the column direction. For example, a left region, which is a part of the display panel 110, may be the narrow-angle area PA, and a right region, which is the other region of the display panel 110, may be the wide-angle area SA. For convenience of explanation, the column direction is illustrated, but the row direction is also possible. That is, the narrow-angle area PA or wide-angle area SA of the display panel 110 is controlled only in either the left-right or up-down direction.

[0082] 7, a display panel 110 in which the viewing angles in the left-right and up-down directions are controlled simultaneously can be seen. Referring to FIG 7, an example can be seen in which a central region of the display panel 110 is a narrow angle region PA, and other regions of the display panel 110 are wide angle regions SA. Simultaneous control of the viewing angles in the left-right and up-down directions can be called "local SPM", "local viewing angle control", or "local viewing angle mode".

[0083] That is, the embodiments of the present disclosure can provide a display device in which the viewing angle of a specific region of a display panel can be controlled.

[0084] The embodiments of the present disclosure can provide a display device in which the viewing angles in the left-right direction and the up-down direction can be controlled simultaneously.

[0085] The embodiments of the present disclosure can provide a display device capable of consuming low power through flexible viewing angle control, as will be described in detail below.

[0086] FIG. 8 is a diagram of a display panel 110 including a number of pixel circuits PC according to an embodiment of the present disclosure.

[0087] Referring to FIG. 8, a display panel 110 may include a number of pixel circuits PC, a number of narrow-angle control lines P, and a number of wide-angle control lines S.

[0088] 8, a display panel 110 having 16 pixel circuits PC, four narrow-angle control lines P, and four wide-angle control lines S can be seen. The number of pixel circuits PC, the number of narrow-angle control lines P, and the number of wide-angle control lines S is not limited thereto.

[0089] One narrow-angle control line P and one wide-angle control line S can be electrically connected to multiple pixel circuits PC.

[0090] Referring to FIG. 8, the first narrow-angle control line P1 may be electrically connected to the first pixel circuit PC1, the second pixel circuit PC2, the third pixel circuit PC3, and the fourth pixel circuit PC4.

[0091] Referring to FIG. 8, the first wide-angle control line S1 may be electrically connected to the first pixel circuit PC1, the second pixel circuit PC2, the third pixel circuit PC3, and the fourth pixel circuit PC4.

[0092] Referring to FIG. 8, the second narrow-angle control line P2 may be electrically connected to the fifth pixel circuit PC5, the sixth pixel circuit PC6, the seventh pixel circuit PC7, and the eighth pixel circuit PC8.

[0093] Referring to FIG. 8, the second wide-angle control line S2 may be electrically connected to the fifth pixel circuit PC5, the sixth pixel circuit PC6, the seventh pixel circuit PC7, and the eighth pixel circuit PC8.

[0094] Referring to FIG. 8, the third narrow-angle control line P3 may be electrically connected to the ninth pixel circuit PC9, the tenth pixel circuit PC10, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12.

[0095] Referring to FIG. 8, the third wide-angle control line S3 may be electrically connected to the ninth pixel circuit PC9, the tenth pixel circuit PC10, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12.

[0096] Referring to FIG. 8, the fourth narrow-angle control line P4 can be electrically connected to the thirteenth pixel circuit PC13, the fourteenth pixel circuit PC14, the fifteenth pixel circuit PC15, and the sixteenth pixel circuit PC16.

[0097] Referring to FIG. 8, the fourth wide-angle control line S4 may be electrically connected to the thirteenth pixel circuit PC13, the fourteenth pixel circuit PC14, the fifteenth pixel circuit PC15, and the sixteenth pixel circuit PC16.

[0098] A number of pixel circuits PC can include one or more sub-pixels SP and a viewing angle control circuit VCC.

[0099] Referring to FIG. 8, each of a number of pixel circuits PC may include one sub-pixel SP and one viewing angle control circuit VCC.

[0100] Referring to FIG. 8, a first pixel circuit PC1 disposed in the first region A1 can be seen.

[0101] The first pixel circuit PC1 may include a first sub-pixel SP1 and a first viewing angle control circuit VCC1.

[0102] The first viewing angle control circuit VCC1 can be electrically connected to the first sub-pixel SP1.

[0103] Referring to FIG. 8, a first viewing angle control circuit VCC1 may be electrically connected to a first narrow angle control line P1 and a first wide angle control line S1.

[0104] The first viewing angle control circuit VCC1 can control the viewing angle of the light emitted from the first sub-pixel SP1 based on signals supplied via the first narrow angle control line P1 and the first wide angle control line S1.

[0105] The characteristics of the sub-pixel SP and the viewing angle control circuit VCC included in the other pixel circuits PC except the first pixel circuit PC1 may be the same as the characteristics of the first sub-pixel SP1 and the first viewing angle control circuit VCC1 included in the first pixel circuit PC1. Therefore, the detailed operations of the multiple pixel circuits PC will be described below by taking the first pixel circuit PC1 as an example.

[0106] 9 and 10 are diagrams relating to a partial configuration of a subpixel SP and a viewing angle control circuit VCC according to an embodiment of the present disclosure.

[0107] 9 and 10, a portion of the configuration of the first sub-pixel SP1 included in the first pixel circuit PC1 and the first viewing angle control circuit VCC1 can be seen. The transistors shown in Figs. 9 and 10 are shown as P-type, but are not limited thereto and may be only N-type. Alternatively, both P-type and N-type transistors may be included.

[0108] The first sub-pixel SP1 may include a number of transistors, a capacitor, two or more light emitting elements, etc. The first sub-pixel SP1 may be designed in various ways, such as 2T1C, 3T1C, 6T1C, etc. Since the specific structure of the first sub-pixel SP1 may be designed in various ways, the following description will focus on the driving transistor TDR and the light emitting element ED included in the sub-pixel SP, and descriptions of other elements may be omitted.

[0109] 9 and 10, the first sub-pixel SP1 may include a driving transistor TDR, a first emission control transistor Ts, a second emission control transistor Tp, a first light emitting element ED_S, a second light emitting element ED_P, and the like.

[0110] A driving current Id may flow through the driving transistor TDR in response to a voltage supplied to the gate node of the driving transistor TDR. The driving current Id may be supplied to the first light-emitting element ED_S or the second light-emitting element ED_P. The first light-emitting element ED_S and the second light-emitting element ED_P may emit light at a luminance corresponding to the driving current Id.

[0111] The first emission control transistor Ts can be electrically connected between the driving transistor TDR and the first light-emitting element ED_S. A gate node of the first emission control transistor Ts may be supplied with a wide-angle control signal S_sel. In response to the wide-angle control signal S_sel, the first emission control transistor Ts can control the electrical connection relationship between the driving transistor TDR and the first light-emitting element ED_S.

[0112] The first light-emitting element ED_S can be electrically connected between the first light-emitting control transistor Ts and a node to which a base voltage VSS is supplied.

[0113] The second emission control transistor Tp can be electrically connected between the driving transistor TDR and the second light-emitting element ED_P. A gate node of the second emission control transistor Tp may be supplied with a narrow-angle control signal P_sel. In response to the narrow-angle control signal P_sel, the second emission control transistor Tp can control the electrical connection relationship between the driving transistor TDR and the second light-emitting element ED_P.

[0114] The second light-emitting element ED_P can be electrically connected between the second light-emitting control transistor Tp and a node to which a base voltage VSS is supplied.

[0115] The first viewing angle control circuit VCC1 may be electrically connected to the first sub-pixel SP1, the first wide-angle control line S1, and the first narrow-angle control line P1. The first viewing angle control circuit VCC1 may control the viewing angle of the light emitted from the first sub-pixel SP1 based on signals supplied from the first wide-angle control line S1 and the first narrow-angle control line P1.

[0116] The first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1, and a second control capacitor C2.

[0117] The first viewing angle control transistor Tss may be electrically connected between the fifth connection node Nc5 and the third connection node Nc3. The first viewing angle control transistor Tss may be electrically connected to the first wide-angle control line S1 via the third connection node Nc3. The gate node of the first viewing angle control transistor Tss may be electrically connected to the fourth connection node Nc4. The gate node of the first viewing angle control transistor Tss may be supplied with a first scan signal Scan1.

[0118] The second viewing angle control transistor Tps may be electrically connected between the sixth connection node Nc6 and the second connection node Nc2. The second viewing angle control transistor Tps may be electrically connected to the first narrow angle control line P1 via the second connection node Nc2. The gate node of the second viewing angle control transistor Tps may be electrically connected to the fourth connection node Nc4. The gate node of the second viewing angle control transistor Tps may be supplied with a first scan signal Scan1.

[0119] The first control capacitor C1 can be electrically connected between the first connection node Nc1 and the fifth connection node Nc5. The first connection node Nc1 may be supplied with a control reference voltage Vcr. The fifth connection node Nc5 can be electrically connected to the gate node of the first light-emitting control transistor Ts.

[0120] The second control capacitor C2 may be electrically connected between the first connection node Nc1 and a sixth connection node Nc6. The first connection node Nc1 may be supplied with a control reference voltage Vcr. The sixth connection node Nc6 may be electrically connected to the gate node of the second light-emitting control transistor Tp.

[0121] The first viewing angle control circuit VCC1 can control the on / off operation of the first emission control transistor Ts and the second emission control transistor Tp based on signals supplied from the first wide angle control line S1 and the first narrow angle control line P1.

[0122] 9, it can be seen that the first emission control transistor Ts is turned on and the second emission control transistor Tp is turned off. A control method for maintaining the first emission control transistor Ts in a turned on state and the second emission control transistor Tp in a turned off state is as follows.

[0123] A first scan signal Scan for maintaining the first viewing angle control transistor Tss and the second viewing angle control transistor Tps in a turned-on state can be supplied to the gate node of the first viewing angle control transistor Tss and the gate node of the second viewing angle control transistor Tps.

[0124] After the first viewing angle control transistor Tss and the second viewing angle control transistor Tps are turned on, a low level signal may be supplied to the fifth connection node Nc5 via the first wide angle control line S1, and a high level signal may be supplied to the sixth connection node Nc6 via the first narrow angle control line P1. At this time, the first connection node Nc1 may be supplied with the control reference voltage Vcr.

[0125] That is, the first control capacitor C1 may store a first control voltage corresponding to the voltage difference between a low level signal and the control reference voltage Vcr, and the second control capacitor C2 may store a second control voltage corresponding to the voltage difference between a high level signal and the control reference voltage Vcr.

[0126] The first control voltage is supplied to the gate node of the first light-emitting control transistor Ts, so that the first light-emitting control transistor Ts can be turned on. At this time, the second control voltage is supplied to the gate node of the second light-emitting control transistor Tp, so that the second light-emitting control transistor Tp can be turned off.

[0127] The first light-emitting element ED_S can emit light by turning on the first light-emitting control transistor Ts and turning off the second light-emitting control transistor Tp. When the first light-emitting element ED_S emits light, the first sub-pixel SP1 can emit light while maintaining the wide angle WA.

[0128] 10, it can be seen that the first emission control transistor Ts is turned off and the second emission control transistor Tp is turned on. A control method for maintaining the first emission control transistor Ts in the turned off state and the second emission control transistor Tp in the turned on state is as follows.

[0129] A first scan signal Scan for maintaining the first viewing angle control transistor Tss and the second viewing angle control transistor Tps in a turned-on state can be supplied to the gate node of the first viewing angle control transistor Tss and the gate node of the second viewing angle control transistor Tps.

[0130] After the first viewing angle control transistor Tss and the second viewing angle control transistor Tps are turned on, a high level signal may be supplied to the fifth connection node Nc5 via the first wide angle control line S1, and a low level signal may be supplied to the sixth connection node Nc6 via the first narrow angle control line P1. At this time, the first connection node Nc1 may be supplied with the control reference voltage Vcr.

[0131] That is, the first control capacitor C1 may store a second control voltage corresponding to the voltage difference between a high-level signal and the control reference voltage Vcr, and the second control capacitor C2 may store a first control voltage corresponding to the voltage difference between a low-level signal and the control reference voltage Vcr.

[0132] The second control voltage is supplied to the gate node of the first light-emitting control transistor Ts, so that the first light-emitting control transistor Ts can be turned off. At this time, the first control voltage is supplied to the gate node of the second light-emitting control transistor Tp, so that the second light-emitting control transistor Tp can be turned on.

[0133] The first emission control transistor Ts is turned off and the second emission control transistor Tp is turned on, so that the second light-emitting element ED_P can emit light. When the second light-emitting element ED_P emits light, the first sub-pixel SP1 can emit light while maintaining the narrow angle NA.

[0134] The first sub-pixel SP1 can be designed in various ways, such as 2T1C, 3T1C, 6T1C, etc. A specific embodiment of the first sub-pixel SP1 will be described below. The specific circuit structure of the first sub-pixel SP1 can also be applied to other sub-pixels SP except the first sub-pixel SP1.

[0135] FIG. 11 is a diagram of the first sub-pixel SP1 and the first viewing angle control circuit VCC1 according to an embodiment of the present disclosure.

[0136] 12 and 13 are operation timing diagrams of the first sub-pixel SP1 and the first viewing angle control circuit VCC1 according to an embodiment of the present disclosure.

[0137] 11, the first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1, and a second control capacitor C2. The first viewing angle control circuit VCC1 shown in FIG. 11 may be the same as the first viewing angle control circuit VCC1 shown in FIG. 9 and FIG. 10.

[0138] The first sub-pixel SP1 may include a number of transistors, a storage capacitor Cst, and two light emitting elements ED_S and ED_P.

[0139] The first transistor T1 may be electrically connected between a first node N1101 and a second node N1102. A gate node of the first transistor T1 may be electrically connected to a third node N1103. The third node N1103 may be supplied with a first scan signal Scan1. The first node N1101 may be supplied with a data voltage Vdata. The first transistor T1 may be a P-type transistor.

[0140] The second transistor T2 may be electrically connected between the fourth node N1104 and the sixth node N1106. A gate node of the second transistor T2 may be electrically connected to a ninth node N1109. The ninth node N1109 may be supplied with the first light-emitting signal EM1. The second transistor T2 may be a P-type transistor.

[0141] The third transistor T3 may be electrically connected between the second node N1102 and the tenth node N1110. A gate node of the third transistor T3 may be electrically connected to an eighth node N1108. The eighth node N1108 may be supplied with a first light-emitting signal EM1. The tenth node N1110 may be supplied with an initialization voltage Vinit. The third transistor T3 may be a P-type transistor.

[0142] The fourth transistor T1 may be electrically connected between a sixth node N1106 and a seventh node N1107. A gate node of the fourth transistor T1 may be electrically connected to an eighth node N1108. The eighth node N1108 may be supplied with a first light-emitting signal EM1. The fourth transistor T1 may be a P-type transistor.

[0143] The fifth transistor T5 may be electrically connected between the tenth node N1110 and the eleventh node N1111. A gate node of the fifth transistor T5 may be electrically connected to a ninth node N1109. The ninth node N1109 may be supplied with a second scan signal Scan2. The fifth transistor T5 may be a P-type transistor.

[0144] The sixth transistor T6 may be electrically connected between the tenth node N1110 and the twelfth node N1112. A gate node of the sixth transistor T6 may be electrically connected to a ninth node N1109. The ninth node N1109 may be supplied with a second scan signal Scan2. The sixth transistor T6 may be a P-type transistor.

[0145] The driving transistor TDR may be electrically connected between a fifth node N1105 and a sixth node N1106. The fifth node N1105 may be supplied with a driving voltage VDD. The gate node of the driving transistor TDR may be electrically connected to the fourth node N1104. The driving transistor TDR may be a P-type transistor.

[0146] The storage capacitor Cst may be electrically connected between the second node N1102 and the fourth node N1104. The storage capacitor Cst may store a voltage corresponding to the difference between the voltage supplied to the second node N1102 and the voltage supplied to the fourth node N1104.

[0147] The first light-emitting control transistor Ts may be electrically connected between the seventh node N1107 and the eleventh node N1111. The gate node of the first light-emitting control transistor Ts may be electrically connected to the fourteenth node N1114. The first control capacitor C1 may be electrically connected between the fourteenth node N1114 and the first connection node Nc1. Therefore, a voltage stored in the first control capacitor C1 may be supplied to the fourteenth node N1114. The on / off state of the first light-emitting control transistor Ts may be controlled according to the voltage stored in the first control capacitor C1. The first light-emitting control transistor Ts may be a P-type transistor.

[0148] The first light emitting element ED_S may be electrically connected between the eleventh node N1111 and the base voltage VSS. When the first light emitting control transistor Ts is turned on, the first light emitting element ED_S may be supplied with a driving current, and at this time, the first light emitting element ED_S may emit light.

[0149] The second light-emitting control transistor Tp may be electrically connected between the seventh node N1107 and the twelfth node N1112. The gate node of the second light-emitting control transistor Tp may be electrically connected to the thirteenth node N1113. The second control capacitor C2 may be electrically connected between the thirteenth node N1113 and the first connection node Nc1. Therefore, the voltage stored in the second control capacitor C2 may be supplied to the thirteenth node N1113. The on / off state of the second light-emitting control transistor Tp may be controlled according to the voltage stored in the second control capacitor C2. The second light-emitting control transistor Tp may be a P-type transistor.

[0150] The second light emitting element ED_P may be electrically connected between the twelfth node N1112 and the base voltage VSS. When the second light emitting control transistor Tp is in a turned-on state, the second light emitting element ED_P may be supplied with a driving current, and at this time, the second light emitting element ED_P may emit light.

[0151] The first subpixel SP1 shown in Fig. 11 may have a subpixel structure in which internal compensation is performed. The circuit structure of the first subpixel SP1 will be described with reference to Fig. 11, and then the operation of the first subpixel SP1 will be described with reference to Figs. 12 and 13.

[0152] 12 and 13, the period in which the first sub-pixel SP1 is driven may include a first period T1, a second period T2, a third period T3, a fourth period T4, and a fifth period T5.

[0153] The first scan signal Scan1 may be in a high level signal state during the first period T1, the second period T2, the fourth period T4, and the fifth period T5. The first scan signal Scan1 may be in a low level signal state during the third period T3. When the first scan signal Scan1 is in a low level signal state, the first transistor T1 may be turned on to supply the data voltage Vdata to the storage capacitor Cst.

[0154] The second scan signal Scan2 may be in a high level signal state during the first period T1, the fourth period T4, and the fifth period T5. The second scan signal Scan2 may be in a low level signal state during the second period T2 and the third period T3. When the second scan signal Scan2 is in a low level signal state, the initialization voltage Vinit may be supplied to the first sub-pixel SP1, and the driving voltage VDD may be supplied to the storage capacitor Cst.

[0155] The first light-emitting signal EM1 may be in a low-level signal state in the first period T1, the second period T2, and the fifth period T5. The first light-emitting signal EM1 may be in a high-level signal state in the third period T3 and the fourth period T4. When the first light-emitting signal EM1 is in a low-level signal state, the first sub-pixel SP1 can emit light through the light-emitting element.

[0156] The period during which the subpixel SP emits light can include an initialization period, a writing period, a sustain period, and a light emission period.

[0157] 12 and 13, the initialization period may be a second period T2.

[0158] The initialization period may be a period in which an initialization voltage Vinit is supplied to the sub-pixel SP to initialize the sub-pixel SP. During the initialization period, the first scan signal Scan1 may be in a high level signal state, and the second scan signal Scan2 may be in a low level signal state. Also, during the initialization period, the first light-emitting signal EM1 may be in a high level signal state.

[0159] 12 and 13, the write period may be a third period T3.

[0160] The write period may be a period during which a voltage for controlling a driving current flowing through the driving transistor TDR is stored in the storage capacitor Cst. During the write period, the first scan signal Scan1 may be in a low level signal state, and the second scan signal Scan2 may be in a low level signal state. Also, during the write period, the first light emission signal EM1 may be in a high level signal state.

[0161] 12 and 13, the sustain period may be a fourth period T4.

[0162] The sustain period may be a period for controlling the emission of the sub-pixel SP to operate stably. During the sustain period, the first scan signal Scan1 may be in a high-level signal state, the second scan signal Scan2 may be in a high-level signal state, and the first emission signal EM1 may be in a high-level signal state.

[0163] 12 and 13, the light emitting period may be a first period T1 and a fifth period T5. The light emitting period advanced in the fifth period T5 is advanced later than the light emitting period advanced in the first period T1.

[0164] The light-emitting period may be a period during which the light-emitting element included in the subpixel SP emits light. During the light-emitting period, the first scan signal Scan1 may be in a high-level signal state, and the second scan signal Scan2 may be in a high-level signal state. Furthermore, during the light-emitting period, the first light-emitting signal EM1 may be in a low-level signal state.

[0165] During the light emission period, the driving current flowing through the driving transistor TDR may be supplied to the light emitting element, which can emit light with a luminance corresponding to the driving current.

[0166] In the light emitting period, the first sub-pixel SP1 can emit light at a wide angle or a narrow angle according to the signals provided to the first wide angle control line S1 and the first narrow angle control line P1.

[0167] 12, a low-level signal may be supplied to the first wide-angle control line S1, and a high-level signal may be supplied to the first narrow-angle control line P1. Referring to Fig. 9, the first light-emitting element ED_S may emit light, and the first subpixel SP1 may emit light at a wide angle. That is, the region in which the first subpixel SP1 is arranged may be the wide-angle region SA.

[0168] 13, a high level signal may be supplied to the first wide-angle control line S1, and a low level signal may be supplied to the first narrow-angle control line P1. Referring to FIG 10, the second light-emitting element ED_P then emits light, and the first sub-pixel SP1 can emit light at a narrow angle. That is, the region in which the first sub-pixel SP1 is disposed may be the narrow-angle region PA.

[0169] FIG. 14 is a diagram relating to the first sub-pixel SP1 and the first viewing angle control circuit VCC1 according to an embodiment of the present disclosure.

[0170] 14, the first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1, and a second control capacitor C2. The first viewing angle control circuit VCC1 shown in FIG. 14 may be the same as the first viewing angle control circuit VCC1 shown in FIG. 9 and FIG. 10.

[0171] The first sub-pixel SP1 may include a number of transistors, a storage capacitor Cst, and two light emitting elements ED_S and ED_P.

[0172] The first transistor T1 may be electrically connected between the second node N1402 and the first node N1401. A gate node of the first transistor T1 may be electrically connected to a third node N1403. The third node N1403 may be supplied with a second scan signal Scan2. The first node N1401 may be supplied with a data voltage Vdata. The first transistor T1 may be a P-type transistor.

[0173] The second transistor T2 may be electrically connected between a fourth node N1404 and the second node N1402. A driving voltage VDD may be supplied to the fourth node N1404. A gate node of the second transistor T2 may be electrically connected to a fifth node N1405. The fifth node N1405 may be supplied with a first light-emitting signal EM1. The second transistor T2 may be a P-type transistor.

[0174] The third transistor T3 may be electrically connected between the sixth node N1406 and the seventh node N1407. A gate node of the third transistor T3 may be electrically connected to an eighth node N1408. The eighth node N1408 may be supplied with a second scan signal Scan2. The third transistor T3 may be a P-type transistor.

[0175] The fourth transistor T4 may be electrically connected between the seventh node N1407 and the ninth node N1409. A gate node of the fourth transistor T4 may be electrically connected to a tenth node N1410. The tenth node N1410 may be supplied with a first light-emitting signal EM1. The fourth transistor T4 may be a P-type transistor.

[0176] The fifth transistor T5 may be electrically connected between the sixth node N1406 and an eleventh node N1411. The eleventh node N1411 may be supplied with an initialization voltage Vini. A gate node of the fifth transistor T5 may be electrically connected to a twelfth node N1412. The twelfth node N1412 may be supplied with a first scan signal Scan1. The fifth transistor T5 may be a P-type transistor.

[0177] The sixth transistor T6 may be electrically connected between the eleventh node N1411 and the thirteenth node N1413. A gate node of the sixth transistor T6 may be electrically connected to the eighth node N1408. The eighth node N1408 may be supplied with a second scan signal Scan2. The sixth transistor T6 may be a P-type transistor.

[0178] The seventh transistor T7 may be electrically connected between the eleventh node N1411 and the fifteenth node N1415. A gate node of the seventh transistor T7 may be electrically connected to the eighth node N1408. The eighth node N1408 may be supplied with a second scan signal Scan2. The sixth transistor T6 may be a P-type transistor.

[0179] The driving transistor DT may be electrically connected between the second node N1402 and the seventh node N1407. The gate node of the driving transistor TDR may be electrically connected to the sixth node N1406. The driving transistor TDR may be a P-type transistor.

[0180] The storage capacitor Cst may be electrically connected between the fourth node N1404 and the sixth node N1406. The storage capacitor Cst may store a voltage corresponding to the difference between the voltage supplied to the fourth node N1404 and the voltage supplied to the sixth node N1406.

[0181] The first light-emitting control transistor Ts may be electrically connected between the ninth node N1409 and the fifteenth node N1415. The gate node of the first light-emitting control transistor Ts may be electrically connected to the sixteenth node N1416. The first control capacitor C1 may be electrically connected between the sixteenth node N1416 and the first connection node Nc1. Thus, the voltage stored in the first control capacitor C1 may be supplied to the sixteenth node N1416. The on / off state of the first light-emitting control transistor Ts may be controlled according to the voltage stored in the first control capacitor C1. The first light-emitting control transistor Ts may be a P-type transistor.

[0182] The first light emitting element ED_S may be electrically connected between the fifteenth node N1415 and a node to which a base voltage VSS is supplied. When the first light emitting control transistor Ts is in a turned-on state, the first light emitting element ED_S may be supplied with a driving current, and at this time, the first light emitting element ED_S may emit light.

[0183] The second light-emitting control transistor Tp may be electrically connected between the ninth node N1409 and the thirteenth node N1413. The gate node of the second light-emitting control transistor Tp may be electrically connected to the fourteenth node N1414. The second control capacitor C2 may be electrically connected between the fourteenth node N1414 and the first connection node Nc1. Therefore, the voltage stored in the second control capacitor C2 may be supplied to the fourteenth node N1414. The on / off state of the second light-emitting control transistor Tp may be controlled according to the voltage stored in the second control capacitor C2. The second light-emitting control transistor Tp may be a P-type transistor.

[0184] The second light emitting element ED_P may be electrically connected between the fourteenth node N1414 and a node to which a base voltage VSS is supplied. When the second light emitting control transistor Tp is in a turned-on state, the second light emitting element ED_P may be supplied with a driving current, and at this time, the second light emitting element ED_P may emit light.

[0185] FIG. 15 is a diagram relating to the first sub-pixel SP1 and the first viewing angle control circuit VCC1 according to an embodiment of the present disclosure.

[0186] 15, the first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1, and a second control capacitor C2. The first viewing angle control circuit VCC1 shown in FIG. 15 may be the same as the first viewing angle control circuit VCC1 shown in FIG. 9 and FIG. 10.

[0187] The first sub-pixel SP1 may include a number of transistors, a storage capacitor Cst, and two light emitting elements ED_S and ED_P.

[0188] The first transistor T1 may be electrically connected between the second node N1502 and the first node N1501. A gate node of the first transistor T1 may be electrically connected to a third node N1503. The third node N1503 may be supplied with a second scan signal Scan2. The first node N1501 may be supplied with a data voltage Vdata. The first transistor T1 may be a P-type transistor.

[0189] The second transistor T2 may be electrically connected between the fourth node N1504 and the second node N1502. The gate node of the second transistor T2 may be electrically connected to a fifth node N1505. The fifth node N1505 may be supplied with the first light-emitting signal EM1. The second transistor T2 may be a P-type transistor.

[0190] The third transistor T3 may be electrically connected between a sixth node N1506 and a seventh node N1507. A gate node of the third transistor T3 may be electrically connected to an eighth node N1508. The eighth node N1508 may be supplied with a second scan signal Scan2. The third transistor T3 may be a P-type transistor.

[0191] The fourth transistor T4 may be electrically connected between the seventh node N1507 and the ninth node N1509. A gate node of the fourth transistor T4 may be electrically connected to a tenth node N1510. The tenth node N1510 may be supplied with a first light-emitting signal EM1. The fourth transistor T4 may be a P-type transistor.

[0192] The fifth transistor T5 may be electrically connected between the sixth node N1506 and an eleventh node N1511. A gate node of the fifth transistor T5 may be electrically connected to a twelfth node N1512. The twelfth node N1512 may be supplied with a first scan signal Scan1. The fifth transistor T5 may be a P-type transistor.

[0193] The seventh transistor T7 may be electrically connected between the eleventh node N1511 and the thirteenth node N1513. The gate node of the seventh transistor T7 may be electrically connected to the eighth node N1508. The eighth node N1508 may be supplied with a second scan signal Scan2. The seventh transistor T7 may be a P-type transistor.

[0194] The eighth transistor T8 may be electrically connected between the fourth node N1504 and the sixteenth node N1516. The gate node of the eighth transistor T8 may be electrically connected to the fifth node N1505. The fifth node N1505 may be supplied with the first light-emitting signal EM1. The seventh transistor T7 may be a P-type transistor.

[0195] The ninth transistor T9 may be electrically connected between a sixteenth node N1516 and a seventeenth node N1517. The seventeenth node N1517 may be supplied with a reference voltage Vref. A gate node of the ninth transistor T9 may be electrically connected to an eighteenth node N1518. The eighteenth node N1518 may be supplied with a second scan signal Scan2. The ninth transistor T9 may be a P-type transistor.

[0196] The tenth transistor T10 may be electrically connected between a sixteenth node N1516 and a seventeenth node N1517. A gate node of the tenth transistor T10 may be electrically connected to a twelfth node N1512. The twelfth node N1512 may be supplied with a first scan signal Scan1. The tenth transistor T10 may be a P-type transistor.

[0197] The twelfth transistor T12 may be electrically connected between the eleventh node N1511 and the fifteenth node N1515. The fifteenth node N1515 may be supplied with an initialization voltage Vini. A gate node of the twelfth transistor T12 may be electrically connected to an eighth node N1508. The eighth node N1508 may be supplied with a second scan signal Scan2. The twelfth transistor T12 may be a P-type transistor.

[0198] The driving transistor DT may be electrically connected between the second node N1502 and the seventh node N1507. The gate node of the driving transistor TDR may be electrically connected to the sixth node N1506. The driving transistor TDR may be a P-type transistor.

[0199] The storage capacitor Cst may be electrically connected between the fourth node N1504 and the sixth node N1506. The storage capacitor Cst may store a voltage corresponding to the difference between the voltage supplied to the fourth node N1504 and the voltage supplied to the sixth node N1506.

[0200] The first light emission control transistor T11 may be electrically connected between the ninth node N1509 and the nineteenth node N1519. The first light emission control transistor T11 may be the eleventh transistor T11. A gate node of the first light emission control transistor T11 may be electrically connected to the twentieth node N1520. The first control capacitor C1 may be electrically connected between the twentieth node N1520 and the first connection node Nc1. Thus, a voltage stored in the first control capacitor C1 may be supplied to the twentieth node N1520. The on / off state of the first light emission control transistor T11 may be controlled according to the voltage stored in the first control capacitor C1. The first light emission control transistor T11 may be a P-type transistor.

[0201] The first light emitting element ED_S may be electrically connected between the 19th node N1519 and a node to which a base voltage VSS is supplied. When the first light emitting control transistor T11 is turned on, the first light emitting element ED_S may be supplied with a driving current, and at this time, the first light emitting element ED_S may emit light.

[0202] The second light-emitting control transistor T6 may be electrically connected between the ninth node N1509 and the thirteenth node N1513. The second light-emitting control transistor T6 may be a sixth transistor T6. The gate node of the second light-emitting control transistor T6 may be electrically connected to the fourteenth node N1514. The second control capacitor C2 may be electrically connected between the fourteenth node N1514 and the first connection node Nc1. Therefore, the voltage stored in the second control capacitor C2 may be supplied to the fourteenth node N1514. The on / off state of the second light-emitting control transistor T6 may be controlled according to the voltage stored in the second control capacitor C2. The second light-emitting control transistor T6 may be a P-type transistor.

[0203] The second light emitting element ED_P may be electrically connected between the fourteenth node N1514 and a node to which a base voltage VSS is supplied. When the second light emitting control transistor T6 is turned on, the second light emitting element ED_P may be supplied with a driving current, and at this time, the second light emitting element ED_P may emit light.

[0204] FIG. 16 is a diagram relating to the first sub-pixel SP1 and the first viewing angle control circuit VCC1 according to an embodiment of the present disclosure.

[0205] 16, the first viewing angle control circuit VCC1 may include a first viewing angle control transistor Tss, a second viewing angle control transistor Tps, a first control capacitor C1, and a second control capacitor C2. The first viewing angle control circuit VCC1 shown in FIG. 16 may be the same as the first viewing angle control circuit VCC1 shown in FIG. 9 and FIG. 10.

[0206] The first sub-pixel SP1 may include a number of transistors, a storage capacitor Cst, and two light emitting elements ED_S and ED_P.

[0207] The driving transistor DRT may be electrically connected between the second node N1602 and the third node N1603. The gate node of the driving transistor DRT may be electrically connected to the first node N1601.

[0208] The first node N1601 may be electrically connected to a source node or a drain node of the scan transistor SCT. The second node N1602 may be electrically connected to a first electrode E1 of the light emitting elements ED_P and ED_S. The third node N1603 may be electrically connected to a driving line DVL that supplies a driving voltage EVDD.

[0209] The scan transistor SCT can control a connection between a first node N1601 of the drive transistor DRT and a corresponding data line DL among a plurality of data lines DL in response to a scan signal SCAN supplied from a corresponding scan line SCL among a plurality of scan lines SCL, which is a type of gate line GL.

[0210] A drain node or a source node of the scan transistor SCT may be electrically connected to a corresponding data line DL. A source node or a drain node of the scan transistor SCT may be electrically connected to a first node N1601. A gate node of the scan transistor SCT may be electrically connected to a scan line SCL, which is a type of gate line GL, to receive a scan signal SCAN.

[0211] The scan transistor SCT is turned on by a scan signal SCAN having a turn-on level voltage, and can transmit a data voltage Vdata supplied from a corresponding data line DL to a first node N1601.

[0212] The scan transistor SCT is turned on by a scan signal SCAN having a turn-on level voltage and turned off by a scan signal SCAN having a turn-off level voltage. Here, if the scan transistor SCT is an n-type, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. If the scan transistor SCT is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

[0213] The sense transistor SENT can control the connection between the second node N1602 and the initialization voltage line IVL in response to a sense signal SENSE supplied from a corresponding one of a number of sense lines SENL, which are a type of gate line GL.

[0214] The drain node or source node of the sense transistor SENT may be electrically connected to the initialization voltage line IVL. The source node or drain node of the sense transistor SENT may be electrically connected to the second node N1602. The gate node of the sense transistor SENT may be electrically connected to a sense line SENL, which is a type of gate line GL, to receive a sense signal SENSE.

[0215] The sense transistor SENT is turned on, and the initialization voltage Vini supplied from the initialization voltage line IVL can be applied to the second node N1602.

[0216] The sense transistor SENT is turned on by the sense signal SENSE of a turn-on level voltage and turned off by the sense signal SENSE of a turn-off level voltage. Here, if the sense transistor SENT is an n-type, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. If the sense transistor SENT is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

[0217] The emission control transistor EMT can control a connection between the third node N1603 and a corresponding one of the driving lines DVL in response to an emission signal EM supplied from a corresponding one of the emission control lines EML, which is a type of gate line GL. That is, as shown in FIG. 16, the emission control transistor EMT can be electrically connected between the third node N1603 and the driving line DVL.

[0218] The drain node or the source node of the emission control transistor EMT may be electrically connected to the drive line DVL. The source node or the drain node of the emission control transistor EMT may be electrically connected to a third node N1603. The gate node of the emission control transistor EMT may be electrically connected to an emission control line EML, which is a type of gate line GL, and an emission signal EM may be applied to the gate node of the emission control transistor EMT. The emission ratio of the light-emitting elements ED_P, ED_S may be controlled by the duty ratio of the emission signal EM supplied to the gate node of the emission control transistor EMT. The duty ratio may be adjusted by pulse width modulation, etc.

[0219] Alternatively, the emission control transistor EMT can control a connection between the second node N1602 and the first electrodes E1 of the light emitting elements ED_P and ED_S. That is, unlike the case shown in FIG. 16, the emission control transistor EMT can be electrically connected between the second node N1602 and the light emitting elements ED_P and ED_S.

[0220] The light emission control transistor EMT is turned on by the light emission signal EM of a turn-on level voltage and turned off by the light emission signal EM of a turn-off level voltage. Here, if the light emission control transistor EMT is an n-type, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. If the light emission control transistor EMT is a p-type, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

[0221] The storage capacitor Cst is electrically connected between the first node N1601 and the second node N1602, and can maintain a data voltage Vdata corresponding to an image signal voltage or a voltage corresponding thereto for one frame time.

[0222] The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DRT, rather than a parasitic capacitor (e.g., Cgs, Cgd), which is an internal capacitor present between the first node N1601 and the second node N1602.

[0223] Each of the drive transistor DRT, the scan transistor SCT, the sense transistor SENT, and the light emission control transistor EMT may be an n-type transistor or a p-type transistor. All of the drive transistor DRT, the scan transistor SCT, the sense transistor SENT, and the light emission control transistor EMT may be an n-type transistor or a p-type transistor. At least one of the drive transistor DRT, the scan transistor SCT, the sense transistor SENT, and the light emission control transistor EMT may be an n-type transistor (or a p-type transistor), and the others may be p-type transistors (or n-type transistors).

[0224] 16 is merely an example for the purpose of explanation, and the subpixel SP may further include one or more transistors, or in some cases, may further include one or more capacitors. Alternatively, each of the multiple subpixels may have the same structure, and some of the multiple subpixels may have different structures.

[0225] The first emission control transistor Ts may be electrically connected between the second node N1602 and the first emission element ED_S. The gate node of the first emission control transistor Ts may be electrically connected to the fifth connection node Nc5. The first control capacitor C1 may be electrically connected between the fifth connection node Nc5 and the first connection node Nc1. Thus, a voltage stored in the first control capacitor C1 may be supplied to the fifth connection node Nc5. The on / off state of the first emission control transistor Ts may be controlled according to the voltage stored in the first control capacitor C1. The first emission control transistor Ts may be a P-type transistor.

[0226] The first light-emitting element ED_S may be electrically connected between the first light-emitting control transistor Ts and a node to which a base voltage VSS is supplied. When the first light-emitting control transistor Ts is in a turned-on state, the first light-emitting element ED_S may be supplied with a driving current, and at this time, the first light-emitting element ED_S may emit light.

[0227] The second light-emitting control transistor Tp may be electrically connected between the second node N1602 and the second light-emitting element ED_P. The gate node of the second light-emitting control transistor Tp may be electrically connected to the sixth connection node Nc6. The second control capacitor C2 may be electrically connected between the sixth connection node Nc6 and the first connection node Nc1. Therefore, a voltage stored in the second control capacitor C2 may be supplied to the sixth connection node Nc6. The on / off state of the second light-emitting control transistor Tp may be controlled according to the voltage stored in the second control capacitor C2. The second light-emitting control transistor Tp may be a P-type transistor.

[0228] The second light emitting element ED_P may be electrically connected between the sixth connection node Nc6 and a node to which a base voltage VSS is supplied. When the second light emitting control transistor Tp is turned on, the second light emitting element ED_P is supplied with a driving current, and at this time, the second light emitting element ED_P may emit light.

[0229] FIG. 17 is a diagram of a number of sub-pixels SP and a first viewing angle control circuit VCC1 according to an embodiment of the present disclosure.

[0230] 17, the first viewing angle control circuit VCC1 may be electrically connected to three sub-pixels SP_R, SP_G, and SP_B, which may be a red sub-pixel SP_R, a green sub-pixel SP_G, and a blue sub-pixel SP_B.

[0231] One pixel may be composed of a red sub-pixel SP_R, a green sub-pixel SP_G, and a blue sub-pixel SP_B, but this is for convenience of explanation, and one pixel may be composed of sub-pixels of, for example, RGB color, WRGB color, and CMY color.

[0232] The first viewing angle control circuit VCC1 can be electrically connected to each of the red sub-pixel SP_R, the green sub-pixel SP_G, and the blue sub-pixel SP_B.

[0233] The first viewing angle control circuit VCC1 can be electrically connected to the narrow angle control line P and the wide angle control line S.

[0234] The first viewing angle control circuit VCC1 can control the viewing angle of one pixel by simultaneously controlling the three sub-pixels SP_R, SP_G, and SP_B.

[0235] That is, the viewing angle can be controlled on a pixel-by-pixel basis, rather than on a subpixel-by-subpixel basis.

[0236] By controlling the viewing angle of the pixel through the first viewing angle control circuit VCC1, the viewing angles in the left-right direction and the up-down direction may be controlled simultaneously as shown in Fig. 7. Although Fig. 7 shows one narrow-angle area PA, the narrow-angle area PA may be controlled to have two or more narrow-angle areas PA.

[0237] The display device 100 can be applied to televisions, smartphones, tablet PCs, vehicles, etc. In particular, when the display device 100 is an in-vehicle display device applied to a vehicle, a user sitting in an auxiliary seat instead of the driver's seat can control the narrow-angle area PA so that a display image close to the auxiliary seat is displayed only in the auxiliary seat. The auxiliary seat described above is an example, and the narrow-angle area PA can be set in any area of ​​the in-vehicle display device.

[0238] As described above, the embodiments of the present disclosure can provide a display device in which the viewing angle of a specific region of a display panel can be controlled.

[0239] The embodiments of the present disclosure can provide a display device in which the viewing angles in the left-right direction and the up-down direction can be controlled simultaneously.

[0240] The embodiments of the present disclosure can provide a display device capable of consuming low power through flexible viewing angle control, as will be described in detail below.

[0241] An embodiment of the present disclosure may provide a display device including a first viewing angle control circuit, a first narrow angle control line electrically connected to the first viewing angle control circuit, a first wide angle control line electrically connected to the first viewing angle control circuit, and a first subpixel electrically connected to the first viewing angle control circuit.

[0242] The first subpixel may include a first light-emitting element, a second light-emitting element different from the first light-emitting element, a driving transistor for driving the first light-emitting element or the second light-emitting element, a first light-emitting control transistor electrically connected between the driving transistor and the first light-emitting element, and a second light-emitting control transistor electrically connected between the driving transistor and the second light-emitting element.

[0243] The first viewing angle control circuit may include a first viewing angle control transistor electrically connected between the first narrow angle control line and the first control capacitor, and a second viewing angle control transistor electrically connected between the first wide angle control line and the second control capacitor, wherein the first viewing angle control transistor is electrically connected to a gate node of the first light-emitting control transistor, and the second viewing angle control transistor is electrically connected to a gate node of the second light-emitting control transistor.

[0244] When a high level signal is supplied to the first controlled capacitor, a low level signal may be supplied to the second controlled capacitor, and when a high level signal is supplied to the second controlled capacitor, a low level signal may be supplied to the first controlled capacitor.

[0245] A control reference voltage may be supplied to a node shared by the first controlled capacitor and the second controlled capacitor.

[0246] The high level signal may be greater than the control reference voltage, and the low level signal may be less than the control reference voltage.

[0247] When the first light-emitting control transistor is turned on, the second light-emitting control transistor may be turned off, and when the second light-emitting control transistor is turned on, the first light-emitting control transistor may be turned off.

[0248] When the first light-emitting control transistor is turned on, the first light-emitting element can emit light, and when the second light-emitting control transistor is turned on, the second light-emitting element can emit light.

[0249] A viewing angle of the light emitted from the first light emitting element may be wider than a viewing angle of the light emitted from the second light emitting element.

[0250] The first viewing angle control circuit may be electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0251] The viewing angles of the light emitted from the first sub-pixel, the second sub-pixel, and the third sub-pixel may be the same.

[0252] The first narrow-angle control line and the first wide-angle control line may be electrically connected to a first pixel circuit and a second pixel circuit.

[0253] A first pixel circuit may include the first viewing angle control circuit and a first sub-pixel, and a viewing angle of light emitted from the first pixel circuit may be narrower than a viewing angle of light emitted from the second pixel circuit.

[0254] The second narrow-angle control line and the second wide-angle control line are electrically connected to a third pixel circuit, and a viewing angle of light emitted from the first pixel circuit may be narrower than a viewing angle of light emitted from the third pixel circuit.

[0255] After the first viewing angle control circuit included in the first pixel circuit is controlled, a second viewing angle control circuit included in the second pixel circuit may be controlled.

[0256] The first subpixel may be arranged in a first row, and a second subpixel different from the first subpixel may be arranged in a second row different from the first row, and after a viewing angle of the first row subpixel arranged in the first row is controlled, a viewing angle of the second row subpixel arranged in the second row may be controlled.

[0257] The first subpixel may include a first transistor electrically connected between a node to which a data voltage is supplied and a first electrode of a storage capacitor, a second transistor electrically connected between a second electrode of the storage capacitor and the driving transistor, a third transistor electrically connected between the first electrode and an initialization node to which an initialization voltage is supplied, a fourth transistor electrically connected to the driving transistor, a fifth transistor electrically connected between the initialization node and the first emission control transistor, and a sixth transistor electrically connected between the initialization node and the second emission control transistor.

[0258] The gate node of the first transistor may be supplied with a first scan signal, the gate node of the second transistor and the gate node of the fifth transistor may be supplied with a second scan signal, and the gate node of the third transistor and the gate node of the fourth transistor may be supplied with an emission signal.

[0259] The period during which the first sub-pixel is driven may include an initialization period during which the initialization voltage is supplied to the first sub-pixel, a writing period during which the data voltage is supplied to the storage capacitor, and an emission period during which the first light-emitting element or the second light-emitting element emits light.

[0260] An embodiment of the present disclosure can provide a display panel including a first pixel circuit electrically connected to a first narrow angle control line and a first wide angle control line, a second pixel circuit electrically connected to the first narrow angle control line and the first wide angle control line, and a third pixel circuit electrically connected to a second narrow angle control line and a second wide angle control line, wherein the viewing angle of light output from the second pixel circuit and the third pixel circuit is a wide angle, and the viewing angle of light output from the first pixel circuit is a narrow angle.

[0261] The above description is merely an illustrative example of the technical idea of ​​the present disclosure, and various modifications and variations are possible within the scope of the essential characteristics of the present disclosure if one has ordinary knowledge in the technical field to which the present disclosure pertains. In addition, the examples disclosed in the present disclosure are intended to explain the technical idea of ​​the present disclosure, rather than to limit it, and therefore the scope of the technical idea of ​​the present disclosure is not limited by such examples. [Explanation of symbols]

[0262] 100:Display device 110: Display panel 120: Data driving circuit 130: Gate drive circuit 140: Controller

Claims

1. A first viewing angle control circuit; a first narrow angle control line electrically connected to the first viewing angle control circuit; a first wide-angle control line electrically connected to the first viewing angle control circuit; a first subpixel electrically connected to the first viewing angle control circuit.

2. The first subpixel is A first light-emitting element; A second light emitting element different from the first light emitting element; a driving transistor for driving the first light emitting element or the second light emitting element; a first light-emitting control transistor electrically connected between the driving transistor and the first light-emitting element; The display device according to claim 1 , further comprising: a second light-emitting control transistor electrically connected between the driving transistor and the second light-emitting element.

3. The first viewing angle control circuit is a first viewing angle control transistor electrically connected between the first narrow angle control line and a first control capacitor; a second viewing angle control transistor electrically connected between the first wide angle control line and the second control capacitor, the first viewing angle control transistor is electrically connected to a gate node of the first light emission control transistor, The display device according to claim 2 , wherein the second viewing angle control transistor is electrically connected to a gate node of the second emission control transistor.

4. When a high level signal is supplied to the first control capacitor, a low level signal is supplied to the second control capacitor; The display device according to claim 3 , wherein when a high level signal is supplied to the second control capacitor, a low level signal is supplied to the first control capacitor.

5. The display device of claim 4 , wherein a control reference voltage is provided to a node shared by the first control capacitor and the second control capacitor.

6. the high level signal is greater than the control reference voltage; The display device according to claim 5 , wherein the low level signal is smaller than the control reference voltage.

7. When the first light-emitting control transistor is turned on, the second light-emitting control transistor is turned off; The display device according to claim 2 , wherein when the second light-emitting control transistor is turned on, the first light-emitting control transistor is turned off.

8. When the first light-emitting control transistor is turned on, the first light-emitting element emits light; The display device according to claim 7 , wherein the second light-emitting element emits light when the second light-emitting control transistor is turned on.

9. The display device according to claim 2 , wherein a viewing angle of the light emitted from the first light emitting element is wider than a viewing angle of the light emitted from the second light emitting element.

10. The display device of claim 1 , wherein the first viewing angle control circuit is electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel.

11. The display device of claim 10 , wherein the viewing angles of the light emitted from the first sub-pixel, the second sub-pixel, and the third sub-pixel are the same.

12. The display device of claim 1 , wherein the first narrow-angle control line and the first wide-angle control line are electrically connected to a first pixel circuit and a second pixel circuit.

13. the first pixel circuit includes the first viewing angle control circuit and the first subpixel; The display device according to claim 12 , wherein a viewing angle of the light emitted from the first pixel circuit is narrower than a viewing angle of the light emitted from the second pixel circuit.

14. the second narrow-angle control line and the second wide-angle control line are electrically connected to the third pixel circuit; The display device according to claim 12 , wherein a viewing angle of the light emitted from the first pixel circuit is narrower than a viewing angle of the light emitted from the third pixel circuit.

15. The display device according to claim 12 , wherein a second viewing angle control circuit included in the second pixel circuit is controlled after the first viewing angle control circuit included in the first pixel circuit is controlled.

16. The first subpixel is disposed in a first row, a second subpixel different from the first subpixel is disposed in a second row different from the first row; The display device of claim 1 , wherein a viewing angle of the first sub-pixel arranged in the first row is controlled, and then a viewing angle of the second sub-pixel arranged in the second row is controlled.

17. The first subpixel is a first transistor electrically connected between a node to which a data voltage is supplied and a first electrode of the storage capacitor; a second transistor electrically connected to the second electrode of the storage capacitor and the driving transistor; a third transistor electrically connected between the first electrode and an initialization node to which an initialization voltage is supplied; a fourth transistor electrically connected to the driving transistor; a fifth transistor electrically connected between the initialization node and the first light emission control transistor; The display device according to claim 2 , further comprising: a sixth transistor electrically connected between the initialization node and the second light-emission control transistor.

18. a first scan signal is supplied to a gate node of the first transistor; a second scan signal is supplied to a gate node of the second transistor and a gate node of the fifth transistor; The display device according to claim 17 , wherein a light emission signal is supplied to a gate node of the third transistor and a gate node of the fourth transistor.

19. The period during which the first sub-pixel is driven is an initialization period in which the initialization voltage is supplied to the first sub-pixel; a write period during which the data voltage is supplied to the storage capacitor; The display device according to claim 18 , further comprising a light emitting period during which the first light emitting element or the second light emitting element emits light.

20. a first pixel circuit electrically connected to the first narrow-angle control line and the first wide-angle control line; a second pixel circuit electrically connected to the first narrow-angle control line and the first wide-angle control line; a third pixel circuit electrically connected to the second narrow-angle control line and the second wide-angle control line; A display panel, wherein a viewing angle of the light emitted from the second pixel circuit and the third pixel circuit is a wide angle, and a viewing angle of the light emitted from the first pixel circuit is a narrow angle.

Images