Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device including a vertical structure including a plurality of plug patterns, and a manufacturing method thereof.SOLUTION: The present technique relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a gate stacked structure GST including insulating films ILD and conductive films CP stacked alternately with each other; a first plug pattern PP1 and a second plug pattern PP2 extending in a vertical direction Z corresponding to a stacking direction of the gate stacked structure GST; first data storage films DS1 disposed between the first plug pattern PP1 and the conductive films CP and second data storage films DS2 disposed between the second plug pattern PP2 and the conductive films CP; an isolation structure SS extending in the vertical direction Z and separating the first plug pattern PP1 and the second plug pattern PP2 from each other; and insulating patterns IP disposed between the first data storage films DS1 adjacent to each other in the vertical direction Z and the second data storage films DS2 adjacent to each other in the vertical direction Z.SELECTED DRAWING: Figure 1a

Description

[Technical field]

[0001] The present invention relates to electronic devices, and more particularly to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Non-volatile memory devices are memory devices that retain stored data even when the power supply is cut off. Recently, as the integration density of two-dimensional non-volatile memory devices, in which memory cells are formed in a single layer on a substrate, has reached its limit, three-dimensional non-volatile memory devices, in which memory cells are stacked vertically on a substrate, have been proposed.

[0003] A three-dimensional non-volatile memory element includes an interlayer insulating film and a gate electrode that are alternately stacked, and a channel film that penetrates them, and memory cells are stacked along the channel film. In order to improve the operational reliability of non-volatile memory elements having such a three-dimensional structure, various structures and manufacturing methods have been developed. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE DISCLOSURE Embodiments of the present invention provide a semiconductor device including a vertical structure that includes a plurality of plug patterns and a method for fabricating the same. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment of the present invention includes a gate stack structure including alternating insulating films and conductive films, a first plug pattern and a second plug pattern extending in a vertical direction which is a stacking direction of the gate stack structure, a first data storage film disposed between the first plug pattern and the conductive film and a second data storage film disposed between the second plug pattern and the conductive film, an isolation structure extending in the vertical direction to separate the first plug pattern and the second plug pattern from each other, and an insulating pattern disposed between the first data storage film adjacent in the vertical direction and the second data storage film adjacent in the vertical direction.

[0006] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are stacked crossing each other, etching a sidewall of the first material film exposed through the hole to a certain thickness to form a recess area, and forming a sacrificial film in the recess area, oxidizing the sacrificial film to form an insulating pattern that protrudes further toward the hole than the sidewall of the second material film, forming a data storage film in a space between the insulating patterns vertically adjacent to each other, forming a plug pattern in the hole extending in the vertical direction, and forming an isolation structure that penetrates the plug pattern in the vertical direction to separate the plug pattern into a first plug pattern and a second plug pattern.

[0007] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are stacked crossing each other, forming a protruding pattern on a sidewall of the second material film exposed through the hole, forming an insulating pattern in a space between vertically adjacent ones of the protruding patterns, the insulating pattern protruding further in a direction toward the hole than the sidewall of the protruding pattern, forming a data storage layer in the space between vertically adjacent ones of the insulating patterns, forming a plug pattern extending in the vertical direction within the hole, and forming an isolation structure penetrating the plug pattern in the vertical direction to separate the plug pattern into a first plug pattern and a second plug pattern.

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are stacked crosswise, forming an insulating pattern on a sidewall of the first material film exposed through the hole, forming a data storage film in a space between vertically adjacent insulating patterns, forming a plug pattern extending in the vertical direction within the hole, and forming an isolation structure penetrating the plug pattern in the vertical direction to separate the plug pattern into a first plug pattern and a second plug pattern.

[0009] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: forming an elliptical hole at least partially penetrating a stack structure in which a first material film and a second material film are stacked crossing each other; etching a sidewall of the first material film exposed through the hole to a certain thickness to form a recess region; forming a sacrificial film in the recess region; oxidizing the sacrificial film to form an insulating pattern protruding further toward the hole than a sidewall of the second material film; forming a data storage film in a space between the insulating patterns adjacent in a vertical direction; and forming a trough extending in the vertical direction on a sidewall of the hole. the step of sequentially forming a tunnel insulating film and a channel film, the channel film being formed so that a cross-sectional thickness in a first horizontal direction is thicker than a cross-sectional thickness in a second horizontal direction perpendicular to the first horizontal direction; etching the channel film to a certain thickness to form a first channel film and a second channel film bisected in the first horizontal direction, exposing a portion of the tunnel insulating film between the first channel film and the second channel film; and sequentially etching the exposed tunnel insulating film and the data storage film to bisect the tunnel insulating film and the data storage film in the first horizontal direction.

[0010] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes forming a stack structure in which a first material film and a second material film are stacked crossing each other, forming a first isolation pattern vertically penetrating the stack structure and extending in a first horizontal direction, forming a hole penetrating the stack structure and the first isolation pattern, etching a sidewall of the first material film exposed through the hole to a certain thickness to form a recess region and forming a sacrificial film in the recess region, oxidizing the sacrificial film to form an insulating pattern that protrudes further in the hole direction than a sidewall of the second material film, forming a data storage film in a space between the insulating patterns vertically adjacent to each other, sequentially forming a tunnel insulating film, a channel film, and a core insulating film on sidewalls of the hole extending in the vertical direction, and forming a second isolation pattern that penetrates the tunnel insulating film, the channel film, and the core insulating film in the vertical direction to separate the channel film into a first channel film and a second channel film.

[0011] a first isolation pattern extending in a first horizontal direction through the stack structure; forming a hole through the stack structure and the first isolation pattern; etching a sidewall of the first material film exposed through the hole to a certain thickness to form a first recess area and forming a sacrificial film in the first recess area; oxidizing the sacrificial film to form an insulating pattern protruding further toward the hole than a sidewall of the second material film; forming a data storage film in a space between the insulating patterns adjacent in the vertical direction; sequentially forming a tunnel insulating film, a channel film, and a core insulating film on sidewalls of the hole extending in the vertical direction; removing the first isolation pattern to form a second recess area; and etching the tunnel insulating film and the channel film exposed through the second recess area to separate the channel film into a first channel film and a second channel film spaced apart from each other.

[0012] a first isolation pattern extending in a first horizontal direction through the stack structure; forming a hole through the stack structure and the first isolation pattern; etching a sidewall of the first material film exposed through the hole to a certain thickness to form a first recess region and forming a sacrificial film in the first recess region; oxidizing the sacrificial film to form an insulating pattern protruding further toward the hole than a sidewall of the second material film; forming a data storage film in a space between the insulating patterns adjacent in the vertical direction; sequentially forming a tunnel insulating film, a channel film, and a core insulating film on sidewalls of the hole, the tunnel insulating film extending in the vertical direction, and a core insulating film on sidewalls of the hole; removing the first isolation pattern to form a second recess region; and performing a wet oxidation process through the second recess region to oxidize a portion of the channel film adjacent to the second recess region to form a channel isolation structure.

[0013] A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are stacked crossing each other; forming a first isolation pattern and a second isolation pattern in contact with an interface between a first sidewall and a second sidewall of the hole facing each other and extending in a vertical direction; forming an insulating pattern on a sidewall of the first material film exposed through the hole; removing the first isolation pattern and the second isolation pattern and forming a data storage film in a space between the insulating patterns vertically adjacent to the first sidewall and the second sidewall; sequentially forming a tunnel insulating film, a channel film, and a core insulating film along a sidewall of the hole; performing an etching process to expose a sidewall of the stack structure; removing the exposed second material film to form a recess region; and performing a wet oxidation process through the recess region to oxidize a portion of the channel film adjacent to the recess region to form a channel isolation structure. Effect of the Invention

[0014] The present technique can increase the number of memory cells by isolating multiple plug patterns from each other with an isolation pattern. [Brief description of the drawings]

[0015] [Figure 1a] 1A and 1B are a cross-sectional view and a plan view for explaining a semiconductor device according to an embodiment of the present invention; [Figure 1b] 1A and 1B are a cross-sectional view and a plan view for explaining a semiconductor device according to an embodiment of the present invention; [Figure 1c] 1A and 1B are a cross-sectional view and a plan view for explaining a semiconductor device according to an embodiment of the present invention; [Figure 2a] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2b] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2c] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2d] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2e] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2f] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2g] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2h] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 2i] 1A and 1B are cross-sectional and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 3a] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 3b] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 3c] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 3d] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 3e] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 3f] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 3g] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 4a] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 4b] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 4c] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 4d] 11A to 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5a] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5b] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5c] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5d] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5e] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5f] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5g] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5h] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5i] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5j] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5k] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5l] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 5m] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6a] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6b] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6c] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6d] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6e] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6f] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6g]13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6h] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6i] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6j] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 6k] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 7a] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 7b] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 7c] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 7d] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 7e] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 7f] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 8a] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 8b] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 8c] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 8d] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 8e]13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 8f] 13 is a plan view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. [Figure 9a] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9b] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9c] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9d] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9e] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9f] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9g] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9h] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9i] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9j] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9k] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9l] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9m] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9n] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9o] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9p] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9q] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9r] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9s] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9t] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9u] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9v] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9w] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9x] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 9y] 13A and 13B are cross-sectional and plan views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. [Figure 10] 1 is a block diagram illustrating a memory system including a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Specific structural or functional descriptions of embodiments in accordance with the inventive concepts disclosed in this specification or application are provided solely for purposes of illustrating embodiments in accordance with the inventive concepts, which may be embodied in various forms and should not be construed as being limited to the embodiments described in this specification or application.

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, in order to provide a detailed description of the present invention to the extent that those skilled in the art can easily implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

[0018] 1a, 1b and 1c are a cross-sectional view and a plan view for explaining a semiconductor device according to an embodiment of the present invention.

[0019] FIG. 1a is a cross-sectional view of the semiconductor device, FIG. 1b is a plan view at one conductive film CP level, and FIG. 1c is a plan view at one interlayer dielectric film ILD level.

[0020] 1a, 1b, and 1c, the gate stack structure GST disposed on the substrate SUB may include a conductive film CP and an interlayer dielectric film ILD that are alternately stacked. The conductive film CP may be a gate electrode of a selection transistor, a memory cell, or the like. The conductive film CP may be a selection line connected to a selection transistor, or a word line connected to a memory cell. The conductive film CP may include a conductive material such as polysilicon, tungsten, or a metal. The interlayer dielectric film ILD is for insulating the stacked conductive films CP from each other. The interlayer dielectric film ILD may include an insulating material such as an oxide or a nitride. The conductive film CP may have a structure in which a side portion thereof protrudes further toward the first plug pattern PP1 or the second plug pattern PP2 compared to the interlayer dielectric film ILD. An insulating pattern IP is disposed on a sidewall of the interlayer dielectric film ILD adjacent to the first plug pattern PP1 or the second plug pattern PP2, and the insulating pattern IP may have a structure in which a side portion thereof protrudes further toward the first plug pattern PP1 or the second plug pattern PP2 compared to the conductive film CP.

[0021] The first plug pattern PP1 and the second plug pattern PP2 may extend through the gate stack structure GST in a first direction Z that is perpendicular to the substrate SUB. That is, the first plug pattern PP1 and the second plug pattern PP2 may extend in a stacking direction of the gate stack structure GST. The stacking direction of the gate stack structure GST may be defined as a stacking direction of the conductive films CP and the interlayer insulating films ILD that are alternately stacked in the gate stack structure GST.

[0022] The first plug pattern PP1 may include a first tunnel insulating film TI1, a first channel film CH1, and a first core insulating film CO1.

[0023] The first core insulating film CO1 extends in the first direction Z and may include an insulating material such as an oxide. An inner wall of the first core insulating film CO1 may be in contact with the isolation structure SS. The first channel film CH1 extends in the first direction Z in contact with an outer wall of the first core insulating film CO1 and may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene. The first tunnel insulating film TI1 extends in the first direction Z in contact with an outer wall of the first channel film CH1 and may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0024] The second plug pattern PP2 may include a second tunnel insulating film TI2, a second channel film CH2, and a second core insulating film CO2.

[0025] The second core insulating film CO2 extends in the first direction Z and may include an insulating material such as an oxide. An inner wall of the second core insulating film CO2 may be in contact with the isolation structure SS. The second channel film CH2 extends in the first direction Z in contact with an outer wall of the second core insulating film CO2 and may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene. The second tunnel insulating film TI2 extends in the first direction Z in contact with an outer wall of the second channel film CH2 and may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0026] An isolation structure SS is disposed between the first plug pattern PP1 and the second plug pattern PP2, and the isolation structure SS extends in a first direction Z and may include an insulating material such as an oxide. The first plug pattern PP1 and the second plug pattern PP2 may have a symmetrical structure with respect to the isolation structure SS. For example, the first plug pattern PP1 and the second plug pattern PP2 may have a symmetrical structure with respect to a second direction X, which is a horizontal direction.

[0027] The isolation structure SS extends in a first direction Z to physically and electrically isolate the first plug pattern PP1 and the second plug pattern PP2 from each other. The isolation structure SS may also extend in a third direction Y, which is a horizontal direction perpendicular to the second direction X. For example, the isolation structure SS may extend in the third direction Y to physically and electrically isolate the first data storage film DS1 and the second data storage film DS2 from each other. The isolation structure SS may also penetrate the blocking insulating film BI in the third direction Y.

[0028] Although not shown, the isolation structure SS can extend further in the third direction Y to penetrate the conductive film CP in the third direction Y.

[0029] A blocking insulating film BI and a data storage film DS1 or DS2 may be disposed between the conductive film CP and the first plug pattern PP1 and second plug pattern PP2. For example, the first data storage film DS1 may be disposed in a space between the insulating patterns IP adjacent to each other in the first direction Z and between the first plug pattern PP1 and the conductive film CP, and the blocking insulating film BI may be disposed to contact the upper and lower surfaces of the first data storage film DS1 and the sidewall of the first data storage film DS1 adjacent to the conductive film CP. Also, the second data storage film DS2 may be disposed in a space between the insulating patterns IP adjacent to each other in the first direction Z and between the second plug pattern PP2 and the conductive film CP, and the blocking insulating film BI may be disposed to contact the upper and lower surfaces of the second data storage film DS2 and the sidewall of the second data storage film DS2 adjacent to the conductive film CP. Also, the blocking insulating film BI may be disposed to extend between the insulating pattern IP and the first tunnel insulating film TI1. That is, the blocking insulating film BI may surround the upper and lower surfaces of the insulating pattern IP and extend to the interface between the insulating pattern IP and the first plug pattern PP1 and the interface between the insulating pattern IP and the second plug pattern PP2.

[0030] The blocking insulating film BI may include a high dielectric film. The data storage film DS may include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0031] 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, and 2i are cross-sectional views and plan views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] Referring to Fig. 2a, a stacked structure ST is formed on a substrate SUB. The stacked structure ST may include a first material film 11 and a second material film 12 that are alternately stacked. The first and second material films 11 and 12 may be stacked in a vertical direction on the substrate SUB. The first and second material films 11 and 12 may be formed using a deposition process such as CVD (Chemical Vapor Deposition).

[0033] The first material film 11 may include a material having a high etching selectivity relative to the second material film 12. As one example, the first material film 11 may include an insulating material such as an oxide, and the second material film 12 may include a sacrificial material such as a nitride. As another example, the first material film 11 may include an insulating material such as an oxide, and the second material film 12 may include a conductive material such as polysilicon or tungsten.

[0034] Next, a hard mask pattern (not shown) may be formed on the stacked structure ST, and an etching process may be performed using the hard mask pattern to form a hole H at least partially penetrating the stacked structure ST. The hole H may extend partially into the substrate SUB.

[0035] 2b, the first material film 11 exposed through the hole H is etched to a certain depth in the horizontal direction to form a recess region R. That is, the sidewall of the first material film 11 is etched to a certain depth so that the second material film 12 protrudes compared to the first material film 11 in the horizontal direction.

[0036] Referring to FIG. 2c, a sacrificial pattern 13 is formed in the recessed region (R in FIG. 2b). The sacrificial pattern 13 may be formed of a polysilicon film or a silicon nitride film. For example, a polysilicon film or a silicon nitride film is formed along the sidewall of the hole H so that the recessed region (R in FIG. 2b) is completely filled. Then, an etch-back process is performed so that the sidewall of the second material film 12 is exposed, leaving the polysilicon film or the silicon nitride film only in the recessed region (R in FIG. 2b), thereby forming the sacrificial pattern 13.

[0037] Referring to Fig. 2d, an oxidation process is performed to selectively oxidize the sacrificial pattern (13 in Fig. 2c) to form an insulating pattern 14. The insulating pattern 14 may be formed to have a protruding portion protruding in the direction of the hole H. As a result, a space S may be formed between the protruding portions of the insulating pattern 14 adjacent to each other in the first direction Z. As a result, an uneven portion may be formed on the sidewall of the hole H.

[0038] Referring to Fig. 2e, a blocking insulating film 15 is formed along the sidewall of the hole H. The blocking insulating film 15 may be formed along the surface of the protruding portion of the insulating pattern 14 and the sidewall of the second material film 12. The blocking insulating film 15 may include a high dielectric constant film. For example, the blocking insulating film 15 may be formed to include a high dielectric constant material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), hafnium silicon oxide (HfSiOx), etc.

[0039] Thereafter, the data storage film 16 is formed in the space (S in FIG. 2d). For example, after forming the data storage film 16 along the sidewall of the blocking insulating film 15, an etch-back process can be performed to leave the data storage film 16 only in the space (S in FIG. 2d). As a result, the blocking insulating film 15 in contact with the sidewall of the insulating pattern 14 can be exposed through the hole H. The data storage film 16 can include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0040] 2f, a tunnel insulating film 17 may be formed along a sidewall of the data storage film 16 exposed through the hole (H in FIG. 2e) and a sidewall of the blocking insulating film 15. The tunnel insulating film 17 may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0041] Thereafter, a channel film 18 is formed on a sidewall of the tunnel insulating film 17. The channel film 18 may be formed of a semiconductor material. In one embodiment, the channel film 18 may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene.

[0042] Then, a core insulating film 19 may be formed to fill the center of the hole. The core insulating film 19 may be made of an insulating material such as an oxide film.

[0043] FIG. 2g is a cross-sectional view of the first level h1-h1' of FIG. 2f. FIG. 2h is a cross-sectional view of the second level h2-h2' of FIG. 2f. Referring to FIG. 2g and FIG. 2h, an etching process is performed to form a linear trench penetrating the core insulating film 19, the channel film 18, the tunnel insulating film 17, the data storage film 16, and the blocking insulating film 15 formed inside the hole in the first direction Z, and the trench is filled with an insulating material to form an isolation structure 20. The isolation structure 20 may extend in the third direction Y. In another embodiment, the isolation structure 20 may extend in the third direction Y to penetrating the core insulating film 19, the channel film 18, the tunnel insulating film 17, the data storage film 16, the blocking insulating film 15, the first material film 11, and the second material film 12, and may be bisected symmetrically in the second direction X.

[0044] Referring to FIG 2i, an etching process is performed to expose the sidewalls of the stack (ST in FIG 2f), and the exposed second material film (12 in FIG 2f) is removed. Then, a third material film 21 is formed in the space from which the second material film was removed. The third material film 21 may include a conductive material such as polysilicon, tungsten, or a metal. The first material film 11 and the third material film 21 may be defined as a gate stack structure GST.

[0045] 3a, 3b, 3c, 3d, 3e, 3f and 3g are cross-sectional views and plan views for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0046] Referring to Fig. 3a, a stacked structure ST is formed on a substrate SUB. The stacked structure ST may include a first material film 31 and a second material film 32 that are alternately stacked. The first and second material films 31 and 32 may be stacked in a direction perpendicular to the substrate SUB. The first and second material films 31 and 32 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0047] The first material film 31 may include a material having a high etching selectivity relative to the second material film 32. As an example, the first material film 31 may include an insulating material such as an oxide, and the second material film 32 may include a sacrificial material such as a nitride. As another example, the first material film 31 may include an insulating material such as an oxide, and the second material film 32 may include a conductive material such as polysilicon or tungsten.

[0048] Next, a hard mask pattern (not shown) may be formed on the stacked structure ST, and an etching process may be performed using the hard mask pattern to form a hole H at least partially penetrating the stacked structure ST. The hole H may extend partially into the substrate SUB.

[0049] 3b, protruding patterns 33 are formed on sidewalls of the second material film 32 exposed through the holes H. For example, the protruding patterns 33 may be formed on the sidewalls of the second material film 32 by performing a selective deposition process. As a result, a first space S1 is formed between the protruding patterns 33 adjacent to each other in the first direction Z. The protruding patterns 33 may be formed of the same material as the second material film 32.

[0050] Referring to FIG. 3c, an insulating pattern 34 may be formed in the first space (S1 in FIG. 3b). For example, a polysilicon film or a silicon nitride film may be formed along the sidewall of the hole H so that the first space (S1 in FIG. 3b) is completely filled. Then, an etch-back process may be performed so that the sidewall of the protruding pattern 33 is exposed, and the polysilicon film or the silicon nitride film may remain only in the first space (S1 in FIG. 3b), forming a sacrificial pattern. Then, an oxidation process may be performed to selectively oxidize the sacrificial pattern, forming the insulating pattern 34. The insulating pattern 34 may be formed to have a protruding portion protruding in the direction of the hole H. As a result, a second space S2 may be formed between the protruding portions of the insulating patterns 34 adjacent to each other in the first direction Z. As a result, an uneven portion may be formed on the sidewall of the hole H.

[0051] Referring to Fig. 3d, a blocking insulating film 35 is formed along the sidewall of the hole (H of 3c). The blocking insulating film 35 may be formed along the surface of the protruding portion of the insulating pattern 34 and the sidewall of the protruding pattern 33. The blocking insulating film 35 may include a high dielectric constant film. For example, the blocking insulating film 35 may be formed to include a high dielectric constant material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), hafnium silicon oxide (HfSiOx), etc.

[0052] Thereafter, the data storage film 36 is formed in the second space (S2 in FIG. 3c). For example, after forming the data storage film 36 along the sidewall of the blocking insulating film 35, an etch-back process can be performed to leave the data storage film 36 only in the second space (S2 in FIG. 3c). As a result, the blocking insulating film 35 in contact with the sidewall of the insulating pattern 34 can be exposed through the hole (H in FIG. 3c). The data storage film 36 can include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0053] Then, a tunnel insulating film 37 may be formed along the sidewall of the data storage film 36 exposed through the hole and the sidewall of the blocking insulating film 35. The tunnel insulating film 37 may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0054] Thereafter, a channel film 38 is formed on a sidewall of the tunnel insulating film 37. The channel film 38 may be formed of a semiconductor material. In one embodiment, the channel film 38 may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene.

[0055] Then, a core insulating film 39 may be formed to fill the center of the hole. The core insulating film 39 may be made of an insulating material such as an oxide film.

[0056] FIG. 3e is a cross-sectional view of the first level h1-h1' of FIG. 3d. FIG. 3f is a cross-sectional view of the second level h2-h2' of FIG. 3d. Referring to FIG. 3e and FIG. 3f, an etching process is performed to form a linear trench penetrating the core insulating film 39, the channel film 38, the tunnel insulating film 37, the data storage film 36, and the blocking insulating film 35 formed inside the hole in the first direction Z, and the trench is filled with an insulating material to form an isolation structure 40. The isolation structure 40 may extend in the third direction Y. In another embodiment, the isolation structure 40 may extend in the third direction Y to penetrating the core insulating film 39, the channel film 38, the tunnel insulating film 37, the data storage film 36, the blocking insulating film 35, the first material film 31, and the second material film 32, and may be bisected symmetrically in the second direction X.

[0057] Referring to Fig. 3g, an etching process is performed to expose the sidewalls of the stack (ST in Fig. 3d), and the exposed second material film (32 in Fig. 3d) is removed, and the exposed protruding pattern (33 in Fig. 3d) is removed. Then, a third material film 41 is formed in the space where the second material film and the protruding pattern have been removed. The third material film 41 may include a conductive material such as polysilicon, tungsten, metal, etc. The first material film 31 and the third material film 41 may be defined as a gate stack structure GST.

[0058] 4a, 4b, 4c and 4d are cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0059] 4a, a stacked structure ST is formed on a substrate SUB. The stacked structure ST may include a first material film 51 and a second material film 52 that are alternately stacked. The first and second material films 51 and 52 may be stacked in a direction perpendicular to the substrate SUB. The first and second material films 51 and 52 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0060] The first material film 51 may include a material having a high etching selectivity relative to the second material film 52. As an example, the first material film 51 may include an insulating material such as an oxide, and the second material film 52 may include a sacrificial material such as a nitride. As another example, the first material film 51 may include an insulating material such as an oxide, and the second material film 52 may include a conductive material such as polysilicon or tungsten.

[0061] Next, a hard mask pattern (not shown) may be formed on the stacked structure ST, and an etching process may be performed using the hard mask pattern to form a hole H at least partially penetrating the stacked structure ST. The hole H may extend partially into the substrate SUB.

[0062] 4b, an insulating pattern 53 is formed on a sidewall of the first material film 51 exposed through the hole H. The insulating pattern 53 may be formed using a selective deposition process, and may include an oxide. As a result, a space S may be formed between the insulating patterns 53 adjacent to each other in the first direction Z. As a result, an uneven portion may be formed on the sidewall of the hole H.

[0063] Referring to FIG. 4c, a blocking insulating film 54 is formed along the sidewall of the hole (H in FIG. 4b). The blocking insulating film 54 may be formed along the exposed surface of the insulating pattern 53 and the sidewall of the second material film 52. The blocking insulating film 54 may include a high dielectric constant film. For example, the blocking insulating film 54 may be formed to include a high dielectric constant material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), hafnium silicon oxide (HfSiOx), etc.

[0064] Thereafter, a data storage layer 55 is formed in the space (S in FIG. 4b). For example, after forming the data storage layer 55 along the sidewall of the blocking insulating layer 54, an etch-back process can be performed to leave the data storage layer 55 only in the space (S in FIG. 4b). As a result, the blocking insulating layer 54 in contact with the sidewall of the insulating pattern 53 can be exposed through the hole (H in FIG. 4b). The data storage layer 55 can include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0065] Thereafter, a tunnel insulating film 56 may be formed along the sidewall of the data storage film 55 exposed through the hole (H in FIG. 4b) and the sidewall of the blocking insulating film 54. The tunnel insulating film 56 may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0066] Thereafter, a channel film 57 is formed on a sidewall of the tunnel insulating film 56. The channel film 57 may be formed of a semiconductor material. In one embodiment, the channel film 57 may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene.

[0067] Thereafter, a core insulating film 58 may be formed so that the center of the hole is filled in. The core insulating film 58 may be formed of an insulating material such as an oxide film.

[0068] 4d, an isolation structure 59 is formed to penetrate the core insulating film 58, the channel film 57, the tunnel insulating film 56, the data storage film 55, and the blocking insulating film 54 in the first direction Z. The isolation structure 59 may be formed by performing an etching process to form a line-shaped trench penetrating the core insulating film 58, the channel film 57, the tunnel insulating film 56, the data storage film 55, and the blocking insulating film 54 formed inside the hole in the first direction Z, and filling the trench with an insulating material, as shown in FIGS. 2g and 2h or 3e and 3f described above.

[0069] Then, an etching process is performed to expose the sidewalls of the stack (ST in FIG. 4c), and the exposed second material film (52 ​​in FIG. 4c) is removed. Then, a third material film 60 is formed in the space from which the second material film was removed. The third material film 60 may include a conductive material such as polysilicon, tungsten, or a metal. The first material film 51 and the third material film 60 may be defined as a gate stack structure GST.

[0070] 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h, 5i, 5j, 5k, 5l, and 5m are cross-sectional and plan views for explaining a manufacturing method of a semiconductor device according to another embodiment of the present invention.

[0071] 5a and 5b, a stacked structure ST is formed on a substrate SUB. The stacked structure ST may include a first material film 61 and a second material film 62 that are alternately stacked. The first and second material films 61 and 62 may be stacked in a direction perpendicular to the substrate SUB. The first and second material films 61 and 62 may be formed using a deposition process such as chemical vapor deposition (CVD).

[0072] The first material film 61 may include a material having a high etching selectivity relative to the second material film 62. As an example, the first material film 61 may include an insulating material such as an oxide, and the second material film 62 may include a sacrificial material such as a nitride. As another example, the first material film 61 may include an insulating material such as an oxide, and the second material film 62 may include a conductive material such as polysilicon or tungsten.

[0073] Next, a hard mask pattern (not shown) may be formed on the stacked structure ST, and an etching process may be performed using the hard mask pattern to form a hole H at least partially penetrating the stacked structure ST. The hole H may extend partially into the substrate SUB.

[0074] The hole H may have an elliptical shape, for example with a diameter X1 in the second direction X larger than a diameter X2 in the third direction Y.

[0075] 5c, the first material film 61 exposed through the hole H is etched to a certain depth in the horizontal direction to form a recess region R. That is, the sidewall of the first material film 61 is etched to a certain depth so that the second material film 62 protrudes compared to the first material film 61 in the horizontal direction.

[0076] Referring to FIG. 5d, a sacrificial pattern 63 is formed in the recessed region (R in FIG. 5c). The sacrificial pattern 63 may be formed of a polysilicon film or a silicon nitride film. For example, a polysilicon film or a silicon nitride film is formed along the sidewall of the hole H so that the recessed region (R in FIG. 5c) is completely filled. Then, an etch-back process is performed so that the sidewall of the second material film 62 is exposed, leaving the polysilicon film or the silicon nitride film only in the recessed region (R in FIG. 5c), thereby forming the sacrificial pattern 63.

[0077] Referring to Fig. 5e, an oxidation process is performed to selectively oxidize the sacrificial pattern (63 in Fig. 5d) to form an insulating pattern 64. The insulating pattern 64 may be formed to have a protrusion protruding in the direction of the hole H. As a result, a space S may be formed between the protrusions of the insulating patterns 64 adjacent to each other in the first direction Z. As a result, an uneven portion may be formed on the sidewall of the hole H.

[0078] Referring to Fig. 5f, a blocking insulating film 65 is formed along the sidewall of the hole H. The blocking insulating film 65 may be formed along the surface of the protruding portion of the insulating pattern 64 and the sidewall of the second material film 62. The blocking insulating film 65 may include a high dielectric constant film. For example, the blocking insulating film 65 may be formed to include a high dielectric constant material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), hafnium silicon oxide (HfSiOx), etc.

[0079] Thereafter, a data storage film 66 is formed in the space (S in FIG. 5e). For example, after forming the data storage film 66 along the sidewall of the blocking insulating film 65, an etch-back process can be performed to leave the data storage film 66 only in the space (S in FIG. 5e). As a result, the blocking insulating film 65 in contact with the sidewall of the insulating pattern 64 can be exposed through the hole H. The data storage film 66 can include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0080] 5g, a tunnel insulating film 67 may be formed along a sidewall of the data storage film 66 exposed through the hole H and a sidewall of the blocking insulating film 65. The tunnel insulating film 67 may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0081] Thereafter, a channel film 68 is formed on a sidewall of the tunnel insulating film 67. The channel film 68 may be formed of a semiconductor material. In one embodiment, the channel film 68 may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene.

[0082] FIG 5h is a cross-sectional view of the first level h1-h1' of FIG 5g. FIG 5i is a cross-sectional view of the second level h2-h2' of FIG 5g. Referring to FIG 5h and FIG 5i, since the hole H has an elliptical shape, the cross-sectional thickness X3 of the channel film 68 in the second direction X may be formed thicker than the cross-sectional thickness X4 in the third direction Y.

[0083] 5j and 5k, the channel film (68 in Figs. 5h and 5i) exposed through the hole H is etched to a certain thickness to form a first channel film 68A and a second channel film 68B bisected in the second direction X. The first channel film 68A and the second channel film 68B may have a crescent shape symmetrical to each other. Also, a portion of the tunnel insulating film 67 facing the third direction Y may be exposed.

[0084] 5l and 5m, the exposed tunnel insulating layer 67 is etched to be bisected in the second direction X. At this time, the data storage layer 66 may be exposed. Then, the exposed data storage layer 66 is etched to be bisected in the second direction X.

[0085] Hole H can then be filled with an insulating material to form an isolation structure.

[0086] Then, as shown in FIG 4d, an etching process is performed to expose the sidewalls of the stack (ST in FIG 5g), and the exposed second material film (62 in FIG 5g) is removed. Then, a third material film is formed in the space from which the second material film was removed. The third material film may include a conductive material such as polysilicon, tungsten, or metal.

[0087] 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h, 6i, 6j and 6k are cross-sectional and plan views for explaining a manufacturing method of a semiconductor device according to another embodiment of the present invention.

[0088] 6a and 6b, a gate stack structure GST is formed on a substrate SUB. The gate stack structure GST may include a first material film 71 and a second material film 72 that are alternately stacked. The first and second material films 71 and 72 may be stacked in a vertical direction with respect to the substrate SUB. The first and second material films 71 and 72 may be formed using a deposition process such as CVD (Chemical Vapor Deposition).

[0089] The first material film 71 may include a material having a high etching selectivity with respect to the second material film 72. As an example, the first material film 71 may include an insulating material such as an oxide, and the second material film 72 may include a conductive material such as polysilicon or tungsten.

[0090] Next, a first isolation structure 73 is formed, penetrating the gate stack structure GST in the first direction Z and extending in the second direction X. For example, an etching process may be performed to form a line-shaped trench penetrating the gate stack structure GST in the first direction Z and extending in the second direction X, and then the trench may be filled with an insulating material to form the first isolation structure 73.

[0091] Then, a hard mask pattern (not shown) may be formed on the gate stack structure GST and the first isolation structure 73, and an etching process using the hard mask pattern may be performed to form a hole H penetrating the first isolation structure 73. The hole H may extend partially into the substrate SUB. The hole H may also penetrate both the first isolation structure 73 and a portion of the adjacent gate stack structure GST.

[0092] The hole H may have an elliptical shape, for example with a diameter in the second direction X larger than a diameter in the third direction Y.

[0093] FIG. 6d is a cross-sectional view of the first level h1-h1' of FIG. 6c. FIG. 6e is a cross-sectional view of the second level h2-h2' of FIG. 6c. Referring to FIGS. 6c, 6d, and 6e, an insulating pattern 74 is formed on a sidewall of the first material film 71 exposed through the hole H. The insulating pattern 74 may be formed using a selective deposition process, and the insulating pattern 74 may include an oxide. As a result, a space S may be formed between the insulating patterns 74 adjacent to each other in the first direction Z. As a result, an uneven portion may be formed on the sidewall of the hole H.

[0094] Both ends of the hole H in the second direction X are in contact with the first isolation structure 73, and therefore no insulating pattern 74 is formed. As a result, the insulating patterns 74 can be formed in a C-shape facing each other based on the second direction X.

[0095] Then, a blocking insulating film 75 is formed along the surface of the second material film 72 exposed through the hole H and the surface of the insulating pattern 74. The blocking insulating film 75 may include a high dielectric constant film. For example, the blocking insulating film 75 may be formed to include a high dielectric constant material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0096] FIG. 6g is a cross-sectional view of the first level h1-h1' of FIG. 6f. FIG. 6h is a cross-sectional view of the second level h2-h2' of FIG. 6f. Referring to FIG. 6f, FIG. 6g, and FIG. 6h, a data storage film 76 is formed in the space (S in FIG. 6c). For example, after forming the data storage film 76 along the sidewall of the blocking insulating film 75, an etch-back process can be performed to leave the data storage film 76 only in the space (S in FIG. 6c). Thus, the blocking insulating film 75 in contact with the sidewall of the insulating pattern 74 can be exposed through the hole (H in FIG. 6d and FIG. 6e). The data storage film 76 can include a charge trapping material, a nitride, a variable resistance material, or a nanostructure, or a combination thereof.

[0097] Then, a tunnel insulating film 77 may be formed along the entire sidewall of the hole (H in FIG. 6d and FIG. 6e). For example, the tunnel insulating film 77 may be formed along the sidewall of the data storage film 76 exposed through the hole (H in FIG. 6d), the sidewall of the blocking insulating film 75, and the sidewall of the first isolation structure 73. The tunnel insulating film 77 may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0098] Thereafter, a channel film 78 is formed on a sidewall of the tunnel insulating film 77. The channel film 78 may be formed of a semiconductor material. In one embodiment, the channel film 78 may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene.

[0099] Thereafter, a core insulating film 79 may be formed so that the center of the hole is filled in. The core insulating film 79 may be formed of an insulating material such as an oxide film.

[0100] FIG 6j is a cross-sectional view of the first level h1-h1' of FIG 6i. FIG 6k is a cross-sectional view of the second level h2-h2' of FIG 6i. Referring to FIG 6i, FIG 6j, and FIG 6k, a second isolation structure 80 is formed penetrating the core insulating film 79, the channel film 78, the tunnel insulating film 77, the data storage film 76, and the blocking insulating film 75 in the first direction Z. The second isolation structure 80 may extend in the second direction X and be connected to the first isolation structure 73.

[0101] The second isolation structure 80 can be formed by performing an etching process to form a linear trench penetrating the core insulating film 79, the channel film 78, the tunnel insulating film 77, the data storage film 76, and the blocking insulating film 75 formed inside the hole in the first direction Z, and then filling the trench with an insulating material.

[0102] 7a, 7b, 7c, 7d, 7e and 7f are plan views for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0103] In another embodiment of the manufacturing method of a semiconductor device according to the present invention, the process steps shown in Figures 7a, 7b, 7c, 7d, 7e and 7f can be performed after the process steps shown in Figures 6a, 6b, 6c, 6d, 6e, 6f, 6g and 6h described above are performed.

[0104] Descriptions of the process steps of Figures 6a, 6b, 6c, 6d, 6e, 6f, 6g, and 6h will be omitted.

[0105] 7a, 7c and 7e are plan views at the second material film 72 level, while FIGS. 7b, 7d and 7f are plan views at the first material film 71 level.

[0106] 7a and 7b, an etching process is performed to remove the first isolation structure (73 in FIGS. 6g and 6h) to form a recess region R. As a result, the tunnel insulating film 77 at both ends in the second direction X may be exposed through the recess region R.

[0107] 7c and 7d, a portion of the tunnel insulating film 77 exposed through the recess region R is etched away to expose the channel film (78 in FIGS. 7a and 7b), and the exposed portion of the channel film (78 in FIGS. 7a and 7b) is etched away to physically separate the first channel film 78A and the second channel film 78B from each other. As a result, the first channel film 78A and the second channel film 78B are spaced apart from each other at both ends in the second direction X and may have a symmetrical structure with respect to each other based on the third direction Y. The recess region R may extend into the core insulating film 79.

[0108] Referring to FIGS. 7e and 7f, an insulating material is filled in the recessed regions (R in FIGS. 7c and 7d) to form third isolation structures 81. As shown in FIG.

[0109] 8a, 8b, 8c, 8d, 8e and 8f are plan views for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[0110] In another embodiment of the manufacturing method of a semiconductor device according to the present invention, the process steps shown in Figures 8a, 8b, 8c, 8d, 8e and 8f can be performed after the process steps shown in Figures 6a, 6b, 6c, 6d, 6e, 6f, 6g and 6h described above are performed.

[0111] Descriptions of the process steps of Figures 6a, 6b, 6c, 6d, 6e, 6f, 6g, and 6h will be omitted.

[0112] 8a and 8b, an etching process is performed to remove the first isolation structure (73 in FIGS. 6g and 6h) to form a recess region R. As a result, the tunnel insulating film 77 at both ends in the second direction X may be exposed through the recess region R.

[0113] 8c and 8d, a wet oxidation process is performed through the recess region R to oxidize the channel film adjacent to the recess region R to form a channel isolation structure 82. As a result, the channel film (78 in FIGS. 8a and 8b) is divided into a first channel film 78A and a second channel film 78B that are spaced apart from each other by the channel isolation structure. The first channel film 78A and the second channel film 78B are spaced apart from each other at both ends in the second direction X and may have a symmetrical structure with respect to each other based on the third direction Y.

[0114] Referring to FIGS. 8e and 8f, an insulating material is filled in the recessed regions (R in FIGS. 8c and 8d) to form third isolation structures 81. As shown in FIG.

[0115] Figures 9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i, 9j, 9k, 9l, 9m, 9n, 9o, 9p, 9q, 9r, 9s, 9t, 9u, 9v, 9w, 9x and 9y are cross-sectional and plan views for explaining a manufacturing method of a semiconductor device in another embodiment of the present invention.

[0116] 9a, 9b, and 9c, a stacked structure ST is formed on a substrate SUB. The stacked structure ST may include a first material film 101 and a second material film 102 that are alternately stacked. The first and second material films 101 and 102 may be stacked in a vertical direction on the substrate SUB. The first and second material films 101 and 102 may be formed using a deposition process such as CVD (Chemical Vapor Deposition).

[0117] The first material film 101 may include a material having a high etching selectivity relative to the second material film 102. As an example, the first material film 101 may include an insulating material such as an oxide, and the second material film 102 may include a sacrificial material such as a nitride. As another example, the first material film 101 may include an insulating material such as an oxide, and the second material film 102 may include a conductive material such as polysilicon or tungsten.

[0118] Next, a hard mask pattern (not shown) may be formed on the stacked structure ST, and an etching process may be performed using the hard mask pattern to form a hole H that at least partially penetrates the stacked structure ST. The hole H may extend partially into the substrate SUB.

[0119] The hole H may be formed such that a width X12 in the first horizontal direction A-A' is narrower than a width X11 in the second horizontal direction B-B'. For example, the cross section of the hole H may be elliptical.

[0120] 9d, 9e, and 9f, an insulating film 103 is formed along a sidewall of the hole H. The insulating film 103 may be an oxide film. The insulating film 103 may include silicon oxide. A thickness D1 of the insulating film 103 formed on a sidewall of the hole H in the first horizontal direction A-A' and a thickness D2 of the insulating film 103 formed on a sidewall of the hole H in the second horizontal direction B-B' may be different from each other. For example, the thickness D1 of the insulating film 103 formed on a sidewall of the hole H in the first horizontal direction A-A' may be thinner than the thickness D2 of the insulating film 103 formed on a sidewall of the hole H in the second horizontal direction B-B'.

[0121] 9g, 9h, and 9i, an etching process is performed to etch the insulating film (103 in FIG. 9d, 9e, and 9f) to a certain thickness and partially remove it. The etching process can be performed using an isotropic etching process. For example, a part of the insulating film 103 can be etched away so that the sidewall of the hole H in the first horizontal direction A-A' is exposed. During the etching process, the thickness of the insulating film 103 formed on the sidewall of the hole H in the first horizontal direction A-A' is thinner than the thickness of the insulating film 103 formed on the sidewall of the hole H in the second horizontal direction B-B'. Therefore, even if the insulating film 103 is etched so that the sidewall of the hole H in the first horizontal direction A-A' is exposed, the insulating film 103 can remain on the sidewall of the hole H in the second horizontal direction B-B'. In addition, during the isotropic etching process, the etching rate in the first horizontal direction A-A' is faster than the etching rate in the second horizontal direction B-B' due to the difference in surface area and surface angle exposed to the etchant. As a result, sacrificial patterns 103P are formed on both side walls in the second horizontal direction B-B' of the hole H. The horizontal cross section of the sacrificial pattern 103P may have a crescent shape. The thickness D3 of the sacrificial pattern 103P may be thinner than the thickness (D2 in FIG. 9f) of the insulating film 103 formed on the side walls in the second horizontal direction B-B' before the etching process.

[0122] The sidewalls of the hole H may be divided into a first sidewall SW1 and a second sidewall SW2 based on the sacrificial pattern 103P. For example, both sides of the first horizontal direction A-A' may be divided into the first sidewall SW1 and the second sidewall SW2.

[0123] 9j, 9k, and 9l, an insulating pattern 104 is formed on a sidewall of the first material film 101 exposed through the hole H. The insulating patterns 104 may be formed on a first sidewall SW1 and a second sidewall SW2 on both sides of a first horizontal direction A-A', and separated from each other. The insulating patterns 104 formed on the first sidewall SW1 and the second sidewall SW2, respectively, may have a symmetrical structure facing each other. The insulating pattern 104 may be formed using a selective deposition process, and may include an oxide.

[0124] As a result, a space S may be formed between the insulating patterns 104 adjacent in the vertical direction. As a result, unevenness may be formed on the first sidewall SW1 and the second sidewall SW2 of the hole H.

[0125] 9m, 9n, and 9o, an etching process is performed to remove the sacrificial pattern (103 in FIG. 9j and FIG. 9l), thereby maintaining the unevenness on the first sidewall SW1 and the second sidewall SW2 of the hole H, and exposing the sidewalls of the first material film 101 and the second material film 102 on both sides of the hole H in the second horizontal direction B-B'.

[0126] 9p, 9q, 9r and 9s, a blocking insulating film 105 is formed along the sidewall of the hole (H in FIG. 9m and FIG. 9n). The blocking insulating film 105 may be formed along the exposed surface of the insulating pattern 104 and the sidewall of the second material film 102 at the first sidewall SW1 and the second sidewall SW2 of the hole H. The blocking insulating film 105 may be formed along the sidewall of the first material film 101 and the second material film 102 at both sides of the hole H in the second horizontal direction B-B'. The blocking insulating film 105 may include a high dielectric constant film. For example, the blocking insulating film 105 may be formed to include a high dielectric constant material such as aluminum oxide (Al2O3), hafnium oxide (HfOx), or hafnium silicon oxide (HfSiOx).

[0127] Thereafter, the data storage film 106 is formed in the space (S in FIG. 9n). For example, after forming the data storage film 106 along the sidewall of the blocking insulating film 105, an etch-back process can be performed to leave the data storage film 106 only in the space (S in FIG. 9n). As a result, the data storage film 106 formed in the space (S in FIG. 9n) can be spaced apart from each other in the vertical direction, and the data storage film 106 formed on the first sidewall SW1 and the second sidewall SW2 of the hole can be spaced apart from each other on both sides of the second horizontal direction B-B' of the hole.

[0128] The data storage film 106 may include charge trapping materials, nitrides, variable resistance materials, and / or nanostructures.

[0129] Then, a tunnel insulating film 107 may be formed along the sidewall of the data storage film 106 exposed through the hole and the sidewall of the blocking insulating film 105. The tunnel insulating film 107 may be a film through which charges are tunneled by FN tunneling or the like, and may include an insulating material such as an oxide or a nitride.

[0130] Thereafter, a channel film 108 is formed on a sidewall of the tunnel insulating film 107. The channel film 108 may be formed of a semiconductor material. In one embodiment, the channel film 108 may include a semiconductor material such as silicon or germanium, or may include a nanostructure such as a nanodot, a nanotube, or graphene.

[0131] Thereafter, a core insulating film 109 may be formed so that the center of the hole is filled in. The core insulating film 109 may be formed of an insulating material such as an oxide film.

[0132] Referring to Figures 9t, 9u, 9v and 9w, an etching process is performed to expose the sidewalls of the stack (ST in Figures 9p and 9q), and the exposed second material film (102 in Figures 9p and 9q) is removed to form a recess region R11.

[0133] Thereafter, a wet oxidation process is performed through the recess region R11 to oxidize the channel film adjacent to the recess region R11, thereby forming a channel isolation structure 110. The channel isolation structure 110 may be formed on both sides in the second horizontal direction B-B' where the data storage film 106 is not formed. By the channel isolation structure 110, the channel film adjacent to the data storage film 106 may be divided into a first channel film 108A and a second channel film 108B that are separated from each other.

[0134] Thereafter, a third material film 111 is formed in the space where the second material film is removed. The third material film 111 may include a conductive material such as polysilicon, tungsten, metal, etc. The first material film 101 and the third material film 111 may be defined as a gate stack structure GST.

[0135] 9x and 9y, a third material film 111 is formed in the recessed region (R11 in FIG. 9t and FIG. 9u). The third material film 111 may include a conductive material such as polysilicon, tungsten, metal, etc. The first material film 101 and the third material film 111 may be defined as a gate stack structure.

[0136] FIG. 10 is a block diagram for explaining a memory system including a semiconductor device according to an embodiment of the present invention.

[0137] 10, a memory system 1000 includes a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 includes a plurality of semiconductor memory devices 500. The plurality of semiconductor memory devices 500 may be divided into a plurality of groups. In the embodiment of the present invention, the host 1300 is illustrated and described as being included in the memory system 1000, but the memory system 1000 may be configured to include only the controller 1200 and the memory device 1100, and the host 1300 may be disposed outside the memory system 1000.

[0138] 10, a plurality of groups GR1-GRn of memory devices 1100 are shown communicating with a controller 1200 via first to n-th channels CH1-CHn, respectively. Each semiconductor memory device 500 may be a semiconductor device as described with reference to FIGS. 1a, 1b, and 1c.

[0139] Each of the groups GR1 to GRn is configured to communicate with the controller 1200 via one common channel. The controller 1200 is configured to control the multiple semiconductor memory devices 500 of the memory device 1100 via the multiple channels CH1 to CHn.

[0140] The controller 1200 is connected between the host 1300 and the memory device 1100. The controller 1200 is configured to access the memory device 1100 in response to a request from the host 1300. For example, the controller 1200 is configured to control read, program, erase, and background operations of the memory device 1100 in response to a host command Host_CMD received from the host 1300. During a program operation, the host 1300 may transmit an address ADD and data to be programmed DATA together with the host command Host_CMD, and during a read operation, the host 1300 may transmit the address ADD together with the host command Host_CMD. During a program operation, the controller 1200 transmits a command corresponding to the program operation and data to be programmed DATA to the memory device 1100. During a read operation, the controller 1200 transmits a command corresponding to the read operation to the memory device 1100, and the read data DATA is transmitted from the memory device 1100 to the host 1300. The controller 1200 is configured to provide an interface between the memory device 1100 and the host 1300. The controller 1200 is configured to drive firmware for controlling the memory device 1100.

[0141] The host 1300 may include a portable electronic device such as a computer, a PDA, a PMP, an MP3 player, a camera, a camcorder, a mobile phone, etc. The host 1300 may request a program operation, a read operation, an erase operation, etc. of the memory system 1000 through a host command Host_CMD. For a program operation of the memory device 1100, the host 1300 may transmit a host command Host_CMD, data DATA, and an address ADD corresponding to the program operation to the controller 1200, and for a read operation, the host 1300 may transmit a host command Host_CMD and an address ADD corresponding to the read operation to the controller 1200. In this case, the address ADD may be a logical address of the data.

[0142] The controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device. As an exemplary embodiment, the controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device to form a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device to form a memory card such as a PC card (personal computer memory card international association, PCMCIA), a CompactFlash card (CF), a SmartMedia card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash storage device (UFS), etc.

[0143] As other examples, the memory system 1000 may be integrated into a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player ... The present invention may be provided as one of various components of an electronic device, such as a wireless player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

[0144] As an illustrative example, memory device 1100 or memory system 1000 may be implemented in a variety of forms of packaging. For example, the memory device 1100 or the memory system 1000 may be packaged and implemented in a manner such as a Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), etc. [Explanation of symbols]

[0145] GST Gate Stack Structure CP conductive film ILD Interlayer insulating film PP1, PP2 First and second plug patterns TI1, TI2 First and second tunnel insulating films CH1, CH2 First and second channel membranes CO1, CO2 First and second core insulating films SS separation structure DS1, DS2 First and second data storage films IP insulation pattern BI blocking insulating film

Claims

1. a gate stack structure including insulating films and conductive films alternately stacked; a first plug pattern and a second plug pattern extending in a vertical direction, which is a stacking direction of the gate stack structure; a first data storage film disposed between the first plug pattern and the conductive film, and a second data storage film disposed between the second plug pattern and the conductive film; an isolation structure extending in the vertical direction to separate the first plug pattern and the second plug pattern from each other; an insulating pattern disposed between the vertically adjacent first data storage film and the vertically adjacent second data storage film.

2. The semiconductor device according to claim 1 , wherein the isolation structure extends in a horizontal direction perpendicular to the vertical direction to isolate the first data storage film and the second data storage film from each other.

3. 2 . The semiconductor device according to claim 1 , wherein the insulating pattern is disposed between the insulating film and the first plug pattern and between the insulating film and the second plug pattern.

4. Each of the first plug pattern and the second plug pattern includes a core insulating film extending in the vertical direction and having an inner wall in contact with the isolation structure; a channel film in contact with an outer wall of the core insulating film; 2. The semiconductor device according to claim 1, further comprising a tunnel insulating film in contact with an outer wall of the channel film.

5. 2. The semiconductor device of claim 1, further comprising a blocking insulating film surrounding upper and lower surfaces of the first data storage film and the second data storage film and sidewalls of the first data storage film and the second data storage film adjacent to the conductive film.

6. 6. The semiconductor device of claim 5, wherein the blocking insulating film surrounds upper and lower surfaces of the insulating pattern and extends to an interface between the insulating pattern and the first plug pattern and an interface between the insulating pattern and the second plug pattern.

7. The semiconductor device according to claim 1 , wherein the conductive film protrudes further in a direction toward the first plug pattern and the second plug pattern than the insulating film.

8. forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are cross-stacked; forming a recess region by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial layer in the recess region; oxidizing the sacrificial layer to form an insulating pattern protruding further toward the hole than a sidewall of the second material layer; forming a data storage layer in a space between vertically adjacent insulating patterns; forming a plug pattern extending in the vertical direction within the hole; forming an isolation structure penetrating the plug pattern in the vertical direction and isolating the plug pattern into a first plug pattern and a second plug pattern.

9. 9. The method of claim 8, further comprising forming a blocking insulating layer extending along sidewalls of the insulating pattern exposed through the hole and sidewalls of the second material layer before forming the data storage layer.

10. The forming of the plug pattern includes forming a tunnel insulating layer along a sidewall of the data storage layer exposed through the hole and a sidewall of the blocking insulating layer; forming a channel layer along a sidewall of the tunnel insulating layer; 10. The method of claim 9, further comprising filling a central region of the hole with an insulating material to form a core insulating film.

11. The step of forming the isolation structure includes the steps of: forming a line-shaped trench penetrating the plug pattern by performing an etching process; 10. The method of claim 9, further comprising filling the trench with an insulating material to form the isolation structure.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the trench extends horizontally and penetrates the data storage film.

13. The method of claim 11, wherein the trench extends horizontally through the data storage layer, the blocking insulating layer, and the second material layer.

14. performing an etching process to expose a sidewall of the stack structure; removing the exposed second material film; 9. The method of claim 8, further comprising: filling a space from which the second material film is removed with a third material film.

15. forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are cross-stacked; forming a protrusion pattern on a sidewall of the second material film exposed through the hole; forming insulating patterns in spaces between the vertically adjacent protruding patterns so as to protrude further toward the hole than sidewalls of the protruding patterns; forming a data storage layer in a space between vertically adjacent insulating patterns; forming a plug pattern extending in the vertical direction within the hole; forming an isolation structure penetrating the plug pattern in the vertical direction and isolating the plug pattern into a first plug pattern and a second plug pattern.

16. The forming of the insulating pattern includes forming a sacrificial layer in a space between the protruding patterns; 16. The method of claim 15, further comprising: oxidizing the sacrificial film to form the insulating pattern protruding further toward the hole than a sidewall of the protruding pattern.

17. 16. The method of claim 15, further comprising forming a blocking insulating layer extending along sidewalls of the insulating pattern exposed through the hole and sidewalls of the second material layer before forming the data storage layer.

18. The forming of the plug pattern includes forming a tunnel insulating layer along a sidewall of the data storage layer exposed through the hole and a sidewall of the blocking insulating layer; forming a channel layer along a sidewall of the tunnel insulating layer; 20. The method of claim 17, further comprising filling a central region of the hole with an insulating material to form a core insulating film.

19. The step of forming the isolation structure includes the steps of: forming a line-shaped trench penetrating the plug pattern by performing an etching process; and filling the trench with an insulating material to form the isolation structure. The method for manufacturing a semiconductor device according to claim 18 , wherein the trench extends horizontally and penetrates the data storage film.

20. 20. The method of claim 19, wherein the trench extends horizontally through the blocking insulating film and the second material film.

21. performing an etching process to expose a sidewall of the stack structure; removing the exposed second material film and the protruding patterns; 16. The method of claim 15, further comprising: filling a space formed by removing the second material film and the protruding pattern with a third material film.

22. forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are cross-stacked; forming an insulating pattern on a sidewall of the first material film exposed through the hole; forming a data storage layer in a space between vertically adjacent insulating patterns; forming a plug pattern extending in the vertical direction within the hole; forming an isolation structure penetrating the plug pattern in the vertical direction and isolating the plug pattern into a first plug pattern and a second plug pattern.

23. 23. The method of claim 22, wherein the forming of the insulating pattern comprises forming the insulating pattern protruding toward the hole beyond a sidewall of the second material film using a selective deposition process.

24. 23. The method of claim 22, further comprising forming a blocking insulating layer extending along sidewalls of the insulating pattern exposed through the hole and sidewalls of the second material layer before forming the data storage layer.

25. The forming of the plug pattern includes forming a tunnel insulating layer along a sidewall of the data storage layer exposed through the hole and a sidewall of the blocking insulating layer; forming a channel layer along a sidewall of the tunnel insulating layer; 25. The method of claim 24, further comprising filling a central region of the hole with an insulating material to form a core insulating film.

26. The method for manufacturing a semiconductor device according to claim 25 , wherein the trench extends horizontally and penetrates the data storage film.

27. 26. The method of claim 25, wherein the trench extends horizontally through the data storage layer, the blocking insulating layer, and the second material layer.

28. performing an etching process to expose a sidewall of the stack structure; removing the exposed second material film; 23. The method of claim 22, further comprising: filling a space from which the second material film is removed with a third material film.

29. forming an elliptical hole at least partially penetrating a stack structure in which a first material film and a second material film are cross-stacked; forming a recess region by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial layer in the recess region; oxidizing the sacrificial layer to form an insulating pattern protruding further toward the hole than a sidewall of the second material layer; forming a data storage layer in a space between vertically adjacent insulating patterns; forming a tunnel insulating film and a channel film on a sidewall of the hole, the tunnel insulating film and the channel film being formed so that a cross-sectional thickness in a first horizontal direction is greater than a cross-sectional thickness in a second horizontal direction perpendicular to the first horizontal direction; forming a first channel film and a second channel film bisected in the first horizontal direction by etching the channel film to a predetermined thickness, and exposing a portion of the tunnel insulating film between the first channel film and the second channel film; and sequentially etching the exposed tunnel insulating film and the data storage film to bisect the tunnel insulating film and the data storage film in the first horizontal direction.

30. 30. The method of claim 29, further comprising filling a central region of the hole with an insulating material to form an isolation pattern.

31. 30. The method of claim 29, wherein the hole has a diameter in the first horizontal direction larger than a diameter in the second horizontal direction.

32. 30. The method of claim 29, wherein the first channel film and the second channel film have crescent shapes that are symmetrical to each other and face each other in the second horizontal direction.

33. performing an etching process to expose a sidewall of the stack structure; removing the exposed second material film; 30. The method of claim 29, further comprising: filling a space from which the second material film is removed with a third material film.

34. forming a laminate structure in which a first material film and a second material film are cross-stacked; forming a first isolated pattern extending vertically through the laminate structure and in a first horizontal direction; forming a hole penetrating the stack structure and the first isolation pattern; forming a recess region by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial layer in the recess region; oxidizing the sacrificial layer to form an insulating pattern protruding further toward the hole than a sidewall of the second material layer; forming a data storage layer in a space between vertically adjacent insulating patterns; sequentially forming a tunnel insulating layer, a channel layer, and a core insulating layer on a sidewall of the hole, the tunnel insulating layer extending in the vertical direction; forming a second isolation pattern penetrating the tunnel insulating film, the channel film, and the core insulating film in the vertical direction to isolate the channel film into a first channel film and a second channel film.

35. 35. The method of claim 34, further comprising forming a blocking insulating layer extending along sidewalls of the insulating pattern exposed through the hole and sidewalls of the second material layer before forming the data storage layer.

36. The forming of the second isolation pattern includes performing an etching process to form a line-shaped trench extending in the first horizontal direction and exposing a sidewall of the first isolation pattern; 35. The method of claim 34, further comprising filling the trench with an insulating material to form the second isolation pattern.

37. forming a laminate structure in which a first material film and a second material film are cross-stacked; forming a first isolated pattern extending vertically through the laminate structure and in a first horizontal direction; forming a hole penetrating the stack structure and the first isolation pattern; forming a first recess region by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial layer in the first recess region; oxidizing the sacrificial layer to form an insulating pattern protruding further toward the hole than a sidewall of the second material layer; forming a data storage layer in a space between vertically adjacent insulating patterns; sequentially forming a tunnel insulating layer, a channel layer, and a core insulating layer on a sidewall of the hole, the tunnel insulating layer extending in the vertical direction; removing the first isolation pattern to form a second recess region; and etching the tunnel insulating film and the channel film exposed through the second recess region to separate the channel film into a first channel film and a second channel film spaced apart from each other.

38. 40. The method of claim 37, further comprising filling the second recessed region with an insulating material to form an isolation structure.

39. 40. The method of claim 37, further comprising forming a blocking insulating layer extending along sidewalls of the insulating pattern exposed through the hole and sidewalls of the second material layer before forming the data storage layer.

40. forming a laminate structure in which a first material film and a second material film are cross-stacked; forming a first isolated pattern extending vertically through the laminate structure and in a first horizontal direction; forming a hole penetrating the stack structure and the first isolation pattern; forming a first recess region by etching a sidewall of the first material layer exposed through the hole to a predetermined thickness, and forming a sacrificial layer in the first recess region; oxidizing the sacrificial layer to form an insulating pattern protruding further toward the hole than a sidewall of the second material layer; forming a data storage layer in a space between vertically adjacent insulating patterns; sequentially forming a tunnel insulating layer, a channel layer, and a core insulating layer on a sidewall of the hole, the tunnel insulating layer extending in the vertical direction; removing the first isolation pattern to form a second recess region; performing a wet oxidation process through the second recess region to oxidize a portion of the channel film adjacent to the second recess region to form a channel isolation structure.

41. 41. The method of claim 40, wherein the channel film is separated into a first channel film and a second channel film spaced apart by the channel isolation structure.

42. 41. The method of claim 40, further comprising filling the second recessed region with an insulating material to form an isolation structure.

43. forming a hole at least partially penetrating a stack structure in which a first material film and a second material film are cross-stacked; forming first and second isolated patterns in contact with boundary surfaces of first and second sidewalls of the hole facing each other and extending in a vertical direction; forming an insulating pattern on a sidewall of the first material film exposed through the hole; removing the first isolation pattern and the second isolation pattern, and forming a data storage layer in a space between the insulating patterns vertically adjacent to the first sidewall and the second sidewall; sequentially forming a tunnel insulating layer, a channel layer, and a core insulating layer along a sidewall of the hole; performing an etching process to expose a sidewall of the stack structure; removing the exposed second material film to form a recess region; and performing a wet oxidation process through the recess region to oxidize a portion of the channel film adjacent to the recess region to form a channel isolation structure.

44. 44. The method of claim 43, wherein the channel film is separated into a first channel film and a second channel film spaced apart by the channel isolation structure.

45. 44. The method of claim 43, further comprising filling the recessed region with a third material.

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