Semiconductor device

Abstract

To provide a semiconductor device capable of preventing degradation of polyimide due to blue light and preventing a decrease in reliability.SOLUTION: In a semiconductor device having an active region and a termination region surrounding the active region, the termination region includes a semiconductor substrate 41 of a first conductivity type, a first semiconductor region 42 of a first conductivity type having a thickness d provided on the surface of the semiconductor substrate 41, an insulating film 19 provided on the surface of the first semiconductor region 42, and a polyimide film 34 selectively provided on the surface of the insulating film 19, and the polyimide film 34 is provided at a distance of 0.66d or more from an end T of the semiconductor device 10.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, a SiC semiconductor device has been proposed in which an edge insulating film and a passivation film are provided on a SiC epitaxial layer, with the passivation film being spaced apart from the edge of a dicing region (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-93209 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, blue light is generated when a reflux current flows through the built-in diode, and the polyimide covering the semiconductor device absorbs the blue light emitted from the edge of the semiconductor device, which can change the composition of the polyimide and deteriorate the adhesion, etc., resulting in a decrease in the reliability of the semiconductor device.

[0005] In order to solve the problems associated with the conventional techniques described above, an object of the present disclosure is to provide a semiconductor device that can prevent degradation of polyimide due to blue light and prevent a decrease in reliability. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object of the present disclosure, the semiconductor device according to the present disclosure has the following features. The semiconductor device has an active region and a termination region surrounding the periphery of the active region. The termination region includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a first conductivity type having a thickness d provided on a surface of the semiconductor substrate, an insulating film provided on the surface of the first semiconductor region, and a polyimide film selectively provided on the surface of the insulating film. The polyimide film is provided at a distance of 0.66d or more from an end of the semiconductor device.

[0007] According to the above disclosure, even if blue light passes through the interlayer insulating film and is emitted from the surface of the semiconductor device, it is not absorbed by the polyimide film. Therefore, the composition of the polyimide film is not changed by blue light, and the adhesion between the polyimide film and the interlayer insulating film is not deteriorated, and the reliability of the semiconductor device is not deteriorated. Effect of the Invention

[0008] The semiconductor device according to the present disclosure has the advantage that it is possible to prevent degradation of polyimide due to blue light and prevent a decrease in reliability. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an edge termination region of a semiconductor device according to an embodiment; [Diagram 2] 1 is a graph showing the relationship between a dicing surface angle of a semiconductor device according to an embodiment and a distance from an end of the semiconductor device to a polyimide film. [Diagram 3] 1 is a cross-sectional view showing a structure of an edge termination region of a semiconductor device according to an embodiment; [Figure 4] 2 is a cross-sectional view showing a structure of an active region of the semiconductor device according to the embodiment; [Diagram 5] FIG. 1 is a cross-sectional view illustrating an edge termination region of a conventional semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <Overview of the embodiment of the present disclosure> In order to solve the above-mentioned problems and achieve the object of the present disclosure, the semiconductor device according to the present disclosure has the following features. The semiconductor device has an active region and a termination region surrounding the periphery of the active region. The termination region includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a first conductivity type having a thickness d provided on a surface of the semiconductor substrate, an insulating film provided on the surface of the first semiconductor region, and a polyimide film selectively provided on the surface of the insulating film. The polyimide film is provided at a distance of 0.66d or more from an end of the semiconductor device.

[0011] According to the above disclosure, even if blue light passes through the interlayer insulating film and is emitted from the surface of the semiconductor device, it is not absorbed by the polyimide film. Therefore, the composition of the polyimide film is not changed by blue light, and the adhesion between the polyimide film and the interlayer insulating film is not deteriorated, and the reliability of the semiconductor device is not deteriorated.

[0012] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, a side of the semiconductor device is inclined by θ degrees from vertical, and the polyimide film is provided at a distance of 0.66d+dtanθ or more from the end.

[0013] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, a side of the semiconductor device is inclined by θ degrees from vertical, and when a film thickness of the semiconductor substrate is D, the polyimide film is provided at a distance of 0.66d+Dtanθ or more from the end.

[0014] According to the above disclosure, even if the side surface of the semiconductor device is inclined by θ degrees from the vertical, blue light is not absorbed by the polyimide film.

[0015] <Foundational knowledge of this disclosure> First, the problems with conventional semiconductor devices will be described. FIG. 5 is a cross-sectional view showing an edge termination region of a conventional semiconductor device. The edge termination region is a region that surrounds the periphery of an active region through which current flows when the device is on, and is provided with a breakdown voltage structure. The breakdown voltage structure is omitted in FIG. 5. In the edge termination region, n + On the starting substrate 141 - A silicon carbide layer 142 is provided, - An interlayer insulating film 119 and a polyimide film 134 are provided on the silicon carbide layer 142 .

[0016] As shown in FIG. 5, the interlayer insulating film 119 is - The polyimide film 134 is provided on the entire surface of the silicon carbide layer 142. The surface of the semiconductor device is protected by a polyimide film 134, which is formed up to the vicinity of a side surface 146 of the semiconductor device. When the semiconductor device is a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the SiC-MOSFET has a built-in diode. When a reflux current flows through the built-in diode, high-energy blue light corresponding to the band gap energy of SiC is generated. When the semiconductor device is a SiC-IGBT (Insulated Gate Bipolar Transistor), blue light is generated and the amount of light emitted is greater than that of a SiC-MOSFET, since the device normally operates in bipolar mode when turned on.

[0017] Since the surface of the semiconductor device is covered with metal electrodes such as a source electrode, the blue light is reflected by the metal electrodes and spreads inside the semiconductor device in the lateral direction E1 without being emitted directly to the surface. The blue light that spreads in the lateral direction may be emitted directly from a side surface 146 of the semiconductor device, or may be reflected by a side surface 146 of the semiconductor device and emitted to the nearby surface side.

[0018] When blue light propagating in the lateral direction E1 inside the semiconductor device is reflected by the side surface 146 of the semiconductor device, the interlayer insulating film 119 and the n -At the interface of silicon carbide layer 142, if the angle of incidence of blue light is small as in route R2, it passes through interlayer insulating film 119, and if the angle of incidence of blue light is large as in route R1, it is reflected by interlayer insulating film 119. When blue light passes through interlayer insulating film 119 as in route R2, in the conventional semiconductor device, polyimide film 134 is formed up to the vicinity of side surface 146 of the semiconductor device, so that the blue light is absorbed by polyimide film 134. Polyimide film 134 that absorbs blue light has a composition that changes due to the energy of the blue light, and properties such as adhesion between interlayer insulating film 119 and polyimide film 134 deteriorate, resulting in a problem of reduced reliability of the semiconductor device.

[0019] A preferred embodiment of the semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. In the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, the description of the same or equivalent should include within 5% in consideration of manufacturing variations.

[0020] (Embodiment) A semiconductor device according to an embodiment for solving the above-mentioned problems will be described below. As the semiconductor device according to the embodiment, the structure of a silicon carbide semiconductor device will be described. Figure 1 is a cross-sectional view showing an edge termination region of a semiconductor device according to the embodiment. In Figure 1, the detailed structure of the edge termination region is omitted (see Figure 3 for the detailed structure).

[0021] As shown in FIG. 1, in the edge termination region of the semiconductor device according to the embodiment, n + On the starting substrate 41, - A silicon carbide layer 42 is provided, - An interlayer insulating film 19 and a polyimide film 34 are provided on the silicon carbide layer 42. + The starting substrate 41 is a drain region, and- The silicon carbide layer 42 is a drift layer formed by epitaxial growth. The interlayer insulating film 19 is an oxide film made of, for example, a SiO2 film. The interlayer insulating film 19 is a n-type - The insulating layer 32 is formed on the entire surface of the silicon carbide layer 42. The surface of the semiconductor device is protected by a polyimide film 34, which is formed away from the vicinity of a side surface 46 of the semiconductor device.

[0022] As mentioned above, when the built-in diode of a SiC-MOSFET is energized or when a SiC-IGBT is turned on, high-energy blue light (including ultraviolet light with a shorter wavelength than blue) is generated. For example, in the case of a MOSFET with a trench gate structure shown in Figure 4 (described later), blue light is emitted through the p + Holes injected from the n-type region 21 + The blue light is mainly emitted from the side surface 46 of the semiconductor device, but a part of it is reflected and travels toward the front surface. Whether this reflected blue light is reflected on the surface of the semiconductor device or transmitted and emitted to the outside depends on n - It is determined by the refractive indexes of the silicon carbide layer 42 and the interlayer insulating film 19 and the angle of incidence of the blue light.

[0023] When blue light propagating in the lateral direction E1 inside the semiconductor device is reflected by the side surface 46 of the semiconductor device, the interlayer insulating film 19 and the n - At the interface of the silicon carbide layer 42, if the angle of incidence of blue light is small as in the case of route R2, it passes through the interlayer insulating film 19, and if the angle of incidence of blue light is large as in the case of route R1, it is totally reflected by the interlayer insulating film 19. Whether it passes through or is totally reflected depends on the distance from the side surface 46 of the semiconductor device, and it passes on the side surface 46 side of the boundary T1, and is totally reflected on the opposite side of the side surface 46 from the boundary T1. For this reason, in the embodiment, the polyimide film 34 is formed away from the edge T of the semiconductor device and the boundary T1, and the position of the polyimide film 34 at the edge T of the semiconductor device is limited to outside the region where blue light is emitted. The edge T of the semiconductor device is the starting point of the side surface 46 of the semiconductor device and is located at the outermost part of the semiconductor device.

[0024] Interlayer insulating film 19 and n - The incidence angle of blue light at the interface of the n-type silicon carbide layer 42 becomes smaller as the light emission position becomes deeper, and the blue light is more likely to be transmitted from the surface. - The n-type silicon carbide layer 42 and + from the interface of the silicon carbide layer 41 - Since the boundary T1 is generated on the n-type silicon carbide layer 42 side, the distance L1 from the end T of the semiconductor device to the boundary T1 is - The thickness L1 depends on the thickness d of the silicon carbide layer 42. By setting L1 to be about 0.66d or more, it is possible to prevent the blue light transmitted through the interlayer insulating film 19 from being absorbed by the polyimide film 34. - The thicker the silicon carbide layer 42 is in a device, the further away the polyimide film 34 must be from the edge T of the semiconductor device.

[0025] For this reason, in the semiconductor device according to the embodiment, the polyimide film 34 is spaced 0.66d or more from the end T of the semiconductor device. As a result, even if the blue light passes through the interlayer insulating film 19 and is emitted from the surface of the semiconductor device as in route R1, it will not be absorbed by the polyimide film 34. Furthermore, in the region where the polyimide film 34 is provided, the blue light will not be totally reflected and emitted from the surface of the semiconductor device as in route R2. For this reason, the composition of the polyimide film 34 is not changed by the blue light, which does not deteriorate the adhesion between the polyimide film 34 and the interlayer insulating film 19, and it is possible to prevent a decrease in the reliability of the semiconductor device.

[0026] Furthermore, when the side surface 46 of the semiconductor device is vertical, its entire surface coincides with the edge T of the semiconductor device, but the side surface 46 of the semiconductor device may not be vertical due to dicing. In this case, the inclined side surface 46 of the semiconductor device approaches the active region, so it is necessary to move the polyimide film 34 further away from the edge T. The incidence angle of blue light becomes smaller the deeper the light emission position is, so n + Starting substrate 41 and n - It is necessary to prevent the blue light reflected near the interface with the silicon carbide layer 42 from being absorbed by the polyimide film 34 .

[0027] When the side surface 46 of the semiconductor device is tilted by θ degrees from the vertical due to dicing, the interlayer insulating film 19 and the n - The side surface 46 at the interface with the n-type silicon carbide layer 42 is + Starting substrate 41 and n - The side surface 46 at the interface with the silicon carbide layer 42 is closer to the polyimide film 34 by dtanθ. + When the thickness of the starting mold substrate 41 is D, n + Starting substrate 41 and n - At the interface with the n-type silicon carbide layer 42, the inclined side surface 46 of the semiconductor device approaches the polyimide film 34 by D tan θ compared to when there is no inclination. For this reason, when the side surface 46 of the semiconductor device is inclined by θ degrees from the vertical, it is preferable to place the polyimide film 34 at a distance of at least 0.66d+d tan θ or more from the end T of the semiconductor device, and it is more preferable to place the polyimide film 34 at a distance of 0.66d+D tan θ or more. This prevents blue light from being absorbed by the polyimide film 34 even when the side surface 46 of the semiconductor device is inclined by θ degrees from the vertical. + When a back surface structure is included, such as an IGBT, the thickness D of the starting mold substrate 41 is the thickness including the back surface structure.

[0028] 2 is a graph showing the relationship between the dicing surface angle of the semiconductor device according to the embodiment and the distance from the edge of the semiconductor device to the polyimide film when the distance is set to 0.66d+Dtanθ. In FIG. 2, the horizontal axis shows the angle θ (dicing surface angle) at which the side surface 46 of the semiconductor device is away from the vertical, in degrees. The horizontal axis shows the distance x, in μm, from the edge T of the semiconductor device. FIG. 2 shows the relationship between the dicing surface angle of the semiconductor device according to the embodiment when the distance from the edge T of the semiconductor device is set to 0.66d+Dtanθ. + The thickness D of the starting mold substrate 41 is, for example, 100 μm. - 4A and 4B show the cases where the thickness d of the type silicon carbide layer 42 is 7 μm, 11 μm, 16 μm, and 31 μm, respectively.

[0029] Next, the structure of the semiconductor device according to the embodiment will be described. Here, the semiconductor device will be described as an example in which it is a SiC-MOSFET. Fig. 3 is a cross-sectional view showing the structure of the edge termination region of the semiconductor device according to the embodiment. The silicon carbide semiconductor device 10 shown in Fig. 3 is a vertical MOSFET with a trench gate structure that includes a breakdown voltage structure 30 in an edge termination region 2 of a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC).

[0030] In the semiconductor substrate 40, a plurality of unit cells (functional units of an element) of the same structure (element structure) of a MOSFET are arranged adjacent to each other in a central portion 1a (see FIG. 4) of an active region 1. The active region 1 is a region through which a main current (drift current) flows when the MOSFET is on. The active region 1 has a substantially rectangular planar shape and is arranged substantially in the center of the semiconductor substrate 40 (chip center). The active region 1 is a region having a p ++ This is a portion extending from the outer end of the mold contact extension 15a (the end (chip end) side of the semiconductor substrate 40) to the inner side (the center side of the chip).

[0031] Edge termination region 2 is a region between active region 1 and the chip edge, and surrounds active region 1 in a substantially rectangular shape. Edge termination region 2 is provided with a breakdown voltage structure 30. Breakdown voltage structure 30 has the function of maintaining a breakdown voltage by mitigating the electric field near the boundary between active region 1 and edge termination region 2. The configuration of breakdown voltage structure 30 will be described later. The breakdown voltage is the limit voltage at which the drain-source voltage does not increase any further even if the drain-source current increases due to an avalanche breakdown occurring at the pn junction.

[0032] The semiconductor substrate 40 is made of silicon carbide. + On the front surface of the starting mold substrate 41, - The n-type drift region (first semiconductor region) 12 - The semiconductor substrate 40 is formed by epitaxially growing an n-type silicon carbide layer 42. - The main surface on the side of the n-type silicon carbide layer 42 is the front surface (first main surface), + The main surface on the mold starting substrate 41 side is defined as the back surface (second main surface).

[0033] n + The starting substrate 41 is n + The semiconductor substrate 40 is a n-type drain region 11. - n-type drift region 12 - The n-type silicon carbide layers 42 are epitaxially grown in multiple stages. - The drift region 12 is an n - This is a portion of the n-type silicon carbide layer 42 where no diffusion region is formed by ion implantation and where the impurity concentration remains the same as during epitaxial growth. - The drift region 12 is an n + It is in contact with the starting mold substrate 41 and is provided from the active region 1 to the chip end.

[0034] The outer peripheral portion 1b of the active region 1 surrounds the periphery of the central portion 1a of the active region 1 in a substantially rectangular shape. + The outer periphery 1b of the active region 1 is the portion from the outermost end of the type source region 14 to the boundary between the active region 1 and the edge termination region 2. In the short direction of the trench 16, the outer periphery 1b of the active region 1 is the portion from the outer sidewall of the outermost trench 16 to the boundary between the active region 1 and the edge termination region 2. No MOSFET unit cells are provided in the outer periphery 1b of the active region 1.

[0035] The peripheral portion 1b of the active region 1 is connected to the front surface of the semiconductor substrate 40 and - The p-type drift region 12 is disposed adjacent to the p-type drift region 12 in the depth direction from the front surface side of the semiconductor substrate 40. ++ p-type contact extension 15a, p-type base extension 13a and p + The lower part 23a, p of the mold extension part + These regions are the p-type extension region 24a of the central region 1a of the active region 1, which will be described later. ++ The p-type contact region 15, the p-type base region 13 and the p + Lower part of the mold area 23, p +These regions (multiple extensions) are formed by extending the upper portion 24 of the n-type region to the outer periphery 1b of the active region 1. - A single p-type peripheral region 25 is formed in the entire area between the p-type drift region 12 and the n-type peripheral region 25 .

[0036] A p-type peripheral region 25 in the peripheral portion 1b of the active region 1 concentrically surrounds the periphery of the central portion 1a of the active region 1. The p-type peripheral region 25 is connected to the n-type terminal of the edge termination region 2 when the MOSFET (silicon carbide semiconductor device 10) is turned off. - The edge termination region 2 is a region for extracting hole (positive hole) current generated in the drift region 12 and flowing toward the active region 1 to a source electrode 44 described later, and is electrically connected to the source electrode 44. When the MOSFET is turned off, the n - The hole current generated in p-type drift region 12 is extracted to source electrode 44 via p-type peripheral region 25, thereby suppressing hole current concentration in edge termination region 2 during avalanche breakdown.

[0037] The breakdown voltage structure 30 in the edge termination region 2 is, for example, a spatially modulated JTE structure in which the JTE structure is a spatially modulated structure, and the front surface of the semiconductor substrate 40 and the n - A plurality of p-type regions 31 and a plurality of p-type drift regions 12 are selectively provided between the p-type drift region 12 and the - The p-type regions 31 and the p-type regions 32 are - Type region 32 is n - The diffusion region is formed in the surface region of the type silicon carbide layer 42 by ion implantation.

[0038] The multiple p-type regions 31 are concentrically arranged around the active region 1, spaced apart from one another. The p-type regions 31 arranged on the outer side have a narrower width (width in the normal direction from the inside to the outside) and are spaced apart from the adjacent p-type regions 31 on the inside. The innermost p-type region 31 is ++ On the outside of the contact extension 15a, ++ It is disposed adjacent to the mold contact extension 15a.

[0039] Multiple p- The p-type regions 32 are arranged concentrically around the active region 1 and spaced apart from each other. - The mold region 32 has a narrower width (width in the normal direction) and has adjacent p - The distance between the outermost p - The width of the mold region 32 is - It may be wider than the width of the mold region 32. - The p-type regions 32 are disposed between all of the adjacent p-type regions 31 , adjacent to the p-type regions 31 on both sides in the normal direction, and surround the bottom corners of all of the p-type regions 31 .

[0040] The innermost p - The inner edge of the p-type region 32 terminates at the same position as the inner edge of the innermost p-type region 31 or further outboard than the inner edge of the innermost p-type region 31. - The innermost p-type region 31 extends outwardly of the outermost p-type region 32. - p outside type region 32 - The n-type region 32 is disposed outside the p-type region 31. - The drift region 12 is formed by dividing all adjacent p - The p-type regions 32 extend between the p-type regions 32 and reach the front surface of the semiconductor substrate 40. - Adjacent to the mold area 32 .

[0041] In addition, the front surface of the semiconductor substrate 40 and the n - Between the n-type drift region 12 and the breakdown voltage structure 30, + A type channel stopper region 33 is optionally provided. + The n-type channel stopper region 33 - The n-type silicon carbide layer 42 is a diffusion region formed by ion implantation in the surface region of the n-type silicon carbide layer 42. + The type channel stopper region 33 is provided outside the breakdown voltage structure 30 and separated from the breakdown voltage structure 30 in the normal direction, and surrounds the breakdown voltage structure 30. + The type channel stopper region 33 contacts the interlayer insulating film 19 on the front surface of the semiconductor substrate 40 .

[0042] n + The type channel stopper region 33 is exposed at a side surface 46 of the semiconductor device. + The channel stopper region 33 and the breakdown voltage structure 30 (the outermost p - Between the type region 32) and n - The n-type drift region 12. + The n-type channel stopper region 33 has a floating potential. No field plate (FP) or channel stopper electrode is provided on the front surface of the semiconductor substrate 40 in the edge termination region 2. + Instead of the p type channel stopper region 33, + A mold channel stop region may be provided.

[0043] Fig. 4 is a cross-sectional view showing a structure of an active region of a semiconductor device according to an embodiment. Silicon carbide semiconductor device 10 shown in Fig. 4 is a vertical MOSFET with a trench gate structure including a breakdown voltage structure 30 in an edge termination region 2 of a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC).

[0044] A trench gate structure is provided in the central portion 1a of the active region 1. The trench gate structure includes a p-type base region 13, an n + Type source region 14, p ++ The p-type contact region 15, the trench 16, the gate insulating film 17 and the gate electrode 18 are included. + type source region 14 and p ++ The contact region 15 is an n - The p-type base region 13 is a diffusion region formed by ion implantation inside the n-type silicon carbide layer 42. The p-type base region 13 is disposed in the central portion 1a of the active region 1 and is connected to the front surface of the semiconductor substrate 40. - It is provided over the entire area between the active region 1 and the mold drift region 12, extends outward, and terminates within the outer periphery 1b of the active region 1.

[0045] n + type source region 14 and p ++The n-type contact regions 15 are selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 13, and are in contact with the p-type base region 13 at their bottoms (lower surface: the end portion on the rear surface side of the semiconductor substrate 40). + The p-type source region 14 is formed only in the central portion 1a of the active region 1. ++ The contact region 15 is in contact with the n + type source region 14 and p ++ The mold contact region 15 is in ohmic contact with an ohmic electrode 43 on its upper surface (the end portion on the front surface side of the semiconductor substrate 40).

[0046] n - Between the n-type drift region 12 and the p-type base region 13, + The n-type current diffusion region 20 and the p-type + The n-type current diffusion region 20 and the p-type current diffusion region 21 and 22 are selectively provided. + The type regions 21 and 22 are n - The n-type current diffusion region 20 is a diffusion region formed by ion implantation inside the p-type silicon carbide layer 42. + Type regions 21 and 22 are + It is preferable that the ion implantation region 14 reaches a deep position on the side of the drain region 11 .

[0047] The n-type current diffusion region 20 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + The n-type current diffusion region 20 contacts the p-type base region 13 at its top surface and contacts the n-type regions 21 and 22 at its bottom. The n-type current diffusion region 20 contacts the p-type base region 13 at its top surface and contacts the n-type regions 21 and 22. The n-type current diffusion region 20 extends in a direction parallel to the front surface of the semiconductor substrate 40, reaches the trench 16, and contacts the gate insulating film 17. - It contacts the mold drift region 12 .

[0048] The n-type current diffusion region 20 may not be provided. When the n-type current diffusion region 20 is not provided, the n-type current diffusion region 20 is replaced by -The drift region 12 reaches the p-type base region 13, and the p-type base region 13 and the p + The insulating film 17 is in contact with the gate insulating film 17 and extends in a direction parallel to the front surface of the semiconductor substrate 40 and reaches the trench 16 .

[0049] p + The n-type regions 21 and 22 are fixed to the potential of a source electrode 44 described later, and have the function of depleting the n-type regions 21 and 22 (or depleting the n-type current diffusion region 20, or both) when the MOSFET (silicon carbide semiconductor device 10) is turned off, thereby reducing the electric field applied to the gate insulating film 17. + The p-type region 21 is provided apart from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction. + The mold region 21 is p + It is partially connected to the mold region 22 and is thereby electrically connected to the source electrode 44 .

[0050] p + The mold region 21 may be in contact with the gate insulating film 17 at the bottom surface of the trench 16, or may be separated from the bottom surface of the trench 16. + The width of the mold region 21 is the same as or wider than the width of the trench 16. + By making the width of the type region 21 wider than the width of the trench 16, + The mold region 21 also faces the bottom corner portion (the boundary between the side wall and the bottom surface) of the trench 16 in the depth direction. + The effect of alleviating the electric field near the bottom surface of the trench 16 by the mold region 21 is further enhanced.

[0051] p + The p-type region 22 is formed between the adjacent trenches 16. + The mold region 21 and the trench 16 are spaced apart. + The upper surface of the p-type region 22 contacts the p-type base region 13 and is electrically connected to the source electrode 44 via the p-type base region 13. + The type region 22 has a depth direction of n - The upper portion (n +A portion 24 on the side of the n-type source region 14 and - The lower portion (n + The portion 23 on the side of the type drain region 11 is adjacent to the first portion 23 .

[0052] The trench 16 has a depth of n + An n-type current diffusion region 20 (or an n-type current diffusion region 20 if no n-type current diffusion region 20 is provided) penetrates the p-type source region 14 and the p-type base region 13. - The trench 16 extends to the p-type drift region 12. + The trench 16 may terminate inside the mold region 21. The trench 16 extends, for example, in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40, and reaches the outer periphery 1b of the active region 1. A gate electrode 18 is provided inside the trench 16 with a gate insulating film 17 interposed therebetween.

[0053] The interlayer insulating film 19 is provided on the entire front surface of the semiconductor substrate 40, and covers the gate electrode 18. The ohmic electrode (first electrode) 43 is provided on a portion of the front surface of the semiconductor substrate 40 that is exposed through a contact hole in the interlayer insulating film 19. The ohmic electrode 43 is connected to an n-type ohmic electrode 44 on the front surface of the semiconductor substrate 40 through the contact hole in the interlayer insulating film 19. + type source region 14 and p ++ Type contact region 15(p ++ In the case where the p-type contact region 15 is not provided, the ohmic electrode 43 is in ohmic contact with the p-type base region 13. The ohmic electrode 43 is, for example, a nickel silicide (NixSiy, where x and y are any integers) film.

[0054] The source electrode (first electrode) 44 is provided on the interlayer insulating film 19 so as to fill the contact hole in the interlayer insulating film 19. The source electrode 44 is provided over substantially the entire area of ​​the central portion 1a of the active region 1. The source electrode 44 is connected to the n-type ohmic electrode 43 via the ohmic electrode 43. + Type source region 14, p ++ The p-type contact region 15, the p-type base region 13, and the p + It is electrically connected to the mold regions 21 and 22 .

[0055] A barrier metal 38 for preventing diffusion of metal atoms toward the gate electrode 18 may be provided on the ohmic electrode 43 and the interlayer insulating film 19. The barrier metal 38 is made of, for example, titanium (Ti) or titanium nitride (TiN). The barrier metal 38 may have a two-layer structure of titanium (Ti) and titanium nitride (TiN). In this case, a source electrode 44 is provided on the barrier metal 38.

[0056] In addition, in order to prevent ion diffusion into the semiconductor element and to insulate and protect the semiconductor element, a polyimide film 34 is formed on the interlayer insulating film 19 in the edge termination region 2 and on the source electrode 44 in the active region 1.

[0057] An opening (not shown) is provided in the polyimide film 34, and the portion of the source electrode 44 exposed in the opening of the polyimide film 34 becomes a source pad. Fig. 3 shows a portion where no opening is provided.

[0058] The drain electrode (second electrode) 45 is disposed on the rear surface (n + The rear surface of the starting substrate 41 is entirely provided with n + Type drain region 11(n + ohmic contact to the starting substrate 41), + The gate electrode 12 is electrically connected to the drain region 11 .

[0059] (Method of Manufacturing a Semiconductor Device According to an Embodiment) Next, a method for manufacturing a semiconductor device according to an embodiment will be described. First, a surface structure is formed on a semiconductor substrate 40 in the same manner as in the conventional semiconductor device manufacturing method. A MOS structure in an active region 1 and a breakdown voltage structure 30 in an edge termination region 2 are formed in the semiconductor substrate 40. Next, an interlayer insulating film 19 is formed on the front surface of the semiconductor substrate 40. Next, an opening is formed in the interlayer insulating film 19 in a central portion 1a of the active region 1, and a barrier metal 38 and a source electrode 44 are formed in the active region 1.

[0060] Next, a polyimide film 34 is selectively formed on the source electrode 44 in the central portion 1a of the active region 1, and on the interlayer insulating film 19 in the peripheral portion 1b of the active region 1 and the edge termination region 2. This polyimide film 34 is formed at a distance of 0.66d or more from the end T of the semiconductor device. If the side surface 46 of the semiconductor device is inclined by θ degrees from the vertical after dicing due to the settings of the dicing device, etc., the polyimide film 34 may be formed at a distance of dtanθ+0.66d or more from the end T of the semiconductor device.

[0061] Next, nickel or titanium (Ti) is formed on the entire back surface of the semiconductor substrate 40, and then annealed to form the drain electrode 45. Next, the polyimide film 34 is selectively removed from the central portion 1a of the active region 1. The portion exposed in the opening of the polyimide film 34 becomes the source pad. Next, the semiconductor substrate is diced (cut) to separate it into individual chips. This completes the semiconductor device according to the embodiment.

[0062] As described above, according to the semiconductor device of the embodiment, the polyimide film is spaced 0.66d or more from the edge of the semiconductor device. This prevents blue light from passing through the interlayer insulating film and being absorbed by the polyimide film even if it is emitted from the surface of the semiconductor device. This prevents the composition of the polyimide film from changing due to blue light, which would deteriorate the adhesion between the polyimide film and the interlayer insulating film, and thus prevents a decrease in the reliability of the semiconductor device.

[0063] As described above, the present disclosure can be modified in various ways without departing from the spirit of the present disclosure, and in each of the above-mentioned embodiments, for example, the dimensions and impurity concentrations of each part are set in various ways according to the required specifications. In addition, each of the above-mentioned embodiments can be applied to semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) as well as other semiconductors. In addition, each of the above-mentioned embodiments has been described using a MOSFET as an example, but can also be applied to semiconductor devices having a pn junction therein, such as an IGBT, a pn diode, and a Schottky barrier diode (SBD) employing a Junction Barrier Schottky (JBS) structure. [Industrial Applicability]

[0064] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present disclosure is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, igniters for automobiles, and the like. [Explanation of symbols]

[0065] 1 active area 1a Central part of the active region 1b Outer periphery of active region 2 Edge Termination Area 10 Silicon carbide semiconductor device 11 n + Type drain region 12 n - Mold Drift Region 13 p-type base region 13a p type base extension 14 n + Type Source Area 15 p ++ Mold Contact Area 15a p ++ Type contact extension 16 Trench 17 Gate insulating film 18 Gate electrode 19, 119 Interlayer insulating film 20 n-type current diffusion region 21 P under the trench + type area 22 p between adjacent trenches + type area 23 p between adjacent trenches + Bottom of the type area 23a p + Lower part of mold extension 24 p between adjacent trenches + Top of the mold area 24a p + Upper part of mold extension 25 p-type outer region 30 Pressure-resistant structure 31 P-type region of voltage-resistant structure 32 Pressure-resistant structure p - type area 33n + Type channel stopper region 34, 134 Polyimide film 40 Semiconductor Substrate 41, 141 n + Starting substrate 42, 142 n - mold silicon carbide layer 43 Ohmic Electrode 44 Source electrode 45 Drain electrode 46 Side of semiconductor device

Claims

1. A semiconductor device having an active region and a termination region surrounding the active region, The termination region is a semiconductor substrate of a first conductivity type; a first semiconductor region of a first conductivity type having a thickness d provided on a surface of the semiconductor substrate; an insulating film provided on a surface of the first semiconductor region; a polyimide film selectively provided on a surface of the insulating film; Equipped with The polyimide film is provided at a distance of 0.66d or more from an end of the semiconductor device.

2. The semiconductor device has a side surface inclined at θ degrees from the vertical, 2. The semiconductor device according to claim 1, wherein the polyimide film is provided at a distance of 0.66d+dtan .theta. or more from an end of the semiconductor device.

3. The semiconductor device has a side surface inclined at θ degrees from the vertical, If the thickness of the semiconductor substrate is D, 2. The semiconductor device according to claim 1, wherein the polyimide film is provided at a distance of 0.66d+Dtan .theta. or more from an end of the semiconductor device.

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