Manufacturing method for thin film transistor, and thin film transistor

Abstract

To provide a manufacturing method for a thin film transistor using a fluorine-containing silicon nitride film as a gate insulating film, in which resist patterning on the gate insulating film can be performed stably.SOLUTION: A manufacturing method for a thin film transistor includes: a semiconductor layer forming step of forming an oxide semiconductor layer 3 on a substrate 2; a gate insulating layer forming step of forming a gate insulating layer 4 consisting of a fluorine-containing silicon nitride film (SiN:F) on the oxide semiconductor layer 3; and a gate electrode forming step of forming a gate electrode 5 on the gate insulating layer 4 by a patterning method using a resist. The gate electrode forming step includes: a surface processing step of forming a surface processing layer for improving the adhesiveness of the resist on the gate insulating layer 4; and a resist applying step of applying the resist on the surface processing layer.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a thin film transistor and a thin film transistor. [Background technology]

[0002] In recent years, thin-film transistors using In-Ga-Zn-O (IGZO) oxide semiconductors as the semiconductor layer (channel layer) have been actively developed. In this thin-film transistor, various insulating layers such as a protective layer and a gate insulating layer made of silicon nitride (SiN) or silicon oxide (SiO) are formed around the semiconductor layer. For example, Patent Document 1 describes a SiCl 4 Gas and SiF 4 This paper describes a method for manufacturing a thin film transistor in which an insulating layer made of a fluorine-containing silicon oxide film is formed on an oxide semiconductor layer by a plasma CVD method using a mixed gas containing a nitrogen gas and an oxygen gas as a process gas. In this manufacturing method, by forming a fluorine-containing silicon oxide film on a semiconductor layer that is an oxide semiconductor, the fluorine can terminate defects in the oxide semiconductor and improve the electrical characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-195610 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the manufacturing method described in the above Patent Document 1 uses relatively expensive SiCl 4 However, the use of gas increases the cost. To reduce the cost, SiCl 4 Without using gas, SiF 4 When a fluorine-containing silicon oxide film is formed using a mixed gas of fluorine gas and oxygen gas, the film formation becomes unstable on a semiconductor layer that is an oxide semiconductor.

[0005] On the other hand, SiF 4 When a fluorine-containing silicon nitride film is formed using a mixed gas consisting of a fluorine gas, a nitrogen gas, and a hydrogen gas, the film can be stably formed on a semiconductor layer that is an oxide semiconductor, and can exhibit high insulating properties. However, in this case, when a gate electrode or the like is formed on the fluorine-containing silicon nitride film by a patterning method using a resist, the adhesion between the fluorine-containing silicon nitride film and the resist is not high, and the developer penetrates between the fluorine-containing silicon nitride film and the resist during the patterning of the resist, making the patterning process unstable.

[0006] The present invention has been made in view of the above problems, and has as its main object to enable stable patterning of a resist on a gate insulating film in a manufacturing method for a thin film transistor using a fluorine-containing silicon nitride film as a gate insulating film. [Means for solving the problem]

[0007] That is, the method for manufacturing a thin film transistor of the present invention is a method for manufacturing a top-gate type thin film transistor, and includes a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a semiconductor layer formed on a substrate, and a gate electrode forming step of forming a gate electrode on the gate insulating layer, the gate electrode forming step including a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve adhesion of a resist, a resist patterning step of applying a resist to a surface of the surface treatment layer and then patterning the resist, and a gate electrode forming step of forming a gate electrode on the gate insulating layer from which the resist has been removed in the resist patterning step.

[0008] In this manufacturing method, the surface treatment layer improves the adhesion between the fluorine-containing silicon nitride film constituting the gate insulating layer and the resist, so that the developer can be prevented from penetrating between the fluorine-containing silicon nitride film and the resist during patterning of the resist, and patterning can be performed stably. This improves the manufacturing yield of top-gate thin film transistors and reduces manufacturing costs.

[0009] A specific embodiment of the surface treatment step includes a hydrophobization step of applying a primer onto the gate insulating layer to make the layer hydrophobic, and an annealing step of removing a solvent contained in the primer by heat treatment. With this method, the surface of the gate insulating layer is made hydrophobic, which can more reliably prevent the intrusion of the developing solution, which is an aqueous solution, during resist patterning. Furthermore, by performing a heat treatment after applying the primer and removing the solvent, the chemical bond between the primer and the fluorine-containing silicon nitride film can be promoted, and the adhesion between the resist layer and the fluorine-containing silicon nitride film can be further improved.

[0010] The primer applied onto the gate insulating layer is likely to remain even after the resist is removed, and may generate unexpected fixed charges or deteriorate the fluorine-containing silicon nitride film. Therefore, it is preferable that the gate electrode forming step includes a surface treatment layer removing step of removing the surface treatment layer remaining on the gate insulating layer after removing the applied resist. In this way, the primer layer remaining after the resist is removed can be reduced, and good thin film transistor characteristics can be obtained.

[0011] A specific example of the gate insulating layer forming step is forming the gate insulating layer by a plasma CVD method.

[0012] Furthermore, a method for manufacturing a thin film transistor of the present invention is a method for manufacturing a bottom-gate type thin film transistor, comprising: a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a gate electrode formed on a substrate; and a semiconductor layer forming step of forming a semiconductor layer on the gate insulating layer, the semiconductor layer forming step comprising: a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve adhesion of a resist; a resist patterning step of applying a resist to a surface of the surface treatment layer and then patterning the resist; and a semiconductor film forming step of forming a semiconductor film on the gate insulating layer from which the resist has been removed in the resist patterning step. Such a manufacturing method can achieve the same effects in manufacturing a bottom-gate thin-film transistor as the above-mentioned manufacturing method of a top-gate thin-film transistor.

[0013] The thin-film transistor of the present invention is a top-gate type thin-film transistor in which a semiconductor layer, a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F), and a gate electrode are laminated in this order on a substrate, and is characterized in that a surface treatment layer for improving adhesion of a resist is present at the interface between the gate insulating layer and the gate electrode.

[0014] Furthermore, the thin film transistor of the present invention is a bottom-gate type thin film transistor in which a gate electrode, a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F), and a semiconductor layer are sequentially laminated on a substrate, and is characterized in that a surface treatment layer for improving adhesion of a resist is present at the interface between the gate insulating layer and the semiconductor layer.

[0015] Such a thin film transistor can provide the same effects as those of the above-described method for producing a thin film transistor of the present invention. Effect of the Invention

[0016] According to the present invention thus configured, in a method for manufacturing a thin film transistor using a fluorine-containing silicon nitride film as a gate insulating film, resist patterning on the gate insulating film can be stably performed. [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 is a longitudinal sectional view illustrating a schematic configuration of a thin film transistor according to the present embodiment. [Diagram 2] FIG. 2 is a diagram illustrating a configuration of a plasma processing apparatus used in the manufacturing method of the embodiment. [Diagram 3] 5A to 5C are schematic views illustrating a gate electrode formation step in the manufacturing method according to the embodiment. [Figure 4] Photographs showing evaluation samples obtained in experimental examples. [Diagram 5] 5A to 5C are schematic views illustrating a gate electrode formation step in the manufacturing method according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] A thin film transistor 1 according to one embodiment of the present invention and a method for manufacturing the same will be described below.

[0019] <1. Thin-film transistor> The thin film transistor 1 of this embodiment is a so-called top-gate type TFT, and uses an oxide semiconductor for the channel. As shown in Fig. 1, the thin film transistor 1 includes a semiconductor layer 3, which is a channel layer, a gate insulating layer 4, and a gate electrode 5, which are laminated in this order from the substrate 2 side, and a source electrode 6 and a drain electrode 7 provided on both sides of the semiconductor layer 3.

[0020] The substrate 2 is made of any material that can transmit light, and may be made of, for example, a resin material such as plastics (synthetic resins) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, etc., or a glass material.

[0021] The semiconductor layer 3 (channel layer) allows the current flowing between the source electrode 6 and the drain electrode 7 to pass. The semiconductor layer 3 of this embodiment is made of an oxide semiconductor and contains, as a main component, an oxide of at least one element selected from, for example, In, Ga, Zn, Sn, Al, Ti, etc. Specific examples of materials constituting the semiconductor layer 3 include, for example, In-Ga-Zn-O (IGZO), In-Al-Mg-O, In-Al-Zn-O, and In-Hf-Zn-O. This semiconductor layer 3 is composed of an amorphous oxide semiconductor film. The semiconductor layer 3 of this embodiment has a single layer structure, but is not limited thereto, and may have a laminated structure formed by stacking multiple layers having different compositions and crystallinity.

[0022] The gate insulating layer 4 is made of any insulating material having high insulating properties, and in this embodiment, it is made of an insulating film (gate insulating film) mainly composed of a silicon nitride film containing fluorine (SiN:F). The gate insulating layer 4 may have a single layer structure or a laminated structure of two or more layers. For example, a SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , Hf 2 and the like may be laminated with an insulating film containing one or more oxides selected from the above.

[0023] The gate electrode 5 controls the carrier density in the semiconductor layer 3 by the gate voltage applied to the thin film transistor 1. The gate electrode 5 is made of any material having high conductivity, and may be made of one or more metals selected from, for example, Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, etc. Also, it may be made of a conductive film of a metal oxide such as Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), In-Ga-Zn-O (IGZO), etc. The gate electrode 5 may be made of a single layer structure of these conductive films or a laminated structure of two or more layers. In the thin film transistor 1 of this embodiment, a surface treatment layer used for surface treatment, such as a primer containing hexamethyldisilazane or the like, exists (remains) at the interface between the gate electrode 5 and the gate insulating layer 4.

[0024] The source electrode 6 and the drain electrode 7 are formed to be spaced apart from each other so as to partially cover the surface of the semiconductor layer 3. Like the gate electrode 5, the source electrode 6 and the drain electrode 7 are made of a highly conductive material so as to function as an electrode. The source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminate structure in which multiple layers made of different materials are stacked on top of each other.

[0025] 2. Thin-film transistor manufacturing method Next, a method for manufacturing the thin film transistor 1 having the above-mentioned structure will be described. The method for manufacturing the thin film transistor 1 of this embodiment includes (1) a semiconductor layer forming step, (2) a gate insulating layer forming step, (3) a gate electrode forming step, and (4) a source / drain electrode forming step. Each step will be described below.

[0026] (1) Semiconductor layer formation process First, an oxide semiconductor film is formed on the substrate 2. The oxide semiconductor film may be formed by a known method, for example, by sputtering a conductive oxide sintered body such as InGaZnO as a target using inductively coupled plasma. However, the method is not limited to this, and the oxide semiconductor film may be formed by other methods. Then, the oxide semiconductor film formed on the substrate 2 may be patterned by, for example, a photolithography process.

[0027] (2) Gate insulation layer formation process Next, a gate insulating film (gate insulating layer 4) is formed on the oxide semiconductor film constituting the semiconductor layer 3. In this embodiment, a gate insulating film mainly composed of a fluorine-containing silicon nitride film is formed by a plasma CVD method using an inductively coupled plasma processing apparatus 100.

[0028] 2, the plasma processing apparatus 100 includes a vacuum vessel 20 having a processing chamber 10 formed therein that is evacuated to a vacuum and into which a process gas G is introduced, an antenna 30 provided inside the processing chamber 10, and a high frequency power supply 40 that applies a high frequency (13.56 MHz) to the antenna 30. When a high frequency is applied from the high frequency power supply 40 to the antenna 30, a high frequency magnetic field generated from the antenna 30 is formed in the processing chamber 10, generating an induced electric field, and thus an inductively coupled plasma P is generated.

[0029] Specifically, in this process, SiF 4 A mixed gas consisting of nitrogen gas and hydrogen gas is supplied into the processing chamber 10 as a process gas, and in this state, a high frequency is applied to the antenna 30 to generate an inductively coupled plasma. In this embodiment, the supply flow rate of the process gas, the high frequency power (RF power) applied to the antenna 30, the pressure inside the processing chamber, the processing time, the substrate temperature, and the like may be known conditions.

[0030] (3) Gate electrode formation process Next, a gate electrode 5 is formed on the gate insulating layer 4. This gate electrode formation process includes (3-1) a surface treatment process, (3-2) a resist patterning process, (3-3) a surface treatment layer removal process, and (3-4) a film formation process.

[0031] (3-1) Surface treatment process The surface treatment step is a step of forming a surface treatment layer on the surface of the gate insulating layer 4 to improve adhesion of the resist to the gate insulating layer 4. The surface treatment step of this embodiment includes (3-1-1) a hydrophobization step of hydrophobizing the surface of the gate insulating layer, and (3-1-2) an annealing step of removing the solvent contained in the applied primer by heat treatment.

[0032] (3-1-1) Hydrophobization process In this step, a primer is applied to the surface of the gate insulating layer (FIGS. 3(a) and 3(b)). The paint constituting the primer has the property of making the surface of the fluorine-containing silicon nitride film constituting the gate insulating layer 4 hydrophobic, and for example, hexamethyldisilazane (HMDS) is preferable. However, the paint constituting the primer is not limited to this, and any paint having similar properties may be used. The primer may be applied using, for example, a spin coater or the like, but is not limited to this.

[0033] (3-1-2) Annealing process After applying a primer to the gate insulating layer 4, an annealing step is performed. By performing this annealing step, the solvent contained in the applied primer is removed, and chemical bonding between the primer and the surface of the silicon nitride film containing fluorine can be promoted. The annealing step is preferably performed, for example, in air or an inert gas atmosphere such as nitrogen, at a temperature of 100° C. or higher and 130° C. or lower, for 1 minute or higher and 10 minutes or lower, but is not limited thereto.

[0034] (3-2) Resist patterning process After forming a surface treatment layer on the surface of the gate insulating layer 4, a resist pattern is formed on the surface treatment layer by a photolithography process. Specifically, after applying a photoresist (photosensitive material) to the entire surface of the surface treatment layer (FIG. 3(c)), exposure and development are performed to remove the photoresist from the surface region of the gate insulating layer 4 where the gate electrode is to be formed (FIG. 3(d)).

[0035] (3-3) Surface treatment layer removal process Next, a process is performed to remove the surface treatment layer (primer) remaining on the surface region of the gate insulating layer 4 on which the gate electrode is to be formed. Specifically, the surface treatment layer is removed by, for example, ashing, UV cleaning, dry etching, or the like (FIG. 3(e)).

[0036] (3-4) Film formation process Then, the surface treatment layer is removed to expose the surface of the gate insulating layer 4, and a gate electrode is formed on the surface of the gate insulating layer 4. The method for forming the gate electrode is not particularly limited, and may be a known method such as a vacuum deposition method. After the gate electrode is formed, the patterned photoresist is peeled off from the gate insulating layer 4 by a lift-off method or the like (FIG. 3(f)).

[0037] (4) Source and drain electrode formation process Then, the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 3. The formation of the source electrode 6 and the drain electrode 7 is not particularly limited, and may be performed by any known method.

[0038] (5) Post-annealing process After all components are formed, post-annealing (heat treatment) may be performed as necessary. This post-annealing may be performed, for example, in a nitrogen atmosphere at atmospheric pressure. The temperature in the furnace during post-annealing is not particularly limited, and is, for example, 150°C or higher and 350°C or lower. The heat treatment time is also not particularly limited, and is, for example, 1 hour or higher and 3 hours or lower.

[0039] In this manner, the thin film transistor 1 of the present embodiment can be obtained.

[0040] <3. Effects of this embodiment> According to the manufacturing method of the present embodiment configured as described above, in the gate electrode formation step, a surface treatment layer is formed on the surface of the gate insulating layer 4 before applying the resist, so that the adhesion between the fluorine-containing silicon nitride film constituting the gate insulating layer 4 and the resist can be improved. This makes it possible to suppress the infiltration of the developer between the fluorine-containing silicon nitride film and the resist during patterning of the resist, and makes it possible to stably pattern the resist. This improves the manufacturing yield of the top-gate thin film transistor 1 and reduces the manufacturing cost.

[0041] The effects of the method for manufacturing the thin film transistor 1 of this embodiment were confirmed by experimental examples. In the experimental example, (A) a sample in which a resist was formed on the surface of a fluorine-containing silicon nitride film without a surface treatment layer, and (B) a sample in which a resist was formed on the surface of a fluorine-containing silicon nitride film via a surface treatment layer were prepared. The surface treatment layer was formed by applying a primer, which is hexamethyldisilazane, to the surface of the fluorine-containing silicon nitride film and then heat-treating it at 110°C for 1 minute. These samples were then exposed and developed to perform resist patterning. The results are shown in Figure 4.

[0042] As shown in Figure 4, in the sample in which the resist was formed without an intermediate surface treatment layer (primer), the resist peeled off during patterning, whereas in the sample in which the resist was formed via a surface treatment layer (primer), the resist remained even after patterning without peeling off.

[0043] <4. Other Modified Embodiments> The present invention is not limited to the above-described embodiment. For example, in the surface treatment step of the above embodiment, a primer is applied as the surface treatment layer, but this is not limited thereto. In another embodiment, in the (3-1) hydrophobization step, a silicon nitride film or a silicon oxide film not containing fluorine may be formed as the surface treatment layer on the surface of the gate insulating layer 4, which is a fluorine-containing silicon nitride film (FIGS. 5(a) and 5(b)). Even in this way, the adhesion of the resist can be improved and the intrusion of the developer during the patterning of the resist can be prevented. In this case, in the (3) gate electrode formation step, after the (3-2) resist patterning step (FIGS. 5(c) and 5(d)), the (3-4) film formation step (FIG. 5(e)) may be performed without performing the (3-3) surface treatment layer removal step.

[0044] In another embodiment, in the gate electrode formation step, the surface treatment layer does not need to be removed after the gate electrode 5 is formed.

[0045] The thin film transistor 1 and the manufacturing method thereof of the embodiment are directed to a top-gate type thin film transistor, but are not limited thereto. The thin film transistor 1 of another embodiment may be a so-called bottom-gate type in which the gate electrode 5, the gate insulating layer 4, and the semiconductor layer 3 are arranged in this order from the substrate 2 side. In this case, the semiconductor layer forming step of forming the semiconductor layer 3 on the gate insulating layer 4, which is a silicon nitride film containing fluorine, may include a surface treatment step of forming a surface treatment layer on the gate insulating layer 4 to improve the adhesion of the resist, a resist patterning step of applying a resist to the surface of the surface treatment layer and then patterning the resist, and a semiconductor film forming step of forming the semiconductor layer 3 on the gate insulating layer 4 exposed in the resist patterning step. In this way, in the resist patterning step when forming the semiconductor layer 3, the developer is prevented from penetrating between the fluorine-containing silicon nitride film and the resist, and the patterning process can be stably performed. In the bottom-gate thin-film transistor 1 manufactured in this manner, a surface treatment layer used for surface treatment, such as a fluorine-free silicon nitride film or silicon oxide film, exists (remains) at the interface between the gate insulating layer 4 and the semiconductor layer 3. At the interface between the gate insulating layer 4 and the semiconductor layer 3, a primer containing hexamethyldisilazane or the like may remain as a surface treatment layer.

[0046] Furthermore, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible without departing from the spirit of the present invention. [Explanation of symbols]

[0047] 1. Thin-film transistor 2. Circuit Board 3. Semiconductor layer 4 Gate insulating layer 5 Gate electrode 6 Source electrode 7 Drain electrode

Claims

1. A method for manufacturing a top-gate thin film transistor, comprising the steps of: a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a semiconductor layer formed on a substrate; forming a gate electrode on the gate insulating layer; The gate electrode forming step includes: a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve the adhesion of the resist; a resist patterning step of applying a resist to the surface of the surface treatment layer and then patterning the resist; and forming a gate electrode on the gate insulating layer from which the resist has been removed in the resist patterning step.

2. The surface treatment step comprises: a hydrophobizing step of applying a primer onto the gate insulating layer to hydrophobize the gate insulating layer; The method for producing a thin film transistor according to claim 1 , further comprising an annealing step of removing a solvent contained in the primer by heat treatment.

3. The gate electrode forming step includes: The method for producing a thin film transistor according to claim 2 , further comprising a surface treatment layer removing step of removing the surface treatment layer remaining on the gate insulating layer after removing the applied resist.

4. 2. The method for producing a thin film transistor according to claim 1, wherein in the gate insulating layer forming step, the gate insulating layer is formed by a plasma CVD method.

5. A method for manufacturing a bottom-gate thin film transistor, comprising the steps of: a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a gate electrode formed on a substrate; forming a semiconductor layer on the gate insulating layer; The semiconductor layer forming step includes: a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve the adhesion of the resist; a resist patterning step of applying a resist to the surface of the surface treatment layer and then patterning the resist; and forming a semiconductor film on the gate insulating layer from which the resist has been removed in the resist patterning step.

6. A top-gate type thin film transistor in which a semiconductor layer, a gate insulating layer made of a silicon nitride film containing fluorine (SiN:F), and a gate electrode are sequentially stacked on a substrate, A thin film transistor in which a surface treatment layer for improving adhesion of a resist is present at the interface between the gate insulating layer and the gate electrode.

7. A bottom-gate type thin film transistor in which a gate electrode, a gate insulating layer made of a silicon nitride film containing fluorine (SiN:F), and a semiconductor layer are sequentially stacked on a substrate, A thin film transistor in which a surface treatment layer for improving adhesion of a resist is present at the interface between the gate insulating layer and the semiconductor layer.

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