Reverse polarity protection circuit, semiconductor device, electronic equipment, vehicle

Abstract

To improve the element withstand capacity of a reverse polarity protection circuit.SOLUTION: A reverse polarity protection circuit 40 comprises: a first transistor 41 connected between a ground electrode T4 and an internal ground node GND_INT; a control circuit 42 that turns the first transistor 41 on when a power supply electrode T1 is at a higher potential than the ground electrode T4 and turns the first transistor 41 off when the power supply electrode T1 is at a lower potential than the ground electrode T4; and a clamp circuit 43 connected between the control end of the first transistor 41 and the ground electrode T4 to limit the voltage between the two ends of the first transistor 41 to become equal to or less than a predetermined upper limit value.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a reverse connection protection circuit, a semiconductor device, an electronic device, and a vehicle. [Background technology]

[0002] The applicant of the present application has proposed many new technologies relating to in-vehicle semiconductor devices (for example, an IPD [intelligent power device] or an SPS [smart power switch]) (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 187785

[0004] [overview] However, in the conventional semiconductor device, there is room for improvement in terms of the element tolerance of the reverse connection protection circuit.

[0005] For example, a reverse connection protection circuit according to the present disclosure includes a first transistor connected between a ground electrode and an internal ground node, a control circuit configured to turn on the first transistor when a power supply electrode has a higher potential than the ground electrode and to turn off the first transistor when the power supply electrode has a lower potential than the ground electrode, and a clamp circuit connected between a control end of the first transistor and the ground electrode and configured to limit a voltage between both ends of the first transistor to a predetermined upper limit value or less. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of a configuration of an electronic device equipped with a semiconductor device. [Diagram 2] FIG. 2 is a diagram illustrating an example of a configuration of an active clamp circuit. [Diagram 3]FIG. 3 is a diagram illustrating an example of an active clamp operation. [Figure 4] FIG. 4 is a diagram showing a first embodiment of a reverse connection protection circuit. [Diagram 5] FIG. 5 is a diagram showing a discharge path when the power supply is open in the first embodiment. [Figure 6] FIG. 6 is a diagram showing operational waveforms when the power supply is open in the first embodiment. [Figure 7] FIG. 7 is a diagram showing a second embodiment of the reverse connection protection circuit. [Figure 8] FIG. 8 is a diagram showing operational waveforms when the power supply is open in the second embodiment. [Figure 9] FIG. 9 is a diagram showing a schematic configuration of a diode integrated in a semiconductor device. [Figure 10] FIG. 10 is a diagram showing a third embodiment of the reverse connection protection circuit. [Figure 11] FIG. 11 is a diagram showing the external appearance of the vehicle.

[0007] [Detailed Description] <Electronic equipment> 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. An electronic device A of this example configuration includes a semiconductor device 1, a DC power supply 2, and a load 3. The DC power supply 2 may be an in-vehicle battery. The load 3 may be an engine control ECU (electronic control unit), an air conditioner, a body device, or the like.

[0008] The semiconductor device 1 is a high-side switch IC (a type of IPD) that connects / disconnects a DC power supply 2 and a load 3. With reference to the figure, the semiconductor device 1 is configured by integrating an output transistor 10 (for example, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]) and a controller 20.

[0009] In this specification, a MOSFET refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0010] In this specification, a MOSFET may be an enhancement type unless otherwise specified. An enhancement type MOSFET is turned off when the gate-source voltage is 0V. In other words, an enhancement type MOSFET has a positive on-threshold voltage. On the other hand, a depletion type MOSFET is turned on when the gate-source voltage is 0V. In other words, a depletion type MOSFET has a negative on-threshold voltage.

[0011] The semiconductor device 1 also includes external terminals T1 to T4 as means for establishing electrical connection with the outside of the device.

[0012] The external terminal T1 is a power supply electrode (VBB pin) for receiving a power supply voltage VB (e.g., 12 V) from a DC power supply 2. The external terminal T2 is a load connection electrode or an output electrode (OUT pin) for externally connecting a load 3 (such as a bulb lamp, a relay coil, a solenoid, a light-emitting diode, or a motor). The external terminal T3 is a signal input electrode (IN pin) for receiving an external input of an external control signal Si from an ECU or the like. The external terminal T4 is a ground electrode (GND pin) to which a ground voltage GND is applied.

[0013] The output transistor 10 may be an insulated gate power transistor. Referring to this figure, the output transistor 10 is connected between external terminals T1 and T2. The output transistor 10 is driven in response to a gate drive signal G1 input to the gate. The output transistor 10 connected in this manner functions as a high-side switch element that connects / disconnects the external terminals T1 and T2. The output transistor 10 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate drive signal G1 is at a low level.

[0014] Furthermore, in the semiconductor device 1 that handles high voltages and large currents, a vertical-structure VDMOSFET (vertical double diffused MOSFET) is preferably used as the output transistor 10. In particular, in developing high-performance, low-cost devices, it is desirable to employ n-type substrate technology.

[0015] The controller 20 includes a plurality of functional circuits for implementing various functions, including, for example, a circuit for generating a gate drive signal G1 for controlling the drive of the output transistor 10 based on an external control signal Si.

[0016] The external terminal T1 supplies a power supply voltage VB to the drain of the output transistor 10 and the controller 20. The external terminal T2 is connected to the source of the output transistor 10 and supplies an output voltage Vo and an output current Io to the load 3. A signal line (e.g., a wire harness) laid between the external terminal T2 and the load 3 generally includes an inductance component L (and a resistance component). The external terminal T3 transmits an external control signal Si to the controller 20. The external control signal Si can be understood as a drive voltage for the controller 20. The external terminal T4 transmits a ground voltage GND to the controller 20. A resistance component R generally includes a resistance component R between the external terminal T4 and the ground terminal.

[0017] <Active clamp circuit> Incidentally, an inductive load 3 may be connected to the external terminal T2 of the semiconductor device 1. Further, an inductance component L may be associated with the signal line laid between the external terminal T2 and the load 3 as described above. Therefore, for example, when the output transistor 10 is switched from the on state to the off state, the output voltage Vo may become a negative voltage (Vo < GND) due to the electrical energy (back electromotive force) stored in the inductive load 3 or the inductance component L of the signal line. Therefore, an active clamp circuit is provided in the semiconductor device 1 as means for absorbing the above electrical energy (back electromotive force).

[0018] FIG. 2 is a diagram showing a configuration example of the active clamp circuit. The active clamp circuit 30 of this configuration example includes, for example, a series of m stages (where m is an integer of 1 or more, for example, m = 2 in this figure) of Zener diodes 31, a series of n stages (where n is an integer of 1 or more, for example, n = 1 in this figure) of diodes 32, a transistor 33 (for example, NMOSFET), and resistors 34 and 35.

[0019] The cathode of the Zener diode 31 and the drain of the transistor 33 are connected to the external terminal T1 together with the drain of the output transistor 10. The anode of the Zener diode 31 is connected to the anode of the diode 32. The cathode of the diode 32 and the first end of the resistor 34 are both connected to the gate of the transistor 33. The source of the transistor 33 and the first end of the resistor 35 are both connected to the gate of the output transistor 10 (= the applied end of the gate drive signal G1). The source of the output transistor 10 and the second ends of the resistors 34 and 35 are all connected to the external terminal T2. An inductive load such as a coil or a solenoid may be connected to the external terminal T2 as the load 3 (see FIG. 1).

[0020] Note that the resistor 34 may be replaced with, for example, a depletion-type NMOSFET with the gate and source short-circuited. Further, the resistor 35 may be replaced with, for example, Zener diodes and diodes connected with opposite polarities to each other.

[0021] In the following, the active clamp operation by the active clamp circuit 30 will be described assuming that the gate-source voltages of the output transistor 10 and the transistor 33 are Vgs1 and Vgs2, respectively, the breakdown voltage of the Zener diode 31 is mVz, and the forward drop voltage of the diode 32 is nVf.

[0022] 3 is a diagram showing an example of an active clamp operation by the active clamp circuit 30. In this diagram, from the top, an external control signal Si, an output voltage Vo, and an output current Io are depicted. Note that an inductive load is connected as the load 3.

[0023] At time t11, when the external control signal Si rises to a high level (=the logic level for turning on the output transistor 10), the gate drive signal G1 rises to a high level, turning on the output transistor 10. Therefore, the output current Io starts to flow, and the output voltage Vo rises to near the power supply voltage VB.

[0024] After that, at time t12, when the external control signal Si falls to a low level (=the logical level when turning off the output transistor 10), the gate drive signal G1 falls to a low level, and the output transistor 10 turns off. At this time, the inductive load (such as a coil or solenoid) connected as the load 3 continues to pass the output current Io until it releases the electrical energy stored during the on-period of the output transistor 10. As a result, the output voltage Vo falls to a negative voltage lower than the ground voltage GND.

[0025] However, due to the action of the active clamp circuit 30, the gate-source voltage Vgs1 of the output transistor 10 is maintained near the on-threshold voltage Vth of the output transistor 10. As a result, the output transistor 10 is turned on (is not fully turned off). Therefore, the output current Io is discharged via the output transistor 10. At this time, the output voltage Vo is limited to a lower limit voltage VB-Vclp (e.g., VB-50V) or higher that is lower than the power supply voltage VB by an active clamp voltage Vclp (=mVz+nVf+Vgs1+Vgs2).

[0026] In this way, the active clamp circuit 30 limits the drain-source voltage Vds (=VB-Vo) of the output transistor 10 to a predetermined active clamp voltage Vclp or less by turning on the output transistor 10 (without turning it fully off) when the output transistor 10 transitions to an off state. Note that it is desirable to set the active clamp voltage Vclp to a voltage value higher than the maximum rated value of the power supply voltage VB and lower than the drain-source breakdown voltage of the output transistor 10.

[0027] <Reverse connection protection circuit (first embodiment)> In addition, the positive and negative polarities of the DC power supply 2 may be erroneously connected in reverse to the semiconductor device 1. That is, an abnormal state in which the power supply voltage VB is applied to the external terminal T4 and the ground voltage GND is applied to the external terminal T1, that is, a so-called power supply reverse connection state, is assumed. Therefore, the semiconductor device 1 is provided with a reverse connection protection circuit as a means for protecting the internal elements of the semiconductor device 1 even in the power supply reverse connection state.

[0028] 4 is a diagram showing a first embodiment of a reverse connection protection circuit (corresponding to a comparative example to be compared with the second and third embodiments described later). A reverse connection protection circuit 40 of this embodiment is integrated into a semiconductor device 1 together with an internal circuit 50.

[0029] In the above-mentioned power supply reverse connection state, i.e., in a state in which the external terminal T1 has a lower potential than the external terminal T4, the reverse connection protection circuit 40 cuts off the current path from the external terminal T4 to the external terminal T1 via the reverse connection protection circuit 40 and the internal ground node GND_INT. This can protect the internal circuit 50 connected between the external terminal T1 and the internal ground node GND_INT.

[0030] Referring to the figure, the reverse connection protection circuit 40 includes a transistor 41 (eg, an NMOSFET) and a control circuit 42.

[0031] The drain of the transistor 41 is connected to the external terminal T4. The source and back gate of the transistor 41 are both connected to the internal ground node GND_INT. The gate of the transistor 41 is connected to the application terminal of the node voltage Vx. The transistor 41 connected in this manner corresponds to a first transistor connected between the external terminal T4 and the internal ground node GND_INT.

[0032] The control circuit 42 switches the node voltage Vx depending on whether the semiconductor device 1 is in a power supply reverse connection state or not. With reference to this figure, the control circuit 42 includes a transistor 42a (for example, a depletion type NMOSFET) and a Zener diode 42b.

[0033] The drain of the transistor 42a is connected to the external terminal T1. The gate, source, and backgate of the transistor 42a and the cathode of the Zener diode 42b are all connected to the application terminal of the node voltage Vx. The anode of the Zener diode 42b is connected to the internal ground node GND_INT.

[0034] In a normal state in which the positive and negative polarities of the DC power supply 2 are correctly connected, the power supply voltage VB is applied to the external terminal T1, and the ground voltage GND is applied to the external terminal T4. Therefore, the external terminal T1 has a higher potential than the external terminal T4. At this time, the control circuit 42 sets the node voltage Vx to a high level. That is, the control circuit 42 raises the gate-source voltage of the transistor 41 above the on-threshold voltage of the transistor 41 to turn on the transistor 41. Therefore, the current path from the external terminal T1 to the external terminal T4 via the internal ground node GND_INT and the reverse connection protection circuit 40 is made conductive. Therefore, the reverse connection protection circuit 40 does not interfere with the normal operation of the semiconductor device 1.

[0035] On the other hand, in the above-mentioned power supply reverse connection state, the ground voltage GND is applied to the external terminal T1, and the power supply voltage VB is applied to the external terminal T4. Therefore, the external terminal T1 has a lower potential than the external terminal T4. At this time, the control circuit 42 sets the node voltage Vx to a low level. That is, the control circuit 42 reduces the gate-source voltage of the transistor 41 below the on-threshold voltage of the transistor 41 to turn off the transistor 41. Therefore, the current path from the external terminal T4 to the external terminal T1 via the reverse connection protection circuit 40 and the internal ground node GND_INT is cut off. Therefore, the internal circuit 50 can be protected.

[0036] <Power supply open test> Incidentally, a power supply open test is one of the safety tests imposed on the semiconductor device 1. In the power supply open test, an open state is established between the DC power supply 2 and the external terminal T1 when the output transistor 10 is in an on state.

[0037] 5 is a diagram showing a discharge path when the power supply is open in the first embodiment. In this diagram, an electrostatic protection circuit 60 is depicted as an example of the above-mentioned internal circuit 50. Below, a brief description of the electrostatic protection circuit 60 will be given before describing the behavior when the power supply is open.

[0038] The electrostatic protection circuit 60 is an ESD (electro-static discharge) clamper that can become a low-resistance discharge path when a positive surge (>GND) is applied to the external terminal T1.

[0039] Referring to this figure, the electrostatic protection circuit 60 includes a transistor 61 (e.g., an NMOSFET), a transistor 62 (e.g., a depletion-type NMOSFET), a Zener diode 63, a Zener diode 64 in series at x stages (where x≧1), a diode 65 in series at y stages (where y≧1), and a resistor 66.

[0040] The drain of the transistor 61 is connected to the external terminal T1. The source and backgate of the transistor 61 are both connected to the internal ground node GND_INT. The transistor 61 is accompanied by a parasitic diode with the drain of the transistor 61 as the cathode and the backgate of the transistor 61 as the anode. The transistor 61 may be a VDMOSFET having a vertical structure, similar to the output transistor 10.

[0041] The drain of the transistor 62 is connected to the gate of the transistor 61. The gate, source, and back gate of the transistor 62 are all connected to the internal ground node GND_INT. The cathode of the Zener diode 63 is connected to the gate of the transistor 61. The anode of the Zener diode 63 is connected to the internal ground node GND_INT. The cathode of the Zener diode 64 is connected to the external terminal T1. The anode of the Zener diode 64 is connected to the anode of the diode 65. The cathode of the diode 65 is connected to the gate of the transistor 61. A first end of the resistor 66 is connected to the gate of the transistor 61. A second end of the resistor 66 is connected to the external terminal T4.

[0042] In the electrostatic protection circuit 60 of this configuration example, when a positive surge is applied to the external terminal T1, the transistor 61 is turned on. At this time, electrical continuity is established between the external terminal T1 and the internal ground node GND_INT, and further between the external terminal T1 and the external terminal T4. As a result, the voltage applied to the external terminal T1 is limited to a predetermined ESD clamp voltage or less.

[0043] Continuing with reference to FIG. 5, the behavior when the power supply is turned on will be described. As shown in this figure, an inductive load 3 can be connected to the external terminal T2. Also, an inductance component L may be associated with the signal line laid between the external terminal T2 and the load 3. Therefore, when the external terminal T1 becomes open while the output transistor 10 is in the on state, the output voltage Vo can become a negative voltage (Vo < GND) due to the electrical energy (back electromotive force) stored in the inductive load 3 or the inductance component L of the signal line.

[0044] At this time, the active clamp circuit 30 restricts the drain-source voltage Vds (= VB - Vo) of the output transistor 10 to be equal to or lower than a predetermined active clamp voltage Vclp by turning on the output transistor 10 (without fully turning it off). At this time, the larger the amount of current flowing through the output transistor 10, the faster the above electrical energy (back electromotive force) can be discharged.

[0045] Incidentally, in the normal active clamp operation activated at the time of the off transition of the output transistor 10, the external terminal T1 is in a non-open state. Therefore, a discharge path can be established from the external terminal T1 to the external terminal T2 via the output transistor 10. That is, in the normal active clamp operation, the internal element intervening on the discharge path is only the output transistor 10. Therefore, it is sufficient to consider only the element withstand of the output transistor 10.

[0046] On the other hand, in the power-on test, the external terminal T1 is set to the open state. Therefore, the above electrical energy (back electromotive force) is discharged through the path from the external terminal T4 via the reverse connection protection circuit 40, the electrostatic protection circuit 60, and the output transistor 10 to the external terminal T2, as indicated by the thick arrow in this figure. Therefore, not only the element withstand of the output transistor 10 but also the element withstand of each of the reverse connection protection circuit 40 and the electrostatic protection circuit 60 becomes important.

[0047] First, focus on the electrostatic protection circuit 60. When the power supply is open, the discharge current flows through the parasitic diode associated with the transistor 61. Therefore, only the forward voltage drop of the parasitic diode associated with the transistor 61 is applied between the drain and source of the transistor 61. Also, as described above, the transistor 61 may be a vertical VDMOSFET similar to the output transistor 10. Therefore, the element withstand voltage of the electrostatic protection circuit 60 can be sufficiently ensured.

[0048] Next, focus on the reverse connection protection circuit 40. When the output voltage Vo becomes a negative voltage (Vo < GND) due to the active clamp operation when the power supply is open, the external terminal T1 becomes a lower potential than the external terminal T4. As a result, the transistor 41 is turned off. At this time, the parasitic diode associated with the transistor 41 is in a reverse bias state. Therefore, an excessive voltage may be applied between the drain and source of the transistor 41.

[0049] FIG. 6 is a diagram showing the operation waveform when the power supply is open in the first embodiment. The solid line indicates the output voltage Vo (and thus the terminal voltage of the external terminal T1). On the other hand, the broken line indicates the potential of the internal ground node GND_INT.

[0050] When the output voltage Vo becomes a negative voltage (Vo < GND) due to the active clamp operation when the power supply is open, the transistor 41 is turned off as described above. Therefore, the internal ground node GND_INT follows the output voltage Vo and becomes a negative voltage. As a result, the voltage ΔV1 (= GND - GND_INT) between the drain and source of the transistor 41 swings largely negatively.

[0051] Note that, unlike the output transistor 10 and the transistor 61, it is difficult to adopt a vertical VDMOSFET as the transistor 41. Therefore, the element withstand voltage of the reverse connection protection circuit 40 may become a problem.

[0052] Hereinafter, in view of the above considerations, for example, a reverse connection protection circuit that can withstand a power-on test is proposed.

[0053] <Reverse connection protection circuit (second embodiment)> FIG. 7 is a diagram showing a second embodiment of the reverse connection protection circuit. The reverse connection protection circuit 40 of the present embodiment is based on the above-described first embodiment (FIG. 4) and further includes a clamp circuit 43.

[0054] The clamp circuit 43 is connected between the gate of the transistor 41 (= the application end of the node voltage Vx) and the external terminal T4. The clamp circuit 43 limits the drain-source voltage of the transistor 41 to a predetermined upper limit value or less. Specifically in this figure, the clamp circuit 43 includes a transistor 43a (for example, an NMOSFET) and a series of z diodes 43b (where z is an integer of 1 or more, for example, z = 3 in this figure).

[0055] Both the source and the back gate of the transistor 43a are connected to the gate of the transistor 41. The gate of the transistor 43a is connected to the drain of the transistor 43a. The transistor 43a connected in this way corresponds to a second transistor diode-connected between the gate of the transistor 41 and the external terminal T4.

[0056] The anode of the diode 43b is connected to the drain of the transistor 43a. The cathode of the diode 43b is connected to the external terminal T4. The diode 43b connected in this way corresponds to at least one diode connected between the gate of the transistor 41 and the external terminal T4.

[0057] As described above, when the output voltage Vo becomes a negative voltage (Vo < GND) due to the active clamp operation at the time of power supply open, the transistor 41 becomes an off state. Therefore, the internal ground node GND_INT becomes a negative voltage following the output voltage Vo.

[0058] On the other hand, the node voltage Vx only drops to a predetermined clamp voltage Vclp2 (e.g., -20V to -25V) due to the operation of the clamp circuit 43. Therefore, as the voltage of the internal ground node GND_INT drops, the gate-source voltage of the transistor 41 is maintained near the on-threshold voltage of the transistor 41. For this reason, the transistor 41 turns on (and does not turn fully off). Note that the clamp voltage Vclp2 may be adjusted according to the number of series stages of the diode 43b.

[0059] FIG. 8 is a diagram showing the operation waveforms at the time of power supply opening in the second embodiment. Similar to the previous FIG. 6, the solid line indicates the output voltage Vo (and thus the terminal voltage of the external terminal T1). On the other hand, the dashed line indicates the potential of the internal ground node GND_INT.

[0060] During the active clamp operation at the time of power supply opening, when the output voltage Vo becomes a negative voltage (Vo < GND), the transistor 41 becomes off as described above. Therefore, the internal ground node GND_INT follows the output voltage Vo and becomes a negative voltage. This point is the same as in the previous first embodiment (FIG. 6).

[0061] However, in this embodiment, as the voltage of the internal ground node GND_INT drops, the transistor 41 turns on (and does not turn fully off). As a result, the drain-source voltage ΔV2 (= GND - GND_INT) of the transistor 41 is suppressed to be smaller than that in the first embodiment. Therefore, an element withstand voltage that can withstand a power supply opening test is ensured.

[0062] Also, for the resistance component R connected to the external terminal T4 (or the external terminal T2), a lower resistance value can be tolerated.

[0063] <Diode> FIG. 9 is a diagram showing the schematic configuration of the diode integrated in the semiconductor device 1 (= a diagram showing the longitudinal sectional structure of the semiconductor device 1). The semiconductor device 1 of this configuration example includes an n-type substrate 101, an n-type epitaxial layer 102, an n-type polysilicon region 103, and a p-type polysilicon region 104.

[0064] N-type substrate 101 corresponds to the drain electrode of output transistor 10. Therefore, power supply voltage VB (however, ground voltage GND when the power supply is reversely connected) can be applied to n-type substrate 101.

[0065] N-type epitaxial layer 102 is an n-type epitaxially grown layer formed on the surface of n-type substrate 101. Note that n-type epitaxial layer 102 is electrically connected to n-type substrate 101. Therefore, like n-type substrate 101, power supply voltage VB (ground voltage GND when the power supply is reversely connected) can be applied to n-type epitaxial layer 102.

[0066] The n-type polysilicon region 103 and the p-type polysilicon region 104 each form a pn junction on the surface layer of the n-type epitaxial layer 102. The n-type polysilicon region 103 is formed by ion-implanting an n-type impurity into a polysilicon film, and functions as the cathode of the polysilicon diode Dpoly. On the other hand, the p-type polysilicon region 104 is formed by ion-implanting a p-type impurity into a polysilicon film, and functions as the anode of the polysilicon diode Dpoly.

[0067] Incidentally, if a MOS diode Depi is formed inside the n-type epitaxial layer 102, a p-type well 105 is first formed inside the n-type epitaxial layer 102, and an n-type semiconductor region 106 and a p-type semiconductor region 107 are then formed inside the p-type well 105. According to this element structure, the p-type well 105 and the p-type semiconductor region 107 function as the anode of the MOS diode Depi, and the n-type semiconductor region 106 functions as the cathode of the MOS diode Depi.

[0068] However, the semiconductor device 1 having the MOS diode Depi is accompanied by a parasitic transistor Qp (=npn type bipolar transistor) having the n-type semiconductor region 106 as an emitter, the p-type well 105 and the p-type semiconductor region 107 as a base, and the n-type substrate 101 and the n-type epitaxial layer 102 as a collector. Therefore, an unintended current may flow from the n-type substrate 101 via the parasitic transistor Qp.

[0069] On the other hand, the polysilicon diode Dpoly described above is not affected by parasitic elements because it is electrically isolated from the n-type substrate 101 and the n-type epitaxial layer 102. Therefore, it can be suitably used as, for example, the diode 43b (see FIG. 7) of the reverse connection protection circuit 40.

[0070] <Reverse connection protection circuit (third embodiment)> 10 is a diagram showing a third embodiment of a reverse connection protection circuit. The reverse connection protection circuit 40 of this embodiment is based on the second embodiment (FIG. 7) and further includes a backgate switching circuit 44.

[0071] The backgate switching circuit 44 connects the backgate of the transistor 41 to the external terminal T4 when the external terminal T1 has a higher potential than the external terminal T4. On the other hand, the backgate switching circuit 44 connects the backgate of the transistor 41 to the internal ground node GND_INT when the external terminal T1 has a lower potential than the external terminal T4. With reference to this figure, the backgate switching circuit 44 includes a transistor 44a (e.g., a depletion-type NMOSFET) and a transistor 44b (e.g., an NMOSFET).

[0072] The drain of the transistor 44a is connected to the internal ground node GND_INT. The gate, source, and back gate of the transistor 44a are all connected to the back gate of the transistor 41.

[0073] The drain of the transistor 44b is connected to the external terminal T4. The source and back gate of the transistor 44b are both connected to the back gate of the transistor 41. The gate of the transistor 44b is connected to the application terminal of the node voltage Vx.

[0074] When the external terminal T1 has a higher potential than the external terminal T4, the control circuit 42 sets the node voltage Vx to a high level and turns on the transistor 44b. Therefore, the backgate of the transistor 41 and the external terminal T4 are electrically connected to each other. This state is understood as a state in which the backgate of the transistor 41 is connected to the external terminal T4.

[0075] On the other hand, when the external terminal T1 has a lower potential than the external terminal T4, the control circuit 42 sets the node voltage Vx to a low level and turns off the transistor 44b. This blocks communication between the backgate of the transistor 41 and the external terminal T4. At this time, the backgate of the transistor 41 is pulled down to the internal ground node GND_INT via the transistor 44a. This state is understood as a state in which the backgate of the transistor 41 is connected to the internal ground node GND_INT.

[0076] According to this embodiment, the back gate of the transistor 41 is always connected to the lowest potential node in the system.

[0077] <Application to vehicles> 11 is a diagram showing the exterior of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0078] The vehicle X includes not only engine vehicles but also electric vehicles (xEVs such as BEVs (battery electric vehicles), HEVs (hybrid electric vehicles), PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0079] The semiconductor device 1 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0080] <Additional Notes> The following is an additional note regarding the above disclosure.

[0081] [Appendix 1] a first transistor (41) connected between a ground electrode (T4) and an internal ground node (GND_INT); a control circuit (42) configured to turn on the first transistor (41) when the power supply electrode (T1) has a higher potential than the ground electrode (T4) and to turn off the first transistor (41) when the power supply electrode (T1) has a lower potential than the ground electrode (T4); a clamp circuit (43) connected between the control end of the first transistor (41) and the ground electrode (T4) and configured to limit a voltage across the first transistor (41) to a predetermined upper limit value or less; A reverse connection protection circuit (40).

[0082] [Appendix 2] 2. The reverse connection protection circuit (40) according to claim 1, wherein the clamp circuit (43) includes a second transistor (43a) diode-connected between a control end of the first transistor (41) and the ground electrode (T4).

[0083] [Appendix 3] 3. The reverse connection protection circuit (40) according to claim 1 or 2, wherein the clamp circuit (43) includes at least one diode (43b) connected between the control end of the first transistor (41) and the ground electrode (T4).

[0084] [Appendix 4] 4. The reverse polarity protection circuit (40) according to claim 3, wherein the at least one diode (43b) is a polysilicon diode (Dpoly) electrically isolated from the semiconductor substrate (101).

[0085] [Appendix 5] The reverse connection protection circuit (40) according to any one of Appendix 1 to 4, further comprising a backgate switching circuit (44) configured to connect a backgate of the first transistor (41) to the ground electrode (T4) when the power supply electrode (T1) has a higher potential than the ground electrode (T4) and to connect the backgate of the first transistor (41) to the internal ground node (GND_INT) when the power supply electrode (T1) has a lower potential than the ground electrode (T4).

[0086] [Appendix 6] The power supply electrode (T1), the ground electrode (T4) and the output electrode (T2); an output transistor (10) connected between the power supply electrode (T1) and the output electrode (T2); an internal circuit (50) connected between the power supply electrode (T1) and the internal ground node (GND_INT); an active clamp circuit (30) configured to limit the voltage across the output transistor (10) below an active clamp voltage (Vclp); A reverse connection protection circuit (40) according to any one of appendix 1 to 5; A semiconductor device (1).

[0087] [Appendix 7] The semiconductor device (1) described in Appendix 6, wherein the internal circuit (50) includes an electrostatic protection circuit (60) configured to provide electrical continuity between the power supply electrode (T1), the internal ground node, and the internal ground node (GND_INT) when a positive surge is applied to the power supply electrode (T1).

[0088] [Appendix 8] A semiconductor device (1) according to appendix 6 or 7; a load (3) connected to the output electrode (T2) of the semiconductor device (1); An electronic device (A).

[0089] [Appendix 9] The electronic device (A) according to appendix 8, wherein the load (3) is an inductive load.

[0090] [Appendix 10] A vehicle (X) equipped with an electronic device (A) according to appendix 8 or 9.

[0091] With the reverse connection protection circuit according to the present disclosure, for example, an element tolerance capable of withstanding a power supply open test can be achieved.

[0092] <Other> In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiment. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects. In addition, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0093] 1. Semiconductor device (high side switch IC) 2 DC power supply 3. Load 10 Output transistor (NMOSFET) 20 Controller 30 Active clamp circuit 31 Zener Diode 32 Diode 33 Transistor (NMOSFET) 34, 35 Resistance 40 Reverse polarity protection circuit 41 Transistor (NMOSFET) 42 Control circuit 42a Transistor (Depletion-type NMOSFET) 42b Zener diode 43 Clamp Circuit 43a Transistor (NMOSFET) 43b Diode 44 Backgate switching circuit 44a Transistor (Depletion-type NMOSFET) 44b Transistor (NMOSFET) 50 Internal circuit 60 Electrostatic protection circuit 61 Transistor (NMOSFET) 62 Transistor (Depletion-type NMOSFET) 63 Zener Diode 64 Zener Diode 65 Diode 66 Resistance 101 n-type substrate 102 n-type epitaxial layer 103 n-type polysilicon region 104 p-type polysilicon region 105 p-type well 106 n-type semiconductor region 107 p-type semiconductor region A Electronic equipment Depi MOS Diode Dpoly Polysilicon Diode GND_INT Internal ground node L Inductance component Qp parasitic transistor (npn) R resistance component T1~T4 External terminals X Vehicle

Claims

1. a first transistor connected between the ground electrode and an internal ground node; a control circuit configured to turn on the first transistor when a power supply electrode is at a higher potential than the ground electrode and to turn off the first transistor when the power supply electrode is at a lower potential than the ground electrode; a clamp circuit connected between the control end of the first transistor and the ground electrode and configured to limit a voltage across the first transistor to a predetermined upper limit value or less; Equipped with a reverse polarity protection circuit.

2. 2. The reverse connection protection circuit according to claim 1, wherein the clamp circuit includes a second transistor diode-connected between the control end of the first transistor and the ground electrode.

3. 2. The reverse connection protection circuit according to claim 1, wherein the clamp circuit includes at least one diode connected between the control end of the first transistor and the ground electrode.

4. 4. The reverse polarity protection circuit of claim 3, wherein the at least one diode is a polysilicon diode electrically isolated from a semiconductor substrate.

5. 2. The reverse connection protection circuit according to claim 1, further comprising a backgate switching circuit configured to connect a backgate of the first transistor to the ground electrode when the power supply electrode is at a higher potential than the ground electrode and to connect the backgate of the first transistor to the internal ground node when the power supply electrode is at a lower potential than the ground electrode.

6. the power supply electrode, the ground electrode and an output electrode; an output transistor connected between the power supply electrode and the output electrode; an internal circuit connected between the power supply electrode and the internal ground node; an active clamp circuit configured to limit a voltage across the output transistor below an active clamp voltage; A reverse connection protection circuit according to any one of claims 1 to 5, A semiconductor device comprising:

7. 7. The semiconductor device according to claim 6, wherein said internal circuitry includes an electrostatic protection circuit configured to establish conduction between said power supply electrode and said internal ground node when a positive surge is applied to said power supply electrode.

8. A semiconductor device according to claim 6, a load connected to the output electrode of the semiconductor device; An electronic device comprising:

9. The electronic device according to claim 8 , wherein the load is an inductive load.

10. A vehicle comprising the electronic device according to claim 8.

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