Semiconductor device and memory module

Abstract

To provide a semiconductor device and a memory module which can correctly maintain a phase relation between a data signal, and a data strobe signal which defines latch timing of the data signal.SOLUTION: A variable delay circuit VDLYs_A generates data strobe signals DQSin, DQSin_M by delaying an input data strobe signal MDQS by delay amounts ST1, ST2, respectively. A timing adjustment circuit TMCT determines a match or mismatch between a data signal DQo from a main slicer SLr and a data signal DQo_M from a slicer SLr_M for a monitor, while changing the delay amount ST2, and adjusts the delay amount ST1 on the basis of a determination result.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a memory module, and more particularly to a semiconductor device such as a data buffer mounted in a memory module. [Background technology]

[0002] Non-Patent Document 1 defines standard specifications for DDR5 data buffers for driving DQ and DQS signals in DDR5 LRDIMM applications, in particular, specifications regarding DC and AC interface parameters and tests. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “DDR5 Data Buffer Definition(DDR5DB01)-Rev1.1”, JESD82-521, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION, December 2021, p.17 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in systems such as clouds and enterprises, high-speed memory modules such as DDR5 (Double Data Rate 5) LRDIMM (Load Reduced Dual Inline Memory Module) are used. As shown in Non-Patent Document 1, such memory modules are equipped with a data buffer for driving a data signal (DQ signal) and a data strobe signal (DQS signal). The data buffer includes a data retention circuit called a slicer that latches an input DQ signal at the edge of the DQS signal. To ensure such a latch operation, the data buffer adjusts the phase of the DQS signal, for example, in the initial sequence, using a variable delay circuit.

[0005] On the other hand, in a data buffer, for example, a decision feedback equalizer (DFE) or the like may be inserted in the transmission path of the input DQ signal to improve the signal quality. For example, the delay time of a DFE or the like changes depending on environmental changes such as temperature and voltage. As a result, even if the phase of the DQS signal is adjusted by the initial sequence, the phase of the DQ signal changes depending on the environmental changes, and as a result, there is a risk that the phase relationship between the DQ signal and the DQS signal cannot be properly maintained.

[0006] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes first and second data holding circuits, a variable delay circuit, and a timing adjustment circuit. The first data holding circuit latches an input data signal in synchronization with a first data strobe signal. The second data holding circuit latches an input data signal in synchronization with a second data strobe signal. The variable delay circuit generates a first data strobe signal and a second data strobe signal by delaying the input data strobe signal by a first delay amount and a second delay amount, respectively. The timing adjustment circuit determines whether a first data signal from the first data holding circuit and a second data signal from the second data holding circuit match / mismatch while changing the second delay amount, and adjusts the first delay amount based on the determination result. Effect of the Invention

[0008] According to one embodiment, it is possible to properly maintain the phase relationship between a data signal and a data strobe signal that determines the latch timing of the data signal. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram showing a configuration example of a memory module according to a first embodiment. [Diagram 2] FIG. 2 is a circuit block diagram showing an example of a schematic configuration of a main part of the data buffer appearing in FIG. [Diagram 3] FIG. 3 is a circuit block diagram showing a schematic configuration example of a read latch circuit and related components according to the first embodiment in the data buffer shown in FIG. [Figure 4] FIG. 4 is a circuit block diagram showing an example of the configuration of the variable delay circuit in FIG. [Diagram 5] FIG. 5 is a circuit block diagram showing an example of the configuration related to the adder-subtractor in FIG. [Figure 6] FIG. 6 is a timing chart showing a schematic example of the operation related to the read latch circuit shown in FIG. [Figure 7A] FIG. 7A is a flowchart showing an example of the process contents of the buffer control circuit shown in FIG. [Figure 7B] FIG. 7B is a supplementary diagram for explaining the flowchart shown in FIG. 7A. [Figure 7C] FIG. 7C is a supplementary diagram for explaining the flowchart shown in FIG. 7A. [Figure 8] FIG. 8 is a circuit block diagram showing a schematic configuration example related to a read latch circuit in the data buffer shown in FIG. 2 in a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a circuit block diagram showing an example of the configuration of the variable delay circuit in FIG. [Figure 10A] FIG. 10A is a circuit block diagram showing a schematic configuration example of a read latch circuit and related components as a first comparative example in the data buffer shown in FIG. [Figure 10B] FIG. 10B is a timing chart showing an example of the operation related to the read latch circuit shown in FIG. 10A. [Figure 11A]FIG. 11A is a circuit block diagram showing a schematic configuration example of a read latch circuit and related components as a second comparative example in the data buffer shown in FIG. [Figure 11B] FIG. 11B is a timing chart showing an example of the operation related to the read latch circuit shown in FIG. 11A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited in principle to a specific number.

[0011] Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be obviously not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] Furthermore, although not particularly limited, the circuit elements constituting each functional block of the embodiment are formed on a semiconductor substrate such as single crystal silicon by known integrated circuit technology such as CMOS (complementary metal oxide semiconductor).

[0013] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0014] (First embodiment) <Outline of memory module operation> Fig. 1 is a schematic diagram showing a configuration example of a memory module according to a first embodiment. The memory module MDL shown in Fig. 1 is, for example, an LRDIMM. The memory module MDL includes a module wiring board MB, a plurality of memory chips MEM mounted on the module wiring board MB, a plurality of data buffers DB, and a registered clock driver RCD.

[0015] The module wiring board MB also includes a plurality of external terminals. The plurality of external terminals include a control external terminal PNc and data external terminals PNdA and PNdB. The control external terminal PNc is an input terminal for memory control signals such as a clock signal CLK, a command signal CMD, and an address signal ADD. The data external terminals PNdA and PNdB are input / output terminals for a data signal DQ and a data strobe signal DQS.

[0016] The registered clock driver RCD is, for example, composed of one semiconductor chip. The registered clock driver RCD redrives the memory control signal inputted at the control external terminal PNc and outputs it to the multiple memory chips MDL via the CA bus BS_CA. The registered clock driver RCD also generates a buffer control signal for the data buffer DB based on the inputted memory control signal and outputs it to the multiple data buffers DB via the BCOM bus BS_BCOM.

[0017] Each of the multiple data buffers DB is, for example, configured with one semiconductor chip. The multiple data buffers DB identify a write period and a read period for the memory chip MEM based on a buffer control signal from the registered clock driver RCD. In the write period, the multiple data buffers DB re-drive the data signals DQ and data strobe signals DQS inputted at the external terminals PNdA and PNdB for data, and output them to the multiple memory chips MEM. In the read period, the multiple data buffers DB re-drive the data signals DQ and data strobe signals DQS from the multiple memory chips MEM, and output them to the external terminals PNdA and PNdB for data.

[0018] Each of the multiple memory chips MEM is, for example, a DDR-SDRAM chip, and more specifically, a DDR5-SDRAM chip or the like. Each memory chip MEM performs a write operation or a read operation in response to a memory control signal from the CA bus BS_CA. In a write operation, each memory chip MEM receives a data signal DQ from the data buffer DB using a data strobe signal DQS and writes the data to a selected memory cell. In a read operation, each memory chip MEM outputs a data signal DQ read from a selected memory cell to the data buffer DB together with the data strobe signal DQS.

[0019] A host provided outside the memory module MDL inputs and outputs the "2×m"-bit data signal DQ input and output by the data buffer DB at m-bit data terminals included in the external terminals PNdA and PNdB for data. At this time, the host inputs and outputs the m-bit data signal DQ at a half clock period "(1 / 2)Tck" based on the double clock frequency "2×fck", and inputs and outputs the m-bit data signal DQ at the following half clock period. The registered clock driver RCD and the multiple data buffers DB absorb the speed difference between the memory interface MEM_IF and the host interface HST_IF by buffering.

[0020] FIG. 2 is a circuit block diagram showing a schematic configuration example of the main part of the data buffer DB in FIG. 1. Here, for the sake of simplicity, a configuration example focusing on a 1-bit data signal DQ is shown. The data buffer DB shown in FIG. 2 includes drivers TXh_St, TXh_Sc, TXh_D, receivers RXh_S, RXh_D, and a slicer SLw provided on the host interface HST_IF side. The data buffer DB also includes drivers TXm_St, TXm_Sc, TXm_D, and a read latch circuit RLT provided on the memory interface MEM_IF side. Furthermore, the data buffer DB includes a buffer control circuit CTRL, a read buffer BUFR, and a write buffer BUFW.

[0021] The drivers TXh_St and TXh_Sc output complementary data strobe signals DQSt and DQSc to the host interface HST_IF. The receiver RXh_S differentially inputs the complementary data strobe signals DQSt and DQSc from the host interface HST_IF and outputs a clock signal for latching to the slicer SLw. The driver TXh_D outputs data from the read buffer BUFR to the host interface HST_IF as a data signal DQ[n].

[0022] The receiver RXh_D differentially inputs the data signal DQ[n] from the host interface HST_IF side and a reference voltage Vref generated in advance, and outputs the data signal DQ[n] to the slicer SLw. The slicer SLw is composed of a flip-flop and the like. The slicer SLw latches the data signal DQ[n] from the receiver RXh_D in synchronization with the clock signal from the receiver RXh_S.

[0023] On the other hand, the drivers TXm_St, TXm_Sc output complementary data strobe signals MDQSt, MDQSc to the memory interface MEM_IF side. The read latch circuit RLT has receivers RXm_S, RXm_D, a variable delay circuit VDLYs, and a slicer SLr. The receiver RXm_S differentially inputs the complementary data strobe signals MDQSt, MDQSc from the memory interface MEM_IF side, and outputs a clock signal for latching to the variable delay circuit VDLYs. The variable delay circuit VDLYs delays the input clock signal and outputs it to the slicer SLr.

[0024] The receiver RXm_D differentially inputs the data signal MDQ[n] from the memory interface MEM_IF side and a reference voltage Vref generated in advance, and outputs the data signal MDQ[n] to the slicer SLr. The slicer SLr is a data holding circuit composed of flip-flops and the like. The slicer SLr latches the data signal MDQ[n] from the receiver RXm_D in synchronization with the clock signal from the variable delay circuit VDLYs.

[0025] Each of the read buffer BUFR and the write buffer BUFW is composed of, for example, a FIFO (First In First Out) buffer. The read buffer BUFR stores a data signal MDQ[n] from the slicer SLr on the memory interface MEM_IF side. The read buffer BUFR then outputs the stored data signal MDQ[n] to the host interface HST_IF side via the driver TXh_D as a data signal DQ[n].

[0026] On the other hand, the write buffer BUFW stores the data signal DQ[n] from the slicer SLw on the host interface HST_IF side. Then, the write buffer BUFW outputs the stored data signal DQ[n] to the memory interface MEM_IF side via the driver TXm_D as a data signal MDQ[n].

[0027] The buffer control circuit CTRL inputs a buffer control signal from the BCOM bus BS_BCOM, and outputs an internal control signal CT for controlling each part in the data buffer DB based on the buffer control signal. The buffer control signal includes, for example, a clock signal BCK, a command signal BCOM, a chip select signal BCS, and a reset signal BRST. The internal control signal CT includes, for example, an enable signal to the driver and receiver, an input clock to the read buffer BUFR and the write buffer BUFW, an output clock, and a delay setting value for the variable delay circuit VDLYs.

[0028] The buffer control circuit CTRL also has a phase locked loop (PLL). The phase locked loop (PLL) generates a new clock signal CK that is synchronized with the input clock signal BCK. Using the generated clock signal CK, the buffer control circuit CTRL generates complementary data strobe signals MDQSt and MDQSc to the memory interface MEM_IF side and complementary data strobe signals DQSt and DQSc to the host interface HST_IF side.

[0029] <Configuration and operation related to the read latch circuit (comparison example)> Fig. 10A is a circuit block diagram showing a schematic configuration example of the read latch circuit RLTc and related components as a first comparative example in the data buffer DB shown in Fig. 2. Fig. 10B is a timing chart showing an operation example of the read latch circuit RLTc and related components shown in Fig. 10A. The read latch circuit RLTc shown in Fig. 10A includes receivers RXm_D and RXm_S, a variable delay circuit VDLYs_C, and a slicer SLr similar to those in Fig. 2.

[0030] Moreover, the buffer control circuit CTRLc shown in FIG. 10A has, for example, a delay locked loop (DLL). The delay locked loop (DLL) includes a variable delay circuit VDLYc, a phase comparator PHD, and a decoder QDEC. The phase comparator PHD searches for the delay amount of the variable delay circuit VDLYc so that the phase of the clock signal CK from the phase locked loop (PLL) matches that of the clock signal obtained by delaying the clock signal CK by the variable delay circuit VDLYc. As a result, the delay amount is determined to be the time "Tck" of one cycle of the clock signal CK.

[0031] The decoder QDEC sets a value "(1 / 4)Tck" which is 1 / 4 of the delay amount "Tck" in the variable delay circuit VDLYs_C in the read latch circuit RLTc. As a result, the data strobe signal MDQS from the receiver RXm_S is input to the slicer SLr as the data strobe signal DQSin after a delay time of "(1 / 4)Tck". The slicer SLr latches the data signal DQin from the receiver RXm_D in synchronization with the data strobe signal DQSin.

[0032] 10B, the phase of the data signal MDQ[n] output from the memory chip MEM coincides with the phase of the data strobe signal MDQS. Also, the delay time td_dq in the transmission path of the data signal MDQ[n] and the delay time td_dqs in the transmission path of the data strobe signal MDQS are adjusted in advance to be equal.

[0033] The delay time td_dq is the delay time from the output terminal of the memory chip MEM to the data input node of the slicer SLr, and includes the delay time due to the receiver RXm_D and the delay time due to the wiring of the transmission path. Similarly, the delay time td_dqs is the delay time from the output terminal of the memory chip MEM to the clock input node of the slicer SLr, and includes the delay time due to the receiver RXm_S and the delay time due to the wiring of the transmission path.

[0034] Therefore, by adding the delay time of "(1 / 4)Tck" from the decoder QDEC to the delay time td_dqs by the variable delay circuit VDLYs_C, the edge timing of the data strobe signal DQSin can be set to the center of the eye width W of the data signal DQin at the input node of the slicer SLr. Figure 10B shows the states of the data strobe signal DQSin and the data signal DQin in the typical case (typ) and the worst case (WC).

[0035] The worst case (WC) is the case where the delay time changes the most depending on the change in the environment, such as temperature and voltage. Since the receivers RXm_D and RXm_S are usually configured with similar circuits, the delay time of each receiver RXm_D and RXm_S is the same even when the environment changes. Therefore, even in the worst case (WC), the edge timing of the data strobe signal DQSin can be set to the center of the eye width W of the data signal DQin.

[0036] FIG. 11A is a circuit block diagram showing a schematic configuration example of the read latch circuit RLTd and related components as a second comparative example in the data buffer DB shown in FIG. 2. FIG. 11B is a timing chart showing an operation example of the read latch circuit RLTd and related components shown in FIG. 11A. The read latch circuit RLTd shown in FIG. 11A has an adder-subtractor DFE_SUM, which is a component of a decision feedback equalizer (DFE), added to the configuration example shown in FIG. 10A. The adder-subtractor DFE_SUM is inserted in the wiring between the receiver RXm_D and the slicer SLr. The buffer control circuit CTRLc is the same as in FIG. 10A.

[0037] For example, as shown in Fig. 1, when a two-rank configuration is used to widen the memory bandwidth, power consumption increases compared to a one-rank configuration. In order to suppress the increase in power consumption, the impedance of the transmission path between the memory chip MEM and the data buffer DB can be increased. Specifically, for example, the resistance value of the termination resistor in the transmission path can be increased to reduce the signal amplitude in the transmission path.

[0038] In this case, however, the signal quality in the transmission path may be degraded. Therefore, in the example shown in Fig. 11A, a decision feedback equalizer (DFE) is provided to compensate for the degradation of the signal quality. The decision feedback equalizer (DFE) is provided not only for the purpose of compensating for the side effects of such low power consumption, but also for the purpose of simply compensating for the degradation of the signal quality that accompanies the increase in the data transfer rate.

[0039] However, when a decision feedback equalizer (DFE) is provided, as shown in Fig. 11B, unlike the case of Fig. 10B, the phase relationship between the data signal DQin and the data strobe signal DQSin may not be maintained correctly. To explain in detail, first, the delay time td_dq in the transmission path of the data signal MDQ[n] and the delay time td_dqs in the transmission path of the data strobe signal MDQS are set to the same value, for example, by properly setting the initial value of the variable delay circuit VDLYs_C during the training period in the initial sequence. This state corresponds to the typical case (typ).

[0040] On the other hand, the adder-subtractor DFE_SUM is composed of an analog circuit. Therefore, the delay time by the adder-subtractor DFE_SUM may change by the time "dt" depending on the change in the environment such as temperature and voltage. Accordingly, the time "dt" is added or subtracted only from the delay time td_dq. As a result, as shown in the worst case (WC), the phase relationship between the data signal DQin and the data strobe signal DQSin changes, and the slicer SLr may not be able to properly latch the data signal DQin with the data strobe signal DQSin.

[0041] In such a case, it is possible to return to a typical case (typ) state by resetting the initial value of the variable delay circuit VDLYs_C by retraining, for example. Specifically, for example, training may be performed periodically, taking into account changes in the environment. However, if training is performed periodically, the system operating time will be shortened by the period of that training. Therefore, it is beneficial to use the method of the embodiment described below.

[0042] <Configuration related to the read latch circuit (embodiment)> Fig. 3 is a circuit block diagram showing a schematic configuration example of the read latch circuit RLTa related to the first embodiment in the data buffer DB shown in Fig. 2. Fig. 4 is a circuit block diagram showing a configuration example of the variable delay circuit VDLYs_A in Fig. 3. Fig. 5 is a circuit block diagram showing a configuration example of the adder-subtractor DFE_SUM related to Fig. 3.

[0043] The read latch circuit RLTa shown in Fig. 3 includes receivers RXm_D and RXm_S, a main slicer (first data holding circuit) SLr, and an adder / subtractor DFE_SUM, similar to the case of Fig. 11A. In addition, the read latch circuit RLTa includes a monitor slicer (second data holding circuit) SLr_M, and a variable delay circuit VDLYs_A different from the case of Fig. 11A.

[0044] 11A, the receivers RXm_D and RXm_S respectively receive the data signal MDQ[n] and the data strobe signal MDQS from the memory chip MEM. In detail, each of the receivers RXm_D and RXm_S is configured with a differential amplifier as shown in FIG. 2, and more specifically, is configured with a differential variable gain amplifier (VGA).

[0045] The main slicer (first data holding circuit) SLr latches the input data signal DQin transmitted from the memory chip MEM via the receiver RXm_D and the adder-subtractor DFE_SUM in synchronization with the main data strobe signal (first data strobe signal) DQSin. On the other hand, the monitor slicer (second data holding circuit) SLr_M latches the input data signal DQin in synchronization with the monitor data strobe signal (second data strobe signal) DQSin_M.

[0046] The variable delay circuit VDLYs_A delays the input data strobe signal MDQS transmitted from the memory chip MEM via the receiver RXm_S by a main delay amount (first delay amount) ST1 and a monitor delay amount (second delay amount) ST2, respectively. As a result, the variable delay circuit VDLYs_A generates a main data strobe signal DQSin reflecting the main delay amount ST1 and a monitor data strobe signal DQSin_M reflecting the monitor delay amount ST2.

[0047] 4, the variable delay circuit VDLYs_A includes, for example, a plurality of cascaded delay elements DE[0]-DE[k] and selection circuits SEL1 and SEL2. Each of the plurality of delay elements DE[0]-DE[k] is formed of, for example, a two-stage CMOS inverter circuit that realizes a delay of a unit delay time “dTof”.

[0048] The selection circuit SEL1 selects one of the multiple outputs from the multiple delay elements DE[0]-DE[k] based on the main delay amount ST1, and outputs it as the main data strobe signal DQSin. Similarly, the selection circuit SEL2 selects one of the multiple outputs from the multiple delay elements DE[0]-DE[k] based on the monitor delay amount ST2, and outputs it as the monitor data strobe signal DQSin_M.

[0049] Returning to Fig. 3, the buffer control circuit CTRLa includes a timing adjustment circuit TMCT in addition to a delay synchronization circuit (DLL) similar to that in Fig. 11A. The timing adjustment circuit TMCT includes an exclusive OR circuit EOR and a search circuit SC. The exclusive OR circuit EOR is a data judgment circuit that judges whether a data signal (first data signal) DQo from the main slicer SLr matches or does not match a data signal (second data signal) DQo_M from the monitor slicer SLr_M. The exclusive OR circuit EOR outputs a monitor judgment result MPF that indicates match or mismatch, in other words, pass or fail.

[0050] In summary, the search circuit SC monitors the monitor determination result MPF while changing the monitor delay amount ST2, and adjusts the main delay amount ST1 based on the monitor determination result MPF. Note that, as a prerequisite for starting such adjustment, the initial value of the main delay amount ST1 before adjustment must be appropriate to a certain extent. In other words, the initial value of the main delay amount ST1 must be at least a value that allows the main slicer SLr to correctly latch the input data signal DQin. Therefore, the search circuit SC determines the initial value of this main delay amount ST1 by reflecting "(1 / 4)Tck" from the delay locked loop circuit (DLL).

[0051] The adder-subtracter DFE_SUM is a component of a decision feedback equalizer (DFE) and is inserted into the transmission path of the input data signal DQin. The decision feedback equalizer (DFE) performs waveform equalization of the input data signal DQin. In detail, as shown in FIG. 5, the decision feedback equalizer (DFE) is composed of, for example, a plurality of delay circuits DLY2, DLY3, ... and a plurality of weighting circuits W1, W2, W3, ... in addition to the adder-subtracter DFE_SUM and the main slicer SLr.

[0052] Each of the multiple delay circuits DLY2, DLY3, ... is composed of, for example, a flip-flop similar to the slicer SLr, and realizes a delay of a clock cycle. The weighting circuit W1 weights, i.e., multiplies, the output of the slicer SLr. Similarly, the weighting circuits W2, W3, ... weight the outputs of the delay circuits DLY2, DLY3, ... respectively. The adder-subtracter DFE_SUM adds or subtracts the outputs from the multiple weighting circuits W1, W2, W3, ... to the input data signal MDQ[n].

[0053] <Outline of operation related to the read latch circuit (embodiment)> Fig. 6 is a timing chart showing a schematic operation example related to the read latch circuit RLTa shown in Fig. 3. The timing adjustment circuit TMCT sequentially changes the monitor delay amount ST2 while fixing the main delay amount ST1. As a result, the edge timing of the monitor data strobe signal DQSin_M is scanned on the setup side and the hold side with the edge timing of the main data strobe signal DQSin as a reference, as shown in Fig. 6.

[0054] The timing adjustment circuit TMCT monitors the monitor determination result MPF from the exclusive OR circuit EOR while successively changing the monitor delay amount ST2 in this manner, thereby detecting the eye width W of the input data signal DQin based on the edge timing at the point of time when the result changes from pass (match) to fail (mismatch). The timing adjustment circuit TMCT adjusts the main delay amount ST1 so that the edge timing of the main data strobe signal DQSin is located in the center of the eye width W.

[0055] By using this method, the phase relationship between the data signal (input data signal DQin) and the data strobe signal (main data strobe signal DQSin) that determines the latch timing of the data signal can be properly maintained. In other words, the edge timing of the data strobe signal can be fixed to the center of the eye width W of the data signal.

[0056] Moreover, by providing a monitor slicer SLr_M and scanning the monitor data strobe signal DQSin_M, it is possible to detect the eye width W of the input data signal DQin without affecting the normal read operation in the memory chip MEM. That is, while transmitting the data signal DQo from the main slicer SLr to the subsequent stage as a read data signal from the memory chip MEM, to the external terminals PNdA and PNdB for data in FIG. 1, the eye width W of the input data signal DQin can be detected in the background.

[0057] This allows the strobe timing to be optimized while tracking the changes in real time, even if the temperature, voltage, or other environmental factors change during a normal read operation, or even if the delay time of the transmission path changes due to a decision feedback equalizer (DFE) or the like. As a result, a system that is robust against environmental changes can be realized. In addition, there is no need to interrupt a normal read operation to retrain the strobe timing, for example. As a result, the system's uptime can be secured.

[0058] Furthermore, since the change in delay time of the transmission path according to the change in the environment can be compensated for, a circuit having temperature dependency such as a decision feedback equalizer (DFE) can be easily installed in the transmission path. By installing a decision feedback equalizer (DFE), it is possible to realize an increase in data transfer speed, or a reduction in power consumption as described in FIG. 11A, or both. Note that, although an example of inserting a decision feedback equalizer (DFE) in the transmission path of the data signal has been described here, the circuit to be inserted is not limited to this, and may be another circuit having temperature dependency.

[0059] <Details of the buffer control circuit (timing adjustment circuit)> FIG. 7A is a flowchart showing an example of the processing contents of the buffer control circuit CTRLa shown in FIG. 3. FIG. 7B and FIG. 7C are supplementary diagrams for explaining the flowchart shown in FIG. 7A. FIG. 7A shows the processing contents in the initial sequence period (step S10) and the processing contents in the normal operation period (step S20) executed thereafter. These processings are mainly executed by the timing adjustment circuit TMCT. The timing adjustment circuit TMCT is composed of a sequencer and the like that executes the processing shown in FIG. 7A.

[0060] In the initial sequence period (step S10), first, the delay synchronization circuit (DLL) is put into a locked state (step S101). That is, as described in FIG. 10A and FIG. 10B, the phase comparison result by the phase comparator PHD converges, and as a result, the decoder QDEC outputs a delay amount of "(1 / 4)Tck". Next, the buffer control circuit CTRLa executes read training using a commonly known training circuit during the training period of the memory chip MEM (step S102).

[0061] By the read training, for example, in FIG. 11A and FIG. 11B, the delay amount of the variable delay circuit that satisfies "td_dq=td_dqs" is searched. The timing adjustment circuit TMCT in FIG. 3 determines the initial value of the main delay amount ST1 by adding the delay amount of "(1 / 4)Tck" from the decoder QDEC to the delay amount obtained by the read training. This creates a state such as that shown in the typical case (typ) in FIG. 11B.

[0062] In the subsequent normal operation period (step S20), the timing adjustment circuit TMCT starts operation from a state in which the main delay amount ST1 is set to the initial value obtained in the initial sequence period (step S10). In step S20, the following process is executed in summary.

[0063] First, as shown in Fig. 7B, the timing adjustment circuit TMCT generates edge timings th and ts of the monitor data strobe signal DQSin_M, more specifically, a monitor delay amount ST2 for obtaining the edge timings th and ts, based on the edge timing tm of the main data strobe signal DQSin. The edge timings th and ts are timings obtained by shifting the edge timing tm by N times the unit delay time "dTof", "N x dTof", on the hold side and the setup side, respectively. In the initial state, "N" is set to an initial value "N_init" (step S201).

[0064] The timing adjustment circuit TMCT judges pass / fail based on the monitor judgment result MPF while setting the edge timing of the monitor data strobe signal DQSin_M to one of the edge timings th and ts, and then judges pass / fail based on the monitor judgment result MPF while setting it to the other.Then, the timing adjustment circuit TMCT sequentially increases the integer "N" to sequentially increase the shift width of the edge timings th and ts based on the edge timing tm as long as the monitor judgment result MPF is pass (steps S202-S206).

[0065] Here, the monitor determination result MPF in steps S203 and S205 is obtained by utilizing a normal read operation for the memory chip MEM. That is, as shown in Fig. 7C, the normal operation period of the memory module MDL, and therefore the memory chip MEM, includes a write cycle and read cycles Trd1 and Trd2 as appropriate. The buffer control circuit CTRLa, and therefore the timing adjustment circuit TMCT, can identify the data read period in the read cycles Trd1 and Trd2 based on the buffer control signal from the BCOM bus BS_BCOM, as described in Fig. 2.

[0066] Thereby, the timing adjustment circuit TMCT acquires the monitor determination result MPF at the hold side edge timing th in step S203 during the data read period in the read cycle Trd1, for example. After that, the timing adjustment circuit TMCT acquires the monitor determination result MPF at the setup side edge timing ts in step S205 during the data read period in the read cycle Trd2.

[0067] On the other hand, if the shift width of the edge timings th and ts is gradually increased, at a certain point in time, a fail occurs in at least one of the edge timings th and ts. First, assume the case (A) where a fail occurs in the edge timing th on the hold side and also a fail occurs in the edge timing ts on the setup side (steps S202, S203, S207, S208, S211). This state indicates that the main edge timing tm is located in the center of the eye width W of the input data signal DQin. Therefore, the timing adjustment circuit TMCT maintains the main edge timing tm, that is, the main delay amount ST1, as it is (step S211), and returns to the state shown in FIG. 7B corresponding to step S201.

[0068] Next, (B) assume that a fail occurs at the edge timing th on the hold side and a pass occurs at the edge timing ts on the setup side (steps S202, S203, S207, S208, S210). This state indicates that the main edge timing tm is located on the hold side from the center of the eye width W. Therefore, the timing adjustment circuit TMCT shifts the main edge timing tm by the unit delay time "dTof" in the setup direction, i.e., in the direction of decreasing the delay (step S210), and returns to step S201.

[0069] Finally, (C) assume that a pass occurs at the edge timing th on the hold side and a fail occurs at the edge timing ts on the setup side (steps S202, S203, S204, S205, S209). This state indicates that the main edge timing tm is located on the setup side rather than the center of the eye width W. Therefore, the timing adjustment circuit TMCT shifts the main edge timing tm by the unit delay time "dTof" in the hold direction, i.e., in the direction of increasing the delay (step S209), and returns to step S201.

[0070] For example, by using such a flowchart, the edge timing tm of the main data strobe signal DQSin can be fixed to the center of the eye width W of the input data signal DQin during the normal operation period (step S20). Since the main delay amount ST1 can be optimized during the normal operation period (step S20) in this way, for example, during the initial sequence period (S10), it is not necessarily necessary to determine the main delay amount ST1, more specifically, the initial value of the main delay amount ST1, with high accuracy. As a result, for example, the delay locked loop (DLL) can be simplified and the time required for locking the delay locked loop (DLL), i.e., the time required for the process in step S101, can be shortened.

[0071] <Various supplementary information> More specifically, in a DDR-SDRAM chip, multiple data signals MDQ are assigned to one data strobe signal MDQS. In this case, the timing adjustment circuit TMCT may perform the process shown in FIG. 7A on a representative data signal MDQ selected from the multiple data signals MDQ.

[0072] Alternatively, the timing adjustment circuit TMCT may perform the process shown in Fig. 7A for a plurality of data signals MDQ. In this case, a plurality of monitor decision results MPF for a plurality of data signals MDQ are simultaneously obtained on each of the hold side and the setup side. For example, when the plurality of monitor decision results MPF include one or more fails, the timing adjustment circuit TMCT may regard the whole as a fail and perform the process shown in Fig. 7A.

[0073] 7C, each of the read cycles Trd1 and Trd2 may include a plurality of data signals MDQ in time series due to burst read, etc. In this case, the timing adjustment circuit TMCT may obtain a plurality of monitor determination results MPF for the plurality of data signals MDQ, and if one or more fails are included among them, it may regard the whole as a fail and perform the process shown in FIG.

[0074] 3, the configuration of the read latch circuit RLTa and the buffer control circuit CTRLa is not necessarily limited to the memory module MDL. That is, the configuration may be applied to a memory interface circuit or the like mounted on a semiconductor chip such as an SoC constituting a host.

[0075] <Main Effects of the First Embodiment> As described above, in the method of the first embodiment, a monitor slicer SLr_M is provided, and the phase of the data strobe signal DQSin to the main slicer SLr is adjusted to an optimal value using the monitor slicer SLr_M. This typically allows the phase relationship between the data signal and the data strobe signal to be correctly maintained. In particular, even if the environment such as temperature and voltage changes during normal operation, the phase of the data strobe signal can be adjusted in real time in the background without retraining.

[0076] (Second embodiment) <Configuration and operation related to the read latch circuit (embodiment)> Fig. 8 is a circuit block diagram showing a schematic configuration example related to the read latch circuit RLTb in the data buffer DB shown in Fig. 2 in the semiconductor device according to the second embodiment. The read latch circuit RLTb shown in Fig. 8 is different from the read latch circuit RLTa shown in Fig. 3 in that it further includes another monitor slicer (third data holding circuit) SLr_M2 in addition to the monitor slicer (second data holding circuit) SLr_M. The monitor slicer SLr_M2 latches the input data signal DQin in synchronization with the monitor data strobe signal (third data strobe signal) like the monitor slicer SLr_M.

[0077] In addition, due to such a difference in configuration, the read latch circuit RLTb includes a variable delay circuit VDLYs_B that is an extension of the configuration of the variable delay circuit VDLYs_A shown in Figures 3 and 4. That is, the variable delay circuit VDLYs_B generates a monitor data strobe signal DQSin_M by delaying the input data strobe signal MDQS by a monitor delay amount ST2 that is smaller than the main delay amount ST1. Furthermore, the variable delay circuit VDLYs_B generates a monitor data strobe signal DQSin_M2 by delaying the input data strobe signal MDQS by a monitor delay amount ST3 that is larger than the main delay amount ST1.

[0078] Fig. 9 is a circuit block diagram showing a configuration example of the variable delay circuit VDLYs_B in Fig. 8. The variable delay circuit VDLYs_B shown in Fig. 9 further includes a selection circuit SEL3 in addition to the configuration example shown in Fig. 4. Similar to the selection circuits SEL1 and SEL2, the selection circuit SEL3 selects one output from among multiple outputs by the multiple delay elements DE[0]-DE[k] based on a monitor delay amount ST3, and outputs it as a monitor data strobe signal DQSin_M2.

[0079] Returning to Fig. 8, the buffer control circuit CTRLb includes a timing adjustment circuit TMCTb that is an extension of the configuration of the timing adjustment circuit TMCT shown in Fig. 3. The timing adjustment circuit TMCTb includes another exclusive OR circuit EOR2 in addition to the exclusive OR circuit EOR shown in Fig. 3. The exclusive OR circuit EOR2 judges whether a data signal (first data signal) DQo from the main slicer SLr matches or does not match a data signal (third data signal) DQo_M2 from the monitor slicer SLr_M2. The exclusive OR circuit EOR2 then outputs a monitor judgment result MPF2 that indicates match or mismatch, in other words, pass or fail.

[0080] On the other hand, the search circuit SC, while changing the monitor delay amount ST2, judges whether the data signal DQo from the main slicer SLr and the data signal DQo_M from the monitor slicer SLr_M match / mismatch using the exclusive OR circuit EOR, as in the case of Fig. 3. In addition, while changing the monitor delay amount ST3, the search circuit SC judges whether the data signal DQo from the main slicer SLr match / mismatch using the exclusive OR circuit EOR2. Then, the search circuit SC adjusts the main delay amount ST1 based on these monitor judgment results MPF, MPF2.

[0081] By using such a configuration, the real-time performance when optimizing the main delay amount ST1 according to changes in the environment such as temperature and voltage can be further improved. That is, in the examples shown in Fig. 7A, Fig. 7B, and Fig. 7C described above, after the monitor determination result MPF at the edge timing th on the hold side is obtained in a certain read cycle, the monitor determination result MPF at the edge timing ts on the setup side is obtained in the next read cycle. By using the configuration example shown in Fig. 8, the monitor determination result MPF2 at the edge timing th on the hold side and the monitor determination result MPF at the edge timing ts on the setup side can be obtained simultaneously in one read cycle.

[0082] <Main Effects of the Second Embodiment> As described above, the method of the second embodiment can provide the same effects as those described in the first embodiment. Furthermore, compared to the method of the first embodiment, the overhead of the circuit area increases slightly, but the real-time performance when optimizing the phase of the data strobe signal in response to changes in the environment can be improved. As a result, a system that is more robust against changes in the environment can be realized.

[0083] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0084] DB Data Buffer DQSin, DQSin_M, DQSin_M2 Data strobe signals DQin Data signal (input data signal) MB module wiring board MDL Memory Module MDQ,DQo,DQo_M,DQo_M2 Data signal MDQS data strobe signal (input data strobe signal) MEM Memory chip External terminal for PNc control External terminal for PNdA,PNdB data RCD Registered Clock Driver SLr, SLr_M, SLr_M2 Slicer (data retention circuit) ST1, ST2, ST3 delay amount TMCT Timing Adjustment Circuit VDLYs Variable Delay Circuit

Claims

1. a first data holding circuit that latches an input data signal in synchronization with a first data strobe signal; a second data holding circuit that latches the input data signal in synchronization with a second data strobe signal; a variable delay circuit that generates the first data strobe signal and the second data strobe signal by delaying an input data strobe signal by a first delay amount and a second delay amount, respectively; a timing adjustment circuit that sets the first delay amount and the second delay amount in the variable delay circuit; Equipped with the timing adjustment circuit determines whether a first data signal from the first data holding circuit and a second data signal from the second data holding circuit match / mismatch while changing the second delay amount, and adjusts the first delay amount based on a result of the determination. Semiconductor device.

2. 2. The semiconductor device according to claim 1, the input data signal and the input data strobe signal are signals output from a memory chip; Semiconductor device.

3. 3. The semiconductor device according to claim 2, The memory chip is a DDR-SDRAM chip. Semiconductor device.

4. 3. The semiconductor device according to claim 2, the timing adjustment circuit operates during a normal operation period during which the memory chip performs a normal read operation; The first data signal is transmitted to a subsequent stage as a read data signal from the memory chip. Semiconductor device.

5. 5. The semiconductor device according to claim 4, an initial sequence period including a training period for the memory chip is provided before the normal operation period; An initial value of the first delay amount is determined during the initial sequence period; the timing adjustment circuit starts operation in the normal operation period from a state in which the first delay amount is set to the initial value. Semiconductor device.

6. 2. The semiconductor device according to claim 1, the timing adjustment circuit detects an eye width of the input data signal by determining whether the signal matches or does not match while changing the second delay amount, and adjusts the first delay amount so that an edge of the first data strobe signal is positioned at the center of the eye width. Semiconductor device.

7. 2. The semiconductor device according to claim 1, The digital signal processing apparatus further includes a decision feedback equalizer (DFE) that is inserted in a transmission path of the input data signal and performs waveform equalization of the input data signal. Semiconductor device.

8. 2. The semiconductor device according to claim 1, a third data holding circuit for latching the input data signal in synchronization with a third data strobe signal; the variable delay circuit generates the second data strobe signal by delaying the input data strobe signal by a second delay amount smaller than the first delay amount, and generates the third data strobe signal by delaying the input data strobe signal by a third delay amount larger than the first delay amount; the timing adjustment circuit determines whether the first data signal and the second data signal match or not and whether the first data signal and the third data signal from the third data holding circuit match or not while changing the second delay amount and the third delay amount, and adjusts the first delay amount based on the determination result. Semiconductor device.

9. 2. The semiconductor device according to claim 1, The semiconductor device is a semiconductor chip that performs the function of a data buffer in a memory module. Semiconductor device.

10. a module wiring board having an external terminal for control and an external terminal for data; A plurality of DDR-SDRAM chips mounted on the module wiring board; a registered clock driver mounted on the module wiring board, which redrives a memory control signal inputted through the external control terminal and outputs the memory control signal to the plurality of DDR-SDRAM chips; a data buffer mounted on the module wiring board, which redrives data signals and data strobe signals inputted at the external terminals for data, and outputs them to the plurality of DDR-SDRAM chips, and redrives input data signals and input data strobe signals inputted from the plurality of DDR-SDRAM chips, and outputs them to the external terminals for data; having The data buffer includes: a first data holding circuit that latches the input data signal in synchronization with a first data strobe signal; a second data holding circuit that latches the input data signal in synchronization with a second data strobe signal; a variable delay circuit that generates the first data strobe signal and the second data strobe signal by delaying the input data strobe signal by a first delay amount and a second delay amount, respectively; a timing adjustment circuit that sets the first delay amount and the second delay amount in the variable delay circuit; Equipped with the timing adjustment circuit determines whether a first data signal from the first data holding circuit and a second data signal from the second data holding circuit match / mismatch while changing the second delay amount, and adjusts the first delay amount based on a result of the determination. Memory modules.

11. 11. The memory module of claim 10, the timing adjustment circuit operates during a normal operation period during which the plurality of DDR-SDRAM chips perform normal read operations; The first data signal is transmitted to the external terminal for data as a read data signal from the plurality of DDR-SDRAM chips. Memory modules.

12. 12. The memory module of claim 11, an initial sequence period including a training period for the plurality of DDR-SDRAM chips is provided before the normal operation period; An initial value of the first delay amount is determined during the initial sequence period; the timing adjustment circuit starts operation in the normal operation period from a state in which the first delay amount is set to the initial value. Memory modules.

13. 11. The memory module of claim 10, the timing adjustment circuit detects an eye width of the input data signal by determining whether the signal coincides with the input data signal while changing the second delay amount, and adjusts the first delay amount so that an edge of the first data strobe signal is positioned at the center of the eye width. Memory modules.

14. 11. The memory module of claim 10, The data buffer further includes a DFE (Decision Feedback Equalizer) that is inserted in a transmission path of the input data signal and performs waveform equalization of the input data signal. Memory modules.

15. 11. The memory module of claim 10, the data buffer further comprises a third data holding circuit that latches the input data signal in synchronization with a third data strobe signal; the variable delay circuit generates the second data strobe signal by delaying the input data strobe signal by a second delay amount smaller than the first delay amount, and generates the third data strobe signal by delaying the input data strobe signal by a third delay amount larger than the first delay amount; the timing adjustment circuit determines whether the first data signal and the second data signal match or not and whether the first data signal and the third data signal from the third data holding circuit match or not while changing the second delay amount and the third delay amount, and adjusts the first delay amount based on the determination result. Memory modules.

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