Display device

Abstract

To provide a display device in which a decrease in electrical characteristic of a transistor can be suppressed.SOLUTION: A display device includes a first pixel including a transistor including an oxide semiconductor layer, a first gate electrode, and a first source electrode, a first gate wire connected to the first gate electrode and extending in a first direction, and a first source wire connected to the first source electrode and extending in a second direction intersecting with the first direction. The first gate electrode and the first gate wire include a first conductive layer. The first source electrode includes a second conductive layer. The first source wire includes a third conductive layer connected to the first source electrode. The thickness of the second conductive layer is smaller than the thickness of the first conductive layer and smaller than the thickness of the third conductive layer.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, transparent displays that allow the background on one side to be viewed from the other side have been developed (Patent Document 1). A transparent display includes, for example, a common electrode and a plurality of pixels each including a transistor electrically connected to a pixel electrode, and can display images, characters, etc., depending on the difference in potential supplied to the common electrode and the pixel electrodes. A transparent display is a display that can achieve a wide viewing angle without using a polarizing plate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-160254 A [Patent Document 2] International Publication No. 2018 / 130920 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, if the electrical characteristics of a transistor included in a display device such as a transparent display are degraded, it may become difficult for the transistor to supply an appropriate potential to a pixel electrode, which may result in a degradation of the display quality of the display device.

[0005] An object of the present invention is to provide a display device in which deterioration of electrical characteristics of a transistor can be suppressed. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention has a first pixel including a transistor having an oxide semiconductor layer, a first gate electrode, and a first source electrode, a first gate wiring connected to the first gate electrode and extending in a first direction, and a first source wiring connected to the first source electrode and extending in a second direction intersecting the first direction, wherein the first gate electrode and the first gate wiring include a first conductive layer, the first source electrode includes a second conductive layer, and the first source wiring includes a third conductive layer connected to the first source electrode, and a thickness of the second conductive layer is thinner than a thickness of the first conductive layer and thinner than a thickness of the third conductive layer. [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective view showing a configuration of a display device according to an embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure of the display device taken along the line A1-A2 shown in FIG. [Diagram 3] 1 is a plan view showing a configuration of a display device according to an embodiment of the present invention. [Figure 4] FIG. 2 is a circuit diagram showing a circuit configuration of a pixel according to an embodiment of the present invention. [Diagram 5] 1 is a planar layout of a pixel according to an embodiment of the present invention. [Figure 6] FIG. 2 is an enlarged planar layout of a pixel according to an embodiment of the present invention. [Figure 7] 7 is a cross-sectional view showing a cross-sectional structure of a pixel taken along line B1-B2 shown in FIG. 6. [Figure 8] 7 is a cross-sectional view showing a cross-sectional structure of a pixel taken along line C1-C2 shown in FIG. 6. [Figure 9] FIG. 2 is an enlarged planar layout of a pixel according to an embodiment of the present invention. [Figure 10] FIG. 2 is an enlarged planar layout of a pixel according to an embodiment of the present invention. [Figure 11]1 is an enlarged view of a planar layout of pixels in a display device according to an embodiment of the present invention. [Figure 12] 1 is an enlarged view of a planar layout of pixels in a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different aspects, and is not to be interpreted as being limited to the description of the embodiments exemplified below. In addition, in order to make the explanation of each embodiment of the present invention clearer, the width, thickness, shape, etc. of each part shown in the drawings may be represented more typically than the actual aspect, but these schematic drawings are only examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements that are the same or similar to those shown and explained in the previous figures may be given the same reference numerals, and duplicate explanations may be omitted. In addition, in this specification and each figure, when multiple identical or similar configurations are to be distinguished from each other, they may be written as -1, -2, etc. Capital or lowercase letters of the alphabet are used. In this specification and each figure, the letters "first" and "second" attached to each element are convenient marks used to distinguish each element, and do not indicate priority or order.

[0009] In the present invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have the same layer structure and the same material. Therefore, these multiple films are defined as existing in the same layer. In addition, when a single film is processed to form multiple films, they may be distinguished and described as -1, -2, etc. in this specification.

[0010] In this specification and each figure, expressions such as "above" and "below" express the relative positional relationship between the structure of interest and other structures. In this specification and each figure, when describing the cross-sectional structure of the structure of interest, the direction from the first substrate to the pixel electrode, which will be described later, is defined as "above", and the direction from the pixel electrode to the first substrate is defined as "below". In this specification and claims, when expressing a mode in which another structure is disposed on a certain structure, the term "above" is used to include both a case in which another structure is disposed directly above the certain structure so as to be in contact with the certain structure, and a case in which another structure is disposed above the certain structure via another structure, unless otherwise specified.

[0011] In this specification, bottom gate driving is driving that uses a gate electrode arranged below a semiconductor layer to control the on / off of a transistor described later. In this specification, top gate driving is driving that uses a gate electrode arranged above a semiconductor layer to control the on / off of a transistor. In this specification, dual gate driving is driving that supplies the same control signal to gate electrodes arranged above and below a semiconductor layer to control the on / off of a transistor.

[0012] In the detailed description of the present invention, when the terms "same", "identical", "parallel" and "perpendicular" are used, the terms "same", "parallel" and "perpendicular" may include cases where an error is included within the design range.

[0013] [Background of the invention] The inventors have developed a display device such as a transparent display including a transistor made of an oxide semiconductor. The transistor made of an oxide semiconductor includes a gate electrode, a source electrode, and a drain electrode. For example, in a manufacturing process of a transistor made of an oxide semiconductor, an oxide semiconductor layer including an oxide semiconductor is damaged when a conductive layer for forming a source electrode and a drain electrode is formed. As a result, the electrical characteristics of the transistor made of an oxide semiconductor are degraded, and the display quality of the display device is degraded.

[0014] The details will be described in the following embodiment with reference to FIGS. 1 to 12, but the inventors have developed a display device 10 capable of suppressing the deterioration of the electrical characteristics of a transistor. One embodiment of the present invention is a display device 10 including a display panel 102 (see FIG. 1) using a polymer dispersed liquid crystal. The display device 10 includes a pixel PIX (first pixel) having a transistor Tr (see FIG. 4) including an oxide semiconductor layer 204 (see FIG. 7, oxide semiconductor as a semiconductor material), a gate wiring GL (see FIG. 4, first gate electrode, first gate wiring connected to the first gate electrode), a conductive layer 206-4 (see FIG. 7, first source electrode), and a source wiring SL (see FIG. 4, first source wiring), and includes a plurality of pixels PIX (see FIG. 1) arranged in a matrix in the D1 direction (see FIG. 1) and the D2 direction (see FIG. 1). The display device 10 also includes a conductive layer 202 (see FIG. 7, first conductive layer) provided on the first surface 150a (see FIG. 7) of the array substrate 150 (see FIG. 7) and including a gate wiring GL of the transistor Tr. The display device 10 also includes an oxide semiconductor layer 204 (see FIG. 7) including an oxide semiconductor and provided on the conductive layer 202, which overlaps with the conductive layer 202. The display device 10 also includes a conductive layer 206-4, a conductive layer 208-3, and a conductive layer 208-4 (see FIG. 10, second conductive layer and third conductive layer) that contact the oxide semiconductor layer 204 and include a source wiring SL of the transistor Tr provided on the oxide semiconductor layer 204 in a plan view. The thickness of the conductive layer 206 in this embodiment is thinner than the thickness of the conductive layer 208 and is thinner than the thickness of the conductive layer 202. In addition, although the thickness of the conductive layer 206 in this embodiment is as thin as the thickness of the oxide semiconductor layer 204, the thickness of the conductive layer 206 is not limited to the configuration of this embodiment. For example, the thickness of the conductive layer 206 may be thinner than the thickness of the oxide semiconductor layer 204, or may be thicker than the thickness of the oxide semiconductor layer 204. The thickness of the conductive layer 206 can be changed as appropriate depending on the specifications and applications of the display device 10.

[0015] For example, since the conductive layer 206 including the drain electrode and source wiring SL of the transistor Tr provided on the oxide semiconductor layer 204 at a distance therefrom is included, and the thickness of the conductive layer 206 is thinner than the thicknesses of the conductive layers 206 and 208, damage to the oxide semiconductor layer 204 including an oxide semiconductor is mitigated compared to the case where the source wiring SL and the drain electrode are formed (patterned) using a thick conductive layer such as the conductive layer 206 or the conductive layer 208 in the manufacturing process of the display device 10. In addition, the source wiring SL includes the conductive layer 208 that is thicker than the thicknesses of the conductive layer 206 and the oxide semiconductor layer 204, and the conductive layer 208 can be used as wiring that is routed within the display region 12.

[0016] As a result, it is possible to suppress deterioration in the electrical characteristics of the transistor Tr of the display device 10, and to suppress deterioration in the display quality of the display device 10. In addition, since the source wiring SL is formed using the conductive layer 206 and the conductive layer 208, it is possible to reduce the resistance value of the source wiring SL, and therefore it is possible to reduce signal delay.

[0017] Each embodiment described below illustrates a display device capable of suppressing degradation of transistor characteristics. A display device 10 according to one embodiment of the present invention will be described with reference to Figs. 1 to 12. As an example, the display device 10 according to one embodiment of the present invention is a transparent display, and the display panel included in the display device 10 is a display panel using polymer dispersed liquid crystal.

[0018] [Overview of display device 10] An overview of the display device 10 will be described with reference to Fig. 1 to Fig. 3. Fig. 1 is a perspective view showing the configuration of the display device 10. Fig. 2 is a cross-sectional view showing the cross-sectional structure of the display device taken along line A1-A2 shown in Fig. 1. Fig. 3 is a plan view showing the configuration of an array substrate 150 of the display device 10.

[0019] As shown in Figures 1, 2 or 3, the display device 10 includes a display panel 102 including an array substrate 150, a counter substrate 152, and a liquid crystal layer (not shown) between the array substrate 150 and the counter substrate 152, a gate driving circuit 28, and a source driving circuit 38, a light source 104, and a first transparent substrate 151A and a second transparent substrate 151B sandwiching the display panel 102.

[0020] In the display device 10, one direction of the plane of the display panel 102 is the D1 direction, the direction perpendicular to the D1 direction is the D2 direction, and the direction perpendicular to the D1-D2 plane is the D3 direction. The array substrate 150 of the display device 10 may be called the first substrate, and the counter substrate 152 of the display device 10 may be called the second substrate.

[0021] The display panel 102 has a display area 12 and a peripheral area 14 outside the display area 12. The display area 12 and the peripheral area 14 overlap the array substrate 150 and the counter substrate 152. The display area 12 includes a plurality of pixels PIX. The plurality of pixels PIX are arranged in a matrix in the row direction and the column direction. Each of the plurality of pixels PIX has a plurality of transistors and a liquid crystal element. For example, the row direction is assumed to be parallel to the D1 direction, and the column direction is assumed to be parallel to the D2 direction. In the display area 12, m (m is a positive integer) pixels are arranged in the row direction, and n (n is a positive integer) pixels are arranged in the column direction. The numerical values ​​m and n are appropriately set according to the display resolution in the vertical direction and the display resolution in the horizontal direction. In the display area 12, gate wiring is arranged in the D1 direction, and source wiring is arranged in the D2 direction. The gate wiring may be called a scanning signal line, and the source wiring may be called a data signal line.

[0022] The peripheral region 14 is provided to surround the display region 12. The peripheral region 14 refers to the region on the array substrate 150 from the display region 12 to the edge of the array substrate 150. In other words, the peripheral region 14 refers to the region on the array substrate 150 other than where the display region 12 is provided (i.e., the region outside the display region 12).

[0023] A gate driving circuit 28 and a source driving circuit 38 are provided in the peripheral region 14 overlapping with the array substrate 150. For example, the gate driving circuit 28 and the source driving circuit 38 are provided as an integrated circuit (IC) and mounted on the array substrate 150 by a COG (Chip on Glass) method. Also, for example, the gate driving circuit 28 and the source driving circuit 38 may be mounted by a COF (Chip on Film) method, or may be formed by a thin film transistor (TFT) formed on the array substrate 150.

[0024] 3, the gate wiring region 32, the source wiring region 42, the common wirings 16, 18, the terminal portions 26, 36, the flexible printed circuits 24, 34, and various inspection circuits are provided in the peripheral region 14. The terminal portions 26, 36 are arranged along one side of the array substrate 150.

[0025] The gate wiring region 32 is a region where a pattern formed by wiring that connects the gate driving circuit 28 and the gate wiring GL arranged in the display region 12 is provided. The common wiring region 22 is a region where a pattern formed by common wiring is provided. In terms of circuitry, the common wiring region 22 is used as wiring that applies a common voltage to a common electrode 218 (see FIG. 7) arranged on the counter substrate 152. The source wiring region 42 is a region where a pattern formed by wiring that connects the source driving circuit 38 and the source wiring SL arranged in the display region 12 is provided. For example, the common voltage may be a voltage between a voltage of a positive voltage amplitude and a voltage of a negative voltage amplitude among the voltages supplied to the source wiring SL, may be a voltage that is a reference for the voltage amplitude, may be 0V, may be a ground voltage, or may be a ground voltage.

[0026] The flexible printed circuit 24 is connected to the terminal section 26. The flexible printed circuit 24 supplies various signals to the gate drive circuit 28, the common wirings 16 and 18, the ESD protection circuit 59, and the QD pad 56. The gate drive circuit 28 is connected to a plurality of gate lines GL, and each of the plurality of gate lines GL (see FIG. 4) is electrically connected to each of the plurality of pixels PIX in the display area 12. In FIG. 3, the area in which the plurality of gate lines GL are provided is represented as a gate line area 32, and the detailed arrangement of the plurality of gate lines GL is omitted. The number of gate lines GL connected to the two gate drive circuits 28 corresponds to the number of rows of the pixels PIX in the display area 12. Note that the configuration of the gate line area 32 shown in FIG. 3 shows a configuration in which the gate line area 32 is provided at a distance from the display area 12, but in reality, the gate lines GL are electrically connected to the pixels PIX.

[0027] The flexible printed circuit 34 supplies a data signal to the source driving circuit 38. The source driving circuit 38 is connected to a plurality of source lines SL (see FIG. 4), and each of the plurality of source lines SL is electrically connected to each of the plurality of pixels PIX in the display area 12. In FIG. 3, the region in which the plurality of source lines SL are provided is represented as a source line region 42, and the detailed arrangement of the plurality of source lines SL is omitted. The number of source lines SL connected to the eight source driving circuits 38 corresponds to at least three times the number of columns of the pixels PIX in the display area 12. A case in which the number of source lines SL of the display device 10 is four times the number of columns of the pixels PIX in the display area 12 will be described. Note that the configuration of the source line region 42 shown in FIG. 3 shows a configuration in which the source line region 42 is provided at a distance from the display area 12, but in reality, the source lines SL and the pixels PIX are electrically connected.

[0028] The common wiring 18, the ESD protection circuit 46, the gate inspection circuit 48, and the inspection line 54 are provided between the gate wiring region 32 and the display region 12. The common wiring 18, the ESD protection circuit 46, the source inspection circuit 52, and the inspection line 54 are provided between the source wiring region 42 and the display region 12. The inspection line 54 is connected to the ESD protection circuit 58 and the QD pad 56. The common wiring 18 is connected to an ESD protection circuit 59.

[0029] The common wiring 16 is provided so as to surround the peripheral region 14 of the array substrate 150, and is supplied with signals from two flexible printed circuits 24. The common wiring 16 is also electrically connected to a mesh-shaped common wiring region 22.

[0030] 1 or 2, the array substrate 150 is larger than the counter substrate 152, and a part of the peripheral region 14 overlapping with the array substrate 150 is exposed from the counter substrate 152. A flexible printed circuit 34 is attached to the peripheral edge of the array substrate 150. The counter substrate 152 is disposed in the direction D3 so as to face the array substrate 150. The array substrate 150 and the counter substrate 152 are bonded together by a sealant 154 in a state in which they are disposed facing each other with a gap therebetween. The array substrate 150 and the counter substrate 152 are translucent. The array substrate 150 and the counter substrate 152 are preferably transparent to visible light.

[0031] As shown in FIG. 1 or FIG. 2, the light source 104 has a structure along the D1 direction. For example, the light source 104 includes light emitting diodes (LEDs) arranged along the D1 direction. The structure of the light source 104 is not limited to light emitting diodes, and may include optical members such as a reflector, a diffuser, and a lens in addition to the light emitting diodes arranged in the D1 direction. The light source 104 and the light emission control circuit 110 that controls the light source 104 may be provided as separate members independent of the display panel 102. The light source 104 may be controlled in terms of the timing of light emission by the light emission control circuit 110 that is synchronized with the gate drive circuit 28 and the source drive circuit 38. The light emission control circuit 110 that controls the light source 104 may be provided as a separate member like the light source 104, separate from the display panel 102, or may be mounted on the array substrate 150 as an individual component, or may be incorporated into the gate drive circuit 28 or the source drive circuit 38.

[0032] The light source 104 is disposed adjacent to one side surface of the first transparent substrate 151A or the second transparent substrate 151B. For example, as shown in FIG. 1 or FIG. 2, the light source 104 is disposed along one side surface (first side surface 15C) of the second transparent substrate 151B. Also, FIG. 2 shows a configuration in which the light source 104 is attached to the array substrate 150, but the method or structure for attaching the light source 104 to the array substrate 150 is not limited to the configuration shown in FIG. 2. As long as the light source 104 can be fixed to the second transparent substrate 151B, there is no limitation on the method or structure for attaching the light source 104 to the array substrate 150. For example, the light source 104 may be supported by a housing surrounding the display panel 102 and attached to the array substrate 150. Note that the light source 104 may be called a side light source because it irradiates light L to the first side surface 15C of the second transparent substrate 151B. In this case, the first side surface 15C of the second transparent substrate 151B facing the light source 104 serves as a light incident surface.

[0033] 1 and 2, the first transparent substrate 151A and the second transparent substrate 151B are provided to sandwich the display region 12 and the peripheral region 14. The first transparent substrate 151A and the second transparent substrate 151B function as protective members for the display panel 102. In addition, the first transparent substrate 151A and the second transparent substrate 151B function as light guide plates that introduce light emitted from the light source 104 to the display panel 102.

[0034] 2, the first transparent substrate 151A is provided on the array substrate 150 side, and the second transparent substrate 151B is provided on the counter substrate 152 side. The first transparent substrate 151A and the second transparent substrate 151B preferably have the same refractive index as the array substrate 150 and the counter substrate 152. For example, the array substrate 150 and the first transparent substrate 151A, and the counter substrate 152 and the second transparent substrate 151B are bonded with a transparent adhesive (not shown).

[0035] The light L incident from the first side surface 15C of the second transparent substrate 151B propagates in a direction away from the first side surface 15C (direction D2) while being reflected by the second plane 15B of the second transparent substrate 151B and the first plane 15A of the first transparent substrate 151A. When the light L travels to the outside from the first plane 15A of the first transparent substrate 151A and the second plane 15B of the second transparent substrate 151B, it travels from a medium with a large refractive index to a medium with a small refractive index. At this time, if the angle of incidence of the light L incident on the first plane 15A and the second plane 15B is larger than the critical angle, it is totally reflected and is guided in the direction D2 while being reflected by the first plane 15A and the second plane 15B.

[0036] For example, the liquid crystal layer 210 includes a polymer-dispersed liquid crystal. The polymer-dispersed liquid crystal includes a bulk and fine particles. For example, the ordinary light refractive indexes of the bulk and the fine particles are equal to each other. The fine particles change their orientation in the bulk according to the potential difference between the potential supplied to the pixel electrode 216 (see FIG. 7) and the potential supplied to the common electrode 218 (see FIG. 7). The potential supplied to the pixel electrode 216 of each of the pixels PIX of the display device 10 is individually controlled. That is, the degree of at least the light transmission and scattering of each of the pixels PIX of the display device 10 is controlled for each of the pixels PIX. The degree of scattering of the liquid crystal layer (fine particles) 210 is controlled according to the potential supplied to each pixel electrode 216 and the potential supplied to the common electrode 218. Between the pixel electrode 216 to which a potential is supplied and the common electrode 218 to which a potential is supplied, the optical axis of the fine particles is tilted by the electric field generated between the pixel electrode 216 and the common electrode 218. Since the optical axis of the bulk does not change due to an electric field, the directions of the optical axis of the bulk and the optical axis of the particles are different from each other. When a potential difference occurs between the pixel electrode 216 and the common electrode 218, the liquid crystal layer 210 is in a scattering state in which the light emitted from the light source 104 is scattered. Therefore, as shown in FIG. 2, for example, when there is a pixel PIX in which the liquid crystal layer 210 is in a scattering state, at least a part of the light L that propagates while being reflected by the first plane 15A and the second plane 15B is scattered. As a result, the incident angle of the scattered light becomes smaller than the critical angle, and the scattered light LA, LB is emitted to the outside from the first surface 150a of the array substrate 150 (see FIG. 7) and the first surface 152a of the counter substrate 152 (see FIG. 7), i.e., the first plane 15A and the second plane 15B. For example, when a data signal is supplied to the source line SL of the pixel PIX and a potential based on the data signal is supplied to the pixel electrode 216, the liquid crystal layer 210 (polymer dispersed liquid crystal) goes into a scattering state, the display device 10 displays an image based on the data signal on the display panel 102, and the viewer can view the image together with the background. On the other hand, when no potential difference is generated between the pixel electrode 216 and the common electrode 218, the refractive index difference between the bulk and the particles becomes zero in all directions. At this time, the liquid crystal layer 210 goes into a non-scattering state in which it does not scatter the light L emitted from the light source 104.For example, light emitted from the light source 104 propagates in a direction away from the light source 104 (light-emitting section) while being reflected by the first surface 150a (see FIG. 7) of the array substrate 150 and the first surface 152a (see FIG. 7) of the counter substrate 152. When there is a pixel PIX in a non-scattering state, the light L passes through the first plane 15A and the second plane 15B. As a result, the viewer can view the background on the counter substrate 152 side from the array substrate 150 side, and can view the background on the array substrate 150 side from the counter substrate 152 side.

[0037] The display panel 102 of the display device 10 is not limited to a panel such as a transparent display including a polymer dispersed liquid crystal, but may be applied to a large panel that is not a transparent display.

[0038] [Pixel circuit] An overview of a pixel circuit included in the display device 10 will be described with reference to Fig. 4. Fig. 4 is a circuit diagram showing the circuit configuration of a pixel PIX. Configurations that are the same as or similar to those in Figs. 1 to 3 will be described as necessary.

[0039] For example, the display device 10 can simultaneously supply an on-voltage to four gate lines GL and simultaneously charge four pixels PIX arranged in a column direction by four source lines SL. As a result, the time required to scan the lines connected to all the pixels arranged in the display area 12 is shortened. Therefore, in a panel such as a transparent display or a large panel, a sufficient charging period for the pixels PIX can be ensured.

[0040] As shown in FIG. 4, four pixels PIX1 to PIX4 are arranged in the column direction (D2 direction). Each of the four pixels PIX1 to PIX4 is electrically connected to each of the four gate lines GL1 to GL4. Each of the four pixels PIX1 to PIX4 is electrically connected to each of the four source lines SL1 to SL4. Each of the four pixels PIX1 to PIX4 is electrically connected to a capacitance line CW. In the description of the display device 10, when the pixels PIX1 to PIX4 are not distinguished, the pixel is described as a pixel PIX, and when the pixels PIX1 to PIX4 are distinguished, the pixel is described as a pixel PIX1 to PIX4. As with the pixel PIX, when the gate lines GL1 to GL4 are not distinguished, the gate line is described as a gate line GL, and when the gate lines GL1 to GL4 are distinguished, the gate line is described as a gate line GL1 to GL4. As with the pixels PIX, when the source lines SL1 to SL4 are not differentiated, the source lines are written as source lines SL, and when the source lines SL1 to SL4 are differentiated, the source lines are written as source lines SL1 to SL4.

[0041] The pixel PIX has a transistor Tr, a liquid crystal element LE, and a storage capacitor C. The gate of the transistor Tr is connected to a gate line GL, the source of the transistor Tr is connected to a source line SL, and the drain of the transistor Tr is connected to one electrode of the liquid crystal element LE and one electrode of the storage capacitor C. The other electrode of the liquid crystal element LE is connected to a common electrode 218 (see FIG. 7). The other electrode of the storage capacitor C is connected to a capacitance line CW.

[0042] The transistor Tr has a function of controlling the time for writing a data signal supplied from the source line SL to the pixel PIX by switching between an on state and an off state. By turning the transistor Tr on, a potential corresponding to the data signal supplied from the source line SL can be written to a storage capacitor C electrically connected to the transistor Tr. In addition, by turning the transistor Tr off, the potential held in the storage capacitor C can be maintained.

[0043] For example, an on-voltage is supplied to the four gate lines GL at the same time, and the transistors Tr of the four pixels PIX1 to PIX4 are simultaneously turned on. In this state, a data signal is supplied to each of the source lines SL1 to SL4. As a result, it becomes possible to drive the four pixels PIX1 to PIX4 arranged in the D2 direction at the same timing.

[0044] [Pixel planar layout and cross-sectional structure] With reference to Figs. 5 to 12, the outline of the planar layout and cross-sectional structure of the pixel included in the display device 10 will be described. Fig. 5 is a planar layout of the pixel showing the configuration of the pixels PIX-A1, PIX-A2, PIX-B1, PIX-B2, PIX-C1, and PIX-C2 viewed in plan. Fig. 6 is an enlarged view of the region 250 of the pixel shown in Fig. 5. Fig. 7 is a cross-sectional view showing the cross-sectional structure of the pixel taken along the line B1-B2 shown in Fig. 6. Fig. 8 is a cross-sectional view showing the cross-sectional structure of the pixel taken along the line C1-C2 shown in Fig. 6. Figs. 9 to 12 are enlarged views of the planar layout of the pixel shown in Fig. 5. Configurations that are the same as or similar to those in Figs. 1 to 4 will be described as necessary. In order to make the drawings easier to see, the illustrations of the planarization film 207, the transparent conductive layer 212, the conductive layer 214, the pixel electrode 216, and the like are omitted in the enlarged view of the region 250 of the pixel shown in Fig. 6.

[0045] First, referring to Fig. 5, the configuration of pixels PIX-A1, PIX-A2, PIX-B1, PIX-B2, PIX-C1, and PIX-C2 in a plan view will be described. As shown in Fig. 5, gate lines GLn-1 to GLn+1 are arranged along the direction D1. Source lines SL1 to SL4 are arranged along the direction D2. For example, the opening region of pixel PIX-B1 is a region surrounded by adjacent gate lines GLn-1, gate line GLn, source line SL1, and source line SL4.

[0046] The pixels PIX-B1 and PIX-B2 aligned along the D2 direction (one column) are sandwiched between the source lines SL1 and SL3, and the source lines SL2 and SL4. In other words, four source lines SL1 to SL4 are disposed between the pixels PIX-A1 and PIX-A2 aligned along the D2 direction (one column) and the pixels PIX-B1 and PIX-B2 aligned along the D2 direction (one column).

[0047] A transistor Tr is provided in a region 250 where the gate line GL and the source lines SL1 to SL4 intersect. The transistor Tr is connected to a pixel electrode (see FIG. 7). The pixel electrode is provided in an aperture region of the pixel PIX-B1. A plurality of spacers SP are arranged with regularity at the intersections of the pixels PIX arranged in a matrix. For example, the spacers may be arranged in every other row and every other column of the pixels PIX. In other words, the spacers SP do not need to be arranged at an intersection adjacent to the intersection where the spacer SP is arranged.

[0048] In the region 250 where the gate line GL and the source lines SL1 to SL4 intersect, the source lines SL2 and SL4 are adjacent to the pixels PIX-A1 and PIX-A2, and the source lines SL1 and SL3 in the region 250 are adjacent to the pixels PIX-B1 and PIX-B2. For example, the spacer SP1 overlaps the source line SL3 adjacent to the pixels PIX-B1 and PIX-B2 and the source line SL2 adjacent to the pixels PIX-A1 and PIX-A2. The spacer SP2 overlaps the source line SL4 adjacent to the pixels PIX-B2 and PIX-B3 (not shown), and the source line SL3 adjacent to the pixels PIX-C2 and PIX-C3 (not shown).

[0049] Next, the region 250 where the gate wiring GL and the source wirings SL1 to SL4 intersect and the cross-sectional structure will be described in detail with reference to FIGS.

[0050] Fig. 6 shows a planar layout of conductive layers 202-1 to 202-9, oxide semiconductor layers 204-1 to 204-5, conductive layers 206-1 to 206-10, conductive layers 208-1 to 208-10, and conductive layer 214 in region 250. The order of stacking of each layer in a cross-sectional view of a pixel included in display device 10 will be described with reference to Fig. 7 showing a cross-sectional structure of a pixel taken along line B1-B2 shown in Fig. 6.

[0051] As shown in FIG. 7, a conductive layer 202-1 is provided on the first surface 150a of the array substrate 150. A gate insulating film 203 is provided on the conductive layer 202-1. An oxide semiconductor layer 204-1 is provided on the gate insulating film 203. The oxide semiconductor layer 204-1 is provided opposite the conductive layer 202-1 via the gate insulating film 203. Conductive layers 206-3 and 206-4 are provided on the oxide semiconductor layer 204-1. An insulating film 205 is provided on the conductive layers 206-3 and 206-4. A conductive layer 208-1 is provided on the insulating film 205.

[0052] When the conductive layers 202 are not differentiated, the conductive layers 202 are described as conductive layers 202-1 to 202-9 when they are differentiated. As with the conductive layer 202, when the oxide semiconductor layers 204 are not differentiated, the oxide semiconductor layers 204 are described as oxide semiconductor layers 204-1 to 204-5 when they are differentiated. As with the conductive layer 202, when the conductive layers 206 are not differentiated, the conductive layers 206 are described as conductive layers 206-1 to 206-10 when they are differentiated. As with the conductive layers 202, when the conductive layers 208 are not differentiated, the conductive layers 208 are described as conductive layers 208, and when the conductive layers 208 are differentiated, the conductive layers 208 are described as conductive layers 208-1 to 208-10.

[0053] The conductive layer 202-1 functions as a gate wiring GL (gate electrode). The conductive layer 206-3 functions as a drain electrode, and the conductive layer 206-4 functions as a source electrode (source wiring SL). The conductive layer 208-1 is a back gate wiring electrically connected to the gate wiring GL (gate electrode), and sandwiches the oxide semiconductor layer 204-1 together with the conductive layer 202-1 functioning as the gate wiring GL (gate electrode), and functions as a back gate of the transistor Tr. The conductive layer 202-1, the gate insulating film 203, the oxide semiconductor layer 204-1, and the conductive layers 206-3 and 206-4 function as the transistor Tr.

[0054] Moreover, the conductive layer 208 of the display device 10 includes a first metal conductive layer 160, a second metal conductive layer 161 provided on and in contact with the first metal conductive layer 160, and a third metal conductive layer 162 provided on and in contact with the second metal conductive layer 161. That is, the conductive layer 208 includes a configuration in which three metal conductive layers are stacked. The thickness of the conductive layer 208 is thicker than the thickness of the oxide semiconductor layer 204, thicker than the thickness of the conductive layer 202, and thicker than the thickness of the conductive layer 206.

[0055] The transistor Tr included in the pixel PIX of the display device 10 is, for example, a bottom-gate driven transistor, but the transistor Tr included in the pixel PIX is not limited to a bottom-gate driven transistor. The transistor Tr of the display device 10 may be a top-gate driven transistor or a dual-gate driven transistor.

[0056] The gate insulating film 203 includes a nitride insulating film 203a and an oxide insulating film 203b, which are stacked. The insulating film 205 includes an oxide insulating film 205a and a nitride insulating film 205b, which are stacked. The oxide semiconductor layer 204-1 is sandwiched between the oxide insulating film 203b and the oxide insulating film 205a. The oxide insulating film 205a and the oxide insulating film 203b release oxygen during the manufacturing process. The released oxygen is supplied to the oxide semiconductor layer 204-1. This is preferable because oxygen defects generated in the oxide semiconductor layer 204-1 during the manufacturing process can be repaired.

[0057] A planarization film 207 is provided on the conductive layer 208-1 and the insulating film 205. The planarization film 207 is provided to reduce unevenness of various wirings constituting the transistor Tr. When the display device 10 is applied to a transparent display, it is preferable to remove the planarization film 207 in the aperture region of the pixel PIX. By removing the planarization film 207 in the aperture region of the pixel PIX, light absorption by the planarization film 207 in the aperture region is suppressed. Therefore, as shown in FIG. 7, the planarization film 207 is disposed in the wiring region, and is removed in the aperture region and is not disposed in the aperture region. More specifically, the planarization film 207 is provided so as to overlap with the gate wirings GLn-1 to GLn+1 and the source wirings SL1 to SL4 shown in FIG. 5. Referring to FIG. 7, the planarization film 207 is provided in a region overlapping with the conductive layer 206-4 and the transistor Tr, and is not provided between the conductive layer 206-3 and the pixel electrode 216-1. As a result, the light transmittance in the aperture region of the display device 10 is improved compared to the case where the planarizing film 207 is provided in the aperture region.

[0058] A transparent conductive layer 212 is provided on the planarization film 207. A conductive layer 214 is provided so as to be in contact with the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as a capacitance line CW. The transparent conductive layer 212 and the conductive layer 214 are provided at positions overlapping the gate lines GLn-1 to GLn+1 and the source lines SL1 to SL4 shown in FIG. 5. The conductive layer 214 also functions as a light blocking layer. Although a configuration in which the conductive layer 214 of the display device 10 is provided on the transparent conductive layer 212 will be described, a configuration in which the transparent conductive layer 212 is provided on the conductive layer 214 may be used. An insulating film 209 is provided on the conductive layer 214. Since the planarization film 207 in the opening region is removed, the insulating film 209 in the opening region is in contact with the insulating film 205. A pixel electrode 216-1 is provided on the insulating film 209. The pixel electrode 216-1 is connected to the conductive layer 206-3 through a contact hole provided in the insulating films 205 and 209. The pixel electrode 216-1 is provided in an opening region of the pixel PIX. The pixel electrode 216-1 does not cover the source line SL and the transistor Tr, but covers a part of the conductive layer 206-3.

[0059] 7, an end of the transparent conductive layer 212 provided on the planarization film 207 overlapping the transistor Tr is provided between an end of the conductive layer 214 and the pixel electrode 216-1, and the conductive layer 214 provided on the planarization film 207 overlapping the transistor Tr is provided so as to overlap the transistor Tr. As a result, the transistor Tr can be shielded from light. Therefore, the display device 10 can suppress leakage current (light leakage) generated in the oxide semiconductor layers 204-1 to 204-5 included in the transistor Tr due to irradiation with light, and can suppress deterioration of the electrical characteristics of the transistor Tr.

[0060] The counter substrate 152 is provided to face the array substrate 150. The counter substrate 152 is provided with a light-shielding layer 219, a common electrode 218, and an insulating film 221. The light-shielding layer 219 functions as a black matrix. In the structure shown in FIG. 7, the light-shielding layer 219 is provided in a region overlapping with the conductive layer 206-4. The light-shielding layer 219 is arranged in a lattice shape so as to cover the gate lines GLn-1 to GLn+1 and the source lines SL1 to SL4. The common electrode 218 has a size that spreads over the entire display area 112. The light-shielding layer 219 may be formed of a metal film, and functions as an auxiliary electrode by being provided in contact with the common electrode 218 formed of a transparent conductive film. A liquid crystal layer 210 is provided between the array substrate 150 and the counter substrate 152, and is sealed by a sealant 154 (see FIG. 1). A liquid crystal element LE is configured by the pixel electrode 216-1, the liquid crystal layer 210, and the common electrode 218. Although not shown in the figure, an alignment film is provided on the array substrate 150 so as to cover the insulating film 209 and the pixel electrode 216-1, and an alignment film is provided on the counter substrate 152 so as to cover the insulating film 221.

[0061] 9 is a planar layout of the conductive layers 202-1 to 202-9, the oxide semiconductor layers 204-1 to 204-5, and the conductive layers 206-1 to 206-10 in the region 250. The conductive layers 202-1 to 202-9 are provided on the array substrate 150. The conductive layer 202-1 extends in the D1 direction and has a region branching in the D2 direction. The conductive layers 202-2 to 202-9 extend in the D2 direction. The oxide semiconductor layers 204-1 to 204-5 are provided on the conductive layer 202-1. The gate insulating film 203 (see FIG. 7) is provided between the oxide semiconductor layers 204-1 to 204-5 and the conductive layer 202-1. The oxide semiconductor layers 204-1 to 204-5 each have an independent rectangular pattern and are arranged so as to be aligned in the D2 direction. The transistor Tr of the pixel PIX is composed of, for example, five oxide semiconductor layers 204-1 to 204-5. The number of oxide semiconductor layers is not limited to five. For example, the number of oxide semiconductor layers may be more than one. For example, by providing the oxide semiconductor layers separately as a plurality of oxide semiconductor layers (for example, the oxide semiconductor layers 204-1 to 204-5), the fluctuation in the characteristics of the transistor Tr caused by heat generation of the oxide semiconductor layers is suppressed. In addition, by providing the oxide semiconductor layers 204-1 to 204-5 on the conductive layer 202-1, the light guided through the glass substrate (array substrate 150) from the conductive layer 202-1 side toward the oxide semiconductor layers 204-1 to 204-5 is reflected by the conductive layer 202-1. As a result, the transistor Tr can suppress the leakage current (light leakage) generated in the oxide semiconductor layers 204-1 to 204-5 by irradiation with light.

[0062] Conductive layers 206-1 to 206-10 are provided on the gate insulating film 203 and the oxide semiconductor layers 204-1 to 204-5. The conductive layers 206-1 and 206-2 extend in the D1 direction, and the conductive layers 206-3 to 206-10 extend in the D2 direction.

[0063] The conductive layer 202-1 overlaps the conductive layer 206-1, and is connected to the conductive layer 206-1 through contact holes 213-1 and 213-2 provided in the gate insulating film 203. Furthermore, the conductive layer 202-1 overlaps the conductive layer 206-2, and is connected to the conductive layer 206-2 through contact holes 213-12 and 213-13 provided in the gate insulating film 203. A region of the conductive layer 202-1 extending in the D1 direction functions as a gate wiring. A region of the conductive layer 202-1 extending in the D2 direction functions as a gate electrode.

[0064] The conductive layers 202-2 and 202-3 overlap with the conductive layer 206-4. The conductive layer 202-2 is connected to the conductive layer 206-4 through a contact hole 213-3 provided in the gate insulating film 203. The conductive layer 202-3 is connected to the conductive layer 206-4 through a contact hole 213-4 provided in the gate insulating film 203. That is, the conductive layer 202-2 is connected to the conductive layer 202-3 through the conductive layer 206-4. The conductive layer 206-4 intersects with the conductive layer 202-1. In addition, a region of the conductive layer 206-4 that does not overlap with the conductive layers 202-2 and 202-3 functions as a source electrode of the transistor Tr. The conductive layer 206-3 functions as a drain electrode of the transistor Tr.

[0065] The conductive layer 202-4 overlaps with the conductive layer 206-5, and is connected to the conductive layer 206-5 through a contact hole 213-5 provided in the gate insulating film 203. The conductive layer 202-5 overlaps with the conductive layer 206-5, and is connected to the conductive layer 206-5 through a contact hole 213-6 provided in the gate insulating film 203. That is, the conductive layer 202-4 is connected to the conductive layer 202-5 through the conductive layer 206-5.

[0066] The conductive layer 202-6 overlaps with the conductive layer 206-6 and is connected to the conductive layer 206-6 through a contact hole 213-7 provided in the gate insulating film 203. The conductive layer 206-6 overlaps with the conductive layer 208-8 (see FIG. 10) and is connected to the conductive layer 208-8 through contact holes 215-11 and 215-12 (see FIG. 10) provided in the insulating film 205. The conductive layer 208-8 overlaps with the conductive layer 206-7 and the conductive layer 202-7 and is connected to the conductive layer 206-7 through contact holes 215-13 and 215-14 (see FIG. 10) provided in the insulating film 205. The conductive layer 202-7 overlaps with the conductive layer 206-7 and is connected to the conductive layer 206-7 through a contact hole 213-8 provided in the gate insulating film 203. That is, conductive layer 202-6 is connected to conductive layer 202-7 via conductive layer 206-6, conductive layer 208-8, and conductive layer 206-7.

[0067] The conductive layer 202-8 overlaps with the conductive layer 206-8 and is connected to the conductive layer 206-8 through a contact hole 213-9 provided in the gate insulating film 203. The conductive layer 206-8 overlaps with the conductive layer 208-9 (see FIG. 10) and is connected to the conductive layer 206-8 through a contact hole 215-18 (see FIG. 10) provided in the insulating film 205. The conductive layer 208-9 overlaps with the conductive layer 206-9 and is connected to the conductive layer 206-9 through contact holes 215-15 and 215-16 (see FIG. 10) provided in the insulating film 205. The conductive layer 206-9 overlaps with the conductive layer 202-9 and is connected to the conductive layer 202-9 through contact holes 213-10 and 213-11 provided in the gate insulating film 203. The conductive layer 202-9 overlaps with the conductive layer 206-10, and is connected to the conductive layer 206-10 via contact holes 213-12 and 213-13 provided in the gate insulating film 203. That is, the conductive layer 202-8 is connected to the conductive layer 202-9 via the conductive layers 206-8, 206-9, and the conductive layer 208-9.

[0068] The conductive layer 202-9 and the conductive layer 208-8 have a bent region. The conductive layer 202-9 has a region where it overlaps and intersects with the conductive layer 208-8 (see FIG. 10). That is, the conductive layer 202-9 has a region where the second source wiring SL2 and the fourth source wiring SL4 intersect. Although detailed description is omitted, as shown in FIG. 5, the conductive layer 202-4 and the conductive layer 208-3 have a bent region. The conductive layer 202-4 has a region where it overlaps and intersects with the conductive layer 208-3. That is, the first source wiring SL1 has a region where it intersects with the third source wiring SL3.

[0069] 9, the conductive layer 202-1 extends along the direction D1. The gate wiring GL in the region intersecting (overlapping) with the source wirings SL1 to SL4 is composed of only the conductive layer 202-1, and the conductive layer 206-1 and the conductive layer 206-2 are disposed apart from each other.

[0070] 10 is a planar layout of conductive layer 202-1, conductive layers 206-1 to 206-10, and conductive layers 208-1 to 208-10 in region 250. Conductive layers 206-1 to 206-10 are as described with reference to FIGS. 5, 7, and 9. Conductive layers 208-1 to 208-10 are provided on insulating film 205 (see FIG. 7). Conductive layer 208-1 has a region extending in the D2 direction and a region extending in the D1 direction. Conductive layer 208-2 extends in the D1 direction, and conductive layers 208-3 to 208-10 extend in the D2 direction.

[0071] A region of the conductive layer 208-1 extending in the D2 direction overlaps with the oxide semiconductor layers 204-1 to 204-5. A region of the conductive layer 208-1 extending in the D1 direction overlaps with the conductive layer 206-1 and is connected to the conductive layer 206-1 via contact holes 215-1 and 215-2 provided in the insulating film 205. The conductive layer 208-1 also overlaps with the conductive layer 202-1 (see FIG. 9) and is connected to the conductive layer 202-1 via contact holes 215-1 (see FIG. 10) and 215-2 (see FIG. 10) provided in the insulating film 205, the conductive layer 206-1, and contact holes 213-1 and 213-2 provided in the gate insulating film 203 (see FIG. 9).

[0072] The conductive layer 208-2 overlaps with the conductive layer 206-2, and is connected to the conductive layer 206-2 through contact holes 215-3 and 215-4 provided in the insulating film 205. Furthermore, the conductive layer 208-2 overlaps with the conductive layer 202-1, and is connected to the conductive layer 202-1 through contact holes 215-3 and 215-4 provided in the insulating film 205, the conductive layer 206-2, and contact holes 213-12 (see FIG. 9) and 213-13 (see FIG. 9) provided in the gate insulating film 203.

[0073] The conductive layer 208-3 overlaps with the conductive layer 206-4, and is connected to the conductive layer 206-4 via contact holes 215-5 and 215-6 provided in the insulating film 205. The conductive layer 208-4 overlaps with the conductive layer 206-4, and is connected to the conductive layer 206-4 via a contact hole 215-7 provided in the insulating film 205. That is, the conductive layer 208-3 is connected to the conductive layer 208-4 via the conductive layer 206-4.

[0074] The conductive layer 208-3 overlaps with the conductive layer 202-2 (see FIG. 9) and is connected to the conductive layer 202-2 via contact holes 215-5 and 215-6 provided in the insulating film 205, the conductive layer 206-4, and a contact hole 213-3 (see FIG. 9) provided in the gate insulating film 203. The conductive layer 208-4 overlaps with the conductive layer 202-3 (see FIG. 9) and is connected to the conductive layer 202-3 via a contact hole 215-7 provided in the insulating film 205, the conductive layer 206-4, and a contact hole 213-4 (see FIG. 9) provided in the gate insulating film 203.

[0075] The conductive layer 208-5 overlaps with the conductive layer 206-5, and is connected to the conductive layer 206-5 through a contact hole 215-8 provided in the insulating film 205. The conductive layer 208-6 overlaps with the conductive layer 206-5, and is connected to the conductive layer 206-5 through a contact hole 215-9 provided in the insulating film 205. That is, the conductive layer 208-5 is connected to the conductive layer 208-6 through the conductive layer 206-5.

[0076] The conductive layer 208-5 overlaps with the conductive layer 202-4 (see FIG. 9) and is connected to the conductive layer 202-4 via a contact hole 215-8 provided in the insulating film 205, the conductive layer 206-5, and a contact hole 213-5 (see FIG. 9) provided in the gate insulating film 203. The conductive layer 208-6 overlaps with the conductive layer 202-5 (see FIG. 9) and is connected to the conductive layer 202-5 via a contact hole 215-9 provided in the insulating film 205, the conductive layer 206-5, and a contact hole 213-6 (see FIG. 9) provided in the gate insulating film 203.

[0077] The conductive layer 208-7 overlaps with the conductive layer 206-6, and is connected to the conductive layer 206-6 through a contact hole 215-10 provided in the insulating film 205. The conductive layer 208-8 overlaps with the conductive layer 206-6, and is connected to the conductive layer 206-6 through contact holes 215-11 and 215-12 provided in the insulating film 205. That is, the conductive layer 208-7 is connected to the conductive layer 208-8 through the conductive layer 206-6.

[0078] The conductive layer 208-7 overlaps with the conductive layer 202-6 (see FIG. 9) and is connected to the conductive layer 202-6 via a contact hole 215-10 provided in the insulating film 205, the conductive layer 206-6, and a contact hole 213-7 (see FIG. 9) provided in the gate insulating film 203. The conductive layer 208-8 overlaps with the conductive layer 202-7 (see FIG. 9) and is connected to the conductive layer 202-7 via contact holes 215-11 and 215-12 provided in the insulating film 205, the conductive layer 206-6, contact holes 215-13 and 215-14 provided in the insulating film 205, a contact hole 213-8 (see FIG. 9) provided in the gate insulating film 203, and the conductive layer 206-7 (see FIG. 9).

[0079] The conductive layer 208-9 overlaps with the conductive layer 206-9, and is connected to the conductive layer 206-9 via contact holes 215-15 and 215-16 provided in the insulating film 205. The conductive layer 208-10 overlaps with the conductive layer 206-10, and is connected to the conductive layer 206-10 via contact holes 215-16 and 215-17 provided in the insulating film 205.

[0080] The conductive layer 208-9 overlaps with the conductive layer 202-8 (see FIG. 9) and is connected to the conductive layer 202-8 via a contact hole 215-18 provided in the insulating film 205, the conductive layer 206-8, and a contact hole 213-9 (see FIG. 9) provided in the gate insulating film 203. The conductive layer 208-9 overlaps with the conductive layer 202-9 (see FIG. 9) and is connected to the conductive layer 202-9 via contact holes 215-15 and 215-16 provided in the insulating film 205, the conductive layer 206-9 (see FIG. 9), and contact holes 213-10 and 213-11 (see FIG. 9) provided in the gate insulating film 203. Furthermore, the conductive layer 208-10 overlaps with the conductive layer 202-9, and is connected to the conductive layer 202-9 via contact holes 215-16 and 215-17 provided in the insulating film 205, the conductive layer 206-10 (see FIG. 9), and contact holes 213-12 and 213-13 (see FIG. 9) provided in the gate insulating film 203. That is, the conductive layer 208-9 is connected to the conductive layer 208-10 via the conductive layers 206-9, 206-10, and the conductive layer 202-9.

[0081] 11 is a planar layout of the planarizing film 207, the transparent conductive layer 212, the conductive layer 214, and the spacer SP in the region 250. Referring to the planar layout of the pixel shown in FIG. 11 and the cross-sectional view of the pixel shown in FIG. 7, the planarizing film 207 is removed in the opening regions of the pixels PIX1 to PIX4. That is, the planarizing film 207 is provided on the wiring region. Specifically, the planarizing film 207 is provided in a lattice shape so as to cover the gate lines GL and the source lines SL1 to SL4. In addition, the transparent conductive layer 212 is provided on the planarizing film 207, and the conductive layer 214 is provided on the transparent conductive layer 212 so as to be in contact with the top of the transparent conductive layer 212. The transparent conductive layer 212 and the conductive layer 214 function as the capacitance wiring CW (see FIG. 4). The conductive layer 214 and the transparent conductive layer 212 are provided in a lattice pattern on the conductive layers 202-1 to 202-9, the conductive layers 206-1 to 206-10, and the conductive layers 208-1 to 208-10 with the planarization film 207 interposed therebetween. Specifically, the conductive layer 214 and the transparent conductive layer 212 are provided in a lattice pattern so as to cover the gate lines GL and the source lines SL1 to SL4, similar to the planarization film 207. The transparent conductive layer 212 has an opening 223, and the conductive layer 214 has an opening 225. The openings 223 and 225 are provided so as to overlap with each other. The transparent conductive layer 212 may be provided on the entire surface, not in a lattice pattern.

[0082] The source lines SL1 to SL4 are spaced apart from the capacitance line CW in the D3 direction, and are therefore less susceptible to the potential supplied to the capacitance line CW. In addition, the electrical resistance of the conductive layer 214 is smaller than that of the transparent conductive layer 212, and the conductive layer 214 is arranged in a lattice pattern. If the conductive layer 214 is not present, the potential supplied from the capacitance line CW to the pixel PIX is not uniform depending on the position of the pixel PIX, and therefore a potential sufficient for stabilizing the display is not supplied to the pixel PIX. On the other hand, since the capacitance line CW of the display device 10 includes the conductive layer 214, the potential supplied from the capacitance line CW to the pixel PIX is uniform, independent of the position of the pixel PIX in the display area 12. As a result, the capacitance line CW of the display device 10 can supply a potential sufficient for stabilizing the display to the pixel PIX.

[0083] Moreover, the transparent conductive layer 212 and the conductive layer 214 are provided so as to cover not only the gate wiring GL and the source wiring SL1 to SL4 but also the transistor Tr. As will be described in detail later, the conductive layer 214 is formed using a metal material and has a light-shielding property. Therefore, the conductive layer 214 can shield the wiring region including the gate wiring GL and the source wiring SL1 to SL4 from light. Furthermore, the light guided through the glass substrate (opposing substrate 152) from the transparent conductive layer 212 and the conductive layer 214 side toward the oxide semiconductor layers 204-1 to 204-5 is reflected by the conductive layer 214. As a result, the display device 10 can suppress a leak current (light leak) generated in the oxide semiconductor layers 204-1 to 204-5 due to irradiation with light.

[0084] The width of the conductive layer 214 is larger than the combined width of the source wirings SL1 to SL4 in a plan view. The width of the conductive layer 214 is larger than the combined width of the gate wirings GL in a plan view. That is, since the conductive layer 214 covers the wiring region including the gate wirings GL and the source wirings SL1 to SL4, it is possible to suppress the light reflected at the ends of the source wirings SL1 to SL4 (reflected light) from being emitted to the inside of the display panel 102. The width of the conductive layer 214 is the length of the conductive layer 214 in a direction (D1 direction) intersecting with the direction (D2 direction) in which the source wirings SL1 to SL4 extend, and the combined width of the source wirings SL1 to SL4 is the combined length of the widths of the source wirings SL1 to SL4 in a direction (D1 direction) intersecting with the direction (D2 direction) in which the source wirings SL1 to SL4 extend. The width of the gate wiring GL is the length of the gate wiring GL in a direction (D2 direction) intersecting with the direction (D1 direction) in which the gate wiring GL extends.

[0085] For example, as described with reference to FIG. 6 to FIG. 10, the pixels PIX include a pixel PIX-B2 arranged alongside the pixel PIX-B1 along the D2 direction. As shown in FIG. 5, the pixel PIX-B2 includes a gate line GL3 (GLn+1) extending in the D1 direction and a source line SL2 extending in the D2 direction in a plan view. The conductive layer 202 includes the gate line GL3 and may function as a gate line and a gate electrode, and the conductive layer 206-6 and the conductive layer 208-7 include a source line SL2 and may function as a source electrode and a source line. The gate line GL3 is provided in the D2 direction at a distance from the gate line GL2 extending in the D1 direction in a plan view. The source line SL2 is provided in the D2 direction so as to be parallel to the source electrode of the transistor Tr included in the conductive layer 206-4 in a plan view, and overlaps (intersects) with the gate line GL2. Moreover, the source line SL2 overlaps (intersects) with the gate line GL3 in a plan view.

[0086] For example, in the planar layouts shown in Figures 6 and 9 and the cross-sectional structure shown in Figure 8, in the region where the source wiring SL2 overlaps with the gate wiring GL2, the source wiring SL2 included in the conductive layer 206-6 and the source electrode of the transistor Tr included in the conductive layer 206-4 overlap with the gate wiring GL2 included in the conductive layer 202-1.

[0087] Referring to the planar layout of the pixel shown in FIG. 6, FIG. 9 to FIG. 11, and the cross-sectional structure shown in FIG. 7 and FIG. 8, the spacer SP is disposed so as to be located at the intersection of the gate line GL2 and the source lines SL2 and SL3. At the intersection of the gate line GL2 and the source lines SL2 and SL3, the gate line GL2 is composed of the conductive layer 202-1, and the source lines SL2 and SL3 are composed of the conductive layers 206-5 and 206-6. The spacer SP is not disposed at the intersection of the gate line GL2 and the source lines SL1 and SL4. At the intersection of the gate line GL2 and the source lines SL1 and SL4, the gate line GL2 is composed of the conductive layer 202-1, and the source lines SL1 and SL4 are composed of the conductive layers 208-1 and 208-9. The film thickness of the conductive layers 206-5 and 206-6 is thinner than the film thickness of the conductive layer 202-1 and thinner than the film thickness of the conductive layers 208-1 and 208-9. As a result, the display device 10 allows the gate lines GL and the source lines SL to cross each other without crossing a conductive layer with a large thickness.

[0088] Further, a transparent conductive layer 212 and a conductive layer 214 are provided on the planarization film 207. An opening 230 is provided in the conductive layer 214. An insulating film 209 is provided on the transparent conductive layer 212 and the conductive layer 214. A spacer SP is provided inside the opening 230 of the conductive layer 214 and on the insulating film 209.

[0089] Moreover, the spacer SP is disposed so as to be located in the region where the conductive layer 202-1 and the conductive layer 206-5 intersect and in the region where the conductive layer 202-1 and the conductive layer 206-6 intersect. Between the spacer SP and the conductive layer 202-1, only the thin conductive layers 206-5 and 206-6, the gate insulating film 203 (the nitride insulating film 203a and the oxide insulating film 203b) and the insulating film 205 (the oxide insulating film 205a and the nitride insulating film 205b), and the planarization film 207 are provided. That is, no thick conductive layer is provided between the spacer SP and the conductive layer 202-1. By disposing the spacer SP so as to be located on the thin conductive layers 206-5 and 206-6, rather than on the thick conductive layer 208, planarization is promoted, and the distance (cell gap) from the upper surface of the array substrate 150 of the display device 10 to the upper surface of the insulating film 209 can be suppressed within a predetermined distance.

[0090] A plurality of spacers SP are provided on the counter substrate 152 (see FIG. 5). Also, as shown in FIG. 8, a light-shielding layer 219 is provided on the counter substrate 152. A common electrode 218 is provided so as to be in contact with the light-shielding layer 219. Also, an insulating film 221 is provided so as to be in contact with the common electrode 218. An opening 232 is provided in the insulating film 221. Also, a region in which the opening 232 is provided in the insulating film 221 overlaps with a region in which the opening 230 is provided in the conductive layer 214. The spacers SP are provided inside the opening 232 in the insulating film 221. The spacers SP are provided so as to be in contact with the common electrode 218.

[0091] 12 is a planar layout of the conductive layers 206-1 to 206-10, the conductive layers 208-1 to 208-10, and the pixel electrodes 216-1 to 216-4 in the region 250. The conductive layers 206-1 to 206-10 and the conductive layers 208-1 to 208-10 are as described with reference to FIGS. 5 and 7 to 10. Referring to the planar layout of the pixel shown in FIG. 12 and the cross-sectional view of the pixel shown in FIG. 7, the pixel electrode 216-1 is provided on the insulating film 209 and is provided in the aperture region of the pixel PIX. The pixel electrodes 216-2 to 216-4 are configured in the same manner as the pixel electrode 216-1, so the pixel electrode 216-1 will be described here, and the pixel electrodes 216-2 to 216-4 will be described as necessary. The pixel electrode 216-1 is connected to the conductive layer 206-3 through contact holes 217-1 and 217-2 provided in the insulating film 209 and contact holes 215-18 and 215-19 (see FIG. 10) provided in the insulating film 205. The contact hole 217-3 provided in the insulating film 209 is provided so as to overlap with the openings 223 and 225 (see FIG. 11) in a plan view. The openings 223 and 225 and the contact hole 217-3 are provided on the planarization film 207. As a result, the display device 10 can release moisture contained in the planarization film 207 through the openings 223 and 225 and the contact hole 217-3.

[0092] As explained with reference to Figures 5 to 12, the gate wiring GL (e.g., GL2) is configured by stacking conductive layers 202-1, 206-1, and 208-1 extending in the D1 direction, and also by stacking conductive layers 202-1, 206-2, and 208-2 extending in the D1 direction.

[0093] 5 to 12, the source wiring SL1 is configured by stacking the conductive layer 202-2 and conductive layer 206-4 extending in the D2 direction, the conductive layer 206-4 and conductive layer 208-3 extending in the D2 direction, 202-3 and conductive layer 206-4 extending in the D2 direction, and conductive layer 206-4 and conductive layer 208-4 extending in the D2 direction. In addition, the source wiring SL1 is configured only by the conductive layer 206-4 in a region intersecting with the gate wiring GL, the conductive layer 202-2 and the conductive layer 202-3 are arranged apart from each other, and the conductive layer 208-3 and the conductive layer 208-4 are arranged apart from each other. The source wiring SL2 is configured by stacking a conductive layer 202-6 and a conductive layer 206-6 extending in the D2 direction, a conductive layer 202-6 and a conductive layer 208-7 extending in the D2 direction, a conductive layer 206-6 and a conductive layer 208-8 extending in the D2 direction, a conductive layer 208-8 and a conductive layer 206-7 extending in the D2 direction, and a conductive layer 206-7 and a conductive layer 202-7 extending in the D2 direction. In addition, the source wiring SL2 is configured only by the conductive layer 206-6 in a region intersecting with the gate wiring GL, the conductive layer 202-6 and the conductive layer 202-7 are arranged at a distance from each other, and the conductive layer 208-7 and the conductive layer 208-8 are arranged at a distance from each other. The source wiring SL3 is configured by stacking conductive layers 202-4 and 206-5 extending in the D2 direction, conductive layers 206-5 and 202-5 extending in the D2 direction, and conductive layers 208-5 and 208-6 extending in the D2 direction. In a region where the source wiring SL3 intersects with the gate wiring GL, the source wiring SL3 is configured only with conductive layer 206-5, conductive layers 202-4 and 202-5 are spaced apart, and conductive layers 208-5 and 208-6 are spaced apart. The source wiring SL4 is configured by stacking conductive layers 202-8 and 206-8 extending in the D2 direction, conductive layers 206-8 and 208-9 extending in the D2 direction, conductive layers 208-9 and 206-9 extending in the D2 direction, and conductive layers 206-9 and 202-9 extending in the D2 direction. In addition, the source wiring SL4 is configured only with conductive layer 208-9 in a region intersecting with the gate wiring GL, and conductive layer 202-8 and conductive layer 202-9 are arranged apart from each other.That is, the conductive layer 202-1 in the region intersecting with the gate line GL intersects with two different conductive layers, the conductive layer 208 and the conductive layer 206.

[0094] Since the source wiring SL of the display device 10 can be configured by laminating a plurality of conductive layers, the source wiring SL1 and the source wiring SL3 can be arranged to cross each other, and the source wiring SL2 and the source wiring SL4 can be arranged to cross each other. Furthermore, since the source wiring of the display device 10 can be configured by laminating a plurality of conductive layers, even if static electricity is generated during the manufacturing process of the display area 12 and the peripheral area 14 of the array substrate 150, the static electricity can be released. Therefore, the manufacturing process of the display device 10 can suppress the occurrence of defects caused by static electricity.

[0095] As described in "Overview of the Display Device 10", the thickness of the conductive layer 206 is smaller than the thicknesses of the conductive layer 202 and the conductive layer 208. This reduces damage to the oxide semiconductor layer 204 containing an oxide semiconductor when the conductive layer 206 for forming the source wiring SL and the drain electrode is formed in the manufacturing process of the display device 10. The source wiring SL includes the conductive layer 208 that is thicker than the conductive layer 206 and the oxide semiconductor layer 204, and the conductive layer 208 can be used as a wiring routed within the display region 12. Thus, the conductive layer 208 not only compensates for an increase in the resistance value of the source wiring SL caused by the conductive layer 206 being as thin as the oxide semiconductor layer 204, but also reduces the resistance value of the source wiring SL to be smaller than the resistance value of a wiring formed using only the conductive layer 202 or the conductive layer 206. As a result, the display device 10 can reduce a signal delay caused by the resistance value of the source wiring SL.

[0096] [Materials of each component of the display device 10] The array substrate 150 and the counter substrate 152 may be rigid substrates that are light-transmitting and not flexible. For example, the rigid substrates that are light-transmitting and not flexible may be glass substrates, quartz substrates, or sapphire substrates. When the array substrate 150 and the counter substrate 152 need to be flexible, the array substrate 150 and the counter substrate 152 may be flexible substrates that contain resin. For example, the flexible substrates that contain resin may be polyimide substrates, acrylic substrates, siloxane substrates, or fluororesin substrates. In order to improve the heat resistance of the array substrate 150 and the counter substrate 152, impurities may be introduced into the resin. In addition, when the display device 10 is applied to a transparent display or a large display, it is preferable to use glass substrates as the array substrate 150 and the counter substrate 152.

[0097] The first transparent substrate 151A and the second transparent substrate 151B are provided to protect the array substrate 150 and the counter substrate 152. Therefore, for example, a substrate having light-transmitting properties can be used for the first transparent substrate 151A and the second transparent substrate 151B. For example, the substrate having light-transmitting properties is a glass substrate, a plastic substrate, or the like.

[0098] For example, the gate insulating film 203, the insulating film 205, and the insulating film 209 may be formed of a material such as silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum nitride (AlNx), aluminum nitride oxide (AlNxOy), silicon oxide (SiOx), silicon oxide nitride (SiOxNy), aluminum oxide (AlOx), and aluminum oxide nitride (AlOxNy). The gate insulating film 203, the insulating film 205, and the insulating film 209 may have a single-layer structure using the above-mentioned materials, or may have a laminated structure using two or more of the above-mentioned materials. For example, as described in "Plane layout and cross-sectional structure of pixel", the gate insulating film 203 is formed of a laminated structure using a nitride insulating film 203a and an oxide insulating film 203b, and the insulating film 205 is formed of a laminated structure using an oxide insulating film 205a and a nitride insulating film 205b. For example, the nitride insulating films 203a, 205b, and the insulating film 209 may be formed of silicon nitride. For example, a film containing silicon nitride is formed by chemical vapor deposition. For example, the oxide insulating films 203b and 205a can be formed using silicon oxide.

[0099] SiOxNy and AlOxNy are silicon compounds and aluminum compounds that contain a smaller ratio (x>y) of nitrogen (N) than oxygen (O). Also, SiNxOy and AlNxOy are silicon compounds and aluminum compounds that contain a smaller ratio (x>y) of oxygen than nitrogen.

[0100] For example, an organic insulating material can be used as the material for forming the planarizing film 207. For example, the organic insulating material is a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluorine resin, a siloxane resin, or the like.

[0101] The conductive layers 202, 206 and 214 may be made of a common metal material. For example, the common metal material may be aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), or an alloy or compound thereof. The conductive layers 202, 206, 208 and 214 may have a single-layer structure using the above-mentioned materials, or may have a laminated structure using two or more of the above-mentioned materials. For example, the thickness of the conductive layer 202 is 250 nm or more and 350 nm or less, and the conductive layer 202 of the display device 10 according to one embodiment of the present invention has a single-layer structure, and the thickness of the conductive layer 202 is 290 nm. For example, the conductive layer 206 is a single layer of titanium (Ti). The thickness of the conductive layer 206 is 50 nm or more and 100 nm or less, and the thickness of the conductive layer 206 of the display device 10 according to one embodiment of the present invention is 100 nm. For example, the thickness of the conductive layer 214 is 250 nm or more and 350 nm or less, and the thickness of the conductive layer 214 of the display device 10 according to one embodiment of the present invention is 310 nm.

[0102] The material forming the first metal conductive layer 160, the second metal conductive layer 161, and the third metal conductive layer 162 included in the conductive layer 208 can be the same metal material as the conductive layers 202, 206, and the conductive layer 214. For example, the material forming the first metal conductive layer 160 and the third metal conductive layer 162 can be titanium (Ti), and the material forming the second metal conductive layer 161 can be aluminum (Al). For example, the film thickness of the first metal conductive layer 160 and the film thickness of the third metal conductive layer 162 are 50 nm or more and 100 nm or less, and the film thickness of the first metal conductive layer 160 and the film thickness of the third metal conductive layer 162 of the display device 10 according to one embodiment of the present invention are 100 nm. For example, the film thickness of the conductive layer 206 and the second metal conductive layer 161 is 300 nm or more and 500 nm or less, and the film thickness of the third metal conductive layer 162 of the display device 10 according to one embodiment of the present invention is 350 nm.

[0103] The material for forming the oxide semiconductor layer 204 may be an oxide semiconductor having semiconductor properties. The oxide semiconductor layer 204 has light-transmitting properties. For example, the material for forming the oxide semiconductor layer 204 may be an oxide semiconductor containing two or more metals including indium (In). For example, the material for forming the oxide semiconductor layer 204 may be an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). In particular, the material for forming the oxide semiconductor layer 204 may be an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4. Note that the material for forming the oxide semiconductor layer 204 constituting the transistor Tr of the display device 10 is not limited to the oxide semiconductor having the above composition ratio, and an oxide semiconductor having a composition ratio different from the above composition ratio may be used. For example, the film thickness of the oxide semiconductor layer 204 is 30 nm or more and 110 nm or less, and the film thickness of the oxide semiconductor layer 204 of the display device 10 according to one embodiment of the present invention is 80 nm, which is as thin as the conductive layer 206.

[0104] The transparent conductive layer 212, the pixel electrode 216, and the common electrode 218 can be formed of a transparent conductive film. For example, the transparent conductive film is a mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO). The transparent conductive film may be formed of a material other than the above. The light-shielding layer 219 used in the black matrix BM can be formed of a black resin or a metal material. The black matrix BM is formed in contact with the common electrode 218 (see Figs. 7 and 8). By forming the black matrix BM using a metal material, the common electrode 218 formed of a transparent conductive film and the black matrix BM formed using a metal material can be laminated. As a result, the black matrix BM can have a function as an auxiliary electrode for reducing the electrical resistance loss of the common electrode 218. The metal material forming the black matrix BM can be a material with a reflectance lower than that of aluminum. For example, materials with a reflectance lower than that of aluminum include chromium, molybdenum, and titanium. The black matrix BM may be a single-layer structure using the metal material, or may be a laminate structure using two or more of the metal materials. For example, the thickness of the transparent conductive layer 212 and the thickness of the pixel electrode 216 are 30 nm or more and 80 nm or less, and the thickness of the transparent conductive layer 212 and the thickness of the pixel electrode 216 according to one embodiment of the present invention are 60 nm.

[0105] For example, as described in "Overview of Display Device 10", the material forming the liquid crystal layer 210 is a polymer dispersed liquid crystal. For example, the liquid crystal layer 210 may be formed using a polymer dispersed liquid crystal that has a higher degree of scattering as the potential difference between the potential supplied to each pixel electrode 216 and the potential supplied to the common electrode 218 increases, and the liquid crystal layer 210 may be formed using a polymer dispersed liquid crystal that has a higher degree of scattering as the potential difference between the potential supplied to each pixel electrode 216 and the potential supplied to the common electrode 218 decreases.

[0106] Various configurations of the display device exemplified as one of the embodiments of the present invention can be appropriately combined as long as they are not mutually contradictory. In addition, various configurations of the display device exemplified as one of the embodiments of the present invention can be appropriately replaced as long as they are not mutually contradictory. Display devices in which a person skilled in the art appropriately adds, deletes, or changes the design of components based on the display device disclosed in this specification and the drawings, or adds, omits, or changes conditions of processes, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0107] Even if there are other effects and advantages different from those brought about by the aspects of the embodiments disclosed in this specification, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0108] 10: display device, 12: display area, 14: peripheral area, 15A: first plane, 15B: second plane, 15C: first side, 16: common wiring, 18: common wiring, 22: common wiring area, 24: flexible printed circuit, 26: terminal section, 28: gate drive circuit, 32: gate wiring area, 34: flexible printed circuit, 36: terminal section, 38: source drive circuit, 42: source wiring area, 46: ESD protection circuit, 48: gate inspection circuit, 52: source inspection circuit, 54: inspection line, 56: QD pad, 58: ESD protection circuit, 59: ESD protection circuit, 10 2: display panel, 104: light source, 110: light emission control circuit, 112: display region, 150: array substrate, 150a: first surface, 151A: first transparent substrate, 151B: second transparent substrate, 152: opposing substrate, 152a: first surface, 154: seal material, 160: first metal conductive layer, 161: second metal conductive layer, 162: third metal conductive layer, 202: conductive layer, 202-1: conductive layer, 202-2: conductive layer, 202-3: conductive layer, 202-4: conductive layer, 202-5: conductive layer, 202-6: conductive layer, 202-7: conductive layer, 202-8: conductive layer, 202-9: conductive layer, 203: gate insulating film , 203a: nitride insulating film, 203b: oxide insulating film, 204: oxide semiconductor layer, 204-1: oxide semiconductor layer, 204-2: oxide semiconductor layer, 204-3: oxide semiconductor layer, 204-4: oxide semiconductor layer, 204-5: oxide semiconductor layer, 205: insulating film, 205a: oxide insulating film, 205b: nitride insulating film, 206: conductive layer, 206-1: conductive layer, 206-10: conductive layer, 206-2: conductive layer, 206-3: conductive layer, 206-4: conductive layer, 206-5: conductive layer, 206-6: conductive layer, 206-7: conductive layer, 206-8: conductive layer, 206-9: conductive layer, 207: Planarization film, 208: conductive layer, 208-1: conductive layer, 208-10: conductive layer, 208-2: conductive layer, 208-3: conductive layer, 208-4: conductive layer, 208-5: conductive layer, 208-6: conductive layer, 208-7: conductive layer, 208-8: conductive layer, 208-9: conductive layer, 209: insulating film, 210: liquid crystal layer, 212: transparent conductive layer, 213-1: contact hole, 213-10: contact hole, 213-11: contact hole, 213-12: contact hole, 213-13: contact hole, 213-2: contact hole, 213-3: contact hole,213-4: contact hole, 213-5: contact hole, 213-6: contact hole, 213-7: contact hole, 213-8: contact hole, 213-9: contact hole, 214: conductive layer, 215-1: contact hole, 215-10: contact hole, 215-11: contact hole, 215-12: contact hole, 215-13: contact hole, 215-14: contact hole, 215-15: contact hole, 215-16: contact hole, 215-17: contact hole, 215-18: contact hole, 215-19: contact hole, 215-3: contact hole, 215-4: contact hole, 215-5: contact hole, 215-6: contact hole, 215-7: contact hole, 215-8: contact hole, 215-9: contact hole, 216: pixel electrode, 216-1: pixel electrode, 216-2: pixel electrode, 216-3: pixel electrode, 216-4: pixel electrode, 217-1: contact hole, 217-2: contact hole, 217-3: contact hole, 218: common electrode, 219: light shielding layer, 221: insulating film, 223: opening, 225: opening, 230: opening, 232: opening, 250: area, GL: gate wiring, SL: source wiring, CL: common wiring, CW: capacitance wiring, C: storage capacitance, LE: liquid crystal element, PIX: pixel,

Claims

1. a first pixel including a transistor including an oxide semiconductor layer, a first gate electrode, and a first source electrode; a first gate wiring connected to the first gate electrode and extending in a first direction; a first source wiring connected to the first source electrode and extending in a second direction intersecting the first direction; having the first gate electrode and the first gate wiring include a first conductive layer; the first source electrode includes a second conductive layer; the first source wiring includes a third conductive layer connected to the first source electrode; a thickness of the second conductive layer is thinner than a thickness of the first conductive layer and thinner than a thickness of the third conductive layer; Display device.

2. Further comprising a first substrate; the first conductive layer, the oxide semiconductor layer, the second conductive layer, and the third conductive layer are stacked in this order from the first substrate side along a third direction intersecting the first direction and the second direction; the oxide semiconductor layer overlaps with a part of the first gate electrode and a part of the first gate wiring in a plan view; the first source electrode is in contact with a part of the oxide semiconductor layer in a plan view and overlaps with a part of the first gate electrode and a part of the first gate wiring; The display device according to claim 1 .

3. the second conductive layer has a single layer structure, the third conductive layer includes a first metal conductive layer, which are stacked in order from the second conductive layer along the third direction, a second metal conductive layer provided on and in contact with the first metal conductive layer, and a third metal conductive layer provided on and in contact with the second metal conductive layer. The display device according to claim 2 .

4. a second pixel disposed alongside the first pixel along the second direction; the second pixel includes a second gate line extending in the first direction and a second source line extending in the second direction; the second gate wiring includes the first conductive layer; The second source wiring includes the second conductive layer and the third conductive layer and extends. the second gate wiring extends in the first direction in a plan view and is spaced apart from the first gate wiring in the second direction; the second source wiring is disposed so as to be located parallel to the first source electrode along the second direction in a plan view, and overlaps with the first gate wiring; the first source line overlaps with the second gate line in a plan view; The display device according to claim 2 .

5. In a first region where the second source wiring overlaps with the first gate wiring in a plan view, a second conductive layer in which the second source wiring is provided and a second conductive layer in which the first source electrode is provided overlap with a first conductive layer in which the first gate wiring is provided. The display device according to claim 4.

6. a first insulating film provided between the first conductive layer and the second conductive layer; a second insulating film provided between the second conductive layer, the oxide semiconductor layer, and the third conductive layer; a fourth conductive layer provided on the second insulating film; a third insulating film provided on the fourth conductive layer; a first transparent conductive layer including a pixel electrode included in the first pixel, contacting the third insulating film, and spaced apart from the fourth conductive layer; a second substrate provided opposite to the first substrate; a spacer provided on the second substrate on the first substrate side; Further comprising: the pixel electrode is electrically connected to the oxide semiconductor layer through a first contact hole provided in the third insulating film and a second contact hole provided in the second insulating film; The display device according to claim 5 .

7. the fourth conductive layer includes a first opening provided in a second region overlapping with the first region; The spacer is disposed inside the first opening. The display device according to claim 6.

8. In a plan view, in the first region, the second conductive layer on which the second source wiring is provided is spaced apart from a third conductive layer on which the second source wiring is provided; the spacer overlaps with a second conductive layer in which the second source wiring is provided and a first conductive layer in which the first gate wiring is provided, and is provided apart from the second conductive layer in which the first source electrode is provided and the third conductive layer; The display device according to claim 7.

9. a light-shielding layer provided on the second substrate; a second transparent conductive layer provided in contact with the light-shielding layer; a fourth insulating film provided in contact with the second transparent conductive layer; and the fourth insulating film includes a second opening provided in a third region overlapping the second region; the spacer is disposed inside the second opening in contact with the second transparent conductive layer; The display device according to claim 8.

10. a liquid crystal layer provided between the first substrate and the second substrate; A light source arranged to direct light toward a side surface of the first substrate or a side surface of the second substrate. The display device according to claim 6.

11. the liquid crystal layer includes a polymer dispersed liquid crystal; When the polymer dispersed liquid crystal is in a scattering state, an image is displayed in a display area where the first pixel and the second pixel overlap each other; When the polymer dispersed liquid crystal is in a non-scattering state, in the display area, the background of the second substrate is visible from the first substrate, and the background of the first substrate is visible from the second substrate. The display device according to claim 10.

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