Packaging substrate and manufacturing method of packaging substrate

Abstract

To provide a packaging substrate, a semiconductor package, a manufacturing method of the packaging substrate, and a manufacturing method of the semiconductor package, which improve a misalignment due to a difference of a metal pitch that is generated when embedding a cavity element.SOLUTION: In a packaging substrate, a core layer that contains a glass core having a first surface and a second surface that are opposite each other, and a cavity part that penetrates the glass core is included. In the cavity part, an element module 45 is arranged, and the element module contains: a cavity element 40; and a cavity distribution layer 70 formed at an upper part of the cavity element. The cavity distribution layer contains rewiring distribution circuit layers 70a to 70c and a cavity heat radiation pattern 75. Each rewiring distribution circuit layer contains a cavity bump layer 701 or a via 705, and a circuit layer 703. The cavity radiation pattern transfers heat generated from the cavity element.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] This document relates to a packaging substrate, a semiconductor package, a method for manufacturing a packaging substrate, a method for manufacturing a semiconductor package, and the like. [Background technology]

[0002] In the manufacture of electronic components, the process of forming circuits on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE). This back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, more than 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been fully supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0004] The packaging substrate is made of ceramic or resin. Ceramic substrates such as silicon substrates have high resistance or high dielectric constant, so it is not easy to mount high-performance, high-frequency semiconductor elements on them. Resin substrates can mount relatively high-performance, high-frequency semiconductor elements, but there is a limit to how much the wiring pitch can be reduced.

[0005] Recently, glass substrates can be used as substrates for high-end packaging. By forming through holes in the glass substrate and filling the through holes with conductive materials, the wiring length between the device and the motherboard can be shortened, resulting in excellent electrical characteristics.

[0006] Related prior art includes Korean Patent Publication No. 10-2006-0041009, Korean Registered Patent No. 10-2016019, and Korean Registered Patent No. 10-2411122. Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the embodiment is to provide a packaging substrate and a method for manufacturing the packaging substrate that improve misalignment caused by a difference in pitch of metal that may occur when embedding a cavity element.

[0008] Another object of the embodiment is to provide a packaging substrate and a method for manufacturing the packaging substrate, which can reduce a defect rate that may occur during connection of a package by increasing the pitch of pads formed in a cavity element.

[0009] Another object of the embodiment is to provide a packaging substrate and a method for manufacturing the packaging substrate, which reduce heat generation and electrical loss by shortening the length of an electrical path through embedding a cavity element.

[0010] Another object of the embodiment is to provide a packaging substrate and a method for manufacturing the packaging substrate, which can effectively dissipate heat generated from a cavity element to the outside. [Means for solving the problem]

[0011] One embodiment to achieve the above object relates to a packaging substrate including a core layer.

[0012] The core layer includes a glass core having a first surface and a second surface opposed to each other, and a cavity portion penetrating the glass core.

[0013] An element module is disposed in the cavity portion.

[0014] The element module is a module in which one or more cavity elements and a cavity distribution layer are modularized with an encapsulation layer.

[0015] The cavity distribution layer may be disposed on top of the cavity element.

[0016] The cavity distribution layer may include a redistribution circuit layer and a cavity heat dissipation pattern.

[0017] The redistribution circuit layer can include i) a cavity bump layer, or ii) a via and circuit layer.

[0018] The cavity heat dissipation pattern dissipates heat generated from the cavity element.

[0019] The cavity heat dissipation pattern may include a heat conduction pattern in the form of a stack via.

[0020] The packaging substrate may further include an upper layer that is a redistribution layer disposed on the core layer.

[0021] An upper layer heat dissipation pattern, which is a heat conduction pattern, may be disposed on the upper layer.

[0022] The upper layer heat dissipation pattern may be connected to the cavity heat dissipation pattern.

[0023] The packaging substrate may further include a semiconductor device portion mounted on the upper layer.

[0024] The packaging substrate may further include a heat dissipation module disposed on the upper layer.

[0025] The heat dissipation module may dissipate heat generated from the semiconductor element portion or the cavity element to the outside of the packaging substrate.

[0026] The upper layer heat dissipation pattern may be connected to the heat dissipation module by a thermal conductive pattern.

[0027] The upper layer heat dissipation pattern may include upper heat dissipation traces and upper heat dissipation stack vias.

[0028] The upper heat dissipation trace is a heat conduction pattern that is connected to the cavity heat dissipation pattern or the upper heat dissipation stack via and extends in a surface direction of the glass core.

[0029] The upper heat dissipation stack via is a stack via that is connected to the cavity heat dissipation pattern or the upper heat dissipation trace and extends in the thickness direction of the glass core.

[0030] The upper layer heat dissipation pattern can dissipate heat from within the element module to the outside.

[0031] The cavity distribution layer may include at least two redistribution circuit layers.

[0032] The cavity bump layer is an electrically conductive layer that contacts the upper portion of the cavity element and is capable of transmitting an electrical signal to the cavity element.

[0033] The via and circuit layer is an electrically conductive layer that is connected to the cavity bump layer and transmits an electrical signal to the outside of the device module.

[0034] The glass core may be formed with a core electrical conductive layer, which is a metal circuit pattern disposed on a surface of the glass core.

[0035] The pitch of the redistribution circuit layer may be narrower than the pitch of the core conductive layer.

[0036] The cavity distribution layer may include a first redistribution circuit layer on which the cavity bump layer is disposed, a second redistribution circuit layer in which a first via and a first circuit layer are disposed recessed into a module insulating layer, and a third redistribution circuit layer in which a second via and a second circuit layer are disposed recessed into the module insulating layer.

[0037] The module insulating layer is an insulating layer disposed within the element module.

[0038] The pitch of the second circuit layer may be greater than the pitch of the first circuit layer.

[0039] The cavity element may include an active element.

[0040] Another embodiment of the present invention is a method for manufacturing a packaging substrate.

[0041] The manufacturing method includes a preparation step of preparing a glass core having a cavity portion and an element module, and an arrangement step of arranging the element module in the cavity portion.

[0042] The element module may be one in which one or more cavity elements and a cavity distribution layer are modularized with an encapsulation layer.

[0043] The cavity distribution layer is a redistribution layer disposed on top of the cavity element.

[0044] The cavity distribution layer may include a redistribution circuit layer and a cavity heat dissipation pattern.

[0045] The cavity heat dissipation pattern is a pattern through which heat generated from the cavity element moves.

[0046] The manufacturing method may further include forming an upper layer on the glass core, mounting a semiconductor device part on the upper layer, and disposing a heat dissipation module on the upper layer.

[0047] An upper layer heat dissipation pattern, which is a heat conduction pattern, may be disposed on the upper layer.

[0048] The upper layer heat dissipation pattern thermally connects the cavity heat dissipation pattern and the heat dissipation module.

[0049] The upper layer heat dissipation pattern may include upper heat dissipation traces and upper heat dissipation stack vias.

[0050] The upper heat dissipation trace is a heat conduction pattern that is connected to the cavity heat dissipation pattern or the upper heat dissipation stack via and extends in a surface direction of the glass core.

[0051] The upper heat dissipation stack via is a stack via that is connected to the cavity heat dissipation pattern or the upper heat dissipation trace and extends in the thickness direction of the glass core.

[0052] The upper heat dissipation stack via may have a cross-sectional area that increases as it moves away from the device module.

[0053] The element module may be manufactured by a modularization step.

[0054] The modularization step is a step of disposing a cavity distribution layer on the upper part of the cavity device, and the cavity distribution layer includes a redistribution circuit layer and a cavity heat dissipation pattern.

[0055] The cavity distribution layer or the cavity heat dissipation pattern may be formed by a SAP (Semi Additive Process) method.

[0056] The cavity heat dissipation pattern may be a thermally conductive layer connected from the cavity element to a surface of the element module. Effect of the Invention

[0057] The packaging substrate and the method for manufacturing the packaging substrate according to the embodiment may improve misalignment caused by differences in metal pitch that may occur when embedding a cavity element.

[0058] In addition, the packaging substrate and the method of manufacturing the packaging substrate according to the embodiment may significantly reduce a defect rate that may occur during connection of a package by increasing the pitch of pads formed in a cavity element.

[0059] In addition, the packaging substrate and the method of manufacturing the packaging substrate according to the embodiment may reduce the length of the electrical path by embedding the cavity element, thereby reducing heat generation and electrical loss.

[0060] In addition, the packaging substrate and the method of manufacturing the packaging substrate according to the embodiment may effectively dissipate heat generated from a cavity device to the outside. [Brief description of the drawings]

[0061] [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 1 is a flowchart illustrating a process of forming a core distribution layer in a process of manufacturing a packaging substrate according to an embodiment. [Diagram 5]1 is a flowchart illustrating a process of forming an insulating layer in a process of manufacturing a packaging substrate according to an embodiment. [Figure 6] 1 illustrates an example of a cross-sectional structure of a packaging substrate produced according to an embodiment. [Figure 7] 1 is a conceptual cross-sectional view illustrating a device module according to an embodiment; [Figure 8] 7 is an enlarged cross-sectional view of an element module in the packaging substrate of FIG. 6. [Figure 9] 1 is a cross-sectional flow chart illustrating a semi-additive process (SAP) according to an embodiment. [Figure 10] 13 is an example of a cross-sectional structure of a packaging substrate produced according to another embodiment. BEST MODE FOR CARRYING OUT THEINVENTION

[0062] The following detailed description is provided to facilitate a comprehensive understanding of the method, device and / or system described herein. However, various changes, modifications and equivalents of the method, device and / or system described herein will become apparent after the contents presented in this application are understood. For example, the order of operations described herein is merely exemplary and is not limited to the operations described herein. Except for steps that necessarily proceed in a certain order, the order of operations may be changed depending on the understanding of the contents presented in this application. In addition, the description of known features may be omitted to improve clarity and conciseness after the disclosure of this application is understood. However, the omission of such features and their descriptions is not intended to be an admission of common knowledge.

[0063] The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein, but rather the embodiments described herein are provided to illustrate some of the many possible ways of implementing the methods, apparatus and / or systems described herein that will become apparent after reading the present disclosure.

[0064] As used herein, terms such as "first," "second," and "third" may be used to describe various members, components, regions, layers, or sections, but are not intended to limit these members, components, regions, layers, or sections to these words. Instead, such terms are used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in any embodiment described herein could also be a second member, component, region, layer, or section without departing from the teachings of the embodiment.

[0065] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "bonded" to another element, it may be described as being directly "on," "connected," or "bonded" to the other element, or there may be one or more intervening elements between them. In contrast, when an element is described as being "directly on," "directly connected," or "directly bonded," there may not be any other intervening elements between them. Similarly, expressions such as "between" and "directly between," and "adjacent" and "directly adjacent" may be interpreted as previously described.

[0066] The terms used herein are merely for describing particular examples and are not used to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any one or more combinations of the associated listed items. As used herein, the terms "comprises," "comprises," and "has" specify the presence of stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. As used herein, the use of the term "can" in connection with an example or embodiment (e.g., what the example or embodiment can include or embody) means that there is at least one example or embodiment in which such feature is included or embodied, but not all examples are limited thereto.

[0067] In this application, "B is located on A" means that B is in direct contact with A or that B is disposed on A with another layer or structure therebetween, and therefore should not be construed as B being in direct contact with A.

[0068] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. Terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with their meaning in the context of the prior art and the present invention, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0069] In one or more of the above examples, the term "A and / or B" means "A, B, or A and B."

[0070] In one or more of the above examples, terms such as "first," "second," "A," or "B" are used to distinguish identical terms from one another.

[0071] In one or more of the above instances, the singular forms are to be construed as including the plural forms as well as the singular forms unless specifically stated otherwise.

[0072] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0073] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to and connects the semiconductor elements 32, 34, and 36 to each other.

[0074] The packaging substrate 20 according to an embodiment includes a core layer 22, a top layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 or an element module 45 can be located.

[0075] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0076] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0077] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the core layer.

[0078] The core layer 22 may include a glass substrate 21 including a first region 221 having a first thickness and a second region 222 adjacent to the first region 221 and having a second thickness that is thinner than the first thickness (half cavity) or 0 mm (full cavity), a number of core vias 23 penetrating the glass substrate 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23 and electrically connecting a first surface 213 of the glass substrate 21 to a second surface 214 facing the first surface through the core vias 23. Figures 2 and 3 show a form in which the second region of the glass substrate, called a full cavity, is perforated.

[0079] The second region 222 of the core layer 22 may serve as a cavity structure.

[0080] Within the same area, the glass substrate 21 has a first surface 213 and a second surface 214 opposed to each other, and the two surfaces are generally parallel to each other, so that the glass substrate 21 has a substantially constant thickness throughout.

[0081] An internal space 281 formed by the difference in thickness between the first section 221 and the second section 222 serves to accommodate a cavity element 40 or a part or the whole of the element module 45 .

[0082] The glass substrate 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222, and may be formed at a desired pitch and pattern.

[0083] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a practical limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0084] In the embodiment, to solve this problem, the glass substrate 21 is used as a support for the core layer 22. In addition, by using the glass substrate 21 and the core via 23 formed penetrating the glass substrate 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0085] The glass substrate 21 is preferably a glass substrate used in semiconductors. For example, a borosilicate glass substrate or an alkali-free glass substrate may be used, but is not limited thereto.

[0086] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined region of the glass substrate 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0087] Specifically, the formation of the core via 23 may be achieved by forming a defect (scratch) on the surface of the glass substrate using a method such as a laser, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0088] Based on a unit area (1 cm×1 cm) of the glass substrate 21, the number of the core vias 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0089] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate through a through via, and a core insulating layer 223 that encases the core distribution pattern. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass substrate 21, and connects the upper and lower parts of the glass substrate over a relatively short distance, thereby allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0090] The shape of the cavity portion 28 is not limited and may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like.

[0091] The cavity element 40 may be generally cylindrical, rectangular, or polygonal in shape.

[0092] The cavity portion may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by a process similar to the process of forming the core via 23, and the area and shape of the cavity portion penetrating the glass substrate 21 may be different from those of the core via 23.

[0093] In this embodiment, an insulating layer may be formed in the cavity portion after the cavity element 40 or element module 45 is arranged in the cavity portion. That is, an insulating layer may be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0094] When the cavity element 40 is directly disposed in the cavity portion, a core distribution pattern 241 may be formed to be electrically connected to the cavity element 40. The case where the element module 45 is arranged in the cavity portion will be described later.

[0095] The cavity element 40 may include an active element such as a transistor, or a power transfer element such as a multi-layer ceramic capacitor (MLCC), i.e., a passive element. The cavity element 40 may also include an active element such as a computing element such as a CPU or GPU, or a storage element such as a memory chip.

[0096] As will be described later, the cavity elements may be modularized and inserted.

[0097] When an element such as a transistor that converts electrical signals between the motherboard and the semiconductor element portion to an appropriate level is applied as the cavity element 40, a transistor or the like is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0098] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via can be applied to such power transfer devices, where an electrical conductive layer with low resistance is required.

[0099] Meanwhile, passive elements such as capacitors may be individually inserted and applied as the cavity element 40, or an element group including a number of passive elements embedded between insulating layers (cavity element insulating layers) may be formed with electrodes exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for insulating layers to be positioned sufficiently and reliably in spaces between complex elements.

[0100] On the other hand, when an active element is applied as a cavity element, there are further considerations such as wiring, heat dissipation, etc., which will be described later.

[0101] The glass substrate 21 acts as an intermediate or mediating role connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as paths for transmitting these electrical signals, thereby ensuring smooth signal transmission. The core vias arranged in the first area 221 are referred to as first area core vias to distinguish them from the core vias in the second area 222 described below.

[0102] A top layer 26 is positioned on the first surface 213 .

[0103] The upper layer 26 may include an upper distribution layer and an upper surface connection layer located on the upper distribution layer, and the top surface of the upper layer 26 may be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0104] The upper distribution layer may include an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251 having a predetermined pattern and being an electrically conductive layer at least partially electrically connected to the core distribution layer 24, embedded in the upper insulating layer 253. The upper distribution patterns 251 arranged one above the other may be connected to each other through blind vias 252.

[0105] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0106] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0107] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0108] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, and an unnecessary part of the electrically conductive layer is selectively removed, an insulating layer is formed again on the electrically conductive layer, the unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern can be formed.

[0109] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the fine pattern may have a width and interval of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 2.3 μm. The width and interval may be 1 μm or more (the same applies to the following description of the fine pattern).

[0110] The upper connection layer includes an upper connection pattern 272 located on the upper insulating layer 253, at least a portion of which is electrically connected to the upper distribution pattern 251, and an upper connection electrode 271 electrically connecting the semiconductor element portion 30 and the upper connection pattern 272.

[0111] The upper surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by a method such as plating, and when the upper surface connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by a method such as surface polishing or surface etching.

[0112] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more elements in a small area, facilitate the connection of electrical signals between elements or with the outside, and enable more integrated packaging.

[0113] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0114] The second area 222 has a thinner glass substrate 21 than the first area 221, and the cavity element 40 can be located in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass substrate 21 serve as an electrical connection structure that connects the cavity element 40 to an external element.

[0115] Also, as described above, a cavity portion may be generated in the first area 221, i.e., penetrating the first surface 213 and the second surface 214 of the glass substrate 1, rather than the second area 222, and a cavity element 40 may be arranged in the cavity portion.

[0116] The packaging substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 may be directly connected to a core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, or may be electrically connected to the motherboard 10 via a board connection part 52 such as a solder ball. The core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located under the core layer 22. The element connection part 51 and the board connection part 52 are collectively referred to as a connection part 50.

[0117] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass substrate 21 .

[0118] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. It is understood that this multi-layered structure is applied for at least two reasons. One is that there is a scale problem when directly bonding a fine pattern of a device to a motherboard, and the other is that there is a risk of damage to wiring due to the difference in thermal expansion coefficient during the bonding process or the operation of the semiconductor device. In the embodiment, this problem is solved by applying a glass substrate with a thermal expansion coefficient similar to that of a semiconductor device, and forming a fine pattern with a fine scale sufficient for mounting a device on the first surface of the glass substrate and its upper layer.

[0119] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0120] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0121] First, as shown in (a) of FIG. 4, a glass substrate 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming a core via. The glass substrate may be a glass substrate used for substrates of electronic devices, for example, but is not limited to, an alkali-free glass substrate. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or other methods.

[0122] 4(b), the glass substrate 21a having the defect (groove) 21b is subjected to an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass substrate forms a via in the defective portion, and the surface of the glass substrate 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied, but in consideration of the troublesome process of applying and removing the masking film, the glass substrate having the defect may itself be etched, and in this case, the thickness of the glass substrate having the core via may be somewhat thinner than the thickness of the initial glass substrate.

[0123] Thereafter, a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass substrate as shown in Fig. 4(c) and (d). The electrically conductive layer may be a metal layer typically including, but not limited to, copper metal.

[0124] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface may be poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal may be improved by two methods, a dry method and a wet method.

[0125] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. In forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc., and in this case, the adhesion between the glass and the metal may be improved due to an anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0126] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0127] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0128] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0129] FIG. 5 illustrates a manufacturing step of forming an insulating layer and an upper distribution pattern according to one embodiment.

[0130] As shown in (a) of Fig. 5, the core via may undergo an insulating layer formation step of filling the vacant space with an insulating layer after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be applied in the form of a film, and for example, a method of vacuum laminating an insulating layer in the form of a film may be applied. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the vacant space inside the core via, so that a core insulating layer without the formation of voids can be formed.

[0131] 5(b)-(e) illustrate the top layer fabrication steps.

[0132] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts the glass substrate at least in part, and therefore has sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have a characteristic that satisfies an adhesion test value of 4B or more according to ASTM D3359.

[0133] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer, and in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0134] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0135] The upper connection pattern and the upper connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etching layer of the electrically conductive layer, or a method of selectively forming only the electrically conductive layer without applying an etching method may be applied. The cover layer may be formed by forming openings (not shown) at positions corresponding to the upper connection electrodes to expose the upper connection electrodes and allow them to be directly connected to the element connection parts or terminals of the element.

[0136] Once the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, the lower distribution layer and / or the lower connection layer, and optionally the cover layer 60 can be formed.

[0137] As described above with reference to FIGS. 2 and 3, the cavity part may be filled with a cavity element, and the cavity element may include an active element or a passive element. Meanwhile, fine metal wiring is required for an electrode connected to the active element, and the fine metal wiring may have a difference in size from the metal wiring formed on the glass substrate. As a result, misalignment may occur when the cavity element is embedded due to a difference in size, i.e., pitch, of the metal wiring that must be connected to each other, and a failure may occur when connecting the package. In addition, the cavity element disposed in the internal space of the cavity part may generate heat when driven, and the heat generated by the cavity element may also cause problems in signal transmission.

[0138] Therefore, the present specification proposes an embodiment for preventing misalignment between a fine metal pattern to be connected to an active element and a metal pattern having a pitch difference, and preventing defects caused thereby. The present specification also proposes an embodiment for effectively dissipating heat generated from a cavity element. According to one embodiment of the present specification, it is proposed to form and embed a fine metal pattern to be connected to a cavity element such as an active element in advance on the cavity element such as an active element. In addition, an embodiment is proposed in which a redistribution line is arranged such that the pitch of vias connected to fine metal bumps and the pitch of circuit layers gradually increase as the layer moves away from the active element in order to facilitate connection of bump parts with high density. In addition, an embodiment is proposed in which a heat dissipation pattern is formed on a cavity element using a thermally conductive material for heat dissipation, and the heat dissipation pattern is connected to a heat dissipation lid, a heat dissipation fan, etc.

[0139] Fig. 6 is an example of a cross-sectional structure of a packaging substrate produced according to an embodiment, Fig. 7 is a conceptual diagram illustrating a cross section of a device module according to an embodiment, and Fig. 8 is an enlarged cross-section of the device module in the packaging substrate of Fig. 6. Fig. 10 is an example of a cross-sectional structure of a packaging substrate produced according to another embodiment.

[0140] The package substrate or element module of Figures 6 to 8 are conceptually simplified diagrams for explaining a packaging substrate generated according to an embodiment, and the package substrate of Figure 10 is a conceptually simplified diagram for explaining a packaging substrate with added heat dissipation function of a cavity element, and all of the contents described with reference to Figures 1 to 3 may be applied.

[0141] For example, the packaging substrate may include a glass substrate 21, i.e., a core layer 22 including a glass core, an upper layer 26 arranged on the upper part of the core layer 22, a lower layer 29 optionally arranged on the lower part of the core layer 22, a semiconductor element portion 30 optionally arranged on the upper part of the upper layer 26, and a heat dissipation module 110 optionally arranged on the upper part of the semiconductor element portion 30.

[0142] The semiconductor device unit 30 may include at least one semiconductor device such as a semiconductor die or a High Bandwidth Memory (HBM).

[0143] The semiconductor element portion 30 can be electrically connected to the cavity element 40 disposed in the core layer 22 through the upper layer 26. On the other hand, the semiconductor element portion 30 may be selectively disposed below the lower layer 29.

[0144] The semiconductor device unit 30 may be encapsulated 305 for each semiconductor device and disposed on the core layer 22. Alternatively, the semiconductor device unit 30 may be encapsulated after the semiconductor devices are arranged.

[0145] The heat dissipation module 110 can dissipate heat generated from the semiconductor device unit 30 to the outside. The heat dissipation module 110 can include a cooling fan 111 and / or a heat dissipation lid 113. The heat dissipation lid 113 surrounds at least a portion of the semiconductor device unit and / or the packaging substrate to protect them, and can perform a heat dissipation function in addition to a general lid. The heat dissipation lid may include at least a thermally conductive layer. The heat dissipation lid may be made of a thermally conductive material. For example, a metal material may be used as the thermally conductive material. The metal material may be at least one of copper, nickel, aluminum, gold, and silver, or an alloy including the same. The heat conductive material may be a polymer resin including a filler. For example, the filler may be a metal filler (e.g., the above-mentioned metal material) and / or a carbonaceous filler (e.g., graphene, etc.).

[0146] The thermal conductivity of the thermally conductive material to which a metal material is applied may be 100 W / mK to 1000 W / mK. The thermal conductivity may be 200 W / mK or more. The thermal conductivity may be 300 W / mK or more. The thermal conductivity may be 800 W / mK or less. The thermal conductivity of the thermally conductive material to which a binder resin containing a filler is applied may be 1 W / mK to 30 W / mK. The thermal conductivity may be 3 W / mK or more. The thermal conductivity may be 5 W / mK or more. The thermal conductivity may be 20 W / mK or less. The thermal conductivity may be 10 W / mK or less.

[0147] According to this embodiment, the heat dissipation lid 113 of the heat dissipation module 110 may be connected to the cavity distribution layer 70 of the cavity element 40 via a heat dissipation pattern.

[0148] Although the heat dissipation module 110 is exemplarily described as including a cooling fan 111, it may be embodied as a metal heat dissipation plate or heat dissipation film instead of a cooling fan, and may additionally include a heat dissipation plate or heat dissipation film.

[0149] For example, the core layer 22 may include a glass substrate 21 having a first surface and a second surface facing each other, and may further include a core via penetrating the glass substrate 21. A core electrically conductive layer 63 may be formed on a surface of the glass substrate 21. The core electrically conductive layer 63 is a general term for the core distribution layer 24 and the core distribution pattern 241.

[0150] The core electrically conductive layer 63 may be selectively formed on the inner wall surface of the core via. Also, for example, the cavity portion 28 according to FIG. 6 may be formed penetrating both the first surface and the second surface of the glass substrate 21. Optionally, the core electrically conductive layer 63 may be formed on the inner wall surface of the cavity portion. The element module 45 may be disposed inside the cavity portion 28. The cavity portion 28 may be formed simultaneously through the same formation step as the core via, or may be formed independently after or before the core via is formed.

[0151] The element module 45 includes a cavity element 40 and a distribution layer, a cavity distribution layer 70 , formed on top of the cavity element 40 .

[0152] The element module 45 is a module in which one or more cavity elements 40 and a cavity distribution layer 70 are modularized with an encapsulation layer 48. The cavity distribution layer 70 is a redistribution layer disposed on top of the cavity elements 40 (see FIG. 7).

[0153] The cavity distribution layer 70 includes a cavity heat dissipation pattern 75 for dissipating heat from the cavity element 40. Specifically, the cavity distribution layer 70 transfers heat generated from the cavity element 40 to the outside of the core layer or the outside of the packaging substrate. The cavity distribution layer 70 may include the cavity heat dissipation pattern 75 in which a thermally conductive material is patterned. A detailed description of the thermally conductive material will be omitted since it overlaps with the above description.

[0154] Depending on the embodiment, the cavity element 40 may include an active element. The element module 45 disposed inside the cavity portion 28 according to FIG. 6 may be diced and encapsulated and inserted into the cavity portion 28 after the cavity distribution layer 70 is formed.

[0155] The cavity distribution layer 70 may include two or more or three or more redistribution circuit layers and / or cavity heat dissipation patterns 75. The redistribution circuit layer refers to i) the cavity bump layer 701; or ii) the via 705 and the circuit layer 703 included in the cavity distribution layer.

[0156] The cavity bump layer 701 is an electrically conductive layer that is in contact with the upper portion of the cavity element 40 and can transmit an electrical signal to the cavity element 40 .

[0157] The vias 705 and the circuit layer 703 refer to an electrically conductive layer that is connected to the cavity bump layer 701 and transmits an electrical signal to the outside of the element module 45 .

[0158] The ii) via 705 and circuit layer 703 (single layer) may be connected to the cavity bump layer 701. The ii) via 705 and circuit layer 703 transmit electrical signals to the cavity bump layer 701 and additional vias 705 and circuit layers 703, or to the outside of the core layer 22.

[0159] The ii) via and circuit layer may be arranged in one or more layers in the redistribution circuit layer, or in two or more layers. Also, the ii) via and circuit layer in the cavity distribution layer 70 may be arranged in 15 layers or less, or 10 layers or less.

[0160] 6 to 8 show an example in which a total of three layers are arranged, including one i) cavity bump layer and two ii) via and circuit layers, although two, four, five or more layers may be arranged.

[0161] The cavity distribution layer 70 can include an electrically conductive layer (including a cavity bump layer 701, a via 705, and a circuit layer 703), a cavity heat dissipation pattern 75, and an insulating layer. The insulating layer is called a module insulating layer 720 to distinguish it from the insulating layers of the core layer, the upper layer, or the lower layer. The module insulating layer 720 is an insulating layer disposed within the module.

[0162] The electrically conductive layer may be, for example, a metal layer. The metal layer refers to all metal patterns arranged in a form similar to a circuit pattern. The metal layer includes a metal pattern. The metal layer may include a redistribution circuit layer and a metal pattern that is not a redistribution circuit layer. Exemplarily, the metal layer may include a metal pattern that is not a redistribution circuit layer, such as a ground pattern, a heat dissipation pattern, etc. However, the cavity distribution layer 70 may be distinguished from other metal layers in that the circuit layer of the cavity distribution layer is electrically connected to the cavity element and the circuit of the package substrate (such as a trace present in the RDL).

[0163] As shown in FIG. 7, the cavity distribution layer 70 may include a first redistribution circuit layer 70a, a second redistribution circuit layer 70b, and a third redistribution circuit layer 70c.

[0164] The first rewiring / distribution circuit layer 70a may be a layer on which a cavity bump layer 701 is disposed.

[0165] The second redistribution circuit layer 70b may be a layer in which the via 705 and the circuit layer 703 are recessed into the module insulating layer 720. The via and the circuit layer of the second redistribution circuit layer are referred to as the first via and the first circuit layer, respectively, to distinguish them from the via and the circuit layer of the third redistribution circuit layer.

[0166] The third redistribution circuit layer 70c may be a layer in which the via 705 and the circuit layer 703 are recessed into the module insulating layer 720. The via and the circuit layer of the third redistribution circuit layer are referred to as the second via and the second circuit layer, respectively, to distinguish them from the via and the circuit layer of the second redistribution circuit layer. The via may be a blind via.

[0167] A first redistribution circuit layer 70a, a second redistribution circuit layer 70b, and a third redistribution circuit layer 70c may be stacked one on top of the other. In this case, the cavity bump layer 701 may contact the first via, the first via may contact the first circuit layer, the first circuit layer may contact the second via, and the second via may contact the second circuit layer. An electrical signal may be transmitted to a cavity element disposed in an element module via such a redistribution circuit layer.

[0168] The circuit layer and vias may be disposed in an insulating layer.

[0169] The insulating layers disposed in each of the layers, such as the first redistribution circuit layer 70a, the second redistribution circuit layer 70b, and the third redistribution circuit layer 70c, may be separated from each other, and in some cases, due to circumstances such as the use of the same insulating material, the layers may appear to be integrated without being separated from each other.

[0170] The thickness of the circuit layers (excluding the cavity bump layer) arranged in the first circuit layer and the second circuit layer corresponding to the circuit layer region of the redistribution circuit layer may be 2 μm or more, 3 μm or more, or 4 μm or more, or may be 20 μm or less. The thickness of the insulating layer of each layer in the cavity distribution layer may be 5 μm or more, 7 μm or more, or 10 μm or more. The thickness of the insulating layer of the cavity distribution layer may be 20 μm or less, or 18 μm or less.

[0171] The precision of the redistribution circuit layers formed on the packaging substrate can be expressed by the pitch, which is the distance between the redistribution circuit layers. The narrower the pitch, the finer the pattern formed.

[0172] According to this embodiment, a core conductive layer 63 may be disposed on the glass core.

[0173] The pitch d 1 of the core electrically conductive layer 63 may be greater than the pitch d 2 of the cavity distribution layer 70 formed over the cavity element 40 .

[0174] In the cavity element 40, an electrically conductive layer that is finer than the core layer 22 can be formed.

[0175] For example, the pitch of the pads formed on the cavity element 40 may be smaller than the pitch of the pads formed on the core layer 22. In this case, it is more preferable to apply an active element as the cavity element for efficient signal transmission. Here, the pad refers to an electrically conductive layer formed as the edge of a via at the upper or lower end of the via.

[0176] The pitch of the redistribution circuit layer may be narrower than the pitch of the core conductive layer 63 .

[0177] In the case of a redistribution circuit layer connected to an active element, a fine pitch is required. In this embodiment, a fine metal pattern is formed in the form of a redistribution circuit layer on the active element to prevent misalignment between the core electrical conductive layer 63 formed on the glass substrate 21 and the active element and to make the pitch similar.

[0178] Also, the pitch of the redistribution circuit layers can be wider as the number of layers of the cavity distribution layer 70 increases (further away from the cavity element).

[0179] When the width of the electrically conductive layer of the first redistribution circuit layer 70a is taken as the width of the electrically conductive layer of the second redistribution circuit layer 70b, and the width of the electrically conductive layer of the third redistribution circuit layer 70c is taken as the width of the electrically conductive layer of the first redistribution circuit layer 70a, the width of the electrically conductive layer of the second redistribution circuit layer 70b, and the width of the electrically conductive layer of the third redistribution circuit layer 70c, the higher the number of layers, the greater the width of the metal layer.

[0180] As shown in FIG. 8, when the width of the pad of the first redistribution circuit layer 70a is w1, the width of the pad of the second redistribution circuit layer 70b is w2, and the width of the pad of the third redistribution circuit layer 70c is w3, the width of the metal pad increases as the number of layers increases (w1 <w2<w3)。

[0181] That is, the width of the electrically conductive layer of the cavity distribution layer 70 formed on the cavity element 40 may be increased toward the upper layer, and may ultimately be formed to be similar to the width of the core electrically conductive layer 63 of the glass core. As the pattern width of the electrically conductive layer becomes wider, the pitch of the metal pads may also be increased.

[0182] The second redistribution circuit layer 70b is a single-layer redistribution circuit layer disposed on the cavity element, and the third redistribution circuit layer 70c is a single-layer redistribution circuit layer disposed on the second redistribution circuit layer 70b. The pitch of the third redistribution circuit layer 70c may be wider than the pitch of the second redistribution circuit layer 70b.

[0183] The second redistribution circuit layer 70b is a single-layer redistribution circuit layer disposed on the first redistribution circuit layer 70a. The pitch of the second redistribution circuit layer 70b may be wider than the pitch of the first redistribution circuit layer 70a.

[0184] In this embodiment, when a cavity element requiring a fine bump pitch is embedded in a glass core, a fine electrically conductive layer is formed on the cavity element in advance, and the pitch of the electrically conductive layer is widened to more easily align with pads having a large pitch.

[0185] The cavity heat dissipation pattern 75 may be formed in the form of a stack via as shown in the figure, the manufacturing method of which will be described later.

[0186] The cavity heat dissipation pattern 75 may be connected to the heat dissipation module 110 via an upper layer heat dissipation pattern formed on the upper layer 26. Through this, heat generated from the cavity element 40 may be dissipated to the outside via the heat dissipation module 110.

[0187] The stacked via has a structure in which vias are stacked on top of each other, and may be filled with an electrically conductive material (e.g., copper, aluminum, etc.) for transmitting an electrical signal. In an embodiment, the stacked via of the cavity heat dissipation pattern 75 may be filled with a thermally conductive material to perform a heat dissipation function. Exemplarily, the thermally conductive material may be metal, ceramic, etc., and may be copper, aluminum, etc. The application of the thermally conductive material serves to dissipate heat generated from the cavity element 40 of the cavity distribution layer 70 or the redistribution circuit layer to the outside.

[0188] A thermally conductive material may be disposed on the cavity heat dissipation pattern 75. The thermally conductive material is as described above. Exemplarily, the cavity heat dissipation pattern 75 may be a metal pattern made of copper, and the cavity heat dissipation pattern 75 may be connected to the upper layer heat dissipation pattern of the upper layer 26 to perform a heat dissipation function.

[0189] In addition, in another embodiment, the cavity heat dissipation pattern 75 may be implemented as a metal pattern formed in the redistribution circuit layer, for example, a staggered via, instead of the stacked via. The description of the filling material for filling the via is the same as that described above, so a detailed description will be omitted.

[0190] A top layer 26 may be formed on top of the core layer 22 .

[0191] The pitch of the electrically conductive layer disposed on the lower surface of the upper layer may be greater than the minimum pitch of the redistribution circuit layer. The pitch of the electrically conductive layer disposed on the lower surface of the upper layer may be equal to or greater than the maximum pitch of the redistribution circuit layer. In this case, the electrically conductive layer on the lower surface of the upper layer refers to, for example, a metal layer that transmits an electrical signal, excluding layers that are not intended to transmit electrical signals, such as a ground layer.

[0192] The top layer 26 may include a cavity heat dissipation pattern 75 and a top layer heat dissipation pattern connected to the heat dissipation module 110 .

[0193] The upper layer heat dissipation pattern may include upper heat dissipation traces 261 and upper heat dissipation stack vias 263 .

[0194] The upper heat dissipation trace 261 is a heat conduction pattern that is connected to the cavity heat dissipation pattern 75 or the upper heat dissipation stack via 263 and extends in the surface direction of the glass core 21 .

[0195] The upper heat dissipation stack via 263 is a stack via that is connected to the cavity heat dissipation pattern 75 or the upper heat dissipation trace 261 and extends in the thickness direction of the glass core 21 .

[0196] The upper heat dissipation trace 261 may be made of the same material as the upper distribution pattern 251. In this case, the upper heat dissipation trace 261 may be formed during the formation of the upper distribution pattern 251, thereby improving process efficiency.

[0197] On the other hand, the upper heat dissipation trace 261 may be included in the upper layer 26 but may not be directly connected to the upper distribution pattern 251. Also, the upper heat dissipation trace 261 may be included in the upper layer 26 but may be connected to a heat dissipation module or may be grounded.

[0198] The upper heat dissipation stack via 263 may be made of the same material as the upper distribution pattern 251, and in this case, may be formed in a similar manner to the process of forming the upper distribution pattern 251. Alternatively, the upper heat dissipation stack via 263 may be formed in a manner in which the upper distribution pattern 251 is formed in the upper layer and then the via is opened at once using a laser, drilling, or the like.

[0199] The cavity heat dissipation pattern 75 of the cavity distribution layer 70 may be connected to the heat dissipation module 110 via the upper heat dissipation trace 261 and the upper distribution pattern 251 of the upper layer 26, through which the heat generated from the cavity element 40 may be more easily discharged to the outside.

[0200] On the other hand, if the cavity element 40 can be directly connected to the heat dissipation module 110 without the semiconductor element portion 30, the cavity heat dissipation pattern 75 can also be connected to the upper heat dissipation stack via 263 without going through the upper heat dissipation trace 261 and contact the heat dissipation lid 113.

[0201] Optionally, a lower layer 29 may be formed below the core layer 22 .

[0202] The pitch of the electrically conductive layer disposed on the upper surface of the lower layer 29 may be greater than the minimum pitch of the electrically conductive layer of the redistribution circuit layer. In this case, the electrically conductive layer on the upper surface of the lower layer refers to an electrically conductive layer that transmits an electrical signal, e.g., a metal layer, excluding layers that are not intended to transmit electrical signals, such as a ground layer.

[0203] Meanwhile, the outermost electrically conductive layer included in the cavity distribution layer 70 may be formed during the modular manufacturing process of the element module 45. Also, the outermost electrically conductive layer included in the cavity distribution layer 70 may be formed during the process of forming wiring on the upper layer 26 after the element module 45 is embedded.

[0204] A method for manufacturing the packaging substrate 20 according to an embodiment will be described as follows.

[0205] The method for manufacturing the packaging substrate includes a preparation step of preparing the glass core 21 having the cavity portion 28 and the element module 45, and an arrangement step of arranging the element module 45 in the cavity portion 28.

[0206] The element module 45 includes one or more cavity elements 40 and a cavity distribution layer 70 modularized by an encapsulation layer 48, and includes a cavity heat dissipation pattern 75. As described above, the cavity element 40 may include an active element and may further include a passive element.

[0207] The cavity distribution layer 70 is a redistribution layer disposed on the cavity element 40. The cavity distribution layer 70 may include at least two redistribution circuit layers. The cavity distribution layer 70 may be formed by a process in which a redistribution layer is formed in a semiconductor manufacturing process.

[0208] A detailed description of the cavity distribution layer 70 will be omitted since it overlaps with the above description.

[0209] Also, the cavity distribution layer further includes a cavity heat dissipation pattern for dissipating heat of the cavity element.

[0210] The manufacturing method of the packaging substrate may further include the steps of forming an upper layer 26 on the top of the glass core 21; mounting a semiconductor element part 30 on the upper layer 26; and arranging a heat dissipation module 110 on the upper layer 26.

[0211] An upper layer heat dissipation pattern, which is a heat conduction pattern, may be disposed on the upper layer 26 .

[0212] The upper layer heat dissipation pattern may thermally connect the cavity heat dissipation pattern 75 and the heat dissipation module 110 .

[0213] The upper layer heat dissipation pattern may include upper heat dissipation traces 261 and upper heat dissipation stack vias 263 .

[0214] The upper heat dissipation trace 261 is a heat conduction pattern that is connected to the cavity heat dissipation pattern 75 or the upper heat dissipation stack via 263 and extends in the surface direction of the glass core 21 .

[0215] The upper heat dissipation stack via 263 is a stack via that is connected to the cavity heat dissipation pattern 75 or the upper heat dissipation trace 261 and extends in the thickness direction of the glass core 21 .

[0216] The upper heat dissipation stack via 263 may have a wider cross-sectional area as it is farther away from the device module 45. In this case, it may be more effective in dissipating heat.

[0217] The cross-sectional area means the cross-sectional area in a plane substantially parallel to the surface of the glass core 21 .

[0218] The method for manufacturing the packaging substrate may further include forming a core conductive layer.

[0219] The core conductive layer forming step may occur between the preparing step and the arranging step, or after the arranging step.

[0220] The core conductive layer forming step is a step of forming a core electrically conductive layer on the glass core.

[0221] The pitch of the redistribution circuit layers 70a, 70b, and 70c may be narrower than the pitch of the core conductive layer, and the pitch of the redistribution circuit layers 70a, 70b, and 70c may be wider as the number of the cavity distribution layers increases (as the layers move away from the cavity element).

[0222] The element module may be manufactured by a modularization step.

[0223] The modularization step is a step of disposing a cavity distribution layer 70 on the cavity element 40. After the disposition, a process of modularizing the cavity element 40 and the cavity distribution layer 70 by encapsulating them with an encapsulation layer 48 may be further included.

[0224] The cavity distribution layer 70 may include at least two redistribution circuit layers and a cavity heat dissipation pattern 75 .

[0225] The cavity distribution layer may be formed by a SAP (Semi Additive Process) method.

[0226] The cavity element may be an active element, and the element module may further include a passive element and be molded (encapsulated).

[0227] The method may further include a pre-molding step after the modularization step.

[0228] The cavity elements may be prepared in a pre-diced form and may be diced after forming a cavity distribution layer and then encapsulated. The dicing step is selectively applied when multiple cavity elements are arranged on one substrate.

[0229] The cavity elements may be diced and fixed in position through a pre-molding process, followed by forming a cavity distribution layer and then encapsulating again.

[0230] The method for manufacturing the packaging substrate 20 will now be described in more detail.

[0231] The glass core 21 having the cavity portion 28 and the element module 45 are prepared (preparation step).

[0232] The cavity portion 28 is a space in which the element module 45 is disposed.

[0233] The element module 45 has at least two rewiring distribution circuit layers and / or a cavity distribution layer including a cavity heat dissipation pattern formed on the top of the cavity element 40, which may be prepared in advance through a separate process.

[0234] The cavity distribution layer 70 may be formed by a semi-additive process (SAP) method for fine wiring. SAP is a process of forming a circuit pattern by processing via holes in a substrate in which a metal substrate and an insulating substrate are combined, performing electroless copper plating, and then performing a dry film bonding / exposure / development process and an electrolytic copper plating process.

[0235] SAP is a process used to form extremely fine metal wiring, and the process is illustrated in FIG.

[0236] First, an insulating layer 91 is formed by a method such as lamination, and vias 92 can be created using a laser or the like (FIG. 9(a)). The vias 92 may be for forming a via (blind via) of a rewiring distribution circuit layer. The vias 92 may be for forming a via (stack via) of a cavity heat dissipation pattern. Also, multiple vias 92 may be formed in the same layer for all of these purposes.

[0237] Thereafter, impurities in the vias 92 may be selectively removed, and an adhesive 93 may be applied onto the insulating layer 91 (FIG. 9(b)). That is, impurities in the vias 92 may be removed. Depending on the embodiment, an adhesive for improving adhesion between the metal foil and the insulating layer may not be applied.

[0238] An electrically conductive layer such as electroless copper may be bonded in the form of a thin film on top of the adhesive 93 to form a seed layer 94 (seed metallization, FIG. 9(c)).

[0239] Thereafter, a photoresist such as a dry film is laminated or coated on the seed layer 94, and then exposed to light to form a photoresist layer 95 including a circuit pattern (FIG. 9(d)).

[0240] Next, an electrically conductive layer 96 or a thermally conductive layer can be formed by plating a metal such as copper on the portion from which the dry film photoresist has been removed (FIG. 9(e)). Different materials may be used as the electrically conductive material and the thermally conductive material depending on the respective purposes, as necessary. Alternatively, the same material may be used for both the electrically conductive and thermally conductive properties. In the latter case, the convenience of the process can be improved.

[0241] Finally, the dry film photoresist is removed, and the seed layer is removed by flash etching (Figure 9(f)).

[0242] 9 is repeated, two or more redistribution circuit layers and cavity heat dissipation patterns 75 can be formed on the upper part of the cavity element 40. By generating the RDL by the SAP method, the pitch of the electrically conductive layer (or pad) included in the redistribution circuit layer of the cavity element 40 can be formed narrower than the pitch of the core metal layer. Also, the pitch of the metal layer (or metal pad) included in the redistribution circuit layer can be formed narrower than the pitch of the core metal layer.

[0243] In addition, the pitch of the redistribution circuit layer may be wider as the number of layers of the redistribution circuit layer of the cavity element 40 increases. That is, as shown in Fig. 7, the metal pad of the redistribution circuit layer may be wider as the layer is higher, and the width of the metal pad that is flush with the core conductive layer 63 may be similar to the width of the core metal layer.

[0244] For example, the cavity bump layer 701 (metal terminal of the die) may have a width of 40 μm or more, 45 μm or more, 50 μm or more, or 55 μm or more at the bottom end. The cavity bump layer 701 (metal terminal of the die) may have a width of 80 μm or less, 75 μm or less, 70 μm or less, 65 μm or less, 60 μm or less, or 55 μm or less at the bottom end.

[0245] The width of the electrically conductive layer may increase gradually from the bottom of the distribution layer of the cavity element 40 (the cavity distribution layer) to the bottom metal layer of the upper layer.

[0246] The width of the thermally conductive layer may increase gradually from the bottom of the distribution layer of the cavity element 40 (the cavity distribution layer) to the bottom metal layer of the upper layer.

[0247] The size of the pads applied to the stack structure of thermally conductive layers may be gradually increased from the bottom of the distribution layer (cavity distribution layer) of the cavity element 40 to the bottom metal layer of the upper layer.

[0248] For example, the width of the electrically conductive layer is as described above.

[0249] For example, the width of the thermally conductive layer may be adapted in the same manner as the width of the electrically conductive layer described above.

[0250] For example, the width of the electrically conductive layer on top of the lower layer may be 90 μm or more, 95 μm or more, 100 μm or more, or 105 μm or more. The width of the electrically conductive layer may be 180 μm or less, 175 μm or less, 170 μm or less, 165 μm or less, 160 μm or less, or 155 μm or less.

[0251] For example, the width of the thermally conductive layer may be adapted in the same manner as the width of the electrically conductive layer described above.

[0252] The width of the electrically conductive layer may increase gradually from the bottom of the distribution layer of the cavity element 40 (the cavity distribution layer) to the top electrically conductive layer of the lower layer.

[0253] For example, the width of the thermally conductive layer may be adapted in the same manner as the width of the electrically conductive layer described above.

[0254] When embedding a cavity element 40, which requires a narrow pitch, specifically an active element, misalignment may occur due to differences in metal pitch, and in this embodiment, the pitch of the electrically conductive layer in the wiring layer is gradually enlarged to ensure an alignment margin. This prevents defects that may occur when connecting the cavity element 40 to the core layer 22 and when connecting the semiconductor element to the core layer 22. That is, in this embodiment, a fine RDL is formed in the cavity element 40 beforehand, and then the cavity element 40 is embedded in the core layer 22, thereby overcoming the problem of the pitch size.

[0255] The cavity heat dissipation pattern 75 may be formed in the form of a stack via. A stack via refers to a via in which vias are stacked on top of one another, i.e., vias with the same axis are formed vertically in succession in multiple layers. Such stack vias occupy less space, so they are effective for forming fine vias and are suitable for build-up technology that configures multiple layers in a certain space.

[0256] The cavity heat dissipation pattern 75 may be formed during the formation of the redistribution circuit layer, or may be formed by drilling vias at once after the redistribution circuit layer is formed. The method of forming vias at once may be a laser drill or a mechanical drill. The redistribution circuit layer may be electrically connected to the upper layer heat dissipation pattern formed on the upper layer 26.

[0257] If necessary, a dicing process may be performed after the cavity distribution layer 70 is formed. Dicing is a process of cutting the diced cavity elements and dividing them into chip units. In this case, the redistribution layer may not be substantially embodied in a predetermined scribe lane (a space of an appropriate width designated to be divided without affecting surrounding elements when cutting out chips / dies from a wafer).

[0258] As an example of a dicing method, blade dicing may be applied. When blade dicing is applied, a blade, which is a wheel-shaped saw blade, is used to separate a wafer into chip units, or a substrate strip that has undergone a process can be separated into individual package units. Blade dicing cuts a wafer using a saw blade whose tip is reinforced with diamond powder (grit), and since a work tolerance occurs when the saw blade rotates, the space of the scribe lane must be secured to be thicker than the wheel.

[0259] Other dicing methods include laser dicing and plasma dicing. In blade dicing, the blade physically contacts the wafer, so the required thickness is thin and the wafer is prone to cracking during the process. For this reason, laser dicing was developed. Laser dicing usually cuts the wafer by irradiating a laser from the back side of the wafer. Since the wafer is cut with a laser, no physical impact is applied and it is also suitable for cutting thin wafers. In addition, the strength of the chip can be increased because there is less damage to the cut surface.

[0260] Plasma dicing is the most recently developed dicing method, which uses plasma etching in the Fab process. It is environmentally friendly as it uses a quasi-gas material rather than a liquid, and since it is applied to the entire wafer at once, the singulation speed per chip is faster than other dicing processes.

[0261] Alternatively, after dicing, the cavity elements may be encapsulated through pre-molding. Encapsulation is a process in which semiconductor elements are wrapped in a specific material to protect them from the external environment. Molding, one of the encapsulation methods, is a material made by mixing thermosetting resin with various inorganic materials, called EMC (Epoxy Molding Compound), which is placed over chips and wires to protect them from external physical and chemical impacts, and the size and shape of the package can be adjusted in various ways.

[0262] To protect and package the cavity device before the device module 45 is placed in the cavity portion 28, a pre-molding may be performed prior to final molding.

[0263] In this process, as shown in FIG. 10, passive elements and active elements on which no wiring layer is formed may be encapsulated together.

[0264] Once the element module 45 is selected and placed in the cavity portion 28, an upper layer can be formed on top of the core layer 22, or a lower layer can be formed below the core layer.

[0265] An upper layer heat dissipation pattern, which is a heat conduction pattern, may be disposed on the upper layer 26 .

[0266] The upper layer heat dissipation pattern may be connected to the cavity heat dissipation pattern 75 .

[0267] The upper layer 26 may have an upper heat dissipation trace 261 and an upper heat dissipation stack via 263 formed thereon, which are connected to the cavity heat dissipation pattern 75 and the heat dissipation module 110 .

[0268] The upper layer 26 may include an upper distribution pattern 251, which is an electrically conductive layer (see FIG. 3). The upper heat dissipation traces 261 and the upper heat dissipation stack vias 263 may be formed during or after the formation of the upper distribution pattern 251.

[0269] The upper heat dissipation trace 261 may be connected with the cavity heat dissipation pattern 75 .

[0270] It may be embodied as a part of the upper distribution pattern 251 or as a ground pattern.

[0271] The upper heat dissipation stack via 263 may be formed in the form of a stack via like the cavity heat dissipation pattern 75 .

[0272] The upper heat dissipation stack vias 263 may be formed during the process of forming the upper distribution pattern 251, or may be formed by a method of drilling a via at once after the upper distribution pattern 251 is formed.

[0273] Depending on the embodiment, when the element module 45 is disposed in the cavity portion 28, the remaining space of the cavity portion 28 may be filled with an insulating material. The insulating material may fill the cavity portion 28 through an insulating layer formation process accompanying a process of forming a distribution layer of the upper layer 26 or the lower layer 29.

[0274] As shown in FIG. 10, a semiconductor device section 30 and a heat dissipation module 110 may be disposed on the upper layer 26. As shown in FIG.

[0275] The upper heat dissipation stack vias 263 may be connected to the heat dissipation lid 113. Thus, heat generated from the cavity device 40 may be more easily dissipated to the outside through the cavity heat dissipation pattern 75, the upper heat dissipation traces 261, and the upper heat dissipation stack vias 263.

[0276] In the embodiment, the semiconductor device part 30 is disposed above the cavity device 40, and the heat dissipation module 110 is disposed above the semiconductor device part 30, so that the upper layer heat dissipation pattern formed on the upper layer 26 may have a "└" shape as shown in Fig. 10. Meanwhile, depending on the change in the arrangement, such as when the semiconductor device part is not disposed above the cavity device, or when the heat dissipation module is not disposed above the semiconductor device part, the shape of the upper layer heat dissipation pattern is not limited to that shown in Fig. 10.

[0277] For example, the upper layer heat dissipation pattern may be embodied as a single structure of a heat dissipation trace or stacked via, and is not limited to a specific pattern as long as it has a structure that can connect the cavity heat dissipation pattern formed in the cavity element to the heat dissipation module to dissipate heat.

[0278] FIG. 10 is an example of a cross-sectional structure of a packaging substrate according to another embodiment.

[0279] According to an embodiment, the element module 45 embedded in the cavity portion 28 of the glass core 21 may further include a passive element 40b in addition to the active element 40a.

[0280] The passive elements 40b may be encapsulated together with the active elements when premolded. As shown, the passive elements 40b may not have a cavity distribution layer formed on top of them.

[0281] In another example, if a cavity distribution layer is formed on the passive elements, the passive elements can also be diced after two or more redistribution circuit layers are formed by the SAP method. After dicing, the passive elements and the active elements can be molded together and placed in the cavity portion 28 of the glass substrate 21.

[0282] Also, the device module may include two or more active devices, or may include two or more active devices and a passive device, and may include a plurality of passive devices on which a distribution layer is formed.

[0283] The packaging substrate and the method for manufacturing the packaging substrate according to the embodiments described above can improve misalignment caused by differences in pitch of an electrically conductive layer such as a metal that may occur when embedding a cavity element, and can significantly reduce the rate of defects that may occur when connecting a package by widening the pitch of pads formed in the cavity element. In addition, the embedding of the cavity element can reduce the length of an electrical path, thereby reducing heat generation and electrical loss.

[0284] The above description of the present specification has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present specification is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the accompanying claims also belong to the scope of the embodiments. Therefore, the true technical scope of protection of the present specification must be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0285] 100 Semiconductor device 10 Motherboard 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging Substrate 21, 21a Glass substrate, glass core 22 Core Layer 223 Core insulation layer 213 Page 1 214 2nd page 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26 Upper layer 251 Upper distribution pattern 252 Blind Via 253 Upper insulating layer 271 Top connection electrode 272 Top connection pattern 28 Cavity 281 Interior Space 29 Lower Layer 40 Cavity element 45 element module 70 Cavity distribution layer 48 Capsule Layer 720 module insulation layer 70a 1st rewiring distribution circuit layer 70b 2nd redistribution circuit layer 70c 3rd rewiring distribution circuit layer 705 Via 703 circuit layer 701 Cavity Bump Layer 63 Core Electrically Conductive Layer 40a Active element among cavity elements 40b Passive elements among cavity elements 50 Connection 51 Element connection part 52 Board connection 60 Cover Layer 75 Cavity heat dissipation pattern 110 Heat Dissipation Module 111 Cooling fan 113 Heat dissipation lid 261 Upper heat dissipation trace 263 Top heat dissipation stack via

Claims

1. A packaging substrate including a core layer, The core layer includes a glass core having a first surface and a second surface opposed to each other, and a cavity portion penetrating the glass core, an element module is disposed in the cavity portion; The element module is a module in which one or more cavity elements and a cavity distribution layer are modularized with an encapsulation layer; the cavity distribution layer is disposed on top of the cavity element; The cavity distribution layer includes a redistribution circuit layer and a cavity heat dissipation pattern; the redistribution circuit layer includes i) a cavity bump layer, or ii) a via and circuit layer; The cavity heat dissipation pattern transfers heat generated from the cavity element.

2. The packaging substrate of claim 1 , wherein the cavity heat dissipation pattern comprises a heat conduction pattern in the form of a stack via.

3. The packaging substrate further includes an upper layer that is a redistribution layer disposed on the upper portion of the core layer, An upper layer heat dissipation pattern, which is a thermal conduction pattern, is disposed on the upper layer; The packaging substrate as claimed in claim 1 , wherein the upper layer heat dissipation pattern is connected to the cavity heat dissipation pattern.

4. the packaging substrate further includes a semiconductor device portion mounted on the upper layer, The packaging substrate further includes a heat dissipation module disposed on the upper layer; The packaging substrate according to claim 3 , wherein the heat dissipation module dissipates heat generated from the semiconductor element portion or the cavity element to an outside of the packaging substrate.

5. The packaging substrate of claim 4 , wherein the upper layer heat dissipation pattern is connected to the heat dissipation module by a thermal conductive pattern.

6. the upper layer heat dissipation pattern includes an upper heat dissipation trace and an upper heat dissipation stack via; the upper heat dissipation trace is a thermal conduction pattern connected to the cavity heat dissipation pattern or the upper heat dissipation stack via and extending in a surface direction of the glass core; the upper heat dissipation stack via is a stack via connected to the cavity heat dissipation pattern or the upper heat dissipation trace and extending in a thickness direction of the glass core; The packaging substrate according to claim 3 , wherein the upper layer heat dissipation pattern dissipates heat from within the element module to the outside.

7. The cavity distribution layer includes at least two rewiring distribution circuit layers; the cavity bump layer is an electrically conductive layer that is in contact with an upper portion of the cavity element and is capable of transmitting an electrical signal to the cavity element; The packaging substrate of claim 1 , wherein the via and circuit layer is an electrically conductive layer connected to the cavity bump layer to transmit an electrical signal to the outside of the device module.

8. The glass core is formed with a core electrical conductive layer, which is a metal circuit pattern disposed on a surface of the glass core; The packaging substrate of claim 7 , wherein a pitch of the redistribution circuit layer is narrower than a pitch of the core electrical conductive layer.

9. The cavity distribution layer comprises: a first rewiring / distribution circuit layer on which the cavity bump layer is disposed; a second redistribution circuit layer in which the first via and the first circuit layer are recessed into the module insulating layer; a third redistribution circuit layer, the second via and the second circuit layer being recessed in the module insulating layer; the module insulating layer is an insulating layer disposed within the element module, The packaging substrate according to claim 7 , wherein a pitch of the second circuit layer is larger than a pitch of the first circuit layer.

10. The packaging substrate of claim 1 , wherein the cavity element includes an active element.

11. A method for manufacturing a packaging substrate, comprising: A preparation step of preparing a glass core having a cavity and an element module; and arranging the element module in the cavity portion, The element module is a module in which one or more cavity elements and a cavity distribution layer are modularized with an encapsulation layer; the cavity distribution layer is a redistribution layer disposed on top of the cavity element; The cavity distribution layer includes a redistribution circuit layer and a cavity heat dissipation pattern; The cavity heat dissipation pattern is a pattern through which heat generated from the cavity element moves.

12. forming a top layer on top of the glass core; mounting a semiconductor element portion on the upper layer; and disposing a heat dissipation module on the upper layer. An upper layer heat dissipation pattern, which is a thermal conduction pattern, is disposed on the upper layer; The method for manufacturing a packaging substrate according to claim 11 , wherein the upper layer heat dissipation pattern thermally connects the cavity heat dissipation pattern and the heat dissipation module.

13. the upper layer heat dissipation pattern includes an upper heat dissipation trace and an upper heat dissipation stack via; the upper heat dissipation trace is a thermal conduction pattern connected to the cavity heat dissipation pattern or the upper heat dissipation stack via and extending in a surface direction of the glass core; the upper heat dissipation stack via is a stack via connected to the cavity heat dissipation pattern or the upper heat dissipation trace and extending in a thickness direction of the glass core; The method of claim 12 , wherein the upper heat dissipation stack via has a cross-sectional area that increases with increasing distance from the device module.

14. The element module is manufactured by a modularization step, The modularization step includes: disposing a cavity distribution layer on top of the cavity element; The cavity distribution layer includes a redistribution circuit layer and a cavity heat dissipation pattern; The method of claim 11, wherein the cavity distribution layer or the cavity heat dissipation pattern is formed by a semi-additive process (SAP).

15. The method for manufacturing a packaging substrate according to claim 14 , wherein the cavity heat dissipation pattern is formed by connecting a thermally conductive layer from the cavity element to a surface of the element module.

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