Actuator, liquid discharge head, and actuator manufacturing method
Patent Information
- Application Number
- JP2023189033
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-11-06
- Publication Date
- 2025-05-19
AI Technical Summary
【0010】 本発明によれば、絶縁層により配線が十分に被覆された電気信頼性の高い圧電アクチュエータが提供される。
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Figure 2025077096000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to an actuator, a liquid ejection head, and a method for manufacturing the actuator. [Background technology]
[0002] Piezoelectric films, whose shape changes when an electric field is applied, are used in a variety of industrial products as a means of minutely and precisely moving or vibrating objects. Examples include small speakers, hard disk drives, and printers (liquid ejection devices). Some printers, in particular, use piezoelectric films as the driving elements of their liquid ejection heads, which eject droplets. In these liquid ejection heads, an electric field is applied using electrodes (upper and lower electrodes) that sandwich the piezoelectric film from above and below, driving the piezoelectric film and ejecting droplets. A voltage of several tens of volts is required to sufficiently displace the piezoelectric film, which is a relatively high voltage for a semiconductor device. Meanwhile, the density of ejection ports in liquid ejection heads is becoming increasingly finer to print high-resolution images, and wiring and electrodes with different potentials are densely arranged on the substrates that house the driving elements.
[0003] Liquid ejection heads equipped with piezoelectric film actuators are prone to short circuits between wiring or between wiring and the lower electrode due to creepage effects on the device surface, as well as failures due to wiring corrosion. For this reason, it is important to adequately cover the wiring with an insulating layer (passivation film). However, it is not easy to cover the unevenness on the side of the wiring due to its thickness without causing the insulating layer to fracture. One solution to this problem is to simply increase the thickness of the insulating layer. However, increasing the thickness is undesirable because it can cause distortion of the substrate (wafer) due to film stress and can increase the processing time required for subsequent etching of the insulating layer.
[0004] In response to the above-mentioned problems, Patent Document 1 discloses a configuration for improving the coverage of an insulating layer on wiring in a semiconductor device having a semiconductor film and wiring on a substrate. By tapering the cross-sectional shape of the wiring, the coverage of the insulating layer that contacts and covers the wiring is improved. In Patent Document 1, the wiring is configured as a multilayer structure, and the tapered shape is obtained by further varying the etching process conditions. This requires film-forming equipment and multiple materials to form multiple layers, and management of the formation process for each layer is necessary. Furthermore, the degree of freedom in the materials that can be used to form the wiring may be limited. It is necessary to select a material that can form a desirable tapered shape while satisfying conditions such as adhesion to the underlying film on which the wiring is formed, ease of etching, electrical resistivity, and atomic diffusion rate into the film contacting the wiring. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-032919 Summary of the Invention [Problem to be solved by the invention]
[0006] Another method for forming a tapered cross-sectional shape of a wiring is to tape the end of a resist film used when etching the wiring and then transfer this shape to the area to be etched. However, in order to achieve the desired shape of the tapered portion of the resist film, the resist film material is limited, and the process of patterning the resist film becomes complicated, which can lead to reduced yields. Process control factors for patterning the resist film include the light exposure dose, temperature, exposure time, and control of exhaust and air flow within the exposure device.
[0007] As described above, the method of tapering the cross-sectional shape of the wiring in order to improve the coverage of the insulating layer that contacts and covers the wiring has the problem that material selection and process control tend to become complicated.
[0008] The present invention, which solves the above problems, has an object to provide a piezoelectric actuator having high electrical reliability in which the wiring is sufficiently covered with an insulating layer. [Means for solving the problem]
[0009] The present invention, which solves the above-mentioned problems, is an actuator having a piezoelectric element having a first electrode, a piezoelectric layer, and a second electrode in this order on a substrate, wiring electrically connected to at least one of the first electrode or the second electrode, and an insulating layer arranged to contact and cover the wiring, In the actuator, the thickness of the wiring is smaller than the thickness of the insulating layer in a direction perpendicular to the substrate, and the thickness of the insulating layer is 500 nm or less. [Effects of the Invention]
[0010] According to the present invention, a piezoelectric actuator having high electrical reliability in which the wiring is sufficiently covered with an insulating layer is provided. [Brief explanation of the drawings]
[0011] [Figure 1] 1 is a diagram illustrating an example of a liquid ejection apparatus according to an embodiment of the present invention. [Figure 2] 1A and 1B are diagrams illustrating an example of a liquid ejection head according to the present invention. [Figure 3] 1A and 1B are diagrams illustrating an example of a liquid ejection unit according to the present invention. [Figure 4] FIG. 1 is a cross-sectional view showing an example of an element substrate of the present invention. [Figure 5] 1 is a plan view showing an example of a piezoelectric actuator of the present invention. [Figure 6] 1 is a cross-sectional view showing an example of a piezoelectric actuator of the present invention. [Figure 7] 1 is an enlarged cross-sectional view showing an example of a piezoelectric actuator of the present invention. [Figure 8] 1 is an enlarged cross-sectional view showing an example of a piezoelectric actuator of the present invention. [Figure 9]3A to 3C are diagrams illustrating a part of the manufacturing process of the piezoelectric actuator of the present invention. [Figure 10] 1 is a cross-sectional view showing an example of a piezoelectric actuator of the present invention. [Figure 11] 1 is a cross-sectional view showing an example of a piezoelectric actuator of the present invention. [Figure 12] 1 is a cross-sectional view showing an example of a piezoelectric actuator of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0012] An embodiment of the present invention will be described with reference to the drawings. Components having the same function will be given the same reference numerals, and repeated description may be omitted. The following describes an example in which the present invention is applied to a piezoelectric actuator used in a liquid ejection head provided in a liquid ejection device such as an inkjet printer. However, the present invention is not limited to the embodiment described below, and other modifications, additions, corrections, deletions, and other changes can be made within the scope of those skilled in the art. Any embodiment that achieves the functions and effects of the present invention is within the scope of the present invention.
[0013] (First embodiment) <Configuration of Liquid Ejection Device> FIG. 1 is another diagram showing an example of the configuration of a liquid ejection device. The liquid ejection device shown in FIG. 1 is a one-pass type that records an image by moving the recording medium 1 in one go. This is an example of a liquid ejection device (hereinafter also referred to as the device body) equipped with a liquid ejection head as a full-line head in which element substrates having ejection ports for ejecting liquid are arranged across the entire width of the recording medium 1. The recording medium 1 is transported in the direction of the arrow by transport means 2, and recording is performed by the liquid ejection head 4. The liquid ejection head according to the present invention can be embodied in any form including the example shown in FIG. 1 and FIG. 1A, and is not limited to other forms. FIG. 1 shows a liquid ejection device equipped with eight liquid ejection heads 4 (4Ka, 4Kb, 4Ya, 4Yb, 4Ma, 4Mb, 4Ca, and 4Cb). These eight liquid ejection heads 4 are positioned within the liquid ejection device by reference members.
[0014] As described above, the liquid ejection head of this embodiment is a one-pass, so-called page-wide, head having a length corresponding to the width of the recording medium (the size in the direction perpendicular to the conveyance direction of the recording medium). However, the present invention can also be applied to a so-called serial liquid ejection head in which recording is performed by scanning the liquid ejection head across the recording medium. An example of a serial liquid ejection head is one equipped with one element substrate for black ink and one for color ink. Another example is a liquid ejection head configured to be shorter than the recording medium, in which several element substrates are arranged so that the ejection openings overlap in the ejection opening array direction.
[0015] <Configuration of liquid ejection head> Fig. 2 shows a perspective view of the liquid ejection head 4, and Fig. 3 shows a perspective view of the liquid ejection unit 7. In the liquid ejection head 4 according to this embodiment, a plurality of liquid ejection units 7, each of which includes an element substrate 10 having ejection ports 19 for ejecting liquid, are fixed onto a support member 40. Note that the present invention can also be suitably used in a liquid ejection head configured such that only one liquid ejection unit 7 is fixed onto one support member.
[0016] As shown in Fig. 2, the liquid ejection head 4 has a plurality of liquid ejection units 7 arranged in a staggered pattern. Each liquid ejection unit 7 has approximately 1000 ejection ports 19, enabling recording at 1200 dpi. An electric wiring board 20, such as a flexible wiring board, is connected to the element substrate 10. The electric wiring board 20 is configured to supply energy and electric signals for ejecting liquid to the ejection ports.
[0017] <Flow path configuration of element substrate> 4 is a cross-sectional view showing the flow path configuration of the element substrate 10 according to this embodiment. The element substrate 10 has a flow path substrate 11, an actuator substrate 12, a pressure chamber substrate 13, and an ejection port substrate 14.
[0018] The flow path substrate 11 has a supply port 15 for supplying the liquid to be ejected from the ejection port 19 to the pressure chamber 17, and an outlet 16 for causing the liquid to flow out of the pressure chamber 17. In other words, the flow path substrate 11 is configured to be able to circulate the liquid between the inside and outside of the pressure chamber. The piezoelectric actuator of the present invention can be suitably used even in a liquid ejection head in which the flow path substrate 11 does not have an outlet 16 and does not have a circulation flow path configuration. The flow path substrate 11 may also be configured to supply liquid to the pressure chamber from both the supply port 15 and the outlet 16 in FIG. 4. The flow path substrate 11 in this embodiment is formed, for example, by etching a silicon substrate, but any material and manufacturing method may be used.
[0019] An actuator substrate 12 is bonded to the flow path substrate 11. The actuator substrate 12 has a substrate (substrate 100, see FIG. 6) and a piezoelectric element 110. The detailed configuration of the actuator substrate 12 will be described later, and in FIG. 4, the configurations of the actuator substrate and the piezoelectric actuators described later are simply shown.
[0020] A pressure chamber substrate 13 is bonded to the surface of the actuator substrate 12 opposite to the surface to which the flow path substrate 11 is bonded. Pressure chambers 17 are provided in the pressure chamber substrate 13 so as to correspond to the piezoelectric elements 110. Like the flow path substrate 11, the pressure chamber substrate 13 in this embodiment may be formed by etching a silicon substrate, for example, and may be made of any material and by any manufacturing method.
[0021] An ejection port substrate 14 is bonded to the surface of the pressure chamber substrate 13 opposite to the actuator substrate 12. The ejection port substrate 14 is provided with an ejection port 19. In the liquid ejection unit 7, liquid is supplied to the pressure chamber 17 from the supply port 15, and is ejected from the ejection port 19 by driving the piezoelectric element 110 and deforming the actuator substrate 12.
[0022] A protective layer may be provided to cover the inner walls of the liquid flow paths that communicate from the supply port 15 to the pressure chamber 17, the discharge port 19, and the outflow port 16. By forming a protective layer on the wall surfaces of the flow paths using a material that is more resistant to the liquid to be discharged than the silicon that constitutes the flow path substrate 11, the pressure chamber substrate 13, etc., it is possible to obtain the effect of improving the long-term reliability of the liquid discharge unit 7. When the flow path substrate 11 and the pressure chamber substrate 13 are constituted by a silicon substrate, for example, SiO2, SiC, Al2O3, HfO2, TaO, DLC (diamond-like carbon), etc. can be used for the protective layer.
[0023] <Configuration of Piezoelectric Actuator> Next, the actuator substrate 12, which is a piezoelectric actuator, will be described in detail. Note that the components described in the following embodiments are merely examples, and are not intended to limit the scope of the present invention to those components.
[0024] Liquid ejection heads often employ a structure in which multiple piezoelectric elements are arranged in an array. Furthermore, to achieve high-resolution printing, the piezoelectric elements are arranged densely on the substrate. FIG. 5 is a partial plan view of the actuator substrate 12 of this embodiment, viewed from the side that is bonded to the flow path substrate 11, and shows two rows of piezoelectric elements 110. Note that in FIG. 5, insulating layers and protective layers, which will be described later, are omitted to make it easier to understand the arrangement of the piezoelectric elements and wiring.
[0025] An upper wiring (second wiring) 140 and a lower wiring (first wiring) 150 are connected to each piezoelectric element 110, and pads 170 and 180 are connected to apply a voltage to the piezoelectric element 110. Note that the pad in this disclosure is an area that is electrically connected to the wiring (upper wiring 140 or lower wiring 150), the surface of which is not covered with a passivation film described below, and is a portion that is connected to an electrical wiring board (such as an FPC) outside the piezoelectric actuator by a wire or the like.
[0026] Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. As shown in Fig. 6, in this embodiment, the actuator substrate 12 has a piezoelectric element 110 in which a lower electrode (first electrode) 111, a piezoelectric layer 112, and an upper electrode (second electrode) 113 are formed in this order on a substrate 100. The piezoelectric element 110 of this embodiment includes a first protective layer 120 formed to cover the lower electrode 111, the piezoelectric layer 112, and the upper electrode 113, a second protective layer 130 formed thereon to cover the first protective layer 120 at a position overlapping at least the lower wiring 150 or the upper wiring 140, and an insulating layer 160 formed thereon as a third protective layer to cover at least the upper wiring 140 and the lower wiring 150.
[0027] The liquid ejection head 4 has pressure chambers 17 (see Figure 4) on the surface of the substrate 100 opposite to the surface on which the piezoelectric elements 110 are arranged, and the piezoelectric layer 112 is arranged so as to overlap the pressure chambers 17 in a direction perpendicular to the surface of the substrate 100.
[0028] The substrate 100 preferably has a flat surface, and the material can be selected appropriately. Suitable materials include silicon, silicon carbide, quartz, gallium nitride, gallium arsenide, indium phosphide, and sapphire. To facilitate the formation of the pressure chambers 17, an SOI (Silicon-On-Insulator) substrate can be used as both the substrate 100 and the pressure chamber substrate 13. An SOI substrate generally has a layered structure in which a silicon oxide layer (BOX layer) is formed on a silicon substrate, and a silicon layer is further formed on that. For example, in an SOI substrate, the thicker silicon substrate can serve as the pressure chamber substrate 13, and the thinner silicon substrate and the BOX layer can serve as the substrate 100. The BOX layer can be formed to a thickness between several tens of nanometers and several hundred micrometers, and the thickness of the silicon layer on top of it can also be selected relatively freely. By appropriately combining these thicknesses and performing selective etching using the BOX layer as an etching stop layer, only the silicon can be removed. When the pressure chamber 17 is formed by such etching, the bottom of the pressure chamber 17 becomes the surface of the BOX layer, so that it is possible to obtain an extremely flat bottom.
[0029] When the substrate 100 is conductive, for example, by being formed of a silicon substrate, it is preferable to have an insulating layer 101 between the lower electrode 111 and the substrate 100. The insulating layer 101 can be made of a general insulating material such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film.
[0030] The lower electrode 111 may be exposed to temperatures of several hundred degrees Celsius during subsequent firing processes for the piezoelectric layer, and is therefore preferably made of a material with a high melting point. Examples include copper, platinum, gold, chromium, cobalt, titanium, and alloys thereof. Furthermore, if the piezoelectric layer 112 is formed in contact with the surface of the lower electrode 111, the lower electrode 111 may also serve as a film for controlling the crystal orientation of the piezoelectric layer 112. In this case, a material having an appropriate crystal structure may be selected for the lower electrode 111. For example, if lead zirconate titanate (PZT) is used for the piezoelectric layer 112, platinum may be used as the lower electrode, which also serves as a crystal orientation control film. Platinum can be deposited using a common deposition method such as magnetron sputtering, and the film thickness is adjusted appropriately to achieve the desired orientation. Furthermore, to improve adhesion between the lower electrode 111 and the insulating layer 101, which serves as the base film, a thin film of titanium, chromium, or the like may be further provided as an adhesion layer. In this case, it is preferable to appropriately select an adhesive layer having an appropriate crystal structure so that the desired crystal orientation of the piezoelectric layer 112 can be obtained.
[0031] Examples of materials suitable for the piezoelectric layer 112 include oxides primarily composed of lithium and niobium or lithium and tantalum (such as lithium niobate and lithium tantalate), oxides primarily composed of lead and titanium (such as lead titanate), oxides to which zirconium has been added (such as lead zirconate titanate), oxides primarily composed of lead and niobium, oxides primarily composed of barium and titanium (such as barium titanate), inorganic materials such as zinc oxide, quartz, and aluminum nitride, and organic materials such as polylactic acid and polyvinylidene fluoride. Among these, lead zirconate titanate (PZT), an oxide primarily composed of lead, zirconium, and titanium, is preferred for its high displacement efficiency. The thickness of the piezoelectric layer 112 is determined by the applied voltage and piezoelectric characteristics required to achieve the desired displacement, and is generally approximately 1 to 2 μm.
[0032] The upper electrode 113 is formed on the piezoelectric layer 112 and may be made of, for example, platinum, titanium, tungsten, or an alloy thereof. As with the lower electrode 111, in order to improve the adhesion between the upper electrode 113 and the piezoelectric layer 112, a thin film of titanium, chromium, or the like may be provided between the upper electrode 113 and the piezoelectric layer 112 as an adhesion layer.
[0033] To apply a desired voltage between the lower electrode 111 and the upper electrode 113 and displace the piezoelectric layer 112, the lower electrode 111 is electrically connected to the lower wiring 150, and the upper electrode 113 is electrically connected to the upper wiring 140. This allows a potential difference to be applied to the piezoelectric layer 112 in response to an externally transmitted electrical signal. The upper wiring 140 and the lower wiring 150 may be made of the same or different materials. While any conductive material may be used for the upper wiring 140 and the lower wiring 150, it is preferable to use a material with low electrical resistance to reduce the probability of wire breakage due to electromigration. Examples of such materials include aluminum, copper, and gold. Furthermore, alloys made of two or more of these elements may also be used. Furthermore, to improve the adhesion of the wiring, a titanium or chromium film may be provided between the lower wiring 150 or the upper wiring 140 and the film in contact with the lower wiring 150 or the upper wiring 140.
[0034] In this embodiment, a silicon oxide film is formed as the insulating layer 130 between the lower wiring 150 and the lower electrode 111, and between the upper wiring 140 and the lower electrode 111 and the piezoelectric layer 112. Note that the silicon oxide film is just an example, and the insulating layer 130 can be made of a suitable material selected from common insulating materials such as silicon nitride, silicon oxynitride, and aluminum oxide, similar to the insulating layer 101. The insulating layer 130 may also be a laminated film in which two or more different types of films are stacked. The insulating layer 130 can be formed by a common film formation method such as chemical vapor deposition (CVD) or sputtering. In this embodiment, the silicon oxide film is formed as the insulating layer 130 by CVD because of its excellent production rate.
[0035] In the piezoelectric element 110 used in a liquid ejection head, a relatively large potential difference is applied between the upper electrode 113 or upper wiring 140 and the lower electrode 111 or lower wiring 150 to sufficiently displace the piezoelectric layer 112, as compared to a semiconductor device. To achieve sufficient displacement, a potential difference of approximately 30 V or more is applied to the piezoelectric layer 112 in the film thickness direction. When the insulating layer 130 is a silicon oxide film formed by CVD, its dielectric breakdown strength is approximately 7 MV / cm. Therefore, to achieve a dielectric strength of, for example, 50 V, the insulating layer 130 should have a thickness of 72 nm or more to reduce the probability of failure. Furthermore, the insulating layer 130 also serves as a moisture-proof film for the layer below it (the protective layer 120, described below). To ensure moisture resistance for the silicon oxide film substrate, a thickness of 200 nm or more is preferable. However, since a too large thickness reduces the displacement characteristics of the piezoelectric element, the insulating layer 130 preferably has a thickness of 1.5 μm or less. That is, the thickness of the insulating layer 130 is preferably 200 nm or more and 1.5 μm or less.
[0036] Furthermore, in order to improve the adhesion of the insulating layer 130, a thin film of titanium, chromium, or the like may be disposed between the insulating layer 130 and the upper wiring 140, and between the insulating layer 130 and the lower wiring 150 (not shown).
[0037] During the formation of the silicon oxide film serving as the insulating layer 130, the piezoelectric layer 112 may be damaged, resulting in deterioration of its piezoelectric properties. Therefore, in this embodiment, an aluminum oxide film serving as the protective layer 120 is formed on the surface of the piezoelectric layer 112 as a protective layer to prevent damage to the piezoelectric layer 112. However, the surface of aluminum oxide deteriorates when exposed to moisture at high temperatures. During the manufacturing process, if the contact holes 131 and 132 (described below) or the upper wiring 140 and the lower wiring 150 are formed while the aluminum oxide is exposed on the outermost surface, the surface of the aluminum oxide film may be exposed to moisture during cleaning after patterning. The moisture remaining on the surface of the aluminum oxide film may deteriorate due to high temperatures during etching or ashing. The presence of an altered aluminum oxide film on the piezoelectric layer may lead to a decrease in insulation resistance and may cause malfunctions. Therefore, it is desirable that the silicon oxide film serving as the insulating layer 130 be formed in contact with and cover the aluminum oxide film serving as the protective layer 120.
[0038] The thickness of the protective layer 120 is preferably the minimum necessary thickness from the viewpoints of minimizing the effect on the displacement characteristics of the piezoelectric element and of contact hole formation. Specifically, the thickness is preferably 50 nm or less, and more preferably 25 nm or less. Furthermore, to obtain a dielectric strength voltage of, for example, 50 V or more, the thickness of the aluminum oxide film 120 is preferably 5 nm or more, taking into consideration step coverage of the piezoelectric layer 112, which has a thickness on the order of μm. That is, the thickness of the first protective layer 120 is preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. Similarly, from the viewpoint of step coverage of the piezoelectric layer 112, when an aluminum oxide film is used for the protective layer 120, it is preferably formed by atomic layer deposition (ALD).
[0039] In addition, in this embodiment shown in Figure 6, the protective layer 120 and the insulating layer 130 have a contact hole 131 for connecting the lower electrode 111 and the lower wiring 150, and a contact hole 132 for connecting the upper electrode 113 and the upper wiring 140.
[0040] As described above, a relatively high voltage is applied to a piezoelectric actuator used in a liquid ejection head to obtain a sufficient displacement to eject liquid. Furthermore, when ejection ports are densely arranged, the surface density of the piezoelectric elements 110 on the element substrate 100 is high. Under these conditions, and in the humid environment in which ink is ejected, current can flow through the surface of the piezoelectric actuator, potentially leading to failure. For piezoelectric actuators used in liquid ejection heads for ejecting liquids such as ink, the presence of liquid has a particularly significant impact on the piezoelectric actuator. For this reason, the upper wiring 140 and the lower wiring 150 are covered with an insulating layer 160, which serves as a passivation film with high moisture resistance and insulation. The insulating layer 160 can be made of silicon oxide, silicon nitride, silicon oxynitride, or the like. In particular, a passivation film partially containing silicon nitride has higher moisture resistance than a silicon oxide film, and can achieve sufficient moisture resistance and insulation even with a thinner film than a silicon oxide film, making it preferable because it is less likely to adversely affect the displacement characteristics of the piezoelectric actuator. Furthermore, the insulating layer 160 preferably has higher moisture resistance than the second protective layer 130. The moisture resistance of the two layers can be compared using a commonly used moisture resistance evaluation method such as the moisture penetration evaluation described above.
[0041] From the viewpoint of insulation, it is desirable that the insulating layer 160 be disposed so as to cover at least the lower wiring 150, the upper wiring 140, and the periphery of the piezoelectric layer 112 when viewed perpendicularly to the substrate 100. The thickness of the insulating layer 160 is preferably the minimum necessary thickness in terms of minimizing the effect on the displacement characteristics of the piezoelectric element and of contact hole formation. On the other hand, in the piezoelectric actuator of this embodiment, the piezoelectric layer is backfilled with an insulating layer or the like to prevent impairment of the displacement characteristics, and the upper and lower wirings formed thereon cannot be planarized by a chemical mechanical polishing (CMP) method or the like. Therefore, the shapes of the upper wiring 140 and the lower wiring 150 inherit the step shape caused by the piezoelectric element 110, and therefore the thickness of the insulating layer 160 must be determined taking into account the step coverage of the piezoelectric layer 112 and the upper and lower wirings. The preferred thickness of the second protective layer, which provides good wiring coverage, will be described later. In order to obtain sufficient insulation resistance in a piezoelectric actuator to which a high voltage of several tens of volts is applied, the thickness of the insulating layer 160 is preferably 100 nm or more.
[0042] In the piezoelectric actuator for a liquid ejection head of this embodiment, as shown in FIG. 5, the lower electrode 111, lower wiring 150, and upper wiring 140 are densely arranged. Specifically, as an example, eight linear rows of piezoelectric elements 110 are arranged at 150 dpi, i.e., approximately 169 μm intervals. FIG. 7 shows a schematic cross-sectional view taken along line VIII-VIII in FIG. 5. As shown in FIGS. 5 and 7, the upper wiring 140 and lower wiring 150 are alternately arranged at narrow intervals. Therefore, when a high voltage of several tens of volts is applied to the actuator, if the insulating layer 160 covering the wiring (upper wiring 140 and lower wiring 150) and the piezoelectric elements 110 does not provide sufficient coverage, or if moisture is present on the actuator surface, short circuits or corrosion of the wiring may occur between the wiring or between the wiring and the lower electrode due to the creeping effect. Therefore, one way to ensure sufficient coverage of the wiring with the insulating layer 160 is to make the insulating layer 160 thicker than the wiring. However, if the wiring is thick (its length in the direction perpendicular to the substrate 100), it may be difficult to form an insulating layer thicker than the wiring. Specifically, ALD, which is a film formation method with high coverage, has a slow film formation rate and may not be suitable for forming an insulating layer with a thickness of several hundred nanometers to several micrometers. In addition, if the insulating layer is too thick, the displacement characteristics of the piezoelectric element may be reduced. For the above reasons, the thickness of the insulating layer 160 is preferably 500 nm or less, and more preferably 200 nm or less. Therefore, in order to make it easier to sufficiently cover the wiring with the insulating layer 160 and to make the thickness of the insulating layer 160 greater than the thickness of the wiring, it is preferable to thin the wiring rather than thicken the insulating layer 160.
[0043] In view of the above problem, the inventors have investigated ways to reduce the thickness of the wiring. First, when viewed from a direction perpendicular to the surface of the substrate, the effective electrode area, which is the area where the upper electrode and the lower electrode overlap, is approximately 0.05 mm 2 When a voltage of 40 V rms and 100 kHz frequency was applied to the element, the current flowing through the wiring was less than 1 μA. Based on this value, wiring with several cross-sectional areas was fabricated and durability tests were carried out. As a result, the cross-sectional area of the wiring was 165 nm 2It was found that a sufficient lifespan was achieved if the cross-sectional area of the wiring was 165 nm or more. 2 When the thickness is smaller than this, disconnection that is thought to be due to electromigration is confirmed. Therefore, it was found that the wiring (upper wiring 140 and lower wiring 150) can be used as a piezoelectric actuator even if it is thin enough to maintain the film shape, that is, to the extent that it does not become island-like. The film thickness of the wiring that does not become island-like depends particularly on the material and film formation method of the film adjacent to it below, so if you want to make the wiring film as thin as possible, it is preferable to check after the process has been confirmed.
[0044] Regarding the upper limit of the thickness of the wiring, the thickness of the wiring is set to be smaller than the thickness of the insulating layer 160, but it has been found that the wiring is more likely to be sufficiently covered by the insulating layer 160 by setting the thickness to 200 nm or less, more preferably 100 nm.
[0045] In view of the above, the piezoelectric actuator of this embodiment has, as an example, a 200 nm thick silicon nitride film as the insulating layer 160 so as to sufficiently cover the 2 μm thick piezoelectric layer 112 and the 100 nm thick lower wiring 150 and upper wiring 140 .
[0046] The wiring (upper wiring 140 and lower wiring 150) and the insulating layer 160 have approximately the same thickness within the area formed on a uniform plane. FIG. 8 shows an enlarged cross-sectional view of the wiring (lower wiring 150) in the short direction. Note that although FIG. 8 shows the lower wiring 150, the same applies to the upper wiring 140. In the present disclosure, the thickness of the insulating layer 160 is d in FIG. p The thickness is shown as d , which indicates the film thickness in the region where the wiring is laminated on the flat insulating layer 130. In a region where the wiring has a sufficient width and length, the film thickness of the insulating layer 160 formed on the top surface of the wiring is also approximately d p In this disclosure, the thickness of the wiring is d w When the insulating layer 130 is flat, the thickness is approximately the same up to the wiring end. wHowever, when the thickness of the wiring is not uniform, the distance between the upper surface and the lower surface of the wiring at the end in the short direction of the wiring is defined as the wiring thickness d w In addition, at the connection portion between the wiring and the electrode (the connection portion between the upper wiring 140 and the upper electrode 113, and the connection portion between the lower wiring 150 and the lower electrode 111), the wiring is formed through a contact hole that penetrates the insulating layer 130 and the protective layer 120 disposed therebetween, and in this disclosure, the film thickness of the wiring near the contact hole indicates the length from the upper surface of the insulating layer 130 to the upper surface of the wiring.
[0047] Furthermore, in order to provide sufficient coverage to the insulating layer 160 even in a configuration in which the thickness of the wiring is not uniform depending on the location, such as when wiring is formed along the end face of the piezoelectric layer 112, it is preferable that the thickness of the wiring (upper wiring 140 or lower wiring 150) in the direction perpendicular to the substrate 100 at any location in the piezoelectric actuator is smaller than that of the insulating layer 160. Note that when the insulating layer 160 has a laminated structure made up of multiple layers, the thickness of all of the multiple laminated layers can be considered to be the thickness of the insulating layer 160.
[0048] <Manufacturing method of piezoelectric actuator> With reference to the drawings, a method for manufacturing a piezoelectric actuator having the structure shown in Fig. 6 will be described. First, as shown in Fig. 9(a), a silicon substrate 100 is prepared, and a silicon thermal oxide film with a thickness of about 500 nm is formed as an insulating layer 101 by wet oxidation using oxygen and hydrogen gas.
[0049] Next, as shown in FIG. 9(b), a lower electrode 111, a piezoelectric layer 112, and an upper electrode 113 are formed on the insulating layer 101 in this order.
[0050] The lower electrode 111 can be formed by, for example, a sputtering method. When the material of the piezoelectric layer 112 is lead zirconate titanate (PZT), it is preferable to use platinum for the lower electrode 111, which also serves as a crystal orientation control film. In this embodiment, as an example, platinum is formed to a film thickness of about 100 nm. A thin film of titanium, chromium, or the like may be formed as an adhesion layer to improve adhesion between the lower electrode 111 and the insulating layer 101.
[0051] The piezoelectric layer 112 is formed by a sol-gel method, in which a starting material such as a sol-gel liquid is applied onto the lower electrode 111 and then fired to achieve a desired crystal orientation. In this embodiment, as an example, a PZT film with a thickness of 2 μm is formed.
[0052] Subsequently, the upper electrode 113 is formed by sputtering etc. In this embodiment, as an example, an alloy film of titanium and tungsten with a thickness of about 100 nm is formed.
[0053] Next, a resist pattern (not shown) is formed by photolithography so that the upper electrode 113 and the piezoelectric layer 112 have a desired pattern, and then the upper electrode 113 and the piezoelectric layer 112 are patterned by etching as shown in FIG. 9(c).
[0054] Next, a resist pattern (not shown) is formed by photolithography so that the lower electrode 111 has a desired pattern, and then the lower electrode 111 is patterned by etching as shown in Fig. 9(d) Through the above steps, a piezoelectric element 110 having the lower electrode 111, the piezoelectric layer 112, and the upper electrode 113 is formed.
[0055] 9(e), an aluminum oxide film is formed as a protective layer 120 so as to cover at least the upper surface 110a and side surface 110b of the piezoelectric element 110, the lower electrode 111, and the upper electrode 113. In this embodiment, ALD is used as the film formation method, and the film thickness is 23 nm.
[0056] 9(f), a silicon oxide film is formed as the insulating layer 130 so as to cover the protective layer 120. In this embodiment, the film thickness is 400 nm, for example.
[0057] 9(g), the upper through-hole 132 and the lower through-hole 131 are formed by photolithography. After a resist pattern (not shown) for forming through-holes that will serve as contact holes in the protective layer 120 and the insulating layer 130 is formed on the insulating layer 130, etching is performed to form the upper through-hole 132 and the lower through-hole 131.
[0058] Next, wiring is formed using a typical semiconductor process. A wiring layer that will become the upper wiring 140 and the lower wiring 150 is formed on the insulating layer 130 by sputtering. In this embodiment, a titanium film (not shown) is formed as an adhesion layer on the surface of the insulating layer 130 by sputtering or vapor deposition, and an aluminum-copper alloy film is formed as the wiring layer on the titanium film. After this, the titanium film and wiring layer are patterned by photolithography using a resist pattern to form the upper wiring 140 and the lower wiring 150 as shown in FIG. 9(h). Dry etching is preferably used for etching the wiring layer, but wet etching may also be used. Specifically, in this embodiment, the thickness of the wiring (upper wiring 140 and lower wiring 150) is 30 nm, and the width (length in the short direction) is 5 μm.
[0059] Next, as shown in FIG. 9(i), a silicon nitride film is formed as the insulating layer 160 so as to cover the upper wiring 140 and the lower wiring 150. The silicon nitride film has higher moisture resistance than the silicon oxide film that forms the insulating layer 130 and is therefore suitable as an insulating layer. In this embodiment, the film thickness is 200 nm, for example. The method for forming the insulating layer 160 is preferably one that provides good coverage to the wiring and has a fast film formation rate, and CVD, for example, is suitable. When the wiring is thin, sputtering or vapor deposition may be used, as the insulating layer 160 can easily cover the wiring and the coverage constraints are reduced. The actuator substrate 12 serving as a piezoelectric actuator is formed by etching the insulating layer 160 into a desired pattern using a photolithography method using a resist pattern.
[0060] Thereafter, a pressure chamber substrate 13 and an ejection port substrate 14 having pressure chambers and ejection ports, and a flow path substrate 11 having a flow path for supplying liquid to the pressure chambers are prepared, and then bonded to an actuator substrate 12 to form a liquid ejection head (see Figure 4).
[0061] In the following embodiment, differences from the first embodiment will be mainly described, and descriptions of parts similar to those in the above-described configuration will be omitted.
[0062] (Second embodiment) In this embodiment, the thickness of the wiring is even thinner than in the first embodiment. The film thickness of the upper wiring 140 and the lower wiring 150 is set to 5 nm, and the other structures are the same as those in the first example. By making the film thickness of the wiring extremely thin in this way, the coverage by the insulating layer 160 is further improved. However, if the film thickness of the piezoelectric layer 112 is thick, a part of the upper wiring 140 formed along the end face of the piezoelectric layer 112 may be affected by unevenness on the end face of the piezoelectric layer 112, and the upper wiring 140 may be broken.
[0063] In this embodiment, ALD is used to form a wiring film that will become the wiring, as a method for preventing disconnection of the thin upper wiring 140. In this case, any material that can be formed by ALD can be used as the wiring material. As an example, the upper wiring 140 and lower wiring 150, which are the wiring layers in this embodiment, are made of Cu with a thickness of 5 nm. For wiring with a very thin thickness, a laminated film in which multiple layers are stacked may be used. For example, a laminated film in which titanium with a thickness of 3 nm and tungsten with a thickness of 2 nm are successively deposited may be used as the upper wiring and lower wiring.
[0064] (Third embodiment) The piezoelectric element of the present disclosure has a piezoelectric layer sandwiched between two electrodes. In many cases, the electrodes and the piezoelectric layer are thin films. Furthermore, the thickness of each film is generally uniform and can be adjusted to the desired size by etching or other processes. As a result, their end faces are generally perpendicular to the film surface. Furthermore, as shown in FIG. 6 , when the upper wiring 140 and the lower wiring 150 are aligned in the direction perpendicular to the substrate 100, at least one of the two wirings connected to the piezoelectric element 110, like the upper wiring 140 in FIG. 6 , is formed along the end face of the piezoelectric layer 112. In this case, when wiring is formed by a typical film formation method, i.e., sputtering or vapor deposition, the thickness of the wiring near the end face of the piezoelectric layer 112 may be thin, making the wiring more susceptible to breakage. Disconnection is particularly likely when the surface of the end face of the piezoelectric layer 112 is significantly uneven. One method for preventing disconnection of the wiring at the end face 112b of the piezoelectric layer is to use ALD to form the wiring, as shown in the second embodiment. As another method for preventing the wiring from breaking, in this embodiment, the wiring is not formed along the end surface 112b of the piezoelectric layer, thereby preventing the occurrence of wire breakage.
[0065] FIG. 10 is a cross-sectional view showing the structure of the piezoelectric actuator of this embodiment. In the direction perpendicular to the substrate 100, the upper wiring 140 and the lower wiring 150 are located on different layers. Therefore, the upper wiring 140 is not formed along the end surface 112b of the piezoelectric layer 112, but is formed vertically above the piezoelectric layer 112 in the direction perpendicular to the substrate 100. Therefore, the pad 170 connected to the wiring 140 is also formed vertically above the piezoelectric layer 112 in the direction perpendicular to the substrate 100. Note that the pad 170 is preferably formed in a position where the piezoelectric layer 112 is less likely to deform, in other words, in a position that does not overlap with the pressure chamber 17 in the direction perpendicular to the surface of the substrate 100. Furthermore, the pad 170 is preferably positioned so as not to intersect with the end surface 112b of the piezoelectric layer in the direction perpendicular to the surface of the substrate 100. The shape of the piezoelectric layer can be appropriately adjusted depending on the shape and position of the upper wiring 140 and the pad 170.
[0066] Furthermore, when multiple piezoelectric elements 110 are arranged in the piezoelectric actuator, the piezoelectric layers 112 of two or more piezoelectric elements 110 may be partially connected. In other words, the piezoelectric layers 112 of two or more piezoelectric elements 110 may be integrally formed, and each piezoelectric element 110 may have a lower electrode 111 and an upper electrode 113.
[0067] The lower wiring 150 electrically connected to the lower electrode 111 is not formed along the end surface 112b of the piezoelectric layer, and therefore, even if it is formed by a film formation method such as sputtering or vapor deposition, its thickness is significantly thin and there is little possibility of it breaking. In FIG. 10, the lower wiring 150 is formed on approximately the same plane as the lower electrode 111. In this case, compared to the configuration shown in FIG. 6, an advantage is obtained in that the process of forming the contact hole 131 for connecting the lower electrode 111 and the lower wiring 150 can be reduced. As in the modified example of this embodiment shown in FIG. 11, the lower electrode 111 may be formed to also serve as the lower wiring 150, and in this case, an advantage is obtained in that the process of forming the lower wiring can be reduced.
[0068] (Fourth embodiment) A fourth embodiment of the present invention will be described with reference to FIGS. 12(a) and 12(b). In this embodiment, a layer located on the upper surface 110a of the piezoelectric element 110 is partially removed to form a recess 190 in the piezoelectric element 110. By forming the recess 190 by partially removing the layer located on the upper surface 110a of the piezoelectric element 110, the rigidity of the piezoelectric actuator can be reduced. This makes it possible to drive the piezoelectric actuator at a lower voltage than in other embodiments, thereby improving the driving efficiency of the piezoelectric actuator. In FIG. 12(a), the second protective layer 130 is configured to have an interrupted recess 190 in the silicon oxide film. That is, the second protective layer 130 has an opening in the area that overlaps with the piezoelectric layer 112 in a plan view. On the other hand, the second protective layer 130 is disposed in positions where leakage is likely to occur, specifically, between the lower electrode 111 and the lower wiring 150, between the lower electrode 111 or the upper electrode 113 and the upper wiring 140, and in positions that overlap with the periphery of the piezoelectric layer 112 in plan view. Therefore, even with the configuration of this embodiment, deterioration of the piezoelectric layer properties due to moisture and dielectric breakdown due to an increase in leakage current are unlikely to occur. Note that the second protective layer 130 may be configured to be recessed in a direction perpendicular to the substrate in plan view, rather than being open, to form a recess 190.
[0069] In manufacturing the piezoelectric actuator of this embodiment, in the step of forming the upper through-holes 132 and the lower through-holes 131 by etching as shown in Fig. 9(g), the recesses 190 can be formed by simultaneously etching at least a part of the central portion of the second protective layer 130 on the upper surface 110a of the piezoelectric element 110. The formation of the recesses 190 may be performed after the step of forming the upper wiring 140 and the lower wiring 150 as shown in Fig. 9(h).
[0070] 12(b), the recess 190 may be formed by recessing or opening the insulating layer 160, instead of the second protective layer 130, in a region that overlaps with the piezoelectric layer 112 in a plan view. The recess 190 may also be formed by opening both the second protective layer 130 and the insulating layer 160. In the present invention, the insulating layer is not thickened to cover the wiring, which makes it easier to reduce the processing time and control the etching depth when etching the insulating layer to form the recess 190. Note that, in terms of ensuring moisture resistance of the piezoelectric layer, it is preferable to reduce the rigidity of the piezoelectric actuator by partially removing the second protective layer 130 rather than using the insulating layer 160, which has better moisture resistance than the second protective layer. [Example]
[0071] The present invention will be described in more detail below with reference to examples and comparative examples, but the present invention is not limited to the following examples in any way as long as the gist of the invention is not exceeded.
[0072] The piezoelectric actuator having the structure shown in Fig. 6, which is shown in the first embodiment, was fabricated by the process shown in Fig. 9. The film thickness of each layer is as described above in the first embodiment.
[0073] A silicon substrate was used as the substrate 100, the insulating layer 101 was a silicon thermal oxide film with a thickness of 500 nm, the lower electrode 111 was platinum with a thickness of 100 nm, the piezoelectric layer 112 was PZT with a thickness of 2 μm, and the upper electrode 113 was an alloy of titanium and tungsten with a thickness of 100 nm. The upper wiring 140 and the lower wiring 150 were made of an aluminum-copper alloy film with a thickness of 30 nm, a width (length in the short direction) of 5 μm, and a cross-sectional area in the short direction of 150,000 nm. 2 An adhesive film of titanium was formed on the surface of insulating layer 130 opposite to substrate 100. Insulating layer 160 was a silicon nitride film with a thickness of 200 nm.
[0074] The piezoelectric actuator fabricated as described above was immersed in a sodium hydroxide solution to observe the degree of corrosion, and no corrosion was observed in the upper wiring 140 or the lower wiring 150. Furthermore, even after applying a voltage of 40 V for 1000 hours in a high-temperature, high-humidity environment, no breaks in the wiring were observed, and good actuation was demonstrated.
[0075] The present disclosure includes the following configurations and methods.
[0076] (Configuration 1) An actuator having a piezoelectric element having a first electrode, a piezoelectric layer, and a second electrode in this order on a substrate, wiring electrically connected to at least one of the first electrode or the second electrode, and an insulating layer arranged to contact and cover the wiring, An actuator, wherein the thickness of the wiring is smaller than the thickness of the insulating layer in a direction perpendicular to the substrate, and the thickness of the insulating layer is 500 nm or less.
[0077] (Configuration 2) The cross-sectional area of the wiring in a direction perpendicular to the substrate is 165 nm 2 The actuator according to configuration 1 is as described above.
[0078] (Configuration 3) 3. The actuator according to claim 2, wherein the thickness of the wiring in a direction perpendicular to the substrate is 200 nm or less.
[0079] (Configuration 4) 3. The actuator according to claim 2, wherein the thickness of the wiring in a direction perpendicular to the substrate is 100 nm or less.
[0080] (Configuration 5) 5. The actuator of any one of configurations 1 to 4, wherein the insulating layer comprises silicon nitride.
[0081] (Configuration 6) 6. The actuator of any one of configurations 1 to 5, wherein the insulating layer has a thickness of 100 nm or more in a direction perpendicular to the substrate.
[0082] (Configuration 7) 7. The actuator according to any one of configurations 1 to 6, wherein the insulating layer has a recess or an opening in a region that overlaps with the piezoelectric layer when viewed in a direction perpendicular to the substrate.
[0083] (Configuration 8) 8. The actuator of any one of configurations 1 to 7, wherein the wiring is primarily composed of at least one element selected from aluminum, copper, and gold.
[0084] (Configuration 9) The actuator of any one of configurations 1 to 8, wherein the wiring includes a first wiring electrically connected to the first electrode and a second wiring electrically connected to the second electrode.
[0085] (Configuration 10) 10. The actuator of claim 9, wherein the first wiring and the second wiring are located in the same layer in a direction perpendicular to the substrate.
[0086] (Configuration 11) 10. The actuator of claim 9, wherein the first wiring and the second wiring are located in different layers in a direction perpendicular to the substrate.
[0087] (Configuration 12) a first protective layer covering the piezoelectric element; a second protective layer disposed between the piezoelectric element and the first wiring and between the piezoelectric element and the second wiring; 10. The actuator according to configuration 9, comprising the first protective layer, the second protective layer, and the insulating layer in this order from the substrate.
[0088] (Configuration 13) 13. The actuator of claim 12, wherein the insulating layer is more moisture resistant than the second protective layer.
[0089] (Configuration 14) 13. The actuator according to claim 12, wherein the second protective layer is disposed so as to cover the piezoelectric layer when viewed in a direction perpendicular to the substrate.
[0090] (Configuration 15) 15. The actuator of any one of configurations 1 to 14, wherein the piezoelectric layer comprises lead zirconate titanate.
[0091] (Configuration 16) 16. A liquid ejection head having the actuator according to any one of configurations 1 to 15, and configured to eject liquid from an ejection port.
[0092] (Configuration 17) a pressure chamber for supplying liquid to the ejection port; 17. The liquid ejection head according to claim 16, wherein the substrate forms one of the walls of the pressure chamber.
[0093] (Configuration 18) 18. The liquid ejection head according to configuration 16 or 17, for ejecting ink as the liquid.
[0094] (Method 1) a piezoelectric element having a first electrode, a piezoelectric layer, and a second electrode in this order on a substrate; wiring electrically connected to at least one of the first electrode and the second electrode; and an insulating layer disposed so as to contact and cover the wiring; a thickness of the wiring in a direction perpendicular to the substrate that is smaller than a thickness of the insulating layer, and the thickness of the insulating layer is 500 nm or less; A method for manufacturing an actuator, comprising the step of forming the insulating layer by ALD. [Explanation of symbols]
[0095] 100 boards 110 Piezoelectric element 111 Lower electrode 112 Piezoelectric layer 113 Upper electrode 120 protective layer 130 Insulating layer 140 upper wiring 150 Bottom wiring 160 Insulating Layer
Claims
1. An actuator having a piezoelectric element having a first electrode, a piezoelectric layer, and a second electrode in this order on a substrate, wiring electrically connected to at least one of the first electrode or the second electrode, and an insulating layer disposed so as to contact and cover the wiring, An actuator, wherein the thickness of the wiring is smaller than the thickness of the insulating layer in a direction perpendicular to the substrate, and the thickness of the insulating layer is 500 nm or less.
2. The cross-sectional area of the wiring in a direction perpendicular to the substrate is 165 nm 2 The actuator according to claim 1 .
3. 3. The actuator according to claim 2, wherein the thickness of the wiring in a direction perpendicular to the substrate is 200 nm or less.
4. The actuator according to claim 2 , wherein the thickness of the wiring in a direction perpendicular to the substrate is 100 nm or less.
5. The actuator of claim 1 , wherein the insulating layer comprises silicon nitride.
6. The actuator according to claim 1 , wherein the insulating layer has a thickness of 100 nm or more in a direction perpendicular to the substrate.
7. The actuator according to claim 1 , wherein the insulating layer has a recess or an opening in a region overlapping with the piezoelectric layer when viewed in a direction perpendicular to the substrate.
8. The actuator according to claim 1 , wherein the wiring is mainly composed of at least one element selected from the group consisting of aluminum, copper, and gold.
9. The actuator according to claim 1 , wherein the wiring includes a first wiring electrically connected to the first electrode and a second wiring electrically connected to the second electrode.
10. The actuator according to claim 9 , wherein the first wiring and the second wiring are located in the same layer in a direction perpendicular to the substrate.
11. The actuator according to claim 9 , wherein the first wiring and the second wiring are located in different layers in a direction perpendicular to the substrate.
12. a first protective layer covering the piezoelectric element; a second protective layer disposed between the piezoelectric element and the first wiring and between the piezoelectric element and the second wiring; The actuator according to claim 9 , comprising the first protective layer, the second protective layer, and the insulating layer in this order from the substrate.
13. The actuator of claim 12 , wherein the insulating layer is more moisture resistant than the second protective layer.
14. The actuator according to claim 12 , wherein the second protective layer is disposed so as to cover the piezoelectric layer when viewed in a direction perpendicular to the substrate.
15. The actuator of claim 1 , wherein the piezoelectric layer comprises lead zirconate titanate.
16. A liquid ejection head comprising the actuator according to claim 1 and configured to eject liquid from an ejection port.
17. a pressure chamber for supplying liquid to the discharge port, The liquid ejection head according to claim 16 , wherein the substrate constitutes one of the walls of the pressure chamber.
18. 17. The liquid ejection head according to claim 16, for ejecting ink as the liquid.
19. a piezoelectric element having a first electrode, a piezoelectric layer, and a second electrode in this order on a substrate, wiring electrically connected to at least one of the first electrode and the second electrode, and an insulating layer disposed so as to contact and cover the wiring; a thickness of the wiring is smaller than a thickness of the insulating layer in a direction perpendicular to the substrate, and the thickness of the insulating layer is 500 nm or less, A method for manufacturing an actuator, comprising the step of forming the insulating layer by ALD.
Citation Information
Patent Citations
Semiconductor device and method of manufacturing semiconductor device
JP2005032919A
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