Semiconductor device

Abstract

To provide a semiconductor device capable of improving practicality and durability as a product.SOLUTION: A semiconductor device includes: a substrate; a semiconductor chip 103 mounted on the substrate; a lead frame 104 mounted on the substrate; a first sintered joint layer joining a substrate conductor 102 of the substrate and the semiconductor chip 103; a second sintered joint layer joining the semiconductor chip 103 and the lead frame 104; a plurality of first grooves 8 formed in a joint portion with the semiconductor chip 103 on the substrate; and a plurality of second grooves 104d formed in the joint portion with the semiconductor chip 103 of the lead frame 104. The first grooves 8 and the second grooves 104d have different groove length directions. A through hole 104e passing through the lead frame 104 is formed in a portion sandwiched between two or more joint surface portions in the lead frame 104.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As a device responsible for power conversion and control in electric vehicles, railway vehicles, power generation systems, etc., semiconductor devices using IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), etc. are used.

[0003] As the background art of this technical field, there is Japanese Patent Application Laid-Open No. 2017-103180 (Patent Document 1). This publication describes that "the copper paste for pressureless bonding is a copper paste for pressureless bonding containing metal particles and a dispersion medium, the metal particles including sub-micro copper particles having a volume average particle diameter of 0.01 μm or more and 0.8 μm or less, and micro copper particles having a volume average particle diameter of 2.0 μm or more and 50 μm or less, the dispersion medium including a solvent having a boiling point of 300°C or higher, and the content of the solvent having a boiling point of 300°C or higher being 2% by mass or more based on the total mass of the copper paste for pressureless bonding." (See the abstract).

[0004] As another background art, there is International Publication No. 2017 / 002793 (Patent Document 2). This publication states that "The semiconductor device (1) includes an electrode (22) having a flat portion and a non-flat portion (6) formed by a concave portion, a bonding layer (3) formed of a sintered body of metal crystal grains provided on the flat portion and the non-flat portion (6) of the electrode (22), and semiconductor elements (4), (5) bonded to the electrode (22) via the bonding layer (3). The bonding layer (3) has a first region (3a) sandwiched between the non-flat portion (6) and the semiconductor elements (4), (5), and a second region (3b) sandwiched between the flat portion and the semiconductor elements (4), (5). The filling rate of the metal crystal grains in the region with the larger layer thickness among the first region (3a) and the second region (3b) is smaller than the filling rate of the metal crystal grains in the region with the smaller layer thickness. According to the present invention, the reliability of the bonding layer made of the sintered body of metal crystal grains is improved." (See the abstract).

[0005] As another background art, there is Japanese Unexamined Patent Application Publication No. 2017-092168 (Patent Document 3). This publication states that "The semiconductor module 200 includes an insulating substrate 210, a wiring layer 212 formed on the insulating substrate, a semiconductor chip 100 disposed on top of the wiring layer and having one terminal electrically connected to the wiring layer, and a metal sintered bonding layer 214 that fixes and electrically connects between the wiring layer and the semiconductor chip. The wiring layer is characterized by having a groove portion inside the outer edge of the overlapping semiconductor chips in a plan view." (See the abstract).

[0006] As another background art, there is Japanese Unexamined Patent Application Publication No. 2023-003573 (Patent Document 4). This publication states that "In a semiconductor module 10 including an insulating substrate 1, a wiring 2 formed on the insulating substrate 1, a semiconductor chip 3, and a lead frame 4, one surface of the semiconductor chip 3 is connected to the wiring 2, and the other surface is connected to the lead frame 4. The wiring 2 has a floating wiring to which the lead frame 4 is connected, and the connection point between the floating wiring and the lead frame 4 is located at a corner of the insulating substrate 1." (See the abstract).

[0007] As another background art, there is International Publication No. 2021 / 177292 (Patent Document 5). This publication describes that "by joining through an upper joining member (50), a first constituent material (110) containing a sintering material is pressure-sintered on one surface (30a) of a semiconductor chip (30), enters between the convex portions (31) and contacts the convex portions (31), disposing a pre-joining layer (51) having a flattened surface on the side opposite to the semiconductor chip (30) side, disposing a second support member (20) on the pre-joining layer (51) via a second constituent material (120) containing a sintering material, and by pressurizing while heating to pressure-sinter the sintering material in the second constituent material (120), the upper joining member (50) is formed together with the pre-joining layer (51)." (See the abstract).

[0008] As another background art, there is Japanese Unexamined Patent Application Publication No. 2018-026417 (Patent Document 6). This publication describes that "a power semiconductor device using a plate-shaped wiring includes at least an insulating substrate having a surface pattern, a semiconductor chip whose back surface is fixed with a first joining layer on the surface pattern of the insulating substrate, an electrode pad provided on the surface of the semiconductor chip, a metal layer covering the electrode pad, and a plate-shaped wiring member fixed with a second joining layer on the metal layer. The first joining layer is made of a sintered body of Ag or Cu, and the second joining layer is a sintered body of Ag or Cu and is made of a sintered body containing voids inside." (See the abstract).

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0010] However, the techniques disclosed in Patent Documents 1 to 6 had room for improvement from the viewpoint of improving the practicality and durability of the semiconductor device as a product. Therefore, an object of the present invention is to provide a semiconductor device capable of improving the practicality and durability of the product.

Means for Solving the Problems

[0011] To solve the above problems, the present invention includes a substrate, a plurality of semiconductor chips mounted on the substrate, a lead frame mounted on the substrate, a first sintered bonding layer bonding the substrate conductor of the substrate and the semiconductor chip, a second sintered bonding layer bonding the semiconductor chip and the lead frame, a plurality of first grooves formed in a bonding portion between the semiconductor chip on the substrate, and a plurality of second grooves formed in a bonding portion between the semiconductor chip of the lead frame, wherein the first groove and the second groove have different groove length directions, and a through hole formed at a position facing a gap between two adjacent semiconductor chips in the previous lead frame. Other means will be described in the mode for carrying out the invention.

Effects of the Invention

[0012] According to the present invention, a semiconductor device capable of improving the practicality and durability of the product can be provided. Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0013]

Figure 1

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Figure 18

Embodiments for Carrying Out the Invention

[0014] Hereinafter, multiple examples of embodiments of the present invention will be described with reference to the drawings. [Embodiment 1] 《Configuration of Semiconductor Device》 First, the configuration of the semiconductor device 1 according to this embodiment will be described. FIG. 1 is a plan view of the semiconductor device 1 according to the first embodiment. FIG. 2 is a side view of the semiconductor device 1. FIG. 3 is a cross-sectional view taken along the line E-E of FIG. 1. As shown in FIGS. 1 to 3, in this semiconductor device 100, a plurality of semiconductor chips 103 and a lead frame 104 are mounted in this order on a substrate conductor 102 formed on an insulating substrate 101 of a substrate 11 (FIG. 5). One surface (the surface on the paper side in FIG. 1) of the semiconductor chip 103 is connected to the substrate conductor 102, and the other surface (the upper surface in FIG. 1) is connected to the lead frame 104.

[0015] Here, as an example of the semiconductor chip 103, an example using a plurality of SiCMOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor) chips is shown, but it is not limited thereto. The semiconductor chip 103 is, for example, a power transistor such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET, or a diode, and is composed of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), etc. Note that the semiconductor device 100 constitutes a power conversion device or the like that connects these semiconductor elements (circuit elements) to perform power conversion such as an inverter. The circuit elements of these semiconductor elements include at least one type of IGBT, MOSFET, and diode.

[0016] Also, as shown in FIG. 1, three insulating substrates 101 are housed in a resin case 107. Note that the number of insulating substrates 101 housed is not limited to three. Although not shown, the surface of the insulating substrate 101 is sealed with an insulating resin together with the substrate conductor 102, the semiconductor chip 103, and the lead frame 104. There is no particular limitation on the materials of the insulating substrate 101 and the substrate conductor 102. For example, ceramics can be used for the insulating substrate 101 and copper can be used for the substrate conductor 102.

[0017] As shown in FIGS. 2 and 3, a heat radiating member 106 having at least a base plate is provided on the surface of the insulating substrate 101 where the semiconductor chip 103 is provided and on the opposite surface thereof. The heat radiating member 106 may further have heat radiating fins 106a. The configuration of the heat radiating fins 106a may be cylindrical or flat plate-shaped. The cooling method of the heat radiating member 106 may be air cooling or water cooling. In the case of air cooling, for example, a fan can be provided to send air to the heat radiating member 106 and the heat radiating fins 106a for cooling. In the case of water cooling, for example, a cooling passage can be provided so that water or a cooling medium comes into contact with the heat radiating member 106 and the heat radiating fins 106a.

[0018] As shown in FIGS. 1 and 3, the lead frame 104 is connected to the substrate conductor 102 via a first connection point 104a and a second connection point 104b. The terminals 105 are provided, for example, on both sides of the insulating substrate 101, and the current from the terminals 105 on one side passes through the substrate conductor 102, the semiconductor chip 103, and the lead frame 104 and is led to the terminals 105 on the other side.

[0019] Here, in the first embodiment, as the substrate conductor 102, a floating wiring 102a that is a floating wiring not used as a circuit, separate from the wiring used as a circuit such as the current path between the terminals 105 on both sides, is provided. Then, in the insulating substrate 101, the floating wiring 102a, which is a part of the substrate conductor 102, and the lead frame 104 are connected at the position of the second connection point 104b.

[0020] As shown in the heat dissipation path 111 of FIG. 3, the heat generated from the semiconductor chip 103 shown in FIG. 1 is guided to the heat dissipation member 106 via the substrate conductor 102 and the insulating substrate 101 directly below the semiconductor chip 103 and is dissipated. Also, as shown in the heat dissipation path 112, the heat generated from the semiconductor chip 103 is guided to the first connection point 104a via the lead frame 104, and then guided to the heat dissipation member 106 via the substrate conductor 102 and the insulating substrate 101 and is dissipated.

[0021] Furthermore, as shown in the heat dissipation path 113, the heat generated from the semiconductor chip 103 is guided to the second connection point 104b via the lead frame 104. The heat guided to the second connection point 104b is guided to the heat dissipation member 106 via the floating wiring 102a and the insulating substrate 101 and is dissipated.

[0022] By the way, between the substrate 11 (FIG. 5), the semiconductor chip 103, and the lead frame 104 of the semiconductor device 100, they are joined by sintering. And the semiconductor device 100 is wired by wire bonding as will be described later. And in the technologies of Patent Documents 1 to 6 described above, there was room for improvement in suppressing the detachment of each member of the substrate 11, the semiconductor chip 103, and the lead frame 104 after sintering and ensuring that there is no obstacle to the above-described wire bonding. Therefore, the technologies of Patent Documents 1 to 6 described above had room for improvement in terms of improving the practicality and durability of the semiconductor device 100 as a product. Hereinafter, the technical content of the first embodiment improved in these aspects will be described.

[0023] FIG. 4 is a plan view showing the main part around the semiconductor chip 103 of the semiconductor device 100 according to the first embodiment. FIG. 5 is a schematic longitudinal sectional view directly below the semiconductor chip. As shown in FIGS. 4 and 5, the semiconductor device 100 has a stacked structure in which the semiconductor chip 103, the substrate 11, and the base 7 are joined to each other. The semiconductor chip 103 is mounted on the substrate 11. The lead frame 104 is also mounted on the substrate 11.

[0024] As shown in FIG. 5, the substrate 11 used in the semiconductor device 100 is composed of a substrate conductor 102, an insulating substrate 101, and a metal layer 5 laminated thereon. The substrate conductor 102 has the function of a wiring layer as a circuit electrode pattern. As the material of the substrate conductor 102, it is desirable to use copper (Cu), a copper (Cu) alloy, aluminum (Al), an aluminum (Al) alloy, etc., which have good electrical conductivity and thermal conductivity. The metal layer 5 has the function of a heat diffusion plate. As the material of the metal layer 5, it is desirable to use, for example, copper, a copper alloy, aluminum, an aluminum alloy, etc., similar to the material of the substrate conductor 102. As the material of the insulating substrate 101, it is desirable to use a material with high insulation and high thermal conductivity, and for example, ceramics such as aluminum nitride, aluminum oxide, silicon nitride, etc. are preferably used. The base 7 has the function of a heat dissipation member to the outside. As the material of the base 7, it is desirable to use a material with high rigidity and high thermal conductivity, and copper, a copper alloy, aluminum, an aluminum alloy, a composite material of aluminum and silicon carbide (AlSiC), a composite material of magnesium and silicon carbide (MgSiC), etc. are preferably used.

[0025] The semiconductor device 100 has a first sintered bonding layer 2 that bonds the substrate conductor 102 of the substrate 11 and the semiconductor chip 103. A plurality of first grooves are formed in the substrate 11 at the bonding portion with the semiconductor chip 103. The semiconductor device 100 further has a base bonding layer 6 that bonds the substrate 11 and the base 7 between them. As the material of the first sintered bonding layer 2, a sintered bonding material such as copper (Cu) nanoparticles or silver (Ag) nanoparticles, which has high thermal conductivity and high heat resistance, is used. As the material of the base bonding layer 6, a material with high thermal conductivity, such as solder mainly composed of, for example, lead (Pb) or tin (Sn), is used.

[0026] The substrate conductor 102 is part of an electric circuit and is electrically connected to the semiconductor chip 103 and terminals for electrical connection to the outside. As shown in FIG. 4, between the electrode surface 103a formed on the upper surface of the plurality of semiconductor chips 103 and the convex portion 104c (concave so as to protrude downward in FIG. 4) formed on the surface of the lead frame 104 facing the semiconductor chip 103 (the lower surface in FIG. 4), a second sintered bonding layer 2b (see FIG. 14) for bonding the semiconductor chip 103 and the lead frame 104 is formed. A plurality of second grooves 104d are formed in the lead frame 104 at the bonding portion with the semiconductor chip 103.

[0027] Furthermore, a first sintered bonding layer 2 (see FIG. 13) for bonding them is also formed between the substrate conductor 102 and the first connection point 104a of the lead frame 104, and between the floating wiring 102a and the second connection point 104b of the lead frame 104. These first sintered bonding layers 2 are also made of a material with high thermal conductivity and high heat resistance, such as a sintered bonding material of copper (Cu) nanoparticles or silver (Ag) nanoparticles. A through hole 104e is formed at a position facing the gap between two adjacent semiconductor chips 103 in the lead frame 104. The through hole 104e is formed in a portion sandwiched between two or more bonding portions in the lead frame 104.

[0028] FIG. 6 is a plan view showing a main part directly below the semiconductor chip 103 of the semiconductor device 1 according to Embodiment 1. FIG. 7 is a cross-sectional view taken along line B-B shown in FIG. 6, and FIG. 8 is a cross-sectional view taken along line C-C shown in FIG. 6. FIG. 9 is a plan view for explaining the bonding region RCH of the semiconductor chip 103 in FIG. 6. FIG. 10 is an enlarged view of part D shown in FIG. 7.

[0029] As shown in FIGS. 5, 6, 7, and 8, on the surface side of the substrate conductor 102 of the substrate 11, there is a bonding region RCH (FIGS. 7 and 8) that bonds to the semiconductor chip 103. In the bonding region RCH on the surface side of the substrate conductor 102, a plurality of first grooves 8 formed by machining, pressing, etching, or the like are provided in parallel, for example. As shown in FIG. 6, the first groove 8 is formed to extend by a length Ly8 outside the outer edge 1OE of the bonding region RCH of the semiconductor chip 103. That is, the substrate conductor 102, which is a wiring layer of the substrate 11, has a plurality of first grooves 8 dug from the bonding region RCH of the semiconductor chip 103 to the outside RO of the bonding region RCH. In the bonding region RCH of the semiconductor chip 103, a thin first sintered bonding layer 2 is formed between the semiconductor chip 103 and the substrate conductor 102, and the inside of the first groove 8 is filled with an excess 12 of sintered metal (FIGS. 7 and 8). The excess 12 is formed by the excess sintered paste entering the first groove 8 during the sintering bonding process described later and being fired. The inside of the first groove 8 formed outside the outer edge RO of the bonding region RCH of the semiconductor chip 103 is also filled with the excess 12.

[0030] As shown in FIG. 6, the outer edge 1OE of the semiconductor chip 103 has a rectangular shape in a top view. That is, the outer edge 1OE of the semiconductor chip 103 has a first side OE1 provided along the first direction X, a second side OE2 that is a side opposite to the first side OE1, a third side OE3 provided between the first side OE1 and the second side OE2, and a fourth side OE4 that is a side opposite to the third side OE3. The third side OE3 and the fourth side OE4 are provided along the second direction Y that is orthogonal to the first direction X. The bonding region RCH of the semiconductor chip 103 provided on the substrate conductor 102 is, in a top view, an area that is substantially the same as the inner rectangular area surrounded by the first side OE1 to the fourth side OE4 of the semiconductor chip 103.

[0031] The lengths of the first side OE1 and the second side OE2 are Lx1, and the lengths of the third side OE3 and the fourth side OE4 are Ly1. A plurality of first grooves 8 are formed on the surface side of the substrate conductor 102 such that the length direction is substantially orthogonal to the first direction X. The length direction of each of the plurality of first grooves 8 is substantially parallel to the second direction Y which is a direction orthogonal to the first direction X. The length Ly8 of the first groove 8 along the second direction Y is formed longer than the length Ly1 of the third side OE3 or the fourth side OE4 of the semiconductor chip 103 along the second direction Y (Ly8>Ly1). In the configuration example of the first groove 8 shown in FIG. 6, the length Ly8 of the first groove 8 is the sum of the length Ly1 of the third side OE3 or the fourth side OE4 of the semiconductor chip 103, the overhang length Ly81 of the first groove 8 from the first side OE1 of the semiconductor chip 103, and the overhang length Ly82 of the first groove 8 from the second side OE2 of the semiconductor chip 103, and is represented by the following formula (1).

Number

[0032] In the example of FIG. 6, Ly81 and Ly82 are of equal length (Ly81 = Ly82). Note that Ly81 and Ly82 may have different lengths. In the first embodiment, the width W8 of the plurality of first grooves 8 in the direction of the first direction X is the same for each first groove 8.

[0033] Here, with reference to FIG. 9, the bonding region RCH of the semiconductor chip 103 will be described. FIG. 9 corresponds to a simplified plan view obtained by removing the semiconductor chip 103 and the first sintered bonding layer 2 from the plan view of FIG. 6. In FIG. 9, the bonding region RCH of the semiconductor chip 103 is within a region surrounded by a rectangular dashed line, and has a first side RCH1 provided along the first direction X, a second side RCH2 which is a side opposite to the first side RCH1, a third side RCH3 provided between the first side RCH1 and the second side RCH2, and a fourth side RCH4 which is a side opposite to the third side RCH3. The third side RCH3 and the fourth side RCH4 are provided along the second direction Y which is orthogonal to the first direction X.

[0034] The bonding region RCH of the semiconductor chip 103 has, in the first direction X, a central portion RCEx of the bonding region RCH and a pair of end portions ROEx provided on both sides of the bonding region RCH. The outside of the end portion ROEx of the bonding region RCH is shown as the outside ROx. No first groove 8 is provided in the outside ROx.

[0035] Also, the bonding region RCH of the semiconductor chip 103 has, in the second direction Y, a central portion RCEy of the bonding region RCH and a pair of end portions ROEy provided on both sides of the bonding region RCH. The outside of the end portion ROEy of the bonding region RCH is shown as the outside ROy. Portions of the first groove 8 protruding from the semiconductor chip 103 (a portion with a protruding length Ly81 and a portion with a protruding length Ly82) are provided in the outside ROy.

[0036] Using FIG. 7, the depths of the plurality of first grooves 8 in the first direction X will be described. As shown in FIG. 7, the first groove 8 is formed on the surface side of the substrate conductor 102 such that the depth of the first groove 8 is different between the central portion RCEx of the bonding region RCH of the semiconductor chip 103 and the end portion ROEx of the bonding region RCH of the semiconductor chip 103. In FIG. 7, as an example, ten first grooves 8 are shown. The first groove 8 is composed of ten grooves 8a, 8b, 8c,..., 8j from the left. The groove 8a has a depth d1. The groove 8b has a depth d2. The groove 8c has a depth d3. The groove 8d has a depth d4. The groove 8e has a depth d5. The groove 8f has a depth d6. The groove 8g has a depth d7. The groove 8h has a depth d8. The groove 8i has a depth d9. The groove 8j has a depth d10.

[0037] The depth d1 of the groove 8a and the depth d10 of the groove 8j provided in the end portion ROEx are formed shallower compared to the depth d5 of the groove 8e and the depth d6 of the groove 8f provided in the central portion RCEx, and are represented by the following formulas (2), (3), (4), and (5).

Number

Number

Number

Number

[0038] In this example, the depth of the first groove 8 is configured such that the depth d2 is deeper than the depth d1 as shown in Equation (6), and thereafter, the depths gradually increase in the order of d3, d4, d5.

Number

[0039] Then, as shown in Equation (7), the depth d7 is shallower than the depth d6, and thereafter, the depths gradually decrease in the order of d8, d9, d10.

Number

[0040] That is, the depth d1 of the groove 8a and the depth d10 of the groove 8j provided at the end portion ROEx are formed to be relatively shallow. The depth d5 of the groove 8e and the depth d6 of the groove 8f provided at the central portion RCEx are formed deeper than the depth d1 of the groove 8a and the depth d10 of the groove 8j.

[0041] The depth of the first groove 8 provided at the central portion RCEx is formed to be the deepest, and the depth of each first groove 8 gradually decreases as going from the central portion RCEx to the end portion ROEx. The depth d5 of the groove 8e and the depth d6 of the groove 8f provided at the central portion RCEx may be the same depth (d5 = d6), or the depths d5 and d6 may be different depths. As shown in FIG. 10, the depth d2 of the adjacent groove 8b and the depth d3 of the groove 8c among the first grooves 8 are different. At least one of the plurality of first grooves 8 and the second grooves 104d gradually becomes shallower from the ones at the central portion of the joining region to the ones at the end portion side.

[0042] As shown in FIG. 8, each of the first grooves 8 extending in the Y direction of the second direction has the deepest central portion dy3 in the Y direction of the second direction, gradually becomes shallower as it approaches the end portions dy2 and dy4, and the outermost end portions dy1 and dy5 exposed to the outside are the shallowest. In this way, the depth of the first groove 8 is the deepest at the central portion of the bonding region RCH and gradually becomes shallower toward the end portions, when viewed from either the X direction of the first direction or the Y direction of the second direction. At least one of the plurality of first grooves 8 and the second grooves 104d only needs to extend to the outside of the bonding region joined to the semiconductor chip.

[0043] As shown in FIGS. 7 and 8, the remaining region of the substrate conductor 102 where the first groove 8 is not formed is the flat surface of the substrate conductor 102, and the flat surface of the substrate conductor 102 and the back surface of the semiconductor chip 103 are joined by the first sintered bonding layer 2 within the bonding region RCH. The portion of the first groove 8 that extends to the outside ROy gradually becomes shallower toward the outside, and the outermost portion has the same height as the flat surface of the substrate conductor 102. The width W8 of the first groove 8 is, for example, 200 μm or less, and the depths d1 to d10 of each first groove 8 are, for example, 200 μm or less. The thickness of the first sintered bonding layer 2 between the surface of the substrate conductor 102 where the first groove 8 is not formed in the bonding region RCH and the semiconductor chip 103 is, for example, around 20 μm.

[0044] Returning to FIG. 4, a plurality of second grooves 104d are also formed in the convex portion 104c formed on the lower surface of the lead frame 104 facing the electrode surface 103a of the semiconductor chip 103. In this example, the plurality of second grooves 104d are parallel to each other. The second groove 104d extends from one end of the convex portion 104c of the lead frame 104 to the opposite end.

[0045] In the region where the second groove 104d is formed, the electrode surface 103a of the semiconductor chip 103 and the convex portion 104c of the lead frame 104 are joined by the second sintered joint layer 2b. The second sintered joint layer 2b forms a thin layer between the electrode surface 103a of the semiconductor chip 103 and the convex portion 104c of the lead frame 104. The sintered metal has entered the second groove 104d as in the case of the first groove 8.

[0046] Then, as is clear from FIG. 4, the length directions of the respective first grooves 8 and the respective second grooves 104d are different, and they intersect rather than being parallel. Further, each wiring 401 of the control electrode 108 is provided so as not to be located on the extension line in the length direction of the second groove 104d. In this way, at least one of the plurality of first grooves 8 and second grooves 104d may have different groove depths on the central portion side and the end portion side of the bonding region joined to the semiconductor chip 103. At least one of the plurality of first grooves 8 and second grooves 104d may be shallower on the end portion side than those on the central portion side of the bonding region.

[0047] 《Manufacturing Method of Semiconductor Device 100》 Next, an outline of the manufacturing method of the semiconductor device 100 described above will be described. In this manufacturing method, the following respective steps are sequentially performed.

[0048] (First Step) First, the substrate 11, the semiconductor chip 103, and the lead frame 104 described above are prepared. The manufacturing apparatus forms the first groove 8 in the substrate 11. The second groove 104d is formed in the lead frame 104. As a method for forming the first groove 8, for example, cutting using a diamond blade saw is preferable. The second groove 104d is preferably formed, for example, by cutting using a diamond blade saw or formed simultaneously when the lead frame 104 is manufactured by forging. As shown in FIG. 11, a flat substrate conductor 102 is formed on the insulating substrate 101, and the first groove 8 is formed in the region where the semiconductor chip 103 is disposed in the substrate conductor 102.

[0049] (Step 2) Next, as shown in FIG. 12, a sintering paste for sintering bonding is applied and supplied by screen printing or the like to the position shown as the first sintering bonding layer 2 in the region of the substrate conductor 102 where the semiconductor chip 103 is disposed. At the same time, a sintering paste for sintering bonding is also applied and supplied to the position shown as the sintering bonding layer 2a. As the sintering paste, a paste obtained by dispersing metal nanoparticles such as Ag nanoparticles coated with an organic protective film in an organic component is used.

[0050] (Step 3) Next, as shown in FIG. 13, using a chip mounter or the like, the semiconductor chip 103 is placed on the sintering paste applied and supplied to the planned position of the first sintering bonding layer 2, and pressure is applied from above with a low load to accommodate the excess sintering paste in the first groove 8.

[0051] (Step 4) Next, as shown in FIG. 14, a sintering paste is potted and applied by a dispenser or the like to the position shown as the second sintering bonding layer 2b on the electrode surface 103a (FIG. 4) of the semiconductor chip 103.

[0052] (Step 5) Next, as shown in FIG. 15, the lead frame 104 is mounted by a mounter, pressure is applied with a low load, and the excess bonding material paste is accommodated in the second groove 104d.

[0053] (Step 6) Next, while applying pressure from above at a low pressure to the formation positions of the first sintered bonding layer 2, the second sintered bonding layer 2b, and the sintered bonding layer 2a, the volatilization process of the reducing agent and the sintering reaction process in the case where the reducing agent is included in the sintered paste are performed at their respective predetermined temperatures. At this time, the outgas generated from the sintered paste is discharged from both end portions on the longitudinal direction side of the first groove 8 and both end portions of the second groove 104d. This outgas is discharged through the through hole 104e provided in the lead frame 104 at a location where the two semiconductor chips 103 are adjacent. Thereby, the first sintered bonding layer 2, the second sintered bonding layer 2b, and the sintered bonding layer 2a are formed without the lead frame 104 being lifted or the position of the semiconductor chip 103 being displaced due to the pressure of the outgas, and the substrate 11, the semiconductor chip 103, and the lead frame 104 are joined as described above.

[0054] (Step 7) Next, as shown in FIG. 16, wire bonding such as an aluminum wire is performed on the control electrode 108 and the voltage monitor electrode 109 on the surface of the semiconductor chip 103 to connect the wiring 401. After that, the entire device may be sealed with an insulating resin. Through the above steps, the manufacture of the basic parts of the semiconductor device 100 can be realized.

[0055] 《Function and Effect》 According to the semiconductor device 100 and its manufacturing method of the first embodiment, the following respective functions and effects can be achieved. First, as shown in FIG. 4, each first groove 8 and each second groove 104d have different groove length directions and intersect. In the example of FIG. 4, the first groove 8 has the vertical direction in FIG. 4 as the length direction, while the length direction of the second groove 104d is inclined about 45° to the right. Therefore, the surfaces of the control electrode 108, the voltage monitor electrode 109, etc. are less likely to be exposed to the outgas generated in the volatilization process and the sintering reaction process in the seventh step, particularly the outgas generated from the second groove 104d. Thus, a film caused by the outgas is less likely to be formed on these surfaces. Therefore, it is less likely to hinder the formation of the wiring 401 by wire bonding on these members.

[0056] Therefore, since it is not necessary to consider the influence of outgassing on wire bonding, the second groove 104d can be sufficiently formed also in the left region 402 in FIG. 4 of the convex portion 104c. As a result, the second groove 104d can be sufficiently formed also in the region 402, and an extra sintering paste can be sufficiently accommodated in the second groove 104d, so that the second sintered bonding layer 2b can be made thin. Therefore, the bonding between the semiconductor chip 103 and the lead frame 104 by the first sintered bonding layer 2 can be strengthened.

[0057] That is, an extra sintering paste can be released into the second groove 104d to form a thin second sintered bonding layer 2b between the semiconductor chip 103 and the lead frame 104, and the outgassing can be easily guided to the outside through the second groove 104d. Therefore, the density of pores in the thin second sintered bonding layer 2b can be reduced. Where two semiconductor chips 103 are adjacent to each other, the outgassing is discharged through the through hole 104e provided in the lead frame 104, and the lead frame 104 is prevented from being lifted or the position of the semiconductor chip 103 from being displaced by the pressure of the outgassing. As a result, the reliability of the bonding between the semiconductor chip 103 and the lead frame 104 in the high-temperature environment in the seventh step is improved, and further, the thermal resistance in the second sintered bonding layer 2b can be reduced to enhance the heat dissipation performance.

[0058] Therefore, according to the first embodiment, the practicality and durability of the semiconductor device 100 as a product can be improved.

[0059] Further, by deepening the first groove 8 below the central portions RCEx and RCEy of the bonding region RCH of the semiconductor chip 103, a sufficient storage capacity for the surplus sintering paste can be ensured. As a result, the first sintered bonding layer 2 between the semiconductor chip 103 and the substrate 11 does not become excessively thick and can maintain a predetermined thickness, so that stress relaxation to the semiconductor chip 103 when the semiconductor device 100 is cooled from the sintering treatment temperature to room temperature in the seventh step can be achieved. Further, since the substrate 11 is less likely to warp, a base 7 without warping can be adopted.

[0060] Furthermore, as shown in FIG. 8, since the outer side ROy of the first groove 8 is not covered by the semiconductor chip 103 and is released, outgassing OG is likely to be released. Therefore, the density of pores in the first sintered bonding layer 2 can be reduced. As a result, even when the seventh step is performed in a high-temperature environment, the reliability of the bonding between the substrate 11 and the semiconductor chip 103 is improved, and the thermal resistance in the first sintered bonding layer 2 can be reduced to enhance heat dissipation.

[0061] Also, as a method for forming the first groove 8, for example, cutting using a diamond blade saw is preferable. In this case, a sintered film is formed on the cutting marks formed on the side walls of the first groove 8 to obtain an anchor effect. Thereby, interfacial peeling of the surplus portion 12 formed in the first groove 8 can be suppressed, and furthermore, it is possible to cope with an increase in the large area of the chip size of the semiconductor chip 103.

[0062] [Embodiment 2] In each of the embodiments described below, for members and the like that are common to Embodiment 1, the same reference numerals as those in the corresponding embodiment are used, and detailed descriptions thereof are omitted.

[0063] Embodiment 2 will be described. FIG. 17 is a longitudinal sectional view taken along line B-B of FIG. 6. In the present Embodiment 2, the depth of each first groove 8 is the same as that in Embodiment 1. What is different between the present Embodiment 2 and Embodiment 1 is the groove width of the first groove 8 (grooves 8a to 8j in FIG. 17). In the present Embodiment 2, the groove widths of the plurality of first grooves 8 are gradually expanded from the central portion RCEx to the end portion ROEx of the semiconductor chip 103. Groove 8a has a width w1 and a depth d1. Groove 8b has a width w2 and a depth d2. Groove 8c has a width w3 and a depth d3. Groove 8d has a width w4 and a depth d4. Groove 8e has a width w5 and a depth d5. Groove 8f has a width w6 and a depth d6. Groove 8g has a width w7 and a depth d7. Groove 8h has a width w8 and a depth d8. Groove 8i has a width w9 and a depth d9. Groove 8j has a width w10 and a depth d10. The depth from groove 8a to groove 8e satisfies the following formula (8), and is gradually widened from the center RCEx of the bonding region RCH to the end ROEx side. [Number]

[0064] The depth from groove 8f to groove 8j satisfies the following formula (9), and is gradually widened from the center RCEx of the bonding region RCH to the end ROEx side. [Number]

[0065] As a result, since the width of the first groove 8 is narrow at the center RCEx of the semiconductor chip 103, the area of the first sintered bonding layer 2 can be relatively enlarged. Thereby, the thermal resistance at the central portion RCEx which is the heat generation center can be reduced.

[0066] On the other hand, as shown by formulas (6) and (7), the depth of the plurality of first grooves 8 gradually becomes shallower from the central portion RCEx to the end portion ROEx of the semiconductor chip 103. That is, even for the first groove 8 having a narrow width, by increasing the depth as in grooves 8e and 8f, it is possible to sufficiently accommodate the surplus amount of the sintered paste.

[0067] Similarly, in the second groove 104d, the same effect can be obtained by setting the same width. At least one of the plurality of first grooves 8 and the second grooves 104d may have a wider width at the end portion side than at the central portion side of the bonding region. At least one of the plurality of first grooves 8 and the second grooves 104d may be gradually widened from the central portion to the end portion side of the bonding region.

[0068] [Embodiment 3] FIG. 18 is an enlarged view of Embodiment 3 corresponding to part D of FIG. 7. The difference between this Embodiment 3 and Embodiment 1 is that the outlet portion 31 of the first groove 8 has a shape that gradually expands outward. According to the third embodiment, in the above manufacturing process, the outlet portion 31 can facilitate the escape of outgassing from the inside of the first groove 8. Further, the outlet portion 31 can suppress stress concentration before and after the heating process in the seventh step. Furthermore, cracks in the semiconductor chip 103 can be suppressed.

[0069] As a method for forming the first groove 8, for example, cutting using a diamond blade saw (Dual type) is preferable. In this case, first, a V-shaped groove is formed in the substrate conductor 102, and then a rectangular deep groove is machined in the groove, whereby the first groove 8 having the outlet portion 31 on the side near the semiconductor chip 103 can be formed. In this case, a sintered film is formed on the cutting marks formed on the side walls in the first groove 8, and an anchor effect is obtained. Similarly, in the second groove 104d, the same effect can be obtained by making the shape of the outlet portion the same. At least one of the plurality of first grooves 8 and second grooves 104d may have an outlet side portion that gradually expands outward.

[0070] Note that the present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. For example, the concept of the groove depth and groove width of the first groove 8 in Embodiment 1 or Embodiment 2 may also be applied to the second groove 104d.

[0071] Also, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is also possible.

[0072] Hereinafter, the configuration and effects of the present invention will be described.

[0073] [1] A substrate, The semiconductor chip (103) mounted on the substrate (11), The lead frame (104) mounted on the substrate (11), A first sintered bonding layer (2) that joins the substrate conductor (102) of the substrate (11) and the semiconductor chip (103), A second sintered bonding layer (2b) that joins the semiconductor chip (103) and the lead frame (104), A plurality of first grooves (8) formed at the joint portion with the semiconductor chip (103) on the substrate (11), A plurality of second grooves (104d) formed at the joint portion of the lead frame (104) with the semiconductor chip (103), and The first groove (8) and the second groove (104d) have different groove length directions, A through hole (104e) penetrating the lead frame is formed in a portion of the lead frame (104) sandwiched between two or more joint surfaces, A semiconductor device characterized by the above.

[0074] Outgassing is discharged from the holes penetrating the lead frame, and the lead frame (104) will not float up or the position of the semiconductor chip (103) will not shift due to the pressure of the outgassing. Thereby, the practicality and durability of the semiconductor device as a product can be improved.

[0075] [2] The semiconductor device according to claim 1, wherein at least one of the plurality of first grooves (8) and the second grooves (104d) has different groove depths on the central portion (RCEx, RCEy) side and the end portion (ROEx, ROEy) side of the joint region (RCH) joined to the semiconductor chip (103).

[0076] As a result, it is possible to sufficiently secure the storage capacity for the surplus sintering paste. Therefore, the first sintering bonding layer (2) or the second sintering bonding layer (2b) can maintain a predetermined thickness and strengthen the bonding. And it is possible to relieve the stress on the semiconductor chip (103) when the semiconductor device (100) is cooled from the sintering treatment temperature to room temperature.

[0077] [3] The semiconductor device according to claim 2, wherein at least one of the plurality of first grooves (8) and the second grooves (104d) is shallower on the end portion (ROEx, ROEy) side than on the central portion (RCEx, RCEy) side of the bonding region (RCH).

[0078] As a result, the bonding by the first sintering bonding layer (2) or the second sintering bonding layer (2b) can be strengthened.

[0079] [4] The semiconductor device according to claim 3, wherein at least one of the plurality of first grooves (8) and the second grooves (104d) is wider on the end portion (ROEx, ROEy) side than on the central portion (RCEx, RCEy) side of the bonding region (RCH).

[0080] As a result, the bonding by the first sintering bonding layer (2) or the second sintering bonding layer (2b) can be strengthened.

[0081] [5] The semiconductor device according to claim 1, wherein at least one of the plurality of first grooves (8) and the second grooves (104d) has an outlet portion (31) that gradually expands outward.

[0082] The outlet portion (31) can make it easier to release outgases from the first groove (8) or the second groove (104d). Also, the outlet portion (31) can suppress stress concentration before and after the heating step in the seventh step. Furthermore, cracks in the semiconductor chip 103 can be suppressed.

[0083] [6] At least one of the plurality of the first grooves (8) and the second grooves (104d) gradually becomes shallower from the ones on the central part (RCEx, RCEy) side of the bonding region (RCH) toward the ones on the end part (ROEx, ROEy) side. The semiconductor device according to claim 3, characterized by this.

[0084] Thereby, the bonding by the first sintered bonding layer (2) or the second sintered bonding layer (2b) can be strengthened.

[0085] [7] At least one of the plurality of the first grooves (8) and the second grooves (104d) gradually becomes wider from the ones on the central part (RCEx, RCEy) side of the bonding region (RCH) toward the ones on the end part (ROEx, ROEy) side. The semiconductor device according to claim 4, characterized by this.

[0086] Thereby, the bonding by the first sintered bonding layer (2) or the second sintered bonding layer (2b) can be strengthened.

[0087] [8] At least one of the plurality of the first grooves (8) and the second grooves (104d) extends to the outside (ROx, ROy) of the bonding region (RCH) that is bonded to the semiconductor chip (103). The semiconductor device according to claim 1, characterized by this.

[0088] Thereby, outgas can be discharged through at least one of the outsides of the first groove and the second groove.

[0089] [9] The semiconductor chip includes a circuit element of a power conversion device that performs power conversion. The semiconductor device according to claim 1, characterized by this.

[0090] Thereby, even for a circuit element of a power conversion device that performs power conversion with a large amount of heat generation, the practicality and durability as a product can be improved.

[0091]

[10] The circuit element includes at least one of an IGBT, a MOSFET, and a diode, and the semiconductor device according to claim 9 is characterized by this.

[0092] Thereby, even if it is any one of an IGBT, a MOSFET, and a diode with a large calorific value, the practicality and durability as a product can be improved.

Explanation of Signs

[0093] 1 Semiconductor device 2 First sintered joint layer 2a Sintered joint layer 2b Second sintered joint layer 5 Metal layer 6 Base joint layer 7 Base 8 First groove 10 Semiconductor module 11 Substrate 12 Surplus 20 Second support member 22 Electrode 30 Semiconductor chip 30a One side 31 Outlet portion 50 Upper layer joint member 51 Pre-joint layer 100 Semiconductor device 101 Insulating substrate 102 Substrate conductor 102a Floating wiring 103 Semiconductor chip 103a Electrode surface 104 Lead frame 104a First connection point 104b Second connection point 104c Protrusion 104d Second groove 104e Through hole RCH Joint region RO Outer side RCEx Central part ROEx End part

Claims

1. A substrate; A semiconductor chip mounted on the substrate; a lead frame mounted on the substrate; a first sintered bonding layer bonding a substrate conductor of the substrate and the semiconductor chip; a second sintered bonding layer bonding the semiconductor chip and the lead frame; a plurality of first grooves formed on the substrate at a bonding portion with the semiconductor chip; a plurality of second grooves formed in a joint portion of the lead frame with the semiconductor chip; The first groove and the second groove have different groove length directions, a hole penetrating the lead frame is formed in a portion of the lead frame sandwiched between two or more bonding surfaces; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein at least one of the plurality of first grooves and the plurality of second grooves has a different groove depth between a central side and an end side of a bonding area bonded to the semiconductor chip.

3. 3. The semiconductor device according to claim 2, wherein at least one of the plurality of first grooves and the plurality of second grooves is shallower on an end side of the junction region than on a central side of the junction region.

4. 4. The semiconductor device according to claim 3, wherein at least one of the plurality of first grooves and the plurality of second grooves is wider on an end side of the junction region than on a central side of the junction region.

5. 2. The semiconductor device according to claim 1, wherein at least one of the first grooves and the second grooves has an outlet portion that gradually widens outward.

6. 4. The semiconductor device according to claim 3, wherein at least one of the plurality of first grooves and the plurality of second grooves becomes gradually shallower from a center side of the junction region toward an end side thereof.

7. 5. The semiconductor device according to claim 4, wherein at least one of the plurality of first grooves and the plurality of second grooves gradually becomes wider from the grooves toward a center of the junction region toward an end of the junction region.

8. 2. The semiconductor device according to claim 1, wherein at least one of the first grooves and the second grooves extends to an outside of a bonding region bonded to the semiconductor chip.

9. 2. The semiconductor device according to claim 1, wherein the semiconductor chip includes circuit elements of a power conversion device that performs power conversion.

10. 10. The semiconductor device according to claim 9, wherein the circuit element includes at least one of an IGBT, a MOSFET, and a diode.

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