Semiconductor device

Abstract

To provide a semiconductor device capable of inhibiting a hump phenomenon from occurring in a drain current-gate voltage (Ids-Vgs) characteristic.SOLUTION: A semiconductor device 1 is provided including a chip 2 having a principal plane, a trench insulation structure 13 defining an active region 14n on the principal plane, a first conductivity type well region formed in the active region 14, a gate electrode 38 formed on the well region through a gate insulation film, a first impurity region 22n formed on one side in a first direction X with respect to the gate electrode 38, a first low concentration impurity region 25n formed between the first impurity region 22n and the trench insulation structure 13 at edge parts 15, 16 of the trench insulation structure 13 in a second direction Y, and a second impurity region 23n formed on the other side in the first direction X with respect to the gate electrode 38.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] For example, Patent Document 1 discloses a method for restricting the formation of divots in a shallow trench isolation (STI) structure. The method of Patent Document 1 includes steps of providing an oxide deposited in a trench formed in a silicon region, oxidizing an upper layer of the silicon region to form a thermal oxide layer on the upper surface of the silicon region, and selectively etching the thermal oxide with respect to the deposited oxide.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] One embodiment of the present disclosure provides a semiconductor device including a chip having a main surface, a trench insulating structure partitioning an active region on the main surface, a well region of a first conductivity type formed in the active region, a gate electrode formed on the well region via a gate insulating film, a first impurity region of a second conductivity type formed on one side in a first direction with respect to the gate electrode and extending in a second direction orthogonal to the first direction, a first low-concentration impurity region formed between the first impurity region and the trench insulating structure at an edge portion of the trench insulating structure in the second direction and having an impurity concentration lower than that of the first impurity region, and a second impurity region of a second conductivity type formed on the other side in the first direction with respect to the gate electrode and extending in the second direction.

Brief Description of the Drawings

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[0006] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0007] Hereinafter, the array direction of a plurality of transistors is defined as a first direction X, the direction orthogonal to the array direction is defined as a second direction Y, and the thickness direction of the chip 2 is defined as a third direction Z. The definitions of the first direction X, the second direction Y, and the third direction Z are not limited thereto.

[0008] [Outline of Semiconductor Device 1] FIG. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure. Referring to FIG. 1, the semiconductor device 1 is, for example, a composite device in which a plurality of elements are mounted on a common chip 2, and includes a CMOS area 3. A CMOS transistor 4 is formed in the CMOS area 3. Although not shown in FIG. 1, in addition to the CMOS area 3, the chip 2 may be formed with, for example, a DMOS area in which a DMOS transistor is formed, a bipolar area in which a bipolar transistor is formed, a passive element area in which passive elements such as a resistance element and a capacitor are formed, and the like.

[0009] In the CMOS area 3, as the CMOS transistor 4, for example, a low-voltage CMOS transistor 5, a medium-voltage CMOS transistor, and a high-voltage transistor may be formed. The low-voltage CMOS transistor 5 may be, for example, a CMOS transistor having a rated voltage of 1.0 V or more and 4.0 V or less. The medium-voltage CMOS transistor may be, for example, a CMOS transistor having a rated voltage of 4.0 V or more and 7.0 V or less. The high-voltage CMOS transistor may be, for example, a CMOS transistor having a rated voltage of 7 V or more and 60 V or less. The rated voltage may be defined within a range of the maximum allowable value of the voltage applied between the source and drain of each CMOS transistor. Further, the rated voltage of each CMOS transistor may be referred to as the breakdown voltage of each CMOS transistor 4.

[0010] Hereinafter, the structure of the low-voltage CMOS transistor 5, particularly the structure of the low-voltage n-channel transistor 6n, will be described in detail. However, the structure of the low-voltage n-channel transistor 6n can also be applied to the low-voltage p-channel transistor 6p, the medium-voltage CMOS transistor, and the high-voltage CMOS transistor.

[0011] <Structure of low-voltage n-channel transistor 6n> Figures 2 and 3 are enlarged plan views of the semiconductor device 1 in FIG. 1. For clarity, in FIGS. 1 and 2, the source low-concentration regions 25n, 25p and the drain low-concentration regions 26n, 26p are shown by hatching, and in FIG. 3, the silicide layer 47 is shown by hatching.

[0012] FIG. 4 is a diagram showing a cross section taken along line IV-IV in FIG. 2. FIG. 5 is a diagram showing a cross section taken along line V-V in FIG. 2. FIG. 6 is a diagram showing a cross section taken along line VI-VI in FIG. 2. FIG. 7 is a diagram showing a cross section taken along line VII-VII in FIG. 2. FIG. 8 is an enlarged view of the portion surrounded by the two-dot chain line VIII in FIG. 7. For clarity, in FIG. 6, the number of source contacts 52 is shown reduced.

[0013] As described above, the low-voltage CMOS transistor 5 includes a low-voltage p-channel transistor 6p and a low-voltage n-channel transistor 6n. The low-voltage p-channel transistor 6p and the low-voltage n-channel transistor 6n are formed on a common chip 2.

[0014] Referring to FIGS. 4 to 7, the chip 2 may include, in this embodiment, a semiconductor substrate 7 and an epitaxial layer 8 in this embodiment. The semiconductor substrate 7 may be a p-type silicon substrate. The impurity concentration of the semiconductor substrate 7 may be, for example, 1.0×10 13 cm -3 or more and 1.0×10 20 cm -3 or less. The semiconductor substrate 7 has a first main surface 9 and a second main surface 10 on the opposite side thereof. The first main surface 9 and the second main surface 10 may be alternatively referred to as the front surface and the back surface of the semiconductor substrate 7, respectively. The notations "p + ", "p - ", "n + ", "n" and "n - " in the drawings of the present application merely show the relative magnitude relationship of the respective impurity regions (semiconductor regions) containing p-type impurities or n-type impurities for convenience, and do not define a specific range of impurity concentrations.

[0015] The epitaxial layer 8 is formed on the semiconductor substrate 7. In this embodiment, the epitaxial layer 8 may be an n-type silicon semiconductor layer. The impurity concentration of the epitaxial layer 8 may be, for example, 1.0×10 13 cm -3 or more and 1.0×10 17 cm -3 or less. The epitaxial layer 8 may have a first main surface 11 and a second main surface 12 on the opposite side thereof. The first main surface 11 and the second main surface 12 may also be referred to as the front surface and the back surface of the epitaxial layer 8, respectively. The second main surface 12 of the epitaxial layer 8 may be a bonding surface with the first main surface 9 of the chip 2.

[0016] Referring to FIGS. 1 to 7, a trench insulation structure 13 for partitioning a region on the first main surface 11 of the epitaxial layer 8 into a plurality of active regions is formed in the epitaxial layer 8. The trench insulation structure 13 may also be referred to as an element isolation portion. Referring to FIG. 1, the trench insulation structure 13 partitions an LV-active region 14 for a low-voltage CMOS transistor 5 on the first main surface 11 of the epitaxial layer 8. The LV-active region 14 includes a p-side active region 14p for a low-voltage p-type channel transistor 6p and an n-side active region 14n for a low-voltage n-type channel transistor 6n.

[0017] The p-side active region 14p and the n-side active region 14n are adjacent to each other with the trench insulation structure 13 therebetween in the first direction X. The p-side active region 14p and the n-side active region 14n may be formed in a rectangular shape of the same size that is longitudinally in the second direction Y in a plan view as seen from the normal direction of the first main surface 11.

[0018] Referring to FIGS. 6 and 7, the n-side active region 14n may have a first edge portion 15 on one side, a second edge portion 16 on the opposite side, and a central portion 17 between the first edge portion 15 and the second edge portion 16 in the second direction Y. There may be no distinct boundary between the first edge portion 15 and the second edge portion 16 and the central portion 17.

[0019] For example, in the n-side active region 14n, the regions occupied by the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n, which will be described later, are the first edge portion 15 and the second edge portion 16, and the region sandwiched between the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n of the first edge portion 15 and the second edge portion 16 may be the central portion 17.

[0020] Also, the range from 0.1 μm or more to 1.0 μm or less inward in the second direction Y from the boundary 18 between the n-side active region 14n and the trench insulating structure 13 may be the first edge portion 15 and the second edge portion 16, and the other portion may be the central portion 17. Since the first edge portion 15 and the second edge portion 16 are formed at the periphery of the n-side active region 14n, they may be respectively referred to as the first active peripheral region and the second active peripheral region.

[0021] Referring to FIGS. 4 to 8, in this embodiment, the trench insulating structure 13 includes a trench 19 formed in the epitaxial layer 8 and an embedded insulator 20 embedded in the trench 19.

[0022] The side wall of the trench 19 may be a plane orthogonal to the first main surface 11 of the epitaxial layer 8 as shown in FIGS. 4 to 7, or may be a plane inclined with respect to the first main surface 11 of the epitaxial layer 8 as shown in FIG. 8. In the case of FIG. 8, the trench 19 may have a tapered shape in which the width becomes narrower from the first main surface 11 toward the bottom wall in the third direction Z in a cross-sectional view.

[0023] The embedded insulator 20 may be, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), or the like. In this embodiment, the embedded insulator 20 is made of silicon oxide. The embedded insulator 20 exposes the open end of the trench 19. Also, the trench insulating structure 13 may be referred to as STI (Shallow Trench Isolation) as a general name.

[0024] In the surface layer portion of the epitaxial layer 8, a p-type well 21 for a low breakdown voltage n-type channel transistor 6n is formed. The impurity concentration of the p-type well 21 is higher than the impurity concentration of the epitaxial layer 8. For example, it may be 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The impurity concentration of the p-type well 21 may be constant in the second direction Y from one boundary 18 to the other boundary 18. For example, the p-type well 21 does not have to have a region where the impurity concentration is low (for example, a region where the impurity concentration is 10 to 100 times or more lower than the central portion of the p-type well 21) in the vicinity of the boundary 18.

[0025] A low breakdown voltage n-type channel transistor 6n is formed in the p-type well 21. In this form, an example in which the p-type well 21 is formed in the epitaxial layer 8 is shown. However, for example, an n-type well having an impurity concentration higher than that of the epitaxial layer 8 may be formed in the epitaxial layer 8, and the p-type well 21 may be formed in the surface layer portion of the n-type well.

[0026] In the surface layer portion of the p-type well 21, an n-type source region 22n (first impurity region) and an n-type drain region 23n (second impurity region) are formed at intervals from each other. The impurity concentrations of the n-type source region 22n and the n-type drain region 23n are higher than the impurity concentration of the p-type well 21. For example, it may be 1.0×10 19 cm -3 or more and 1.0×10 21 cm -3 or less.

[0027] The n-type source region 22n and the n-type drain region 23n are formed at the same depth from the first main surface 11. In FIG. 1, as the structures of the low breakdown voltage p-type channel transistors 6p corresponding to the n-type source region 22n and the n-type drain region 23n, a p-type source region 22p and a p-type drain region 23p are shown, respectively.

[0028] In this form, a pair of n-type source regions 22n and n-type drain regions 23n are formed at intervals in the first direction X. Referring to FIGS. 1 and 2, the pair of n-type source regions 22n and n-type drain regions 23n extend parallel to each other along the second direction Y. The pair of n-type source regions 22n and n-type drain regions 23n may be formed in a rectangular shape of the same size that is long along the second direction Y in a plan view. Referring to FIGS. 4 and 7, the region sandwiched between the n-type source region 22n and the n-type drain region 23n in the p-type well 21 is a channel region 24 where a channel of the transistor is formed.

[0029] In this form, an n-type source low-concentration region 25n and an n-type drain low-concentration region 26n that extend integrally from each of the n-type source region 22n and the n-type drain region 23n are further formed in the n-side active region 14n. The impurity concentrations of the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n are lower than the impurity concentrations of the n-type source region 22n and the n-type drain region 23n. For example, they may be 1.0×10 18 cm -3 or more and 1.0×10 20 cm -3 or less. The n-type source low-concentration region 25n and the n-type drain low-concentration region 26n may be respectively referred to as an n-type source LDD (Lightly Doped Drain) region and an n-type drain LDD region.

[0030] Note that in FIG. 1, as the structures of the low-voltage p-type channel transistors 6p corresponding to the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n, a p-type source low-concentration region 25p and a p-type drain low-concentration region 26p are respectively shown.

[0031] Referring to FIG. 2, the n-type source low-concentration region 25n extends in both the first direction X and the second direction Y from the n-type source region 22n in a plan view. More specifically, the n-type source low-concentration region 25n selectively extends from the n-type source region 22n toward the n-type drain region 23n in the first direction X and extends to both sides toward the trench insulating structure 13 in the second direction Y.

[0032] Accordingly, the n-type source low-concentration region 25n integrally includes a pair of first portions 27n linearly formed along the first direction X at the first edge portion 15 and the second edge portion 16, and a second portion 28n linearly formed along the second direction Y connecting the pair of first portions 27n. The n-type source region 22n is surrounded by the n-type source low-concentration region 25n from three sides by the pair of first portions 27n and the second portion 28n in a plan view.

[0033] Referring to FIGS. 4 and 6, in a cross-sectional view, the n-type source low-concentration region 25n is formed deeper than the n-type source region 22n and is distributed over the entire lower region of the n-type source region 22n. Accordingly, the side and bottom portions of the n-type source region 22n are covered by the n-type source low-concentration region 25n, preventing contact with the p-type well 21. Note that the n-type source low-concentration region 25n may be formed shallower than the n-type source region 22n. In this case, the n-type source region 22n may be in contact with the p-type well 21.

[0034] Referring to FIG. 6, in a cross-sectional view, the n-type source low-concentration region 25n includes a first edge low-concentration portion 29n and a second edge low-concentration portion 30n formed at the first edge portion 15 and the second edge portion 16, respectively. The first edge low-concentration portion 29n and the second edge low-concentration portion 30n correspond to the aforementioned first portions 27n.

[0035] The n-type source low-concentration region 25n further extends in the second direction Y in the region below the n-type source region 22n, and includes a central low-concentration portion 31n that connects the first-edge low-concentration portion 29n and the second-edge low-concentration portion 30n. The central low-concentration portion 31n is integrally formed with the first-edge low-concentration portion 29n and the second-edge low-concentration portion 30n. Thereby, the side portion and the bottom portion of the n-type source region 22n are surrounded by the first-edge low-concentration portion 29n, the second-edge low-concentration portion 30n, and the central low-concentration portion 31n. In other words, the n-type source region 22n may be formed in a floating state on the surface layer portion of the n-type source low-concentration region 25n so as to be spaced apart from the bottom portion and the periphery of the n-type source low-concentration region 25n.

[0036] Referring to FIG. 2, the n-type drain low-concentration region 26n is formed to extend in both the first direction X and the second direction Y from the n-type drain region 23n in a plan view. More specifically, the n-type drain low-concentration region 26n selectively extends from the n-type drain region 23n toward the n-type source region 22n in the first direction X and extends to both sides toward the trench insulating structure 13 in the second direction Y.

[0037] Thereby, the n-type drain low-concentration region 26n integrally includes a pair of first portions 32n linearly formed along the first direction X at the first-edge portion 15 and the second-edge portion 16, and a second portion 33n that connects the pair of first portions 32n and is linearly formed along the second direction Y. The n-type drain region 23n is surrounded by the n-type drain low-concentration region 26n from three sides by the pair of first portions 32n and the second portion 33n in a plan view.

[0038] Referring to FIG. 4, the n-type drain low-concentration region 26n is formed deeper than the n-type drain region 23n in a cross-sectional view and is distributed over the entire lower region of the n-type drain region 23n. Therefore, the side and bottom portions of the n-type drain region 23n are covered by the n-type drain low-concentration region 26n, preventing contact with the p-type well 21. Note that the n-type drain low-concentration region 26n may be formed shallower than the n-type drain region 23n. In this case, the n-type drain region 23n may be in contact with the p-type well 21.

[0039] In a cross-sectional view, the n-type drain low-concentration region 26n includes a first edge low-concentration portion 34n and a second edge low-concentration portion 35n formed on the first edge portion 15 and the second edge portion 16, respectively. The first edge low-concentration portion 34n and the second edge low-concentration portion 35n correspond to the aforementioned first portion 32n.

[0040] The n-type drain low-concentration region 26n further includes a central low-concentration portion 36n that extends in the second direction Y in the lower region of the n-type drain region 23n and connects the first edge low-concentration portion 34n and the second edge low-concentration portion 35n. The central low-concentration portion 36n is integrally formed with the first edge low-concentration portion 34n and the second edge low-concentration portion 35n. As a result, the side and bottom portions of the n-type drain region 23n are surrounded by the first edge low-concentration portion 34n, the second edge low-concentration portion 35n, and the central low-concentration portion 36n. In other words, the n-type drain region 23n may be formed in a floating state on the surface layer portion of the n-type drain low-concentration region 26n so as to be spaced apart from the bottom and periphery of the n-type drain low-concentration region 26n.

[0041] In the n-side active region 14n, an n-side planar gate structure 37n is formed on the first main surface 11 of the epitaxial layer 8. In FIG. 1, a p-side planar gate structure 37p is shown as the structure of the low-voltage p-type channel transistor 6p corresponding to the n-side planar gate structure 37n. The n-side planar gate structure 37n is formed on the first main surface 11. The n-side planar gate structure 37n crosses the n-side active region 14n in the second direction Y and has both ends on the trench insulating structure 13. In the first direction X, an n-type source region 22n is disposed on one side of the n-side planar gate structure 37n, and an n-type drain region 23n is disposed on the other side.

[0042] The n-side planar gate structure 37n includes a gate electrode 38, a gate insulating film 39, and sidewalls 40.

[0043] The gate electrode 38 has a rectangular shape (linear shape) in plan view that crosses the n-side active region 14n in the second direction Y. Referring to FIGS. 4 and 5, the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n are formed self-aligned with respect to the gate electrode 38. Also, the n-type source region 22n and the n-type drain region 23n are formed on one side and the other side of the gate electrode 38 in the first direction X, respectively, and are formed line-symmetric with respect to the gate electrode 38. The gate electrode 38 is made of, for example, polysilicon in this form, but may be composed of a metal material such as aluminum (Al).

[0044] The gate electrode 38 includes a gate main body portion 41 and a gate edge portion 42. The gate main body portion 41 and the gate edge portion 42 integrally constitute the gate electrode 38. The gate main body portion 41 and the gate edge portion 42 are distinguished from each other by a gate boundary 43 that crosses the gate electrode 38 along the first direction X. This gate boundary 43 coincides with the extension line in the first direction X of the boundary between the n-type source region 22n and the n-type source low-concentration region 25n (first portion 27n) and the extension line in the first direction X of the boundary between the n-type drain region 23n and the n-type drain low-concentration region 26n (first portion 32n).

[0045] In this form, gate boundaries 43 are set at the ends on one side and the other side of the second direction Y in a rectangular shape in plan view. The outer rectangular region closer to the trench insulating structure 13 than this pair of gate boundaries 43 is the gate edge portion 42. On the other hand, the rectangular region sandwiched between the pair of gate boundaries 43 in the second direction Y is the gate main body portion 41. Therefore, the gate electrode 38 may have three regions of one gate edge portion 42, the gate main body portion 41, and the other gate edge portion 42 in order from one end to the other end in the second direction Y.

[0046] The gate main body portion 41 faces the central portion 17 of the n-side active region 14n and faces the channel region 24. The channel of the transistor is formed in the channel region 24 mainly by the electric field from the gate main body portion 41.

[0047] The gate edge portion 42 is adjacent to the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n in the first direction X and is sandwiched between them. Referring to FIG. 7, the gate edge portion 42 further crosses the boundary 18 in the second direction Y and is partially disposed on the trench insulating structure 13.

[0048] The gate insulating film 39 is formed between the gate electrode 38 and the first main surface 11. The gate insulating film 39 may include a silicon oxide film. The gate insulating film 39 preferably includes a silicon oxide film made of the oxide of the epitaxial layer 8.

[0049] Referring to FIG. 8, the cross-sectional structure of the n-side planar gate structure 37n at the first edge portion 15 and the second edge portion 16 of the n-side active region 14n will be described in detail. In FIG. 8, the structure at the first edge portion 15 among the first edge portion 15 and the second edge portion 16 is shown as an example, but the structure of the first edge portion 15 can also be applied to the second edge portion 16. Further, the structure of the first edge portion 15 can also be applied to both ends in the first direction X of the n-side active region 14n.

[0050] In the vicinity of the first edge portion 15 of the n-side active region 14n, a depression 44 is selectively formed in the embedded insulator 20. The depression 44 is a depression 44 generated due to a cleaning process (light etching with a hydrofluoric acid solution, etc.) performed each time before the thermal oxidation process for forming the gate insulating film 39. The depression 44 may be referred to as a divot. The depression 44 may be continuously formed over the entire periphery of the n-side active region 14n so as to surround the n-side active region 14n.

[0051] The gate insulating film 39 covers the opening end of the trench 19 so as to be integrally connected to the embedded insulator 20 within the depression 44. At the boundary portion 45 between the embedded insulator 20 and the gate insulating film 39 in the vicinity of the depression 44, a prominent thin film portion 46 is formed in the gate insulating film 39. For example, the thickness T1 of the gate insulating film 39 at the central portion 17 is 50 Å or more and 250 Å or less, and the thickness T2 of the thin film portion 46 is smaller than the thickness T1 of the gate insulating film 39 at the central portion 17. The thin film portion 46 causes leakage and leads to a decrease in the breakdown voltage of the gate insulating film 39. In addition, since the thin film portion 46 forms a region with a low threshold value partially, it leads to deterioration of the static characteristics (such as instability of the threshold value) of the low breakdown voltage n-type channel transistor 6n. Therefore, in this form, a structure is provided in which such deterioration of the static characteristics does not occur.

[0052] The gate electrode 38 (gate edge portion 42) covers the boundary portion 45 and the depression 44 of the embedded insulator 20, and may include an embedded portion 58 embedded in the depression 44. Thereby, the gate electrode 38 straddles both sides of the trench insulation structure 13 side and the n-side active region 14n side with respect to the boundary portion 45 at the first edge portion 15 of the n-side active region 14n.

[0053] The sidewall 40 is formed around the gate electrode 38. The sidewall 40 is continuously formed over the entire periphery of the gate electrode 38 so as to cover the side surface of the gate electrode 38. The sidewall 40 is, for example, silicon oxide (SiO 2) It may also be silicon nitride (SiN) or the like. Referring to FIG. 4, the n-type source region 22n and the n-type drain region 23n are formed self-aligned with respect to the sidewall 40. Further, the second portion 28n of the n-type source low-concentration region 25n and the second portion 33n of the n-type drain low-concentration region 26n are covered by the sidewall 40.

[0054] A silicide layer 47 is formed on the first main surface 11. Referring to FIG. 3, the silicide layer 47 covers the first main surface 11 in the n-type source region 22n and the n-type drain region 23n, and is formed so as to selectively expose the first main surface 11 in the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n. The silicide layer 47 can reduce the contact resistance to the n-type source region 22n and the n-type drain region 23n.

[0055] The silicide layer 47 is further formed so as to cover the upper surface of the gate body portion 41 of the gate electrode 38 and selectively expose the upper surface of the gate edge portion 42.

[0056] Thereby, the silicide layer 47 is formed in the same shape as the n-type source region 22n in plan view, and includes a source silicide layer 48 that covers the n-type source region 22n. Further, the silicide layer 47 is formed in the same shape as the n-type drain region 23n in plan view, and includes a drain silicide layer 49 that covers the n-type drain region 23n. Further, the silicide layer 47 is formed in the same shape as the gate body portion 41 in plan view, and includes a gate silicide layer 50 that covers the gate body portion 41. The source silicide layer 48, the drain silicide layer 49, and the gate silicide layer 50 are electrically and physically separated from each other.

[0057] The silicide layer 47 may be, for example, cobalt silicide, nickel silicide, titanium silicide, aluminum silicide, copper silicide, or the like.

[0058] On the first main surface 11 of the epitaxial layer 8, an interlayer insulating film 51 is formed. The interlayer insulating film 51 may be, for example, silicon oxide (SiO 2 ) or silicon nitride (SiN), etc. In this embodiment, the interlayer insulating film 51 is made of silicon oxide.

[0059] Source contacts 52, drain contacts 53, and gate contacts 54 are formed in the interlayer insulating film 51. These contacts 52 to 54 are embedded in the interlayer insulating film 51. The contacts 52 to 54 may be, for example, a metal material such as tungsten (W). Referring to FIGS. 1 and 2, a plurality of source contacts 52 and drain contacts 53 are formed at intervals along the second direction Y, respectively. A plurality of gate contacts 54 are formed at intervals along the first direction X.

[0060] Referring to FIGS. 4, 6, and 7, source wiring 55, drain wiring 56, and gate wiring 57 are formed on the interlayer insulating film 51. The wirings 55 to 57 may be, for example, a metal material such as aluminum (Al). The source wiring 55 is electrically connected to the n-type source region 22n via the source contact 52 and the source silicide layer 48. The drain wiring 56 is electrically connected to the n-type drain region 23n via the drain contact 53 and the drain silicide layer 49. The gate wiring 57 is electrically connected to the gate electrode 38 via the gate contact 54.

[0061] <Manufacturing Method of Semiconductor Device 1> FIG. 9A and FIGS. 9B to 17A and 17B are diagrams showing a part of the manufacturing process of semiconductor device 1 in the order of the process. FIG. 18 is a diagram showing a mask pattern used when forming the source / drain regions. Among FIGS. 9A and 9B to 17A and 17B, the figures with "A" appended to the figure number correspond to the cross-section of FIG. 4, and the figures with "B" appended to the figure number correspond to the cross-section of FIG. 5. Further, for clarity, in FIG. 18, the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n are shown by solid-line hatching, and the portion covered by the mask 59 is shown by broken-line hatching.

[0062] To manufacture the semiconductor device 1, for example, referring to FIGS. 9A and 9B, an n-type epitaxial layer 8 is grown on a p-type semiconductor substrate 7. Specifically, silicon crystals are epitaxially grown while adding an n-type impurity (for example, phosphorus). The thickness of the epitaxial layer 8 may be, for example, 0 μm or more and 20 μm or less.

[0063] Next, a trench insulating structure 13 is formed. For example, a hard mask (not shown) made of an insulating film such as a silicon nitride film (SiN) is formed on the first main surface 11 of the epitaxial layer 8. An opening corresponding to the region where the trench insulating structure 13 is to be formed is formed in the hard mask. Next, the epitaxial layer 8 is selectively etched by reactive ion etching (RIE) using the hard mask. Thereby, a trench 19 is formed. Next, for example, an insulating material is formed on the entire surface of the first main surface 11 of the epitaxial layer 8 by chemical vapor deposition (CVD), and then planarization is performed by chemical mechanical polishing (CMP). Thereby, a buried insulator 20 is formed, and an LV-active region 14 (n-side active region 14n) is defined in the epitaxial layer 8. Thereafter, the hard mask is removed.

[0064] Next, an impurity ion implantation process and an impurity ion diffusion process for forming the p-type well 21 or the like are performed. Specifically, p-type impurity ions are implanted into the formation region of the p-type well 21. At this stage, the impurity concentrations of p-type wells (not shown) such as medium-voltage CMOS transistors and high-voltage CMOS transistors other than the low-voltage n-type channel transistor 6n are the same as each other. Next, ion implantation is performed to adjust the impurity concentration on the outermost surface of the low-voltage n-type channel transistor 6n. This ion implantation is ion implantation for adjusting the gate threshold voltage Vth of the low-voltage n-type channel transistor 6n. Thereby, the p-type well 21 is formed.

[0065] Next, referring to FIGS. 10A and 10B, an n-side planar gate structure 37n is formed. Specifically, first, by thermally oxidizing the first main surface 11 of the epitaxial layer 8, a base insulating film (in this form, silicon oxide) is formed on the first main surface 11. Next, by the CVD method, a conductive material (in this form, polysilicon) is formed on the entire surface of the first main surface 11 of the epitaxial layer 8. Thereafter, the conductive material (conductive film) and the base insulating film are selectively etched away, so that the gate insulating film 39 and the gate electrode 38 are formed, and the n-side planar gate structure 37n is formed.

[0066] Next, referring to FIGS. 11A and 11B, an n-type source low-concentration region 25n and an n-type drain low-concentration region 26n are formed. In the n-side active region 14n, n-type impurity ions are implanted into the entire surface of the n-side active region 14n. The n-type impurity ions accelerated toward the n-side active region 14n are inhibited from being implanted into the lower region by the n-side planar gate structure 37n, and are selectively implanted into the outer region of the n-side planar gate structure 37n. Thereby, the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n are self-alignedly formed with respect to the n-side planar gate structure 37n.

[0067] Next, referring to FIGS. 12A and 12B, a sidewall 40 is formed. For example, by a CVD method, an insulating material (in this form, silicon oxide) is formed on the entire first main surface 11 of the epitaxial layer 8 so as to cover the n-side planar gate structure 37n. Next, by etching back this insulating material (insulating film), the sidewall 40 is formed by the insulating film remaining on the side surface of the gate electrode 38.

[0068] Next, referring to FIGS. 13A and 13B, an n-type source region 22n and an n-type drain region 23n are formed. Specifically, first, a mask 59 made of, for example, a photoresist is formed on the first main surface 11 of the epitaxial layer 8. Referring to FIG. 18 here, an opening 60 corresponding to the region where the n-type source region 22n and the n-type drain region 23n are to be formed is formed in the mask 59. In this form, the first edge portion 15 and the second edge portion 16 of the n-side active region 14n are covered by a strip-shaped region of the mask 59 extending in the first direction X.

[0069] Then, n-type impurity ions are selectively implanted into the n-side active region 14n through this mask 59. Thereby, an n-type source region 22n and an n-type drain region 23n are formed in the central portion 17 of the n-side active region 14n. On the other hand, since the ion implantation into the first edge portion 15 and the second edge portion 16 of the n-side active region 14n is inhibited by the mask 59, an n-type source low-concentration region 25n and an n-type drain low-concentration region 26n remain exposed on the first main surface 11 at the first edge portion 15 and the second edge portion 16.

[0070] Next, referring to FIGS. 14A and 14B, and FIGS. 15A and 15B, a silicide layer 47 is formed. Specifically, first referring to FIGS. 14A and 14B, a silicide block film 61 made of, for example, an insulating material (in this form, silicon oxide) is formed on the first main surface 11 of the epitaxial layer 8. An opening corresponding to the region where the silicide layer 47 is to be formed is selectively formed in the silicide block film 61. As a result, the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n exposed from the sidewall 40 are covered with the silicide block film 61.

[0071] Then, through the silicide block film 61, for example, by a sputtering method, a metal film 62 is formed on the first main surface 11 of the epitaxial layer 8. At this stage, as shown in FIG. 14A, in addition to the n-type source region 22n, the n-type drain region 23n, and the gate electrode 38 (gate main body 41), the metal film 62 is also formed on the sidewall 40 and the trench insulating structure 13. The metal film 62 is made of, for example, cobalt, nickel, titanium, aluminum, copper, etc., and in this form, cobalt is used.

[0072] Next, referring to FIGS. 15A and 15B, by heat-treating the epitaxial layer 8, the portion of silicon (including polysilicon) in contact with the metal film 62 changes to a metal silicide. On the other hand, the metal film 62 on the insulating film does not change and remains the original metal material. As a result, a source silicide layer 48 and a drain silicide layer 49 are formed on the n-type source region 22n and the n-type drain region 23n made of silicon, respectively, and a gate silicide layer 50 is formed on the gate electrode 38 (gate main body 41) made of polysilicon. On the other hand, the material of the metal film 62 on the sidewall 40 and the trench insulating structure 13 does not change. Thereafter, by chemical solution treatment, only the material of the metal film 62 on the selectively oxidized film (in this form, the sidewall 40 and the trench insulating structure 13) is selectively removed. At this time, the source silicide layer 48, the drain silicide layer 49, and the gate silicide layer 50 remain without being chemically solution-treated.

[0073] Next, referring to FIGS. 16A and 16B, an interlayer insulating film 51 is formed on the first main surface 11 of the epitaxial layer 8, for example, by a CVD method.

[0074] Thereafter, referring to FIGS. 17A and 17B, contact holes for contacts 52 to 54 are formed, and wirings 55 to 57 are formed.

[0075] Through the above steps, a semiconductor device 1 including a CMOS transistor 4 including a low breakdown voltage n-type channel transistor 6n, etc., and further a DMOS transistor, a bipolar transistor, a passive element, etc. is manufactured on a common semiconductor substrate 7.

[0076] <Effect of Semiconductor Device 1> According to the semiconductor device 1 according to the present disclosure, an n-type source region 22n and an n-type drain region 23n are not formed in the first edge portion 15 and the second edge portion 16 of the n-side active region 14n, and an n-type source low concentration region 25n and an n-type drain low concentration region 26n are formed. Thereby, the n-type impurity concentration in the vicinity of the depression 44 (see FIG. 8) of the trench insulating structure 13, which is a cause of the hump phenomenon, can be selectively suppressed to be low. Therefore, the gate threshold voltage Vth in the first edge portion 15 and the second edge portion 16 can be selectively increased.

[0077] As a result, even if a thin film portion 46 of the gate insulating film 39 is formed in the vicinity of the depression 44 as shown in FIG. 8, it is possible to suppress the formation of a channel in the first edge portion 15 and the second edge portion 16. Thereby, when a gate voltage is applied, a channel can be preferentially and stably formed in the channel region 24. As a result, it is possible to suppress the occurrence of a hump phenomenon in the drain current-gate voltage (Ids-Vgs) characteristics.

[0078] Furthermore, in the semiconductor device 1, in the n-side active region 14n, the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n are regions where the silicide layer 47 is not selectively formed. As a result, the sheet resistance of the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n is increased compared to the sheet resistance of the silicide layer 47 in the n-type source region 22n and the n-type drain region 23n. Therefore, the amount of current flowing from the source contact 52 through the source silicide layer 48 to the n-type source low-concentration region 25n can be suppressed. Similarly, the amount of current flowing from the drain contact 53 through the drain silicide layer 49 to the n-type drain low-concentration region 26n can be suppressed. As a result, the formation of channels in the first edge portion 15 and the second edge portion 16 can be further suppressed, so that the hump phenomenon can be effectively suppressed.

[0079] The hump phenomenon can be described with reference to FIG. 19. FIG. 19 is a diagram showing an example of the static characteristics of a transistor. In FIG. 19, the change in the drain current Ids with respect to the gate voltage Vgs when the source is grounded and the drain voltage Vds = 0.1 V is shown. The broken line indicates the characteristics when the hump phenomenon occurs, and the solid line indicates the characteristics when the hump phenomenon does not occur. The plurality of characteristic curves shown in FIG. 19 indicate the characteristics when the back gate voltage BGV is set to 0 V, -1 V, -2 V, -3 V, -4 V, and -5 V, respectively. From FIG. 19, it can be seen that the tendency of the hump phenomenon becomes more prominent as the back gate voltage BGV increases. The cause of the hump is that a thin film portion 46 (see FIG. 8) corresponding to the depression 44 is formed in the gate insulating film 39, and partial conduction occurs in the thin film portion 46.

[0080] From FIG. 19, it can be seen that without taking measures to form the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n, a phenomenon called hump occurs where multiple threshold values appear, and the tendency is more prominent as the back gate voltage BGV is higher. Note that FIG. 19 shows a characteristic example of a low-voltage p-type channel MOS transistor, but the same decrease also occurs in the aforementioned low-voltage n-type channel transistor 6n, medium-voltage CMOS transistor, high-voltage CMOS transistor, etc.

[0081] On the other hand, in the configuration of the semiconductor device 1, by forming the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n, the gate threshold voltage Vth at the first edge portion 15 and the second edge portion 16 can be selectively increased. Also, by not forming the silicide layer 47 on the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n, the current amount flowing into the n-type source low-concentration region 25n and the n-type drain low-concentration region 26n can be restricted. As a result, the hump phenomenon can be effectively suppressed.

[0082] Although the embodiments of the present disclosure have been described, the present disclosure can also be implemented in other forms.

[0083] For example, as shown in FIGS. 20 to 22, the gate electrode 38 may be formed in an annular shape in plan view, and an opening 63 may be formed at the center. In this form, an n-type source region 22 may be formed inside the opening 63, and an n-type drain region 23n may be formed around the n-type source region 22 (on both sides in the first direction X in FIG. 20).

[0084] For example, in the description of the above-described embodiments and the accompanying drawings, the n-type regions may be replaced with p-type regions, and the p-type regions may be replaced with n-type regions.

[0085] The embodiments of the present disclosure are illustrative in all respects and should not be construed in a limiting sense, and it is intended that changes are included in all respects.

[0086] The following features can be extracted from the description of this specification and the drawings.

[0087] [Appendix 1-1] A chip (2) having a main surface (11), A trench insulation structure (13) that partitions an active region (14n) on the main surface (11), A well region (21) of a first conductivity type formed in the active region (14n), A gate electrode (38) formed on the well region (21) via a gate insulating film (39), A second impurity region (22n) of a second conductivity type that is formed on one side of the gate electrode (38) in a first direction (X) and extends in a second direction (Y) orthogonal to the first direction (X), A first low-concentration impurity region (25n) that is formed between the first impurity region (22n) and the trench insulation structure (13) at an edge portion (15, 16) of the trench insulation structure (13) in the second direction (Y) and has an impurity concentration lower than that of the first impurity region (22n), A semiconductor device (1) including a second impurity region (23n) of a second conductivity type that is formed on the other side of the gate electrode (38) in the first direction (X) and extends in the second direction (Y).

[0088] [Appendix 1-2] A chip (2) having a main surface (11), A trench insulation structure (13) that partitions an active region (14n) on the main surface (11), A well region (21) of a first conductivity type formed in the active region (14n), A gate electrode (38) formed on the well region (21) via a gate insulating film (39), A second impurity region (22n) of a second conductivity type that is formed on one side of the gate electrode (38) in a first direction (X) and extends in a second direction (Y) orthogonal to the first direction (X), A first low-concentration impurity region (25n) is formed between the first impurity region (22n) and the trench insulating structure (13) at an edge portion (15, 16) of the trench insulating structure (13) in the second direction (Y), and the first low-concentration impurity region (25n) has an impurity concentration lower than that of the first impurity region (22n). A second impurity region (23n) of a second conductivity type, which is formed on the other side of the gate electrode (38) in the first direction (X) and extends in the second direction (Y). Including a silicide layer (47, 48, 49, 50) selectively formed on the active region (14n). The semiconductor device (1), wherein the silicide layers (47, 48, 49) cover the main surface (11) in the first impurity region (22n) and are formed to expose the main surface (11) in the first low-concentration impurity region (25n).

[0089] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-1 or 2, further including a second low-concentration impurity region (26n) formed between the second impurity region (23n) and the trench insulating structure (13) at an edge portion (15, 16) of the trench insulating structure (13) in the second direction (Y), and the second low-concentration impurity region (26n) has an impurity concentration lower than that of the second impurity region (23n).

[0090] [Appendix 1-4] Further including a silicide layer (47, 48, 49, 50) selectively formed on the active region (14n). The semiconductor device (1) according to Appendix 1-1, wherein the silicide layers (47, 48, 49) cover the main surface (11) in the first impurity region (22n) and are formed to expose the main surface (11) in the first low-concentration impurity region (25n).

[0091] [Appendix 1-5] The silicide layer (50) further covers the upper surface of the gate body portion (41) of the gate electrode (38) adjacent to the first impurity region (22n) in the first direction (X), and exposes the upper surface of the gate edge portion (42) of the gate electrode (38) adjacent to the first low-concentration impurity region (25n) in the first direction (X), and the semiconductor device (1) according to appended claim 1-2 or appended claim 1-4.

[0092] [Appended claim 1-6] The edge portions (15, 16) of the trench insulation structure (13) include an active peripheral region set with a width of 0.1 μm or more and 1.0 μm or less from the boundary (18) between the trench insulation structure (13) and the active region (14n) to the inside of the active region (14n), and the semiconductor device (1) according to any one of appended claims 1-1 to appended claim 1-5.

[0093] [Appended claim 1-7] The well region (21) has a constant impurity concentration from the boundary (18) with one trench insulation structure (13) in the second direction (Y) to the boundary (18) with the other trench insulation structure (13), and the semiconductor device (1) according to any one of appended claims 1-1 to appended claim 1-6.

[0094] [Appended claim 1-8] The gate electrode (38) is formed in a rectangular shape in plan view extending in the second direction (Y), and the semiconductor device (1) according to any one of appended claims 1-1 to appended claim 1-7.

[0095] [Appended claim 1-9] The first low-concentration impurity region (25n) integrally includes a pair of first portions (27n) formed along the first direction (X) at the edge portions (15, 16) of the trench insulation structures (13) on one side and the other side in the second direction (Y), and a second portion (28n) formed along the second direction (Y) in the vicinity of the gate electrode (38) connecting the pair of first portions (27n). The semiconductor device (1) according to Supplementary Note 1-8, wherein the first impurity region (22n) is surrounded by the pair of first portions (27n) and the second portion (28n) from three sides to form the first low-concentration impurity region (25n).

[0096] [Supplementary Note 1-10] further including a sidewall (40) formed on a side surface of the gate electrode (38), The semiconductor device (1) according to Supplementary Note 1-9, wherein the second portion (28n) of the first low-concentration impurity region (25n) is covered by the sidewall (40).

[0097] [Supplementary Note 1-11] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-10, wherein the first low-concentration impurity region (25n) integrally includes edge low-concentration portions (29n, 30n) formed between the first impurity region (22n) and each of the trench insulating structures (13) on one side and the other side in the second direction (Y), and a central low-concentration portion (31n) that extends in the second direction (Y) in a region below the first impurity region (22n) and connects the edge low-concentration portions (29n, 30n) on one side and the other side in the second direction (Y).

[0098] [Supplementary Note 1-12] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-11, wherein the first impurity region (22n) and the second impurity region (23n) are formed symmetrically with respect to the gate electrode (38) in the first direction (X).

[0099] [Supplementary Note 1-13] The trench insulating structure (13) includes a trench (19) formed on the main surface (11), an insulator (20) embedded in the main surface (11) so as to expose an opening end of the trench (19), and a depression (44) that is recessed toward a bottom wall of the trench (19) at an upper end portion of the insulator (20). The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-12, wherein the gate electrode (38) is formed so as to cover the depression (44).

[0100] [Supplementary Note 1-14] The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-13, wherein the first impurity region (22n) is a source region (22n) and the second impurity region (23n) is a drain region (23n).

[0101] [Supplementary Note 1-15] The active region (14n) includes a CMOS region (3) for a CMOS transistor (4), The semiconductor device (1) according to Supplementary Note 1-14, wherein the source region (22n) and the drain region (23n) are part of the CMOS transistor (4).

Explanation of Reference Numerals

[0102] 1: Semiconductor device 2: Chip 3: CMOS area 4: CMOS transistor 5: Low-voltage CMOS transistor 6n: Low-voltage n-channel transistor 6p: Low-voltage p-channel transistor 7: Semiconductor substrate 8: Epitaxial layer 9: First main surface 10: Second main surface 11: First main surface 12: Second main surface 13: Trench insulation structure 14: Active region 14n: n-side active region 14p: p-side active region 15: First edge portion 16: Second edge portion 17: Central portion 18: Boundary 19: Trench 20: Embedded insulator 21: p-type well 22: n-type source region 22n: n-type source region 22p: p-type source region 23n: n-type drain region 23p: p-type drain region 24: Channel region 25n: n-type source low concentration region 25p: p-type source low concentration region 26n: n-type drain low concentration region 26p: p-type drain low concentration region 27n: First part 28n: Second part 29n: First edge low concentration part 30n: Second edge low concentration part 31n: Central low concentration part 32n: First part 33n: Second part 34n: First edge low concentration part 35n: Second edge low concentration part 36n: Central low concentration part 37n: n-side planar gate structure 37p: p-side planar gate structure 38: Gate electrode 39: Gate insulating film 40: Sidewall 41: Gate body part 42: Gate edge part 43: Gate boundary 44: Depression 45: Boundary part 46: Thin film part 47: Silicide layer 48: Source silicide layer 49: Drain silicide layer 50: Gate silicide layer 51: Interlayer insulating film 52: Source contact 53: Drain contact 54: Gate contact 55: Source wiring 56: Drain wiring 57: Gate wiring 58: Embedded part 59: Mask 60: Opening 61: Silicide block film 62: Metal film 63: Opening

Claims

1. a chip having a major surface; a trench isolation structure defining an active area on said major surface; a well region of a first conductivity type formed in the active region; a gate electrode formed on the well region via a gate insulating film; a first impurity region of a second conductivity type formed on one side of the gate electrode in a first direction and extending in a second direction perpendicular to the first direction; a first low concentration impurity region formed between the first impurity region and the trench insulation structure at an edge portion of the trench insulation structure in the second direction, the first low concentration impurity region having an impurity concentration lower than that of the first impurity region; a second impurity region of a second conductivity type formed on the other side of the gate electrode in the first direction and extending in the second direction.

2. a chip having a major surface; a trench isolation structure defining an active area on said major surface; a well region of a first conductivity type formed in the active region; a gate electrode formed on the well region via a gate insulating film; a first impurity region of a second conductivity type formed on one side of the gate electrode in a first direction and extending in a second direction perpendicular to the first direction; a first low concentration impurity region formed between the first impurity region and the trench insulation structure at an edge portion of the trench insulation structure in the second direction, the first low concentration impurity region having an impurity concentration lower than that of the first impurity region; a second impurity region of a second conductivity type formed on the other side of the gate electrode in the first direction and extending in the second direction; a silicide layer selectively formed on the active region; the silicide layer is formed to cover the main surface in the first impurity region and to expose the main surface in the first low-concentration impurity region.

3. 3. The semiconductor device according to claim 1, further comprising a second low concentration impurity region formed between the second impurity region and the trench insulation structure at an edge portion of the trench insulation structure in the second direction, the second low concentration impurity region having an impurity concentration lower than that of the second impurity region.

4. a silicide layer selectively formed on the active region; 2. The semiconductor device according to claim 1, wherein said silicide layer is formed so as to cover said main surface in said first impurity region and to expose said main surface in said first low concentration impurity region.

5. 5. The semiconductor device according to claim 2, wherein the silicide layer is further formed to cover an upper surface of a gate body portion of the gate electrode adjacent to the first impurity region in the first direction and to expose an upper surface of a gate edge portion of the gate electrode adjacent to the first low concentration impurity region in the first direction.

6. 3. The semiconductor device according to claim 1, wherein the edge portion of the trench isolation structure includes an active peripheral region set with a width of 0.1 μm or more and 1.0 μm or less inside the active region from a boundary between the trench isolation structure and the active region.

7. 3. The semiconductor device according to claim 1, wherein the well region has a constant impurity concentration from a boundary with the trench insulating structure on one side to a boundary with the trench insulating structure on the other side in the second direction.

8. The semiconductor device according to claim 1 , wherein the gate electrode is formed in a rectangular shape in a plan view extending in the second direction.

9. the first lightly doped impurity region integrally includes a pair of first portions formed along the first direction at each of the edge portions of the trench insulating structure on one side and the other side in the second direction, and a second portion connecting the pair of first portions and formed along the second direction in the vicinity of the gate electrode, 9. The semiconductor device according to claim 8, wherein said first impurity region is surrounded on three sides by said first low concentration impurity region and said pair of first portions and said second portion.

10. The gate electrode further includes a sidewall formed on a side surface thereof, 10. The semiconductor device according to claim 9, wherein said second portion of said first low concentration impurity region is covered with said sidewall.

11. 3. The semiconductor device according to claim 1, wherein the first low concentration impurity region integrally includes edge low concentration portions formed between the first impurity region and each of the trench insulation structures on one side and the other side in the second direction, and a central low concentration portion extending in the second direction through a region below the first impurity region and connecting the edge low concentration portions on one side and the other side in the second direction.

12. 3. The semiconductor device according to claim 1, wherein the first impurity region and the second impurity region are formed line-symmetrically with respect to the gate electrode in the first direction.

13. the trench isolation structure includes a trench formed in the main surface, an insulator embedded in the main surface so as to expose an open end of the trench, and a recess recessed toward a bottom wall of the trench at an upper end of the insulator, 3. The semiconductor device according to claim 1, wherein said gate electrode is formed so as to cover said recess.

14. 3. The semiconductor device according to claim 1, wherein the first impurity region is a source region, and the second impurity region is a drain region.

15. the active area includes a CMOS area for a CMOS transistor; 15. The semiconductor device of claim 14, wherein the source region and the drain region are part of the CMOS transistor.

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