Semiconductor device

Abstract

To provide a semiconductor device capable of enhancing performance and an integration degree.SOLUTION: A semiconductor device according to the present invention, includes: a semiconductor substrate; and a first transistor that is positioned on the semiconductor substrate. The first transistor includes: an insulation structure that is positioned on the semiconductor substrate; a channel region that extends in a direction crossing the semiconductor substrate on a side surface of the insulation structure, and that is constituted of a semiconductor layer; a source and drain regions that are electrically connected to the channel region; a gate insulation layer that is positioned on the channel region; and a gate electrode that is positioned on the gate insulation layer. A first region as one of the source and the drain regions and a second region as another one of the source and the drain regions have mutually different materials or mutually different crystal structures.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and an electronic system including the same. [Background technology]

[0002] Semiconductor devices are widely used in various electronic industries because they can be miniaturized and perform various functions. As the electronics industry develops, research into technologies for improving the performance and integration of semiconductor devices is ongoing. For example, the integration of a semiconductor device can be improved by reducing the size of a plurality of circuit elements included in the semiconductor device. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a semiconductor device capable of improving performance and integration density, and an electronic system including the same. [Means for solving the problem]

[0004] A semiconductor device according to one embodiment of the present invention made to achieve the above object includes a semiconductor substrate and a first transistor located on the semiconductor substrate. The first transistor includes an insulating structure located on the semiconductor substrate, a channel region extending on a side of the insulating structure in a direction intersecting the semiconductor substrate and made of a first semiconductor layer, source and drain regions electrically connected to the channel region, a gate insulating layer located on the channel region, and a gate electrode located on the gate insulating layer. The first region, which is one of the source and drain regions, and the second region, which is the other of the source and drain regions, have different materials or different crystal structures.

[0005] A semiconductor device according to another aspect of the present invention, which has been made to achieve the above object, includes a semiconductor substrate and a plurality of transistors, including a first transistor and a second transistor, located on the semiconductor substrate and having different structures. The first transistor includes an insulating structure located on the semiconductor substrate, a channel region extending on a side surface of the insulating structure in a direction inclined or perpendicular to the semiconductor substrate and made of a first semiconductor layer, source and drain regions electrically connected to the channel region, a gate insulating layer located on the channel region, and a gate electrode located on the gate insulating layer. One of the source and drain regions is formed as a part of the semiconductor substrate.

[0006] In order to achieve the above object, an electronic system according to an embodiment of the present invention includes a main board, the above-mentioned semiconductor device located on the main board, and a controller electrically connected to the semiconductor device on the main board. Effect of the Invention

[0007] According to the present invention, the high-voltage transistor has a vertical structure (e.g., a vertical channel structure), thereby improving the integration degree. Also, the second region, which is one of the source and drain regions of the high-voltage transistor, is configured as a part of the semiconductor substrate, thereby improving the performance of the high-voltage transistor. [Brief description of the drawings]

[0008] [Figure 1] 1 is a partial cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment; [Diagram 2] 2 is an enlarged cross-sectional view showing an example of a channel structure included in the semiconductor device shown in FIG. 1. [Diagram 3] 2 is a partial cross-sectional view showing a schematic diagram of a circuit region included in the semiconductor device shown in FIG. [Figure 4] 2 is a partial cross-sectional view showing a schematic view of a part of a circuit region included in the semiconductor device shown in FIG. [Diagram 5]4 is a plan view showing a schematic diagram of high-voltage transistors and low-voltage transistors included in the circuit region shown in FIG. 3. [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] 11 is a cross-sectional view showing a part of a circuit region included in a semiconductor device according to another embodiment. [Figure 14] 11 is a cross-sectional view showing a part of a circuit region included in a semiconductor device according to another embodiment. [Figure 15] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a further embodiment. [Figure 16] 1 is a diagram illustrating an electronic system including a semiconductor device according to an exemplary embodiment; [Figure 17] 1 is a perspective view that illustrates a schematic diagram of an electronic system including a semiconductor device according to an exemplary embodiment. [Figure 18] 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. [Figure 19] 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, various embodiments will be described in detail with reference to the drawings so that those skilled in the art can easily carry out the embodiments. The embodiments may be implemented in various forms and are not limited to the embodiments described herein.

[0010] In order to clearly describe the present invention, parts that are not relevant to the description will be omitted, and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0011] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not limited to the drawings. For convenience of explanation and / or simple illustration, the thickness of some layers and regions are enlarged or exaggerated.

[0012] In addition, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, it does not only mean that it is "directly above" the other part, but also when there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in the middle. In addition, when a part is said to be "on" or "above" a reference part, it means that it is located above or below the reference part, and does not necessarily mean that it is located "above" or "above" the opposite direction of gravity.

[0013] Additionally, throughout the specification, when a part "comprises" a certain element, unless specifically stated to the contrary, it does not mean to exclude other elements, but rather to further include other elements.

[0014] Additionally, throughout the specification, "on a plane" or "when viewed from a plane" means when the subject part is viewed from above, and "on a cross section" or "when viewed from a cross section" means when the subject part is cut vertically and viewed from the side.

[0015] Hereinafter, a semiconductor device and a manufacturing method thereof according to one embodiment will be described in detail with reference to FIGS.

[0016] Fig. 1 is a schematic partial cross-sectional view of a semiconductor device 10 according to an embodiment, and Fig. 2 is an enlarged cross-sectional view of an example of a channel structure (CH) included in the semiconductor device 10 shown in Fig. 1. For clear understanding, the coordinates in Fig. 1 are shown centered on a portion corresponding to a cell array region 100, and the circuit region 200 is shown as a cross section taken along line A-A' in Fig. 5, regardless of the coordinates.

[0017] 1 and 2, a semiconductor device 10 according to an embodiment includes a cell region 100 in which a memory cell structure is provided, and a circuit region 200 in which a peripheral circuit structure for controlling the operation of the memory cell structure is provided. As an example, the circuit region 200 and the cell region 100 are parts corresponding to a first structure 1100F and a second structure 1100S of a semiconductor device 1100 included in an electronic system 1000 shown in FIG. 16, respectively. Alternatively, the circuit region 200 and the cell region 100 may be parts including a first structure 3100 and a second structure 3200 of a semiconductor chip 2200 shown in FIG. 18, respectively.

[0018] Here, the circuit region 200 includes a peripheral circuit structure formed on a first substrate 210, and the cell region 100 includes a gate stack structure 120 and a channel structure (CH) formed on a second substrate 110 as a memory cell structure. The circuit region 200 includes a first wiring unit 230, and the cell region 100 includes a second wiring unit 180 electrically connected to the memory cell structure.

[0019] In an exemplary embodiment, the cell region 100 is located above the circuit region 200. This eliminates the need to secure an area corresponding to the circuit region 200 separately from the cell region 100, thereby reducing the area of ​​the semiconductor device 10. However, the embodiment is not limited to this, and the circuit region 200 may be located next to the cell region 100. Various other modifications are possible.

[0020] The cell region 100 includes a cell array region 102 and a connection region 104. In the cell array region 102, a gate stack structure 120 and a channel structure (CH) are formed on a second substrate 110. Structures for connecting the gate stack structure 120 and / or the channel structure (CH) formed in the cell array region 102 to a circuit region 200 or an external circuit are located in the cell array region 102 and / or the connection region 104.

[0021] In one embodiment, the second substrate 110 includes a semiconductor layer including a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate made of a semiconductor material, or may be a semiconductor layer formed on a base substrate. For example, the second substrate 110 may be made of silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Here, the semiconductor layer included in the second substrate 110 is doped with p-type or n-type impurities. For example, the p-type impurities include boron (B), gallium (Ga), and the like, and the n-type impurities include phosphorus (P), arsenic (As), and the like. However, the embodiment is not limited to the material of the second substrate 110, the conductive type of the impurities doped into the semiconductor layer, and the material.

[0022] In the cell array region 102, a gate stack structure 120 including cell insulating layers 132 and gate lines 130 alternately stacked on one surface (for example, the front or top surface) of the second substrate 110, and a channel structure (CH) extending through the gate stack structure 120 in a direction intersecting the second substrate 110 (the Z-axis direction in the drawing) are formed.

[0023] In an exemplary embodiment, horizontal conductive layers 112, 114 are included between the second substrate 110 and the gate stack structure 120 in the cell array region 102, electrically connecting (for example, directly connecting) the channel structure (CH) and the second substrate 110. The horizontal conductive layers 112, 114 include a first horizontal conductive layer 112 and / or a second horizontal conductive layer 114 sequentially positioned on the second substrate 110. The first horizontal conductive layer 112 functions as a part of a common source line of the semiconductor device 10. For example, the first horizontal conductive layer 112 functions as a common source line together with the second substrate 110.

[0024] The first and second horizontal conductive layers 112, 114 may include a semiconductor material (e.g., polycrystalline silicon). For example, the first horizontal conductive layer 112 may include a polycrystalline silicon layer including impurities. The embodiment is not limited thereto, and the second horizontal conductive layer 114 may be composed of a different material (e.g., an insulating material) than the first horizontal conductive layer 112, or the second horizontal conductive layer 114 may not be provided.

[0025] A gate stack structure 120 in which cell insulating layers 132 and gate lines 130 are alternately stacked is located on the second substrate 110 (for example, on the first and second horizontal conductive layers 112, 114 formed on the second substrate 110).

[0026] The gate line 130 may include various conductive materials. For example, the gate line 130 may include metal materials such as tungsten (W), copper (Cu), aluminum (Al), polycrystalline silicon, metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or combinations thereof. As shown in the enlarged view of FIG. 2, a portion (e.g., first blocking layer 156a) of the blocking layer 156 made of an insulating material is located outside the gate line 130. The cell insulating layer 132 may include various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k material having a dielectric constant smaller than that of silicon oxide, or combinations thereof.

[0027] In one embodiment, a channel structure (CH) is formed to pass through the gate stack 120 and extend in a direction intersecting the second substrate 110 (for example, a vertical direction perpendicular to the second substrate 110) (Z-axis direction in the drawing).

[0028] The channel structure (CH) includes a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate line 130 and the channel layer 140. The channel structure (CH) further includes a core insulating layer 142 located inside the channel layer 140, but as another example, the core insulating layer 142 may not be provided. The channel structure (CH) further includes a channel pad 144 disposed on the channel layer 140 and / or the gate dielectric layer 150. The gate dielectric layer 150 located between the gate line 130 and the channel layer 140 includes a tunneling layer 152, a charge storage layer 154, and a blocking layer 156, which are sequentially formed on the channel layer 140.

[0029] Each channel structure CH forms one memory cell string, and a plurality of channel structures CH are arranged in rows and columns on a plane, spaced apart from each other. For example, a plurality of channel structures CH are arranged in various patterns, such as a lattice pattern or a zigzag pattern, on a plane. The channel structures CH have a columnar shape. As an example, the channel structures CH have inclined sides such that the width becomes narrower closer to the second substrate 110 according to the aspect ratio when viewed in cross section. However, the embodiment is not limited thereto, and the arrangement, structure, shape, etc. of the channel structures CH may be modified in various ways.

[0030] The channel layer 140 includes a semiconductor material, such as polycrystalline silicon. The core insulating layer 142 can include a variety of insulating materials. For example, the core insulating layer 142 can include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0031] The tunneling layer 152 includes an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) that allows tunneling of charges. The charge storage layer 154 is used as a data storage region, and includes polycrystalline silicon, silicon nitride, etc. The blocking layer 156 includes an insulating material that can prevent unwanted charges from flowing into the gate line 130. For example, the blocking layer 156 includes silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In one embodiment, the blocking layer 156 includes a first blocking layer 156a including a portion that extends horizontally along the gate line 130, and a second blocking layer 156b that extends vertically between the first blocking layer 156a and the charge storage layer 154.

[0032] However, the materials and stacked structures of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150 may be modified in various ways, and the embodiment is not limited thereto.

[0033] The channel pad 144 is disposed to cover the upper surface of the core insulating layer 142 and to be electrically connected to the channel layer 140. The channel pad 144 may include a conductive material, such as, but not limited to, polysilicon doped with impurities.

[0034] In an exemplary embodiment, the gate stack 120 includes a plurality of gate stacks 120a and 120b stacked in sequence. By increasing the number of stacked gate lines 130, the number of memory cells can be increased in a stable structure. Although FIG. 1 illustrates the gate stack 120 including two gate stacks 120a and 120b, the gate stack 120 may be composed of one or more gate stacks.

[0035] As described above, when the gate stack structures 120a and 120b are provided, the channel structure (CH) includes a plurality of channel structures (CH1 and CH2) that penetrate the gate stack structures 120a and 120b and are connected to each other. The channel structures (CH1 and CH2) each have a slanted side surface that narrows toward the second substrate 110 according to the aspect ratio when viewed in cross section, and a bent portion due to the width difference is provided at the connection portion of the channel structures (CH1 and CH2). As another example, the channel structures (CH1 and CH2) may have a slanted side surface that is continuously connected without a bent portion. In FIG. 1, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the channel structures (CH1 and CH2) are illustrated as extending from each other to have an integral structure. As another example, the gate dielectric layer 150, the channel layer 140, and the core insulating layer 142 of the multiple channel structures (CH1, CH2) may be formed separately and electrically connected to each other, or a separate channel pad may be additionally provided at the connection portion of the multiple channel structures (CH1, CH2). Thus, the embodiment is not limited to the form of the multiple channel structures (CH1, CH2).

[0036] In one embodiment, the gate stack structure 120 extends in a direction intersecting the second substrate 110 (for example, a vertical direction, the Z-axis direction in the drawing) and is divided into a plurality of parts on a plane by isolation structures 146 penetrating the gate stack structure 120. An upper isolation region 148 is formed on the upper part of the gate stack structure 120. The isolation structures 146 and / or upper isolation regions 148 extend in a first direction (the Y-axis direction in the drawing) on ​​a plane and are provided in a plurality of parts spaced apart from each other at predetermined intervals in a second direction (the X-axis direction in the drawing) intersecting the first direction.

[0037] The isolation structure 146 or the upper isolation region 148 may be filled with various insulating materials. For example, the isolation structure 146 or the upper isolation region 148 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiments are not limited thereto, and the structure, shape, material, etc. of the isolation structure 146 or the upper isolation region 148 may be modified in various ways.

[0038] In order to connect the gate stack structure 120 and the channel structure (CH) provided in the cell array region 102 to the circuit region 200 or an external circuit, a connection region 104 and a second wiring unit 180 are provided. The connection region 104 is disposed on the periphery of the cell array region 102, and a part of the second wiring unit 180 is located therein.

[0039] Here, the second wiring unit 180 includes all of the gate lines 130, the channel structures (CH), the horizontal conductive layers 112, 114, and / or the components that electrically connect the second substrate 110 to the circuit region 200 or an external circuit. For example, the second wiring unit 180 includes the bit lines 182, the gate contact units 184, the source contact units, the through plugs 188, the contact vias 180a connected thereto, and the connection wiring 190 that connects them.

[0040] The bit lines 182 extend in a second direction (the X-axis direction in the drawing) intersecting the first direction in which the gate lines 130 extend. The bit lines 182 are electrically connected to a channel structure (CH), e.g., a channel pad 144, through a contact via 180a, e.g., a bit line contact via, penetrating the cell insulating layer 132.

[0041] In the connection region 104, the gate contact portions 184 are electrically connected to the gate lines 130 extending to the connection region 104 through the cell insulating layer 132. Although the gate lines 130 are shown to have a stepped shape in one direction or in multiple directions in the connection region 104 in the drawings, the embodiment is not limited thereto. In the connection region 104, the source contact portions are electrically connected to the horizontal conductive layers 112, 114 and / or the second substrate 110 through the cell insulating layer 132, and the through plugs 188 are electrically connected to the first wiring portions 230 of the circuit region 200 by passing through the gate stack structure 120 or disposed outside the gate stack structure 120.

[0042] 1, the gate contact portion 184, the source contact portion, and / or the through plug 188 have inclined side surfaces that narrow toward the second substrate 110 according to the aspect ratio when viewed in cross section, and a bent portion is provided at the boundary between the plurality of gate stack structures 120a, 120b. However, the embodiment is not limited thereto. It is also possible that the source contact portion and / or the through plug 188 does not have a bent portion at the boundary between the plurality of gate stack structures 120a, 120b. Various other modifications are possible.

[0043] 1 illustrates an example in which the connection wiring 190 is provided in a single layer located on the same plane as the bit line 182, and the second insulating layer 192 is located in a portion other than the second wiring portion 180. However, this is merely a simplified illustration for convenience. Therefore, the connection wiring 190 may include multiple wiring layers for electrical connection with the bit line 182, the gate contact portion 184, the source contact portion, and / or the through plug 188, and may further include a contact via.

[0044] The second wiring section 180 is connected to the first wiring section 230, and the bit line 182, gate line 130, horizontal conductive layers 112, 114, and / or second substrate 110 connected to the channel structure (CH) are electrically connected to the circuit element 220 in the circuit region 200.

[0045] The circuit region 200 includes a first substrate 210, and a circuit element 220 and a first wiring portion 230 formed on the first substrate 210.

[0046] The first substrate 210 is a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate made of a semiconductor material, or a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the first substrate 210 may be made of single crystal or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator.

[0047] The circuit elements 220 formed on the first substrate 210 include various circuit elements that control the operation of the memory cell structures provided in the cell region 100. As an example, the circuit elements 220 constitute peripheral circuit structures such as a decoder circuit (reference numeral 1110 in FIG. 16), a page buffer (reference numeral 1120 in FIG. 16), and a logic circuit (reference numeral 1130 in FIG. 16).

[0048] The circuit element 220 includes, for example, a plurality of transistors 260, 270. In one embodiment, the plurality of transistors 260, 270 includes a first transistor 260 and a second transistor 270, which will be described in more detail below. In addition, the circuit element 220 may include not only active elements such as the transistors 260, 270, but also passive elements such as a capacitor, a resistor, an inductor, and the like.

[0049] The first wiring unit 230 located on the first substrate 210 is electrically connected to the circuit element 220. In an exemplary embodiment, the first wiring unit 230 includes a plurality of wiring layers 236 spaced apart from each other by first insulating layers 232 and connected to form a desired path by contact vias 234. The wiring layers 236 or the contact vias 234 include various conductive materials, and the first insulating layers 232 include various insulating materials. As an example, the uppermost wiring layer 236 of the plurality of wiring layers 236 adjacent to the cell region 100 includes or constitutes a pad portion to which the gate contact portion 184, the source contact portion, the through plug 188, etc. are connected.

[0050] The plurality of transistors 260, 270 including the first transistor 260 and the second transistor 270 will be described in more detail with reference to Figures 3 to 5 together with Figures 1 and 2. Figure 3 is a partial cross-sectional view that shows a schematic representation of a circuit region 200 included in the semiconductor device 10 shown in Figure 1, and Figure 4 is a partial cross-sectional view that shows a schematic representation of a portion of the circuit region 200 included in the semiconductor device 10 shown in Figure 1. Figure 5 is a plan view that shows a schematic representation of the first transistor 260 and the second transistor 270 included in the circuit region 200 shown in Figure 3.

[0051] Fig. 4 is a cross-sectional view taken along line B-B' in Fig. 5. For the sake of simple illustration and clear understanding, Fig. 5 focuses on the first gate electrode 268 and the first and second regions 264a and 264b of the first transistor 260, and shows the gate contact 234g, the first contact 234a, and the second contact 234b connected to the first gate electrode 268, the first region 264a, and the second region 264b, respectively, by dotted lines.

[0052] 1-5, in one embodiment, the first substrate 210 includes a bulk region 210b, a second region 264b that is part of the first transistor 260, and source and drain regions 274s, 274d that are part of the second transistor 270.

[0053] For example, the bulk region 210b is a region of the semiconductor substrate having a first conductivity type (e.g., p-type or n-type). The second region 264b is another region of the semiconductor substrate having a second conductivity type (e.g., n-type or p-type) opposite to the first conductivity type. The source and drain regions 274s, 274d of the second transistor 270 are another region of the semiconductor substrate having a second conductivity type (e.g., n-type or p-type) opposite to the first conductivity type.

[0054] In the embodiment, the bulk region 210b and the second region 264b have the same material (e.g., the same semiconductor material) and the same crystal structure, but are opposite in conductivity type. The second region 264b is formed by doping a partial region of the first substrate 210 constituting the bulk region 210b with an impurity having an opposite conductivity type to that of the bulk region 210b. Similarly, the bulk region 210b and the source and drain regions 274s, 274d have the same material (e.g., the same semiconductor material) and the same crystal structure, but are opposite in conductivity type. The source and drain regions 274s, 274d are formed by doping a partial region of the first substrate 210 constituting the bulk region 210b with an impurity having an opposite conductivity type to that of the bulk region 210b.

[0055] For example, the bulk region 210b includes a single crystal semiconductor material having a p-type (e.g., single crystal silicon), the second region 264b includes a single crystal semiconductor material having an n-type (e.g., single crystal silicon), and the source and drain regions 274s, 274d include a single crystal semiconductor material having an n-type (e.g., single crystal silicon). For example, the p-type impurities include boron, gallium, etc., and the n-type impurities include phosphorus, arsenic, etc.

[0056] However, the embodiment is not limited thereto. A conductive well having a second conductivity type may be formed, and source and drain regions 274s and 274d of the second transistor 270 having the first conductivity type may be provided in the second transistor 270.

[0057] In the embodiment, a plurality of transistors 260, 270 are provided on a first substrate 210. The plurality of transistors 260, 270 includes a first transistor 260 and a second transistor 270 having an operating voltage lower than that of the first transistor 260.

[0058] In this case, the first transistor 260 is a high voltage (HV) transistor having a relatively high operating voltage, and the second transistor 270 is a low voltage (LV) transistor having a relatively low operating voltage. For example, the operating voltage of the second transistor 270 is 0.1V to 10V, and the operating voltage of the first transistor 260 is higher than that of the second transistor 270, that is, 10V to 100V. As an example, the operating voltage of the first transistor 260 may be 20V or more (e.g., 20V to 100V). However, the embodiment is not limited to the numerical range of the operating voltages of the first and second transistors 260, 270.

[0059] The first transistor 260, which is a high-voltage transistor, is applied to a transistor that generates or transmits a high voltage. For example, at least a part of transistors included in a decoder circuit (reference number 1110 in FIG. 16), a page buffer (reference number 1120 in FIG. 16), etc. is composed of the first transistor 260. As an example, the first transistor 260 is connected to a through plug 188 electrically connected to a gate contact portion 184, and transmits a voltage to the gate contact portion 184. The second transistor 270, which is a low-voltage transistor, has high-speed operating characteristics and excellent reliability, and is therefore applied to a transistor that is required to operate at high speed.

[0060] For the sake of clear understanding and simple illustration, the drawings illustrate an example in which the first transistor 260 is located at the bottom of the connection region 104, and the second transistor 270 is located at the bottom of the cell array region 102. As another example, the first transistor 260 and the second transistor 270 may be located together at the bottom of the cell array region 102. Or, the first transistor 260 and the second transistor 270 may be located together at the bottom of the connection region 104. In addition, the positions of the first transistor 260 and the second transistor 270 may be changed in various ways.

[0061] In the embodiment, the first transistor 260 includes an insulating structure 232a, a channel region 262, first and second regions 264a, 264b, a first gate insulating layer 266, and a first gate electrode 268. The second transistor 270 includes source and drain regions 274s, 274d, a second gate insulating layer 276, and a second gate electrode 278. The first transistor 260 and the second transistor 270 have different structures.

[0062] In one embodiment, the first transistor 260 has a vertical structure. For example, the first transistor 260 has a vertical channel structure. Here, the vertical structure means that the channel region 262 or the first gate electrode 268 includes a portion formed in a direction intersecting the first surface 2101 or the second surface 2102 of the first substrate 210 (e.g., in an inclined or vertical direction), and the vertical channel structure means that the channel region 262 includes a portion formed in a direction intersecting the first surface 2101 or the second surface 2102 of the first substrate 210 (e.g., in an inclined or vertical direction).

[0063] In one embodiment, the second transistor 270 has a different structure from the first transistor 260. For example, the second transistor 270 has a planar structure. For example, the second transistor 270 has a planar channel structure. Here, the planar structure means that a channel portion located between the source and drain regions 274s, 274d or the second gate electrode 278 includes a portion parallel to the first surface 2101 or the second surface 2102 of the first substrate 210, and the planar channel structure means that a channel portion located between the source and drain regions 274s, 274d includes a portion parallel to the first surface 2101 or the second surface 2102 of the first substrate 210.

[0064] In the first transistor region (A1) where the first transistor 260 is provided, an insulating structure 232a is located on the first substrate 210. The insulating structure 232a is an insulating layer on which a channel region 262 and / or a first gate electrode 268 is formed on a side surface. The insulating structure 232a (e.g., the second portion 2322) has a predetermined thickness (T1) so that the channel region 262 formed on the side surface of the insulating structure 232a has a sufficient length.

[0065] The insulating structure 232a includes a first portion 2321 filling the trench portion 210t of the first substrate 210, and a second portion 2322 located on the first surface 2101 of the first substrate 210 and the first portion 2321, and having a certain thickness.

[0066] In the embodiment, the first portion 2321 serves as an isolation portion that isolates the first transistor 260. The second portion 2322 is a portion formed such that the channel region 262, the first gate electrode 268, etc. are located on the side thereof. The first portion 2321 and the second portion 2322 may contain the same material or different materials. In the final structure, the boundary between the first portion 2321 and the second portion 2322 may or may not be visible.

[0067] A channel region 262 is located on a side surface of the insulating structure 232a (e.g., a side surface of the insulating structure 232a adjacent to the recess 232t) and extends in a direction intersecting the first substrate 210. For example, the channel region 262 includes a side extension portion that extends in a direction inclined or perpendicular to the first surface 2101 or the second surface 2102 of the first substrate 210.

[0068] The insulating structure 232a may include various insulating materials. For example, the insulating structure 232a may include an insulating material such as an oxide, a nitride, or an oxynitride. As an example, the insulating structure 232a may include an insulating material such as a silicon oxide, a silicon nitride, or a silicon oxynitride. However, the embodiment is not limited thereto, and the material of the insulating structure 232a may be changed in various ways.

[0069] In the embodiment, the channel region 262 is composed of a first semiconductor layer including a semiconductor material, and is provided separately from the first substrate 210, and has a different material or crystal structure from the first substrate 210. Here, the first semiconductor layer of the channel region 262 has the same first conductivity type (e.g., p-type or n-type) as the bulk region 210b of the first substrate 210. The dopants contained in the channel region 262 and the dopants contained in the bulk region 210b of the first substrate 210 may be the same or different. For example, the p-type impurities include boron, gallium, etc., and the n-type impurities include phosphorus, arsenic, etc. For example, the channel region 262 is composed of a polycrystalline semiconductor layer having the first conductivity type. For example, the channel region 262 includes polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, etc.

[0070] The embodiments are not limited to the above-mentioned materials of the channel region 262, the crystal structure of the channel region 262, the impurities doped in the channel region 262, and the like.

[0071] The source and drain regions of the first transistor 260 are each electrically connected to a channel region 262. In an embodiment, a first region 264a, which is one of the source and drain regions, and a second region 264b, which is the other of the source and drain regions, have different materials or different crystal structures.

[0072] More specifically, the first region 264a is composed of a second semiconductor layer including a semiconductor material, is provided separately from the first substrate 210, and has a different material or a different crystal structure than the first substrate 210. Here, the second semiconductor layer of the first region 264a has a second conductivity type (e.g., n-type or p-type) opposite to that of the channel region 262. For example, the first region 264a is composed of a polycrystalline semiconductor layer having the second conductivity type. For example, the first region 264a includes polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, etc.

[0073] At this time, the first semiconductor layer of the channel region 262 and the second semiconductor layer of the first region 264a have a layered shape that is connected to each other (for example, continuously extending). For example, the first semiconductor layer of the channel region 262 and the second semiconductor layer of the first region 264a include the same semiconductor material and have the same or similar thickness. For example, the first semiconductor layer of the channel region 262 and the second semiconductor layer of the first region 264a have a thickness difference of less than 10%.

[0074] The channel region 262 and the first region 264a have the same material and the same crystal structure, but have opposite conductivity types. The first region 264a is formed by doping a portion of the first semiconductor layer constituting the channel region 262 with impurities having the opposite conductivity type to that of the channel region 262. For example, the channel region 262 includes a polycrystalline semiconductor material (e.g., polycrystalline silicon) having a p-type, and the first region 264a includes a polycrystalline semiconductor material (e.g., polycrystalline silicon) having an n-type.

[0075] As described above, the second region 264b is adjacent to the first substrate 210 and is configured as part of the first substrate 210. Thus, the second region 264b has the same second conductivity type as the first region 264a, but has a different material or a different crystal structure than the first region 264a.

[0076] In one embodiment, the thickness of the channel region 262 or the thickness of the first region 264a is smaller than the thickness of the first substrate 210. Here, the thickness of the channel region 262 or the thickness of the first region 264a means a minimum thickness as a thickness measured in a direction perpendicular to the side surface 232s or the upper surface 232u of the insulating structure 232a. The thickness of the first substrate 210 means a minimum thickness as a thickness measured in a direction perpendicular to the first substrate 210 (Z-axis direction in the drawing). As an example, the thickness of the channel region 262 or the thickness of the first region 264a may be 200 nm or less. This can reduce the manufacturing time of the process of forming the channel region 262 or the first region 264a. However, the embodiment is not limited thereto, and the thickness of the channel region 262 or the thickness of the first region 264a may be more than 200 nm.

[0077] The thickness of the channel region 262 or the first region 264a is different from the thickness of the second region 264b. Here, the thickness of the second region 264b means the maximum thickness as a thickness measured in a direction perpendicular to the first substrate 210 (Z-axis direction in the drawing). This is because the channel region 262 or the first region 264a is formed in a semiconductor layer, and the second region 264b is formed in the first substrate 210. For example, the thickness of the channel region 262 or the first region 264a is smaller than the thickness of the second region 264b. This can reduce the manufacturing time of the process of forming the channel region 262 or the first region 264a, and the second region 264b can be stably formed with a sufficient size. However, the embodiment is not limited thereto. As another example, the thickness of the channel region 262 or the first region 264a may be the same as or larger than the thickness of the second region 264b.

[0078] In one embodiment, a semiconductor layer is located on the side surface 232s and the top surface 232u of the insulating structure 232a. The first region 264a or second semiconductor layer is located in the portion located on the top surface 232u of the insulating structure 232a, and the channel region 262 or first semiconductor layer is located in the portion including the portion located on the side surface 232s of the insulating structure 232a.

[0079] In this manner, the channel region 262 or the first semiconductor layer is formed extending from a first side adjacent to the top surface 232u on the insulating structure 232a to a second side adjacent to the first substrate 210. The first side of the channel region 262 is connected to a first region 264a located on the top surface 232u of the insulating structure 232a, and the second side of the channel region 262 is connected to one surface or a second region 264b of the first substrate 210.

[0080] In one embodiment, the second region 264b includes a low concentration region 2642 having a relatively low doping concentration and a contact region 2641 having a doping concentration higher than that of the low concentration region 2642. The contact region 2641 is a region having a relatively high doping concentration and is referred to as a high concentration region. The second contact 234b is connected to the contact region 2641, and the contact resistance of the second contact 234b can be reduced. The low concentration region 2642 is formed in a region other than the contact region 2641, and a depletion region is stably formed, and the performance of the first transistor 260 can be improved. In one embodiment, the second side of the channel region 262 is connected to the low concentration region 2642.

[0081] A first gate insulating layer 266 is located above the channel region 262. The first gate insulating layer 266 includes at least one of an oxide, a nitride, an oxynitride, a high-k material having a higher dielectric constant than silicon oxide, and a low-k material having a lower dielectric constant than silicon oxide. For example, the first gate insulating layer 266 includes at least one of a silicon oxide, a silicon nitride, a silicon oxynitride, a hafnium oxide, an aluminum oxide, and a tantalum oxide. The first gate insulating layer 266 can be composed of one insulating layer or can include multiple insulating layers.

[0082] In the drawings, the first gate insulating layer 266 is illustrated as being entirely formed on the first substrate 210, the channel region 262 and the first region 264a, and the upper surface 232u of the insulating structure 232a. This allows the first gate insulating layer 266 to be formed without a separate patterning process. However, the embodiment is not limited thereto, and various modifications are possible, such as the first gate insulating layer 266 being partially formed on the region including the channel region 262. For clear understanding, the boundaries of the first gate insulating layer 266 are illustrated in the drawings, but in the final structure, the boundaries of the first gate insulating layer 266 may not be identified.

[0083] In one embodiment, the channel region 262 of the first transistor 260 includes a portion (e.g., a side extension portion) surrounded by the insulating structure 232a and the first gate insulating layer 266. For example, in the channel region 262, four outer surfaces of the portion (i.e., the side extension portion) formed on the side surface 232s of the insulating structure 232a are surrounded by the insulating structure 232a and the first gate insulating layer 266. This structure results from the channel region 262 being formed on the side surface 232s of the insulating structure 232a.

[0084] A first gate electrode 268 is located on the first gate insulating layer 266 located on the channel region 262. The first gate electrode 268 extends in a direction intersecting the first substrate 210 on the channel region 262 and the first gate insulating layer 266 located on a side surface of the insulating structure 232a (e.g., a side surface of the insulating structure 232a adjacent to the recess 232t). For example, the first gate electrode 268 includes a side extension portion extending in a direction inclined or perpendicular to the first surface 2101 or the second surface 2102 of the first substrate 210.

[0085] The first gate electrode 268 includes a conductive material. For example, the first gate electrode 268 includes at least one of a metal, a metal alloy, a metal nitride, a metal silicide, and a doped semiconductor material. Here, the metal or metal alloy included in the first gate electrode 268 includes at least one of titanium, tungsten, molybdenum, aluminum, copper, cobalt, tantalum, and ruthenium. The metal nitride included in the first gate electrode 268 includes at least one of titanium nitride, tungsten nitride, molybdenum nitride, and tantalum nitride. The first gate electrode 268 may further include a metal oxide or a metal oxynitride in which the above-mentioned material is oxidized. The semiconductor material doped with impurities may be a semiconductor material (e.g., a polycrystalline semiconductor material) doped with n-type or p-type impurities.

[0086] An interlayer insulating layer 232m is located on the insulating structure 232a, the channel region 262 and the first region 264a, the first gate insulating layer 266, and the first gate electrode 268 arranged on the first substrate 210. A contact via 234 is located through the first gate insulating layer 266 and / or the interlayer insulating layer 232m. The contact via 234 includes a gate contact 234g connected to the first gate electrode 268, a first contact 234a connected to the first region 264a, and a second contact 234b connected to the second region 264b. The contact via 234 further includes a body contact 234c connected to the first substrate 210. A first wiring layer 2361 connected to the contact via 234 connected to the first transistor 260 is located on the interlayer insulating layer 232m.

[0087] The first wiring layer 2361 in the first transistor region (A1) includes a first electrode wiring connected to the first region 264a via a first contact 234a, a second electrode wiring connected to the second region 264b via a second contact 234b, and a first gate electrode wiring connected to the first gate electrode 268 via a gate contact 234g.

[0088] On the first wiring layer 2361, one or more interlayer insulating layers 232m and one or more second wiring layers 2362 are further located.

[0089] When viewed in a plan view, the gate contact 234g connected to the first gate electrode 268 is located at a first position (upper position in FIG. 5) in one direction (X-axis direction in the drawing), and the first contact 234a connected to the first region 264a and the second contact 234b connected to the second region 264b are located at a second position (lower position in FIG. 5) different from the first position in one direction (X-axis direction in the drawing). This allows the gate contact 234g, the first contact 234a, and the second contact 234b to be stably positioned.

[0090] In one embodiment, the first region 264a formed of a part of the semiconductor layer of the first transistor 260 is a source region, and the second region 264b formed of a part of the first substrate 210 is a drain region. In this case, the through plug 188 connected to the gate line 130 is electrically connected to the first region 264a. However, the embodiment is not limited thereto.

[0091] For example, the second region 264b is shared by a pair of first transistors 260a, 260b adjacent to each other in one direction (the Y-axis direction in the drawing). That is, one second region 264b is included in both of the pair of first transistors 260a, 260b, and the pair of first transistors 260a, 260b have a symmetrical structure in one direction (the Y-axis direction in the drawing). This makes it possible to effectively reduce the size of the second transistor 270.

[0092] A trench portion 210t is formed in a second transistor region (A2) in which the second transistor 270 is provided, and the trench portion 210t is filled with a first insulating layer 232. In the embodiment, the trench portion 210t filled with the first insulating layer 232 serves as an element isolation portion that isolates the second transistor 270.

[0093] The first insulating layer 232 located in the second transistor region (A2) may include various insulating materials. For example, the first insulating layer 232 may include an insulating material such as an oxide, a nitride, or an oxynitride. As an example, the first insulating layer 232 may include an insulating material such as a silicon oxide, a silicon nitride, or a silicon oxynitride. However, the embodiment is not limited thereto, and the material of the first insulating layer 232 may be changed in various ways.

[0094] In the drawings, the second width of the trench portion 210t located in the second transistor region (A2) is smaller than the first width of the trench portion 210t located in the first transistor region (A1). This allows the active region of the first transistor 260 of the high voltage transistor to be stably separated in the first transistor region (A1) where the first transistor 260 is located. However, the embodiment is not limited thereto. Therefore, the first width of the trench portion 210t located in the first transistor region (A1) may be equal to or smaller than the second width of the trench portion 210t located in the second transistor region (A2).

[0095] In one embodiment, the second transistor 270 includes a second gate insulating layer 276 formed horizontally on the first substrate 210, a second gate electrode 278 formed horizontally on the second gate insulating layer 276, and source and drain regions 274s, 274d located on portions of the first substrate 210 located on both sides of the second gate electrode 278 when viewed in a plan view. In addition, the second transistor 270 further includes a gate capping layer and / or a gate spacer.

[0096] In the second transistor 270, the channel portion is formed as part of the bulk region 210b of the first substrate 210 located between the source and drain regions 274s, 274d under the second gate electrode 278 and the second gate insulating layer 276. This differs from the channel region 262 of the first transistor 260, which is formed separately from the first substrate 210 and on the side surface 232s of the insulating structure 232a.

[0097] The second gate insulating layer 276 is comprised of a portion that extends horizontally on the first surface 2101 or the second surface 2102 of the first substrate 210, which differs from the first gate insulating layer 266 that includes a portion that is inclined or perpendicular to the first surface 2101 or the second surface 2102 of the first substrate 210. The thickness of the second gate insulating layer 276 is smaller than the thickness of the first gate insulating layer 266. This is because the first transistor 260 is a high-voltage transistor and the second transistor 270 is a low-voltage transistor. However, depending on the embodiment, the thickness of the second gate insulating layer 276 may be the same as or larger than the thickness of the first gate insulating layer 266.

[0098] The second gate insulating layer 276 includes at least one of an oxide, a nitride, an oxynitride, a high-k material having a higher dielectric constant than silicon oxide, and a low-k material having a lower dielectric constant than silicon oxide. For example, the second gate insulating layer 276 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, and tantalum oxide. The second gate insulating layer 276 can be composed of one insulating layer or can include multiple insulating layers.

[0099] The second gate electrode 278 includes a conductive material. For example, the second gate electrode 278 includes at least one of a metal, a metal alloy, a metal nitride, a metal silicide, and a doped semiconductor material. Here, the metal or metal alloy included in the second gate electrode 278 includes at least one of titanium, tungsten, molybdenum, aluminum, copper, cobalt, tantalum, and ruthenium. The metal nitride included in the second gate electrode 278 includes at least one of titanium nitride, tungsten nitride, molybdenum nitride, and tantalum nitride. The second gate electrode 278 may further include a metal oxide or a metal oxynitride in which the above-mentioned material is oxidized. The semiconductor material doped with impurities may be a semiconductor material (e.g., a polycrystalline semiconductor material) doped with n-type or p-type impurities.

[0100] A gate capping layer (not shown) is located on the second gate electrode 278, and a gate spacer is located on the side of the second gate electrode 278. The gate capping layer functions as a mask layer when forming the second gate insulating layer 276 and the second gate electrode 278. A gate spacer is located on the side of the second gate electrode 278, and insulates the second gate electrode 278 from the source and drain regions 274s and 274d. For example, the gate spacer is located at least on both side surfaces in the intersecting direction (Y-axis direction in the drawing) intersecting with the second gate electrode 278, and extends along the extension direction of the second gate electrode 278 (X-axis direction in the drawing). A gate spacer is located on the side of the gate capping layer, and the gate capping layer is located on the gate spacer.

[0101] The gate capping layer or gate spacer may comprise various insulating materials such as oxides, nitrides, oxynitrides, etc. For example, the gate capping layer or gate spacer may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate capping layer or gate spacer may be comprised of one insulating layer or may comprise multiple insulating layers.

[0102] However, embodiments are not limited to the above, and the second gate insulating layer 276, the second gate electrode 278, the gate capping layer, the gate spacer, and / or the source and drain regions 274s, 274d may have various materials, structures, etc.

[0103] An interlayer insulating layer 232m is located on the first substrate 210 on the second gate insulating layer 276 and the second gate electrode 278. A contact via 234 is located through the interlayer insulating layer 232m. The contact via 234 includes a gate contact connected to the second gate electrode 278, and source and drain contacts 234s, 234d connected to source and drain regions 274s, 274d. A first wiring layer 2361 connected to the contact via 234 connected to the second transistor 270 is located on the interlayer insulating layer 232m.

[0104] The first wiring layer 2361 in the second transistor region (A2) includes a source electrode wiring connected to the source region 274s via the source contact 234s, a drain electrode wiring connected to the drain region 274d via the drain contact 234d, and a second gate electrode wiring connected to the second gate electrode 278 via a gate contact. That is, in this embodiment, the first wiring layer 2361 including the source electrode wiring, drain electrode wiring, and second gate electrode wiring of the second transistor region (A2) and the first wiring layer 2361 including the first electrode wiring, second electrode wiring, and first gate electrode wiring of the first transistor region (A1) are located in the same layer.

[0105] On the first wiring layer 2361, one or more interlayer insulating layers 232m and one or more second wiring layers 2362 are further disposed.

[0106] In the embodiment, the thickness (T1) of the insulating structure 232a, the length (L) of the side surface 232s of the insulating structure 232a, or the length of the channel region 262 in the first transistor 260 is greater than the thickness (T2) of the second gate electrode 278 in the second transistor 270. This ensures a sufficient channel length of the channel region 262 of the first transistor 260.

[0107] Here, the thickness (T1) of the insulating structure 232a is the thickness of the second portion 2322 located on the first surface 2101 of the first substrate 210 in a portion where the trench portion 210t is not provided, and means a value measured in a direction perpendicular to the first substrate 210 (Z-axis direction in the drawing). The length (L) of the side 232s of the insulating structure 232a means the shortest length among the lengths measured along the side 232s of the insulating structure 232a. The length of the channel region 262 means the shortest length among the lengths measured along the channel region 262 located between the first region 264a and the second region 264b (or the first substrate 210). The thickness (T2) of the second gate electrode 278 means the thickness measured in a direction perpendicular to the first substrate 210 (Z-axis direction in the drawing).

[0108] In the embodiment, the thickness (T1) of the insulating structure 232a, the length (L) of the side 232s of the insulating structure 232a, or the length of the channel region 262 in the first transistor 260 is greater than the distance between the source region 274s and the drain region 274d (i.e., the length of the channel portion) in the second transistor 270. This allows the channel length of the channel region 262 of the first transistor 260 to be sufficiently secured. Here, the length of the channel portion of the second transistor 270 or the distance between the source region 274s and the drain region 274d means the shortest distance.

[0109] According to the embodiment, the first transistor 260 of the high voltage transistor has a vertical structure (e.g., a vertical channel structure), and the size or area of ​​the first transistor 260 can be reduced by 3D integration, thereby improving the degree of integration.

[0110] At this time, the second region 264b, which is one of the source and drain regions of the first transistor 260, is configured as a part of the first substrate 210, and the first transistor 260 (particularly the channel region 262) has a structure in which it is joined to the first substrate 210 having a large volume. This prevents problems caused by the floating body effect and prevents punch-through from occurring in the off state. This improves the performance of the first transistor 260 to which a high voltage is transmitted.

[0111] Meanwhile, in a conventional high-voltage transistor having a vertical structure, the source region, the channel region, and the drain region are each provided separately from the semiconductor substrate to form a floating body, and therefore, the high-voltage transistor to which a high voltage is transmitted may not be suitable for operation as a high-voltage transistor since punch-through occurs due to the depletion region in the off state.

[0112] The circuit region 200 including the first substrate 210, the first transistor 260, and the second transistor 270 described above is provided in a semiconductor device 10 including a cell region 100 in which a memory cell structure is provided. For example, the semiconductor device 10 including the circuit region 200 according to the embodiment may be a flash memory device. This is because the high-voltage transistor or the first transistor 260 of a flash memory device must be driven by a higher operating voltage than other memory devices or other semiconductor devices. Thus, according to the embodiment, the performance and integration degree of a flash memory device including the high-voltage transistor or the first transistor 260 driven by a high operating voltage can be effectively improved. In particular, the embodiment is provided in a flash memory device including a large number of gate lines 130 and first transistors 260 in order to increase data storage capacity, and the integration degree can be significantly improved.

[0113] However, although the length direction (X-axis direction in the drawing) of the first or second gate electrode 268, 278 crosses the extension direction of the gate line 130, and the direction in which the source and drain regions 274s, 274d or the first and second regions 264a, 264b are located (Y-axis direction in the drawing) is parallel to the extension direction of the gate line 130, the embodiment is not limited thereto. From the drawing, the length direction (X-axis direction in the drawing) of the first or second gate electrode 268, 278 may be parallel to the extension direction of the gate line 130, and the direction in which the source and drain regions 274s, 274d or the first and second regions 264a, 264b are located (Y-axis direction in the drawing) may cross the extension direction of the gate line 130. Various other modifications are possible.

[0114] An example of a method for manufacturing the semiconductor device 10 having the above-described structure will be described in detail with reference to Figures 6 to 12 as well as Figures 1 to 5. Detailed description of the parts that have already been described will be omitted, and parts that have not been described will be described in detail.

[0115] 6 to 12 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. In Fig. 6 to 12, the first transistor 260 in the circuit region 200 of the semiconductor device 10 shown in Fig. 3 is mainly shown, and the following mainly describes the method for manufacturing the first transistor 260 in the circuit region 200 of the semiconductor device 10.

[0116] As shown in Fig. 6, a first mask layer 240a is formed on a first surface 2101 of a first substrate 210 to expose boundaries of a plurality of first transistors (reference numeral 260 in Fig. 10, the same applies below). A part of the first substrate 210 is etched from the first surface 2101 side of the first substrate 210 using the first mask layer 240a to form a trench portion 210t. Various processes such as dry etching can be used as the etching process. At this time, the first substrate 210 is composed of a bulk region 210b having a first conductivity type.

[0117] 7, an insulating structure 232a including a first portion 2321 filling the trench portion 210t is formed. The insulating structure 232a includes the first portion 2321 filling the trench portion 210t of the first substrate 210, and a second portion 2322 located on the first surface 2101 of the first substrate 210 and the first portion 2321, and having a certain thickness.

[0118] In one embodiment, a process of forming the first portion 2321 filling the trench portion 210t of the first substrate 210 and a process of forming the second portion 2322 are performed by separate processes. More specifically, an insulating material layer is formed to fill the trench portion 210t of the first substrate 210, and then a chemical mechanical polishing process is performed to form the first portion 2321. The first mask layer 240a is removed during the chemical mechanical polishing process, but the embodiment is not limited thereto. Then, an insulating material layer is formed on the first substrate 210 to form the second portion 2322. In some cases, a chemical mechanical polishing process may be performed after the second portion 2322 is formed.

[0119] The insulating material layer may be formed using various processes, such as a deposition process (eg, chemical vapor deposition or physical vapor deposition).

[0120] In one embodiment, a step of forming the second region 264b of the first transistor 260 is performed between the step of forming the first portion 2321 and the step of forming the second portion 2322. The second region 264b is formed by doping a portion of the first substrate 210 with a second conductive type impurity. The step of forming the second region 264b is performed by various doping processes. However, the embodiment is not limited thereto, and the step of forming the second region 264b may be performed in a different order. For example, the step of forming the second region 264b may be performed after the step of forming the recess 232t.

[0121] 8, a second mask layer 240b is formed on the insulating structure 232a to expose a region of the first substrate 210 located between the trench portions 210t of the first substrate 210. A portion of the insulating structure 232a is etched using the second mask layer 240b to form a recess 232t on the insulating structure 232a. As the etching process, various processes such as dry etching can be used.

[0122] 7 and 8, the second portion 2322 is entirely formed, and then the recess 232t is formed by a patterning process, but the embodiment is not limited thereto. The second portion 2322 may be formed so as to have the recess 232t in the process of forming the second portion 2322.

[0123] 9, the channel region 262 and the first region 264a of the first transistor 260 are formed.

[0124] In one embodiment, a semiconductor layer is formed on the entire surface of the upper surface 232u and the side surface 232s of the insulating structure 232a, and on the first surface 2101 of the first substrate 210 exposed by the recess 232t. For example, the semiconductor layer is formed by a method such as deposition. Then, the remaining portions except for the regions corresponding to the channel region 262 and the first region 264a are etched to leave the semiconductor layer corresponding to the channel region 262 and the first region 264a. For example, the semiconductor layer is patterned by dry etching using a mask layer. However, the embodiment is not limited thereto.

[0125] By the patterning process, the semiconductor layer includes a portion located on the upper surface 232u and the side surface 232s of the insulating structure 232a located on one side of the recess 232t, and a portion located on the upper surface 232u and the side surface 232s of the insulating structure 232a located on the other side of the recess 232t. As a result, the portion located on one side of the recess 232t constitutes one first transistor 260, and the portion located on the other side of the recess 232t constitutes another first transistor 260. As a result, the process can be simplified and the size of the first transistor 260 can be reduced.

[0126] For example, when forming the semiconductor layer, a first semiconductor layer including a first conductive type impurity is formed, and then a portion corresponding to the first region 264a is doped with a second conductive type impurity to form the first region 264a. The remaining first semiconductor layer that is not doped with the second conductive type impurity constitutes the channel region 262. This allows the process to be simplified while maintaining good characteristics of the channel region 262. However, the embodiment is not limited thereto.

[0127] As another example, when forming the semiconductor layer, a second semiconductor layer including a second conductive type impurity is formed, and then a portion corresponding to the channel region 262 is doped with a first conductive type impurity to form the channel region 262. As yet another example, when forming the semiconductor layer, an undoped semiconductor layer including no impurities is formed, and then a portion corresponding to the channel region 262 is doped with a first conductive type impurity and a portion corresponding to the first region 264a is doped with a second conductive type impurity to form the channel region 262 and the first region 264a.

[0128] Subsequently, as shown in FIG. 10, a first gate insulating layer 266 and a first gate electrode 268 are formed.

[0129] A first gate insulating layer 266 is formed on the first surface 2101 of the first substrate 210 to cover the insulating structure 232a, the channel region 262 and the first region 264a. The first gate insulating layer 266 can be formed by various methods, such as deposition.

[0130] A first gate electrode 268 is formed on the first gate insulating layer 266. After the first gate electrode 268 is formed overall, a patterning process is performed to remove a portion other than the portion located on the side surface 232s of the insulating structure 232a. As a result, the first gate electrode 268 is formed on the channel region 262 located on the side surface 232s of the insulating structure 232a and the first gate insulating layer 266. The first gate electrode 268 is formed by various methods such as deposition and plating. The patterning process of the first gate electrode 268 is performed by dry etching using a mask layer. However, the embodiment is not limited thereto.

[0131] 11, an interlayer insulating layer 232m is formed on the first gate insulating layer 226 to fill the insulating structures 232a and the recesses 232t. For example, after forming an insulating material to fill the recesses 232t, a chemical mechanical polishing process is performed to form the interlayer insulating layer 232m.

[0132] Then, the contact via 234 penetrating the first gate insulating layer 266 and / or the interlayer insulating layer 232m and the first wiring layer 2361 connected to the contact via 234 are formed. At this time, the contact via 234 includes a gate contact (reference symbol 234g in FIG. 4) connected to the first gate electrode 268, a first contact 234a connected to the first region 264a, and a second contact 234b connected to the second region 264b, and further includes a body contact 234c connected to the first substrate 210. For example, a conductive material is formed to fill the through portion to form the contact via 234. As an example, another interlayer insulating layer 232m exposing the contact via 234 is formed, and the conductive material is filled, and then a chemical mechanical polishing process is performed to form the first wiring layer 2361. However, the embodiment is not limited thereto, and various modifications are possible.

[0133] Subsequently, as shown in FIG. 12, one or more interlayer insulating layers 232m and one or more second wiring layers 2362 are further formed on the first wiring layer 2361 to form the first wiring section 230.

[0134] According to the embodiment, the first transistor 260 having excellent performance and an integrated structure can be formed through a simple manufacturing process.

[0135] A semiconductor device according to another embodiment different from the embodiment described above will be described in more detail below with reference to Figures 13 to 15. Detailed descriptions of parts that are the same as or very similar to parts already described will be omitted, and only different parts will be described in detail.

[0136] 13 is a cross-sectional view showing a part of a circuit region included in a semiconductor device according to another embodiment of the present invention, which corresponds to the part shown in FIG.

[0137] 13, in the first transistor 260 according to the embodiment, the second region 264b is composed of a contact region 2641 formed locally in a region corresponding to the second contact 234b, and does not include a low concentration region (reference numeral 2642 in FIG. 3). In this case, the channel region 262 of the first transistor 260 is connected to the bulk region 210b of the first substrate 210. As a result, the area of ​​the doped region of the first substrate 210 can be reduced.

[0138] 14 is a cross-sectional view showing a part of a circuit region included in a semiconductor device according to another embodiment of the present invention, which corresponds to the part shown in FIG.

[0139] 14, in the embodiment, the first transistor region (A1) includes a first wiring layer 2361 to which a gate contact (reference number 234g in FIG. 4, the same applies below) included in the first transistor 260 and connected to the first gate electrode 268, the first region 264a, and the second region 264b, respectively, the first contact 234a, and the second contact 234b are connected. Of the multiple wiring layers 236 located in the first transistor region (A1), the first wiring layer 2361 is the wiring layer closest to the first transistor 260.

[0140] In the first transistor region (A1), the first wiring layer 2361 includes a first electrode wiring connected to the first region 264a via a first contact 234a, a second electrode wiring connected to the second region 264b via a second contact 234b, and a first gate electrode wiring connected to the first gate electrode 268 via a gate contact 234g.

[0141] In the second transistor region (A2), an additional wiring layer 2364 is located between the first wiring layer 2361, which is located in the same layer as the first wiring layer 2361 in the first transistor region (A1), and the second transistor 270. As a result, of the multiple wiring layers 236 located in the second transistor region (A2), the additional wiring layer 2364 is closer to the second transistor 270 than the first wiring layer 2361.

[0142] In the second transistor region (A2), the additional wiring layer 2364 includes a source electrode wiring connected to the source region 274s via the source contact 234s, a drain electrode wiring connected to the drain region 274d via the drain contact 234d, and a second gate electrode wiring connected to the second gate electrode 278 via a gate contact. That is, in this embodiment, the additional wiring layer 2364 including the source electrode wiring, drain electrode wiring, and second gate electrode wiring in the second transistor region (A2) is located in a layer different from the first wiring layer 2361 including the first electrode wiring, second electrode wiring, and first gate electrode wiring in the first transistor region (A1).

[0143] The thickness of the second gate electrode 278 of the second transistor 270 is smaller than the thickness of the insulating structure 232a included in the first transistor 260. By utilizing this, an additional wiring layer 2364 can be positioned between the second transistor 270 and the first wiring layer 2361, thereby improving the integration density of the wiring layer 236.

[0144] FIG. 15 is a schematic cross-sectional view of a semiconductor device 20 according to a further embodiment.

[0145] 15, the semiconductor device 20 according to the embodiment has a chip-to-chip (C2C) structure bonded by a wafer bonding method. That is, a lower chip including a circuit region 200a formed on a first substrate 210 is manufactured, an upper chip including a cell region 100a formed on a second substrate 110a is manufactured, and then these are bonded to manufacture the semiconductor device 20.

[0146] The circuit region 200a includes a first substrate 210, a circuit element 220, a first wiring portion 230, and a first junction structure 240 that is electrically connected to the first wiring portion 230 and is located on a surface facing the cell region 100a. The area on the surface facing the cell region 100a other than the first junction structure 240 is covered with a first insulating layer 232.

[0147] The cell region 100a includes a second substrate 110a, a gate stack structure 120, a channel structure (CH), a second wiring portion 180, and a second junction structure 194 electrically connected to the second wiring portion 180 and located on a surface facing the circuit region 200a. The area other than the second junction structure 194 is covered with an insulating layer 196.

[0148] In the embodiment, the second substrate 110a may be a semiconductor substrate including a semiconductor material. For example, the second substrate 110a may be a semiconductor substrate including a semiconductor material, or a semiconductor substrate including a semiconductor layer formed on a base substrate. For example, the second substrate 110a may be made of monocrystalline or polycrystalline silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator. Alternatively, the second substrate 110a may be made of a support member including an insulating layer or an insulating material. This is because, after bonding the cell region 100a to the circuit region 200a, the semiconductor substrate included in the cell region 100a may be removed, and a support member including an insulating layer or an insulating material may be formed.

[0149] In one embodiment, the gate stack 120 is stacked in order under the second substrate 110a in the drawing, and is arranged in a structure obtained by vertically inverting the gate stack 120 shown in FIG. 1. The channel structure (CH) penetrating the gate stack 120 also has a structure obtained by vertically inverting the channel structure (CH) shown in FIG. 2. As a result, the channel structure (CH) has a side surface that is inclined so that the width narrows from the circuit region 200a toward the second substrate 110a when viewed in cross section. The channel pad 144 and the second wiring part 180 located on the gate stack 120 are located adjacent to the circuit region 200a.

[0150] For example, the first and / or second bonding structures 240, 194 may be made of aluminum, copper, tungsten, or an alloy including these. In one example, the first and second bonding structures 240, 194 may include copper, and the cell region 100a and the circuit region 200a may be bonded (for example, bonded in direct contact) by a copper-to-copper bond.

[0151] Although FIG. 15 illustrates the gate stack structure 120 including a plurality of gate stack structures, the gate stack structure 120 may include one or more than three gate stack structures. Unless otherwise noted, the description of the gate stack structure 120 and the channel structure (CH) described with reference to FIG. 1 and FIG. 2 may be applied as is. FIG. 15 illustrates an electrical connection structure between the channel structure (CH) and the horizontal conductive layers 112, 114 and / or the second substrate 110a that is the same as that of FIG. 2. The embodiment is not limited thereto, and the electrical connection structure between the channel structure (CH) and the horizontal conductive layers 112, 114 and / or the second substrate 110a may be modified in various ways.

[0152] The semiconductor device 20 according to an example includes an I / O pad and a through plug or an I / O connection wiring electrically connected thereto. The through plug or the I / O connection wiring is electrically connected to a part of the second junction structure 194. The I / O pad is located, for example, on an insulating film covering an outer surface of the second substrate 110a. According to an embodiment, a separate I / O pad is provided that is electrically connected to the circuit region 200a.

[0153] In the embodiment, the circuit region 200a includes a first transistor 260 and a second transistor 270. The first region 264a of the first transistor 260 is electrically connected to the gate contact portion 184 via the first wiring portion 230, the first junction structure 240, and the second junction structure 194. According to the embodiment, the first transistor 260 is connected to the gate contact portion 184 without a through plug (reference number 188 in FIG. 1), thereby simplifying the structure. Unless otherwise stated, the description of the structure of the circuit region 200 with reference to FIGS. 1 to 12 may be directly applied to the circuit region 200a.

[0154] As an example, the circuit region 200a and the cell region 100a are parts corresponding to the first structure 1100F and the second structure 1100S of the semiconductor device 1100 included in the electronic system 1000 shown in Fig. 16. Alternatively, the circuit region 200a and the cell region 100a are regions including the first structure 4100 and the second structure 4200 of the semiconductor chip 2200a shown in Fig. 19.

[0155] An example of an electronic system including the above-mentioned semiconductor device will now be described in detail.

[0156] FIG. 16 is a schematic diagram of an electronic system including a semiconductor device according to an example embodiment.

[0157] 16, an electronic system 1000 according to an exemplary embodiment includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0158] The semiconductor device 1100 may be a non-volatile memory device, for example, a NAND flash memory device described with reference to FIGS. 1-15. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed beside the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line (BL), a common source line (CSL), a word line (WL), a first and second gate upper line (UL1, UL2), a first and second gate lower line (LL1, LL2), and a memory cell string (CSTR) between the bit line (BL) and the common source line (CSL).

[0159] In the second structure 1100S, each memory cell string (CSTR) includes lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) can be variously changed depending on the embodiment.

[0160] In an exemplary embodiment, the lower transistors (LT1, LT2) include ground select transistors, and the upper transistors (UT1, UT2) include string select transistors. The first and second gate lower lines (LL1, LL2) are gate lines of the lower transistors (LT1, LT2), respectively. The word lines (WL) are gate lines of the memory cell transistors (MCT), and the gate upper lines (UL1, UL2) are gate lines of the upper transistors (UT1, UT2), respectively.

[0161] The common source line (CSL), the first and second gate bottom lines (LL1, LL2), the word lines (WL), and the first and second gate top lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via a first connection wiring 1115 that extends to the second structure 1100S in the first structure 1100F. The bit lines (BL) are electrically connected to the page buffer 1120 via a second connection wiring 1125 that extends to the second structure 1100S in the first structure 1100F.

[0162] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 execute a control operation for at least one memory cell transistor selected from a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1100 communicates with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via an input / output connection wiring 1135 extending to the second structure 1100S in the first structure 1100F.

[0163] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. According to an embodiment, the electronic system 1000 includes multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1100.

[0164] The processor 1210 controls the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 operates according to a predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface (I / F) 1221 that processes communication with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor (MCT) of the semiconductor device 1100, data to be read from the memory cell transistor (MCT) of the semiconductor device 1100, etc. are transmitted via the NAND interface 1221. The host interface 1230 provides a communication function between the electronic system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0165] FIG. 17 is a perspective view that illustrates a schematic diagram of an electronic system including a semiconductor device according to an exemplary embodiment.

[0166] 17, an electronic system 2000 according to an exemplary embodiment includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0167] The main board 2001 includes a connector 2006 including a plurality of pins for coupling with an external host. The number and arrangement of the plurality of pins of the connector 2006 vary depending on the communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 communicates with the external host according to any of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the electronic system 2000 operates with power supplied from the external host via the connector 2006. The electronic system 2000 further includes a Power Management Integrated Circuit (PMIC) for distributing the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0168] The controller 2002 can record data to and read data from the semiconductor package 2003 to improve the operating speed of the electronic system 2000 .

[0169] The DRAM 2004 is a buffer memory for mitigating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 also operates as a kind of cache memory, providing space for temporarily storing data in a control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 further includes a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0170] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0171] The package substrate 2100 may be a printed circuit board including package top pads 2130. Each semiconductor chip 2200 includes an input / output pad 2210. The input / output pads 2210 correspond to the input / output pads 1101 of FIG. 16. Each of the semiconductor chips 2200 includes a gate stack 3210 and a channel structure 3220. The semiconductor chips 2200 each include a semiconductor device as described with reference to FIGS. 1 to 15.

[0172] In an exemplary embodiment, the connection structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package top pad 2130. Thus, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are electrically connected to each other in a bonding wire manner and electrically connected to the package top pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 can be electrically connected by a connection structure including a through silicon via (TSV) instead of the connection structure 2400 in the bonding wire manner.

[0173] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on an interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0174] 18 and 19 are cross-sectional views each illustrating a schematic semiconductor package according to an exemplary embodiment. Each of FIG. 18 and FIG. 19 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 17, and conceptually illustrates a region of the semiconductor package 2003 of FIG. 17 cut along cutting line II'.

[0175] 18, in a semiconductor package 2003, a package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body 2120, a package upper pad 2130 disposed on an upper surface of the package substrate body 2120, a package lower pad 2125 disposed on a lower surface of the package substrate body 2120 or exposed through the lower surface, and an internal wiring 2135 electrically connecting the package upper pad 2130 and the package lower pad 2125 inside the package substrate body 2120. The package upper pad 2130 is electrically connected to a connection structure 2400. The package lower pad 2125 is connected to a wiring pattern 2005 of a main substrate 2001 of an electronic system 2000 through a conductive connection part 2800 as shown in FIG.

[0176] The semiconductor chip 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 which are sequentially stacked on the semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and an isolation structure 3230 which pass through the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a gate connection wiring electrically connected to a word line (WL in FIG. 16 ) of the gate stack structure 3210.

[0177] In the semiconductor chip 2200 or semiconductor device according to the embodiment, the first transistor 260 has a vertical structure and includes a portion of a semiconductor substrate or is formed adjacent to the semiconductor substrate, which can improve the performance and integration density of the semiconductor chip 2200 or semiconductor device.

[0178] Each of the semiconductor chips 2200 is electrically connected to the peripheral wiring 3110 of the first structure 3100 and includes a through wiring 3245 extending into the second structure 3200. The through wiring 3245 penetrates the gate stack structure 3210 and is further disposed outside the gate stack structure 3210. Each of the semiconductor chips 2200 is electrically connected to the peripheral wiring 3110 of the first structure 3100 and further includes an input / output connection wiring 3265 extending into the second structure 3200 and an input / output pad 2210 electrically connected to the input / output connection wiring 3265.

[0179] In an exemplary embodiment, in the semiconductor package 2003, the semiconductor chips 2200 are electrically connected to each other by a connection structure 2400 in the form of bonding wires. As another example, the semiconductor chips 2200 or parts constituting the semiconductor chips 2200 are electrically connected to each other by a connection structure including a through electrode.

[0180] Referring to FIG. 19, in semiconductor package 2003A, each of semiconductor chips 2200a includes a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 using a wafer bonding method.

[0181] The first structure 4100 includes a peripheral circuit region including a peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 includes a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and an isolation structure 4230 penetrating the gate stack structure 4210, and a second junction structure 4250 electrically connected to the channel structure 4220 and a word line (WL in FIG. 16, the same applies below) of the gate stack structure 4210. For example, the second junction structure 4250 is electrically connected to the channel structure 4220 and the word line (WL) through a bit line 4240 electrically connected to the channel structure 4220 and a gate connection wiring electrically connected to the word line (WL). The first joint structure 4150 of the first structure 4100 and the second joint structure 4250 of the second structure 4200 are joined while being in contact with each other. The joined portions of the first joint structure 4150 and the second joint structure 4250 are formed of, for example, copper (Cu).

[0182] In the semiconductor chip 2200a or semiconductor device according to the embodiment, the first transistor 260 has a vertical structure and includes a portion of a semiconductor substrate or is formed adjacent to the semiconductor substrate, thereby improving the performance and integration density of the semiconductor chip 2200 or semiconductor device.

[0183] Each of the semiconductor chips 2200a further includes an input / output pad 2210 and an input / output connection wiring 4265 below the input / output pad 2210. The input / output connection wiring 4265 is electrically connected to a portion of the second joint structure 4250.

[0184] In one embodiment, the semiconductor chips 2200a in the semiconductor package 2003A are electrically connected to each other by a bonding wire type connection structure 2400. As another example, the semiconductor chips 2200a or parts thereof are electrically connected to each other by a connection structure including a through electrode.

[0185] Although the embodiments have been described in detail above, the technical scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concept of the present invention also fall within the technical scope of the present invention. [Explanation of symbols]

[0186] 10, 20 Semiconductor device 100, 100a cell area 110, 110a Second substrate 120 Gate stack structure 140 Channel Layer 150 Gate Dielectric Layer 180 2nd wiring section 194 Second joint structure 200, 200a circuit area 210 First board 220 Circuit Elements 230 1st wiring section 232 First insulating layer 232a, 232b Insulating structure 232m Interlayer Insulation Layer 234 Contact Via 240 First joint structure 260 1st Transistor 262 Channel Area 264a 1st area 264b Second area 266 First gate insulating layer 268 First gate electrode 270 Second Transistor

Claims

1. A semiconductor substrate; a first transistor located on the semiconductor substrate; The first transistor is an insulating structure located on the semiconductor substrate; a channel region extending in a direction intersecting the semiconductor substrate on a side surface of the insulating structure and made of a first semiconductor layer; source and drain regions electrically connected to the channel region; a gate insulating layer overlying the channel region; a gate electrode located on the gate insulating layer; A semiconductor device, characterized in that a first region which is one of said source and drain regions and a second region which is the other of said source and drain regions have mutually different materials or mutually different crystal structures.

2. the first region is formed of a second semiconductor layer having an opposite conductivity type to the channel region; The semiconductor device according to claim 1 , wherein the second region is configured as a part of the semiconductor substrate.

3. the channel region includes a portion surrounded by the insulating structure and the gate insulating layer; or 2. The semiconductor device according to claim 1, wherein the channel region or the gate electrode is inclined or perpendicular to the first surface or the second surface of the semiconductor substrate.

4. The first transistor includes a pair of first transistors adjacent to each other in one direction, the pair of first transistors share the second region; 2 . The semiconductor device according to claim 1 , wherein the pair of first transistors have a symmetrical structure in the one direction with respect to the second region.

5. a first contact connected to the first region and a second contact connected to the second region; the second region includes a low concentration region and a high concentration region having a doping concentration higher than that of the low concentration region; the second contact is connected to the high concentration region; 2. The semiconductor device according to claim 1, wherein the channel region is connected to the low concentration region.

6. 2. The semiconductor device according to claim 1, wherein the channel region is connected to a bulk region of the semiconductor substrate.

7. a second transistor having an operating voltage lower than that of the first transistor and having a structure different from that of the first transistor; 2. The semiconductor device of claim 1, wherein a thickness of the insulating structure, a lateral length of the insulating structure, or a length of the channel region is greater than a thickness of a second gate electrode included in the second transistor, or a thickness of the insulating structure, a lateral length of the insulating structure, or a length of the channel region is greater than a distance between a source region and a drain region of the second transistor.

8. a circuit region including the semiconductor substrate and the first transistor; 2. The semiconductor device according to claim 1, further comprising: a cell region located on said circuit region and including a memory cell structure.

9. A semiconductor substrate; a plurality of transistors, the transistors including a first transistor and a second transistor, the first transistor and the second transistor being located on the semiconductor substrate and having different structures; The first transistor is an insulating structure located on the semiconductor substrate; a channel region extending in a direction inclined or perpendicular to the semiconductor substrate on a side surface of the insulating structure and formed of a first semiconductor layer; source and drain regions electrically connected to the channel region; a gate insulating layer overlying the channel region; a gate electrode located on the gate insulating layer; A semiconductor device, wherein one of the source and drain regions is formed as part of the semiconductor substrate.

10. the first transistor has a vertical channel structure; The semiconductor device according to claim 9 , wherein the second transistor has a planar channel structure.

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