Semiconductor device and manufacturing method of the same

Abstract

To improve a performance of a semiconductor device.SOLUTION: A manufacturing method of a semiconductor device includes: a step of forming a sealing body MR; and a step of irradiating with a laser beam LZ a region where each part of a plurality of leads LD from the sealing body MR is covered. Each of the plurality of leads LD provided to a lead frame LF includes: a part LDm having an upper surface LDt and a lower surface LDb positioned to the side opposite to the upper surface LDt; and a part LDe of which a thickness is thinner than that of the part LDm. The part LDe includes: an upper surface LDt; and a lower surface LDb2 that is positioned to the side opposite to the upper surface LDt. In the step of emitting the laser beam LZ, the lower surface LDb2 is exposed by selectively irradiating with the laser beam LZ the part covering each lower surface LDb2 of the plurality of leads LD from the sealing body MR.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2005-191240 (Patent Document 1) and Japanese Patent Laid-Open Publication No. 2014-007287 (Patent Document 2) describe a semiconductor device in which a step surface (recess) is provided on the lower surface of a lead. Also, Japanese Patent Laid-Open Publication No. 2014-187308 (Patent Document 3) describes a method of irradiating a laser beam as a method of removing resin in a dam filled in a groove on the upper surface of a lead in a manufacturing method of a semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-191240 A [Patent Document 2] JP 2014-007287 A [Patent Document 3] JP 2014-187308 A Summary of the Invention [Problem to be solved by the invention]

[0004] As a package form of a semiconductor device, there is a package in which the leads, which are external terminals, are exposed from the bottom surface of the sealing body. Examples of such packages include QFN (Quad Flat Non-leaded package) type and DFN (Dual Flat Non-leaded package) type. When a package in which the leads are exposed from the bottom surface of the sealing body is mounted on a mounting board, the package is mounted by bonding a bonding material such as solder to the exposed surface of the leads. In addition, from the viewpoint of improving the visibility of the solder during inspection after mounting the package, there is a method of providing a step portion at the tip of the lead, thereby forming a solder fillet at the tip of the lead, as in the above-mentioned Patent Documents 1 and 2.

[0005] However, for example, as the semiconductor device becomes smaller, the distance between two adjacent leads becomes smaller, which may cause a concern that the two leads may short-circuit each other via the solder. Specifically, as in the above-mentioned Patent Document 2, when cutting each lead with a dicing blade, which is a rotary blade, metal burrs extending in the arrangement direction of the multiple leads may be formed on the side of the sealing body, i.e., the surface cut by the dicing blade (particularly, the portion between the two adjacent leads). When the metal burrs are formed, the solder may spread along the metal burrs when the package is mounted, which may cause the two leads to short-circuit each other.

[0006] Therefore, in order to improve the reliability of semiconductor devices, a technique capable of preventing short circuits between adjacent leads is required.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one embodiment includes the steps of (a) preparing a lead frame, (b) mounting a semiconductor chip on the lead frame, (c) electrically connecting the semiconductor chip and a plurality of leads, (d) forming an encapsulant that encapsulates a portion of a die pad, a portion of each of the plurality of leads, and the semiconductor chip, (e) irradiating a laser beam onto an area of ​​the encapsulant that covers each of the portions of the plurality of leads, and (f) forming a metal film on each of the portions of the plurality of leads after the step (e). The die pad has a first upper surface and a first lower surface located opposite the first upper surface. Each of the plurality of leads of the lead frame prepared in the step (a) includes a first portion having a second upper surface and a second lower surface located opposite the second upper surface, and a second portion that is located farther from the die pad than the first portion and has a thickness smaller than that of the first portion. Each of the plurality of leads is arranged adjacent to each other so as to be spaced apart from each other in a first direction. The sealing body has a third upper surface facing the same direction as the first upper surface and a third lower surface opposite the third upper surface, and the second portion has the second upper surface and a fourth lower surface located opposite the second upper surface. A distance from the second upper surface to the fourth lower surface is shorter than a distance from the second upper surface to the second lower surface. In the step (e), the laser light is selectively irradiated to a portion of the sealing body covering the fourth lower surface of each of the plurality of leads, thereby exposing the fourth lower surface.

[0009] A semiconductor device according to another embodiment includes a die pad having a first upper surface and a first lower surface opposite to the first upper surface, a plurality of leads having a second upper surface facing the same direction as the first upper surface and a second lower surface opposite to the second upper surface and spaced apart from the die pad, a semiconductor chip having a plurality of electrodes and mounted on the first upper surface of the die pad, a plurality of conductive members electrically connecting the plurality of electrodes of the semiconductor chip and the plurality of leads, a third upper surface facing the same direction as the first upper surface and a third lower surface opposite to the third upper surface, and an encapsulant encapsulating a portion of the die pad, a portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip such that the first lower surface of the die pad and the second lower surfaces of each of the plurality of leads are exposed. Each of the plurality of leads includes a first portion having the second upper surface and the second lower surface, and a second portion disposed farther from the die pad than the first portion and thinner than the first portion. Each of the plurality of leads is arranged in a first direction. The second portion has the second upper surface and a fourth lower surface located opposite to the second upper surface. A distance from the second upper surface to the fourth lower surface is shorter than a distance from the second upper surface to the second lower surface. The plurality of leads arranged in the first direction have two leads adjacent to each other. A part of the encapsulant made of an insulating material is interposed between the second portion of one of the two adjacent leads and the second portion of the other of the two adjacent leads. In a thickness direction of the encapsulant, the fourth lower surface is located closer to the third upper surface of the portion than the third lower surface of the portion. Effect of the Invention

[0010] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief description of the drawings]

[0011] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment; [Diagram 2]2 is a bottom view of the semiconductor device shown in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 4] 2 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 1 removed. [Diagram 5] FIG. 3 is an enlarged cross-sectional view taken along line BB in FIG. 2. [Figure 6] 4 is a cross-sectional view showing a state in which the semiconductor device shown in FIG. 3 is mounted on a mounting surface of a mounting board via a bonding material. [Figure 7] 6 is a flow chart showing an example of a manufacturing process for the semiconductor device shown in FIGS. 1 to 5. FIG. [Figure 8] 8 is a plan view of a lead frame prepared in a lead frame preparing step shown in FIG. 7. [Figure 9] FIG. 9 is an enlarged plan view of two of the device formation portions shown in FIG. 8. [Figure 10] FIG. 10 is an enlarged cross-sectional view taken along line CC in FIG. [Figure 11] FIG. 10 is an enlarged cross-sectional view taken along line DD in FIG. [Figure 12] 8 is a plan view showing a sealing body formed in the sealing body step shown in FIG. 7. FIG. [Figure 13] 13 is an enlarged cross-sectional view taken along line EE in FIG. 12, showing a state in which a lead frame is placed in a cavity of a molding die. [Figure 14] 8 is an enlarged cross-sectional view showing a state in which a sealing body covering an end portion of a lead is irradiated with laser light in the laser irradiation step shown in FIG. 7. FIG. [Figure 15] 8 is an enlarged plan view showing an example of a scanning direction of a position to be irradiated with laser light in the laser irradiation step shown in FIG. 7. FIG. [Figure 16] 8 is an enlarged plan view showing an example after the sealing body is removed by the laser irradiation step shown in FIG. 7. FIG. [Figure 17] FIG. 17 is an enlarged cross-sectional view taken along the line FF in FIG. 16. [Figure 18] FIG. 17 is an enlarged cross-sectional view taken along line GG in FIG. 16. [Figure 19]FIG. 15 is an enlarged cross-sectional view showing an example of consideration corresponding to FIG. 14. [Figure 20] FIG. 16 is an enlarged plan view showing an example of consideration corresponding to FIG. 15. [Figure 21] FIG. 8 is an explanatory view illustrating an example of a metal film forming step illustrated in FIG. 7. [Figure 22] 18 is an enlarged cross-sectional view showing a state in which a metal film is formed on the lead shown in FIG. 17. [Diagram 23] 8 is an enlarged cross-sectional view showing the singulation step shown in FIG. 7. [Figure 24] 8 is an enlarged side view showing one side surface of the semiconductor device after the singulation process shown in FIG. 7 is completed. [Diagram 25] FIG. 15 is an enlarged cross-sectional view showing a modification of FIG. [Figure 26] FIG. 16 is an enlarged plan view showing a modification of FIG. [Figure 27] FIG. 15 is an enlarged cross-sectional view showing another modified example of FIG. [Figure 28] FIG. 16 is an enlarged plan view showing another modified example of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Description format, basic terms and usage in this application) In this application, the description of the embodiment is conveniently divided into multiple sections, etc., as necessary, but unless otherwise specified, these are not mutually independent and separate, and regardless of the description, each part of a single example, one is a partial detail of the other, or a partial or complete modified example, etc. In addition, as a general rule, repeated explanations of similar parts will be omitted. In addition, each component in the embodiment is not essential, unless otherwise specified, when it is theoretically limited to that number, or when it is clearly not from the context.

[0013] Similarly, in the description of the embodiments, when a material, composition, etc. is described as "X made of A," it does not exclude those containing elements other than A, unless otherwise specified or clearly indicated from the context. For example, when it comes to components, it means "X containing A as a main component." For example, when it comes to "silicon components," it goes without saying that it is not limited to pure silicon, but also includes SiGe (silicon germanium) alloys and other multi-component alloys whose main component is silicon, and components containing other additives. In addition, when it comes to gold plating, Cu layer, nickel plating, etc., it includes not only pure ones, but also components whose main components are gold, Cu, nickel, etc., unless otherwise specified.

[0014] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, it may be a number greater than that specific number, or a number less than that specific number, unless it is theoretically limited to that number or unless it is clearly different from the context.

[0015] In addition, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated as a general rule.

[0016] In the accompanying drawings, hatching and the like may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, the background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the explanation, etc. Furthermore, hatching or dot patterns may be added even if the drawing is not a cross section in order to clearly indicate that it is not a void or to clearly indicate the boundaries of the area.

[0017] The technology described in the following embodiments can be applied to various package-type semiconductor devices in which the leads are exposed on the underside of the encapsulant. In the present embodiments, as an example, the technology described is applied to a QFN-type semiconductor device in which multiple leads, which are external terminals, are exposed from the encapsulant on the underside (mounting surface) of the encapsulant.

[0018] <Semiconductor device> Fig. 1 is a top view of the semiconductor device of this embodiment, Fig. 2 is a bottom view of the semiconductor device shown in Fig. 1, and Fig. 3 is a cross-sectional view taken along line AA in Fig. 1. Fig. 4 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in Fig. 1 removed. Fig. 5 is an enlarged cross-sectional view taken along line BB in Fig. 2.

[0019] In Fig. 1 to Fig. 5, either the X direction (see Fig. 1, Fig. 2, Fig. 3, and Fig. 4), the Y direction (see Fig. 1, Fig. 2, Fig. 4, and Fig. 5), or the Z direction (see Fig. 3 and Fig. 5) is described. The Y direction is a side that intersects with the X direction, and in the following description, the X direction and the Y direction are perpendicular to each other. The Z direction is a direction perpendicular to each of the X direction and the Y direction. In other words, the Z direction is a normal direction to the XY plane that includes the X direction and the Y direction. In the following description, "thickness" basically means the length in the Z direction. In addition, in the following description, "planar view" basically means a planar view of the XY plane.

[0020] The semiconductor device PKG1 of this embodiment includes a die pad (chip mounting portion, tab) DP (see FIG. 3 and FIG. 4) and a semiconductor chip CP (see FIG. 3 and FIG. 4) mounted on the die pad DP via a die bond material DB (see FIG. 3 and FIG. 4). The semiconductor device PKG1 also includes a plurality of leads (terminals, external terminals) LD arranged around the semiconductor chip CP (die pad DP), and a plurality of wires (conductive members) BW (see FIG. 3 and FIG. 4) that electrically connect a plurality of pads (electrodes, bonding pads) PD (see FIG. 3 and FIG. 4) of the semiconductor chip CP to the plurality of leads LD. A plurality of suspension leads TL (see FIG. 4) are connected to the die pad DP. The semiconductor device PKG1 also includes an encapsulant (resin body) MR that encapsulates the semiconductor chip CP, the plurality of wires BW, and a portion of the plurality of leads LD.

[0021] The planar shape of the sealing body (resin body) MR shown in Fig. 1 is a rectangle, and in this embodiment, for example, a square. The sealing body MR has an upper surface MRt, a lower surface (rear surface, mounting surface) MRb (see Fig. 2) located opposite to the upper surface MRt, and a side surface MRs located between the upper surface MRt and the lower surface MRb. In the example shown in Fig. 3, the side surface MRs intersects with the upper surface MRt and the lower surface MRb. More specifically, in the example shown in Fig. 3, the side surface MRs is perpendicular to the upper surface MRt and the lower surface MRb.

[0022] 2, in the semiconductor device PKG1, a plurality of leads LD are arranged along each side (side surface MRs) of the sealing body MR. Each of the plurality of leads LD is made of a metal material, and in this embodiment, is made of, for example, copper (Cu) or a copper alloy.

[0023] 2, a part of each lead LD (lower surface LDb) is exposed from the sealing body MR at the lower surface MRb of the sealing body MR. A metal film SD is formed on the exposed portion of the lead LD from the sealing body MR, and the lower surface LDb is covered with the metal film SD. The metal film SD is a plating film formed by, for example, a plating method, and is made of, for example, a solder material, and functions as a bonding material when the lead LD is bonded to a terminal on the mounting board side, which will be described later.

[0024] The metal film SD (solder material) of this embodiment is made of so-called lead-free solder that does not substantially contain lead (Pb), such as tin (Sn) only, tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag). Here, lead-free solder means solder containing 0.1 wt% or less lead (Pb), and this content is set as the standard of the RoHS (Restriction of Hazardous MBstances) Directive. Hereinafter, in this embodiment, when solder material or solder components are described, lead-free solder is meant unless otherwise specified.

[0025] As shown in FIG. 2, each of the multiple leads LD has a portion (wire bond portion) LDm and a portion (end portion, step portion) LDe that is disposed at a position farther from the die pad DP than the portion LDm.

[0026] As shown in FIG. 3, the portion LDm has an upper surface LDt and a lower surface LDb located opposite the upper surface LDt. A wire BW is connected to the upper surface LDt of the portion LDm. The portion LDe has an upper surface LDt and a lower surface (step surface) LDb2 located opposite the upper surface LDt. The distance from the upper surface LDt to the lower surface LDb2 is shorter than the distance from the upper surface LDt to the lower surface LDb. The thickness of the portion LDe is thinner than the thickness of the portion LDm.

[0027] Although the details will be described later, in the peripheral portion of the lower surface (mounting surface) of the semiconductor device PKG1, a portion LDe, which is a step portion, is provided in each of the plurality of leads LD, thereby improving visibility in an inspection after mounting. In addition, as shown in FIG. 5, in the case of this embodiment, a portion (part) MRW of the sealing body MR made of an insulating material is interposed between the portions LDe of the adjacent leads LD. In detail, the plurality of leads LD arranged in the Y direction shown in FIG. 4 have two leads LD adjacent to each other. Among the two adjacent leads LD shown in FIG. 5, a portion MRW of the sealing body MR made of an insulating material is interposed between one portion LDe and the other portion LDe. In the thickness direction (Z direction) of the sealing body MR, the length from the upper surface MRt to the lower surface MRb of the portion MRW is longer than the length from the upper surface MRt of the sealing body MR to the lower surface LDb2 of the portion LDe of the lead LD, as shown in FIG. 5. If a plane including the lower surface LDb2 is taken as a reference plane, the portion MRW protrudes from the reference plane so that the length from the upper surface MRt to the lower surface MRb of the portion MRW is longer than the length from the upper surface MRt of the sealing body MR to the lower surface LDb2 of the portion LDe of the lead LD.

[0028] When a partial MRW is interposed between the portions LDe of two adjacent leads LD, the direction of spreading of the solder joined to the lead LD is restricted by the partial MRW (more specifically, the portion of the partial MRW that protrudes from the reference plane including the lower surface LDb2). As a result, compared to the case where there is no partial MRW, even if the distance between the adjacent leads LD is made smaller, it is possible to prevent short circuits between the leads.

[0029] The portion LDm has a side surface (lead side surface) LDs facing the die pad DP (specifically, a side surface DPs of the die pad DP) and a side surface (lead side surface) LDs2 located opposite the side surface (lead side surface) LDs3. The side surface LDs is continuous with the upper surface LDt and the lower surface LDb. The side surface LDs2 is continuous with the lower surface LDb2 and the lower surface LDb.

[0030] The part LDe has a side surface (lead side surface) LDs that is located at a position farthest from the part LDm. The side surface LDs is located at a position farthest from the die pad DP among the multiple lead side surfaces that each of the multiple leads LD has. The side surface LDs is connected to the upper surface LDt and the lower surface LDb2. Although details will be described later, the semiconductor device PKG1 is manufactured by a so-called MAP type manufacturing method. In the MAP type semiconductor device, the lead LD is cut together with the sealing body MR in a singulation process that will be described later. For this reason, as shown in FIG. 3, the side surface LDs is arranged on an extension of the side surface MRs of the sealing body MR. In other words, the side surface MRs and the side surface LDs are arranged in the same plane. In further other words, in the Z direction, the position of the side surface LDs and the position of the side surface MRs match. Such a state is called "the side surface LDs and the side surface MRs are flush with each other."

[0031] As shown in FIG. 2, the lower surface DPb of the die pad (chip mounting portion, tab) DP is exposed from the sealing body MR at the lower surface MRb of the sealing body MR. That is, the semiconductor device PKG1 is a die pad exposed type (tab exposed type) semiconductor device. The die pad DP is made of a metal material having a higher thermal conductivity than the sealing body MR, and in this embodiment, is made of, for example, copper (Cu) or a copper alloy. In this way, the die pad exposed type semiconductor device can improve the heat dissipation of the package compared to a semiconductor device in which the die pad DP is not exposed by exposing a metal member (die pad DP) such as copper (Cu) having a higher thermal conductivity than the sealing body MR. In the example shown in FIG. 2 and FIG. 3, a metal film SD that functions as a bonding material during mounting is formed on the lower surface DPb of the die pad DP, and covers the lower surface of the above-mentioned base material. The metal film SD is a plating film (solder film) formed by, for example, a plating method as described above.

[0032] As shown in Figures 2 and 4, the top surface (chip mounting surface) DPt of the die pad DP has a quadrangle (four-sided) planar shape. In this embodiment, it is, for example, a square. In the example shown in Figure 4, the outer size (planar size) of the die pad DP is larger than the outer size (planar size of the back surface CPb) of the semiconductor chip CP. In this way, by mounting the semiconductor chip CP on a die pad DP having an area larger than its outer size and exposing the lower surface DPb of the die pad DP from the sealing body MR, it is possible to improve heat dissipation.

[0033] 3 and 4, a semiconductor chip CP is mounted on the die pad DP. The semiconductor chip CP is mounted in the center (region including the center) of the die pad DP. As shown in FIG. 3, the semiconductor chip CP is mounted on the die pad DP via a die bond material (adhesive material) DB with the back surface CPb facing the top surface DPt of the die pad DP. That is, the semiconductor chip CP is mounted by a so-called face-up mounting method in which the opposite surface (back surface CPb) of the front surface (main surface) CPt on which the multiple pads PD are formed faces the chip mounting surface (top surface DPt). This die bond material DB is an adhesive material used when die-bonding the semiconductor chip CP. In this embodiment, for example, a die bond material DB containing metal particles made of silver (Ag) or the like in an epoxy-based thermosetting resin is used.

[0034] As shown in Fig. 4, the planar shape of the semiconductor chip CP mounted on the die pad DP is a rectangle. In this embodiment, it is, for example, a square. Also, as shown in Fig. 3, the semiconductor chip CP has a front surface (main surface, upper surface) CPt, a back surface (main surface, lower surface) CPb located opposite to the front surface CPt, and a side surface CPs located between the front surface CPt and the back surface CPb.

[0035] 3 and 4, a plurality of pads (bonding pads) PD are formed on the front surface CPt of the semiconductor chip CP, and in this embodiment, the plurality of pads PD are formed along each side of the front surface CPt. Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (more specifically, a semiconductor element forming region provided on the upper surface of the base material (semiconductor substrate) of the semiconductor chip CP). The plurality of pads PD are electrically connected to the semiconductor elements via wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip CP (more specifically, between the front surface CPt and the semiconductor element forming region, not shown).

[0036] The semiconductor chip CP (more specifically, the substrate of the semiconductor chip CP) is made of, for example, silicon (Si). An insulating film covering the substrate and wiring of the semiconductor chip CP is formed on the surface CPt, and the surfaces of the multiple pads PD are exposed from the insulating film at openings formed in the insulating film. The pads PD are made of metal, and in this embodiment, are made of, for example, aluminum (Al) or an alloy layer mainly containing aluminum (Al).

[0037] 4, a plurality of leads LD made of, for example, the same copper (Cu) as the die pad DP are arranged around the semiconductor chip CP (in other words, around the die pad DP). Each of the plurality of leads LD is arranged so as to be spaced apart from the die pad DP. Also, each of the plurality of leads LD is arranged so as to be spaced apart from one another.

[0038] A plurality of pads (bonding pads) PD formed on a surface CPt of the semiconductor chip CP are electrically connected to a plurality of leads LD via a plurality of wires (conductive members) BW. The wires BW are made of, for example, gold (Au) or copper (Cu), and a part (for example, one end) of the wires BW is bonded to the pads PD, and the other part (for example, the other end) is bonded to a bonding region on the upper surface LDt of the lead LD. Although not shown, a plating film is formed on the surface of the bonding region of the lead LD. The plating film is made of, for example, silver (Ag) or gold (Au). By forming a plating film made of silver (Ag) or gold (Au) on the surface of the bonding region (wire bonding region) of the lead LD (inner lead portion), the bonding strength with the wires BW made of gold (Au) can be improved.

[0039] As shown in FIG. 4, a plurality of hanging leads TL are connected (joined) to the die pad DP. One end of each of the hanging leads TL is connected to a corner of the die pad DP, which is a rectangle in plan view. The other end of each of the hanging leads TL extends toward a corner of the sealing body MR. By extending the hanging leads TL toward the corner of the sealing body MR, the arrangement of the leads LD arranged along each side (each main side) of the sealing body MR can be arranged without being disturbed, so that the number of leads LD, that is, the number of terminals of the semiconductor device PKG1 can be increased. In addition, the hanging leads TL are half-etched from the lower surface side, and the lower surface side is sealed by the sealing body MR. This allows the hanging leads TL and the sealing body MR to be firmly fixed, so that the hanging leads TL can be prevented from falling off the sealing body MR.

[0040] <State after semiconductor device mounting> Next, a state in which the semiconductor device described with reference to Figures 1 to 4 is mounted on a mounting board will be described. Figure 6 is a cross-sectional view showing a state in which the semiconductor device shown in Figure 3 is mounted on the mounting surface of a mounting board via a bonding material. The mounting board structure shown in Figure 6 has a mounting board MB and a semiconductor device PKG1 mounted on the mounting board MB.

[0041] A mounting board (motherboard, wiring board) MB has an upper surface (mounting surface) MBt which is an electronic component mounting surface, and the semiconductor device PKG1 described with reference to Figs. 1 to 4 is mounted on the upper surface MBt. A plurality of lands (terminals) LND which are terminals on the mounting board side are arranged on the upper surface MBt. In the example shown in Fig. 6, the mounting board MB includes a plurality of lands (terminals for connecting leads) LNDa and lands (terminals for connecting die pads) LNDb. The upper surface MBt is covered with an insulating film (solder resist film) SR1, and the insulating film SR1 has openings formed at positions overlapping with the plurality of lands LND, and the plurality of lands LND are exposed from the insulating film SR1 through the openings.

[0042] A bonding material SD1 is disposed (applied) on each of the lands LND. The bonding material SD1 is made of, for example, a solder material, and is a metal member integrated with the metal film SD shown in FIG.

[0043] In the process of electrically connecting the semiconductor device PKG1 and the mounting board MB via the bonding material SD1 made of solder, for example, a reflow process is performed in which the solder is heated to the melting point of the solder or higher and then cooled. At this time, the metal film SD (see FIG. 3) is integrated with the bonding material SD1. By this reflow process, the bonding material SD1 is bonded to the leads LD and lands LNDa (or to the die pad DP and lands LNDb), and the semiconductor device PKG1 and the mounting board MB are electrically connected via the bonding material SD1.

[0044] At this time, when the bonding material SD1 is heated, the bonding material SD1 spreads over the entire exposed surface of the land LND. The bonding material SD1 also spreads over the entire lower surface DPb, which is the exposed surface of the die pad DP. The bonding material SD1 also spreads over the lower surface LDb of the exposed surface of the lead LD, and over the step portion ST between the lower surface LDb and the lower surface LDb2, which is shown in FIG. 10 to be described later. On the other hand, as shown in FIG. 3, the metal film SD is not formed on the side surface LDs, so the bonding material SD1 shown in FIG. 6 does not easily spread over the side surface LDs.

[0045] Next, after the semiconductor device PKG1 is mounted on the mounting board MB, the mounting state of the mounted semiconductor device PKG1 is visually inspected. In this process, the connection between the semiconductor device PKG1 and the mounting board MB, i.e., the bonding state by the bonding material SD1, is inspected. In this process, for example, the inspection is performed visually from the upper surface side of the semiconductor device PKG1 (the upper surface MRt side of the sealing body MR shown in FIG. 6) or by using image processing.

[0046] In this embodiment, a step portion (part LDe) is provided on the periphery of each of the leads LD. In this case, the distance (height difference) from the lower surface LDb2 of the part LDe to the land LNDa is greater than the distance (height difference) from the lower surface LDb of the part LDm to the land LNDa. Therefore, a solder fillet that is easy to see from above (in other words, easy to judge pass / fail) is formed on the periphery of the bonding material SD1.

[0047] As described above, in the present embodiment, each of the multiple leads LD has a portion LDe on the periphery of the semiconductor device PKG1, so that the electrical connection state between the multiple leads LD and the multiple lands LNDa can be easily confirmed during visual inspection after mounting on the mounting board MB.

[0048] A more detailed structure of the portion LDe of the lead LD will be described later.

[0049] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device shown in Figures 1 to 4 will be described. Figure 7 is a flow diagram showing an example of the manufacturing process of the semiconductor device shown in Figures 1 to 5. In the example shown in Figure 7, the manufacturing method of the semiconductor device of this embodiment includes a lead frame preparation step, a semiconductor chip mounting step, a wire bonding step, a sealing step, a laser irradiation step, a metal film formation step (plating step), and a singulation step.

[0050] <Lead frame preparation process> First, in the lead frame preparation step shown in Fig. 7, the lead frame LF shown in Figs. 8 and 9 is prepared. Fig. 8 is a plan view of the lead frame prepared in the lead frame preparation step shown in Fig. 7. Fig. 9 is an enlarged plan view of two of the multiple device formation parts shown in Fig. 8. Fig. 10 is an enlarged cross-sectional view taken along line CC in Fig. 9. Fig. 11 is an enlarged cross-sectional view taken along line DD in Fig. 9. Although Fig. 9 is a plan view, the thin-walled part LFhf is shown by hatching to clearly indicate the range of the part where the plate thickness is thin.

[0051] 8, the leadframe LF prepared in this step includes a plurality of device forming portions LFd connected to a frame portion LFf. The leadframe LF also includes a dicing portion LFc provided between adjacent device forming portions LFd among the plurality of device forming portions LFd.

[0052] The lead frame LF is made of, for example, copper (Cu) or a copper alloy. Each of the device forming parts LFd is connected to a frame part LFf. The frame part LFf is a support part that supports each member formed in the device forming part LFd until the singulation process shown in FIG.

[0053] Each of the multiple device forming parts LFd corresponds to one semiconductor device PKG1 shown in FIG. 1. Each of the multiple device forming parts LFd has a die pad DP and multiple leads LD arranged at a distance from the die pad DP. The lead frame LF is a so-called multi-piece substrate in which multiple device forming parts LFd are arranged in a matrix. In this way, by using a lead frame LF having multiple device forming parts LFd, multiple semiconductor devices PKG1 (see FIG. 1) can be manufactured collectively, thereby improving manufacturing efficiency.

[0054] The dicing portion LFc is a region to be cut by a dicing blade in the singulation process shown in Fig. 7. The multiple dicing portions LFc include multiple dicing portions LFcX extending in the X direction and multiple dicing portions LFcY extending in the Y direction.

[0055] As shown in Fig. 9, the dicing portion LFc is formed so as to surround the periphery of the device forming portion LFd. Furthermore, in the dicing portion LFc, a tie bar LFtb is arranged so as to surround the periphery of the device forming portion LFd. The tie bar LFtb is formed integrally with a plurality of leads LD and a frame portion (frame body) LFf shown in Fig. 8.

[0056] When distinguishing between the two device formation parts LFd shown in Fig. 9, they can be distinguished as device formation part LFd1 and device formation part LFd2. For example, the embodiment shown in Fig. 9 can be expressed as follows. That is, the lead frame LF has a device formation part LFd1, a device formation part LFd2 arranged adjacent to the device formation part LFd1 in the X direction, and a dicing part LFcY arranged between the device formation parts LFd1 and LFd2 and extending in the Y direction.

[0057] Also, a part of the lead frame LF is processed in advance so as to have a thinner plate thickness. In other words, as shown by hatching in FIG. 9, the lead frame LF has a thin portion (half-etched portion) LFhf that is thinner than other regions. In the example shown in FIG. 9 to FIG. 11, the thin portion LFhf is formed by half-etching, which performs etching from the lower surface LDb side of the lead LD to the middle of the thickness direction. In more detail, the thickness of the tie bar LFtb and a portion of the lead LD adjacent to the tie bar LFtb (portion LDe shown in FIG. 10) is thinner than the thickness of the other portion of the lead LD (portion LDm shown in FIG. 10).

[0058] As shown in Fig. 10, the tie bar LFtb and a part of the lead LD arranged in the dicing section LFc between the adjacent device formation sections LFd are made into a thin section LFhf. In other words, the tie bar LFtb and a part of the lead LD have a part of the lower surface side of the lead frame removed, and are thinner than the other parts of the lead LD. In yet another way, the tie bar LFtb and the part LDe of the lead LD have a part of the metal removed in advance, and a step section ST is formed.

[0059] As a variation of this embodiment, there is a method in which a step portion is not formed in the lead frame preparation process, and the metal of the lead LD is removed in the laser irradiation process shown in FIG. 7 to form the portion LDe shown in FIG. 3 and FIG. 5.

[0060] In the case of this embodiment, the step portion ST (in other words, the portion LDe of the lead LD) shown in Fig. 10 is formed in advance in the lead frame preparation process. In this way, when the step portion ST is formed in advance, the resin in the step portion ST is removed in the laser irradiation process shown in Fig. 7. Therefore, the irradiation time of the laser light in the laser irradiation process can be shortened.

[0061] Furthermore, in the lead frame preparation step, if the inside of the dicing portion LFc is already formed into the thin portion LFhf, the amount of the metal material to be cut can be reduced in the singulation step shown in Fig. 7. This reduces metal burrs and the like that occur during cutting, and improves the reliability of the semiconductor device.

[0062] 11, the hanging lead TL has a thin portion LFhf. By forming the hanging lead TL as the thin portion LFhf in this manner, the lower surface side of the hanging lead TL can be sealed in the sealing process shown in FIG. 7, and therefore, it is possible to prevent the die pad DP from falling off from the sealing body.

[0063] Incidentally, as described with reference to FIG. 6, in order to form a solder fillet that is easily visible in an appearance inspection, it is preferable that the depth D1 of the step portion ST shown in FIG. 10 is deep. For example, in the case of the example shown in FIG. 10, the depth D1 of the step portion ST is half the thickness T1 of the portion LDm of the lead LD. In other words, the thickness T2 of the portion LDe of the lead LD is half the thickness T1 of the portion LDm. The thickness T2 of the portion LDe of the lead LD can be thinned within a range in which the strength that each of the multiple leads LD can hold is obtained during the lead preparation process to the singulation process shown in FIG. 7. Therefore, it is preferable that the depth D1 of the step portion ST is half or more of the thickness T1 of the portion LDm of the lead LD. Also, it is preferable that the thickness T2 of the portion LDe of the lead LD is half or less of the thickness T1 of the portion LDm. For example, the thickness T1 of the portion LDm of the lead LD is 150 μm to 200 μm. On the other hand, the depth D1 of the step portion ST is preferably about 75 μm to 100 μm.

[0064] In this embodiment, the etching process is described as a method for forming the partial LDe, but there are various modified methods for forming the partial LDe (methods for removing a part of the metal member constituting the lead frame). For example, a method for forming the partial LDe by so-called half dicing using a cutting tool such as a dicing blade DB1 shown in FIG. 19, which will be described later, can be exemplified.

[0065] When forming the partial LDe by half dicing, metal burrs may occur around the partial LDe. However, even if metal burrs occur in the lead frame preparation process, the metal burrs are sealed in the sealing process shown in Fig. 7. Therefore, in addition to the etching process, various modified methods can be applied as a method for forming the partial LDe in the lead frame preparation process.

[0066] <Semiconductor chip installed> In the semiconductor chip mounting process shown in Fig. 7, a semiconductor chip CP is mounted on a die pad DP via a die bond material DB as shown in Fig. 3 and Fig. 4. This process will be described with reference to Fig. 3 and Fig. 4, and the semiconductor chip CP is mounted on the die pad DP of each of the multiple device formation parts LFd shown in Fig. 9.

[0067] In this process, for example, the semiconductor chip CP is mounted in a so-called face-up mounting manner in which the back surface CPb (the surface opposite to the front surface CPt on which the multiple pads PD are formed) of the semiconductor chip CP faces the top surface DPt of the die pad DP. As shown in Fig. 4, the semiconductor chip CP is mounted in the center of the die pad DP such that each side of the front surface CPt is disposed along each side of the die pad DP.

[0068] In this process, the semiconductor chip CP is mounted via a die bond material DB, which is, for example, an epoxy-based thermosetting resin, and the die bond material DB is a paste material that has fluidity before being hardened (thermosetting). When a paste material is used as the die bond material DB in this way, the die bond material DB is first applied onto the die pad DP, and then the back surface CPb of the semiconductor chip CP is bonded to the top surface DPt of the die pad DP. After bonding, the die bond material DB is hardened (for example, by performing a heat treatment), and the semiconductor chip CP is fixed onto the die pad DP via the die bond material DB, as shown in FIG.

[0069] In this step, the die bond material DB and the semiconductor chip CP are arranged on the die pads DP provided in each of the device formation portions LFd, and the semiconductor chip CP is mounted on each of the device formation portions LFd.

[0070] In the present embodiment, the die bond material DB is a paste material made of a thermosetting resin, but various modifications can be applied. For example, a solder material may be used as the die bond material DB.

[0071] <Wire bonding process> Next, in the wire bonding process shown in Figure 7, as shown in Figures 3 and 4, multiple pads (electrodes) PD and multiple leads LD of the semiconductor chip CP are electrically connected to each other via multiple wires (conductive members) BW.

[0072] In this process, for example, a lead frame LF on which semiconductor chips CP (see FIG. 3) are mounted on die pads DP of a plurality of device forming parts LFd shown in FIG. 9 is placed on a heat stage (lead frame heating table) not shown. Then, as shown in FIGS. 3 and 4, pads PD and leads LD of the semiconductor chip CP are electrically connected via wires BW. In this embodiment, the wires BW are connected by a so-called nail head bonding method in which the wires BW are supplied via a capillary not shown, and are bonded by using ultrasonic waves and thermocompression in combination. Note that various modified examples can be applied to the wire bonding method.

[0073] A plating film made of, for example, silver (Ag) or gold (Au) is formed on a part of the lead LD (a bonding region arranged at the tip of the inner lead), and a part of the wire BW is electrically connected to the lead LD through this plating film. The wire BW is made of a metal, and in this embodiment, it is made of, for example, gold (Au) or copper (Cu).

[0074] In this embodiment, the wire is connected by a so-called positive bonding method in which a part (end) of the wire is connected to the pad PD of the semiconductor chip CP, and then the other part of the wire BW is connected to a bonding area (a part of the upper surface of the lead LD) of the lead LD. The wire bonding area is located opposite to the lower surface LDb shown in Fig. 3. In other words, the wire BW is bonded to the thick part LDm of the lead LD, so that a sufficient load can be applied when bonding the wire BW to the lead LD, thereby improving the bonding strength.

[0075] In this process, wires BW are bonded to a plurality of leads LD provided in each of the device formation parts LFd shown in Fig. 9. As a result, in each of the device formation parts LFd, the semiconductor chip CP and the plurality of leads LD are electrically connected to each other via the plurality of wires BW.

[0076] <Sealing process> Next, in the sealing step shown in Fig. 7, a sealing body MR is formed to seal a part of the die pad DP, each part of the leads LD, the wires BW, and the semiconductor chip CP, as shown in Fig. 13. Fig. 12 is a plan view showing a sealing body formed in the sealing body step shown in Fig. 7. Fig. 13 is an enlarged cross-sectional view taken along line EE in Fig. 12, showing a state in which the lead frame is placed in the cavity of a molding die.

[0077] In this step, as shown in FIG. 13, the sealing body MR is formed so that the lower surfaces LDb of the leads LD provided in the respective device formation portions LFd are exposed and the lower surface DPb of the die pad DP is exposed.

[0078] In this process, for example, in a state in which the lead frame LF is sandwiched between the molding die 50 shown in Fig. 13, softened resin is pressed into the molding die 50 and then hardened, thereby forming the sealing body MR shown in Fig. 12 by a so-called transfer molding method. The resin is made of an insulating material.

[0079] The molding die 50 includes an upper die (die) 51 arranged above the lead frame LF, and a lower die (die) 52 arranged below the lead frame LF. The upper die 51 includes a clamp surface (not shown) for pressing the lead frame LF, and a cavity (recessed portion) 53 formed inside the clamp surface. The lower die 52 includes a support surface (die surface, pressing surface, surface) 52a arranged opposite the cavity 53 and supporting the lead frame LF. In this embodiment, since a QFN type package is manufactured, no cavity is formed in the support surface 52a of the lower die 52.

[0080] In the sealing process, sealing resin is pressed into the cavity 53 to seal the semiconductor chip CP (see FIG. 13) and the plurality of wires BW (see FIG. 13). In addition, a portion of the plurality of leads LD (a portion excluding the lower surface LDb) and a portion of the die pad DP (a portion excluding the lower surface DPb) are also sealed with the sealing resin.

[0081] As shown in FIG. 13, a tape material (resin film) TP is placed between the lead frame LF and the lower die 52. A pressing force is applied to the lower surface side (rear surface side, mounting surface side) of the lead frame LF from the support surface 52a of the lower die 52 via the tape material TP. Therefore, as shown in FIG. 13, the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP are easily adhered to the tape material TP. In other words, in the sealing process of this embodiment, the sealing body MR is formed in a state in which the tape material is adhered to the lower surface DPb of the die pad DP and the lower surface LDb of each of the multiple leads LD. By adhering the tape material TP, it is possible to suppress the sealing resin from wrapping around the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP. In other words, it is possible to expose the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP.

[0082] Next, the resin supplied to the cavity 53 is thermally cured to form the sealing body MR shown in FIG. 12. More specifically, after the sealing body MR is molded by the cavity 53, a part of the thermosetting resin contained in the sealing body MR is heated until it is cured (called temporary curing). When this temporary curing makes it possible to remove the lead frame LF from the molding die, the lead frame LF is removed from the molding die. Then, the lead frame LF is transported to a heating furnace for further heat treatment (cure bake). As a result, the remaining part of the thermosetting resin is cured, and the sealing body MR is obtained.

[0083] In this embodiment, a sealing body MR is formed so as to seal a plurality of device formation portions LFd collectively. Focusing on the portion shown in FIG. 13, the sealing process includes the following steps. The sealing process includes a step of adhering one tape material TP over the device formation portions LFd1 and LFd2. The sealing process also includes a step of housing the device formation portions LFd1 and LFd2 in one cavity 53. The sealing process also includes a step of supplying resin into the cavity 53 to seal both the device formation portions LFd1 and LFd2 collectively.

[0084] The timing for adhering the tape material TP to the lead frame LF may be as follows. For example, when an adhesive layer is provided on one surface of the tape material TP, the tape material TP may be attached in advance before placing the lead frame LF in the cavity 53. In another example, the tape material TP is placed in advance on the support surface 52a of the lower die 52, and the lead frame LF is placed on top of it. In this case, the lead frame LF and the tape material TP are pressed and adhered to each other by the supply pressure of the sealing resin.

[0085] A semiconductor package in which a sealing body MR is formed so as to collectively cover a plurality of device forming portions LFd arranged in a matrix (array) as in this embodiment is called a MAP (Multi Array Package) type semiconductor device. Also, a sealing method for sealing a plurality of device forming portions LFd collectively is called a block molding method. In a MAP type semiconductor device, the distance between each of the plurality of device forming portions LFd can be reduced, so that the effective area of ​​one lead frame LF is increased. In other words, the number of products that can be obtained from one lead frame LF increases. In this way, by increasing the effective area of ​​one lead frame LF, the efficiency of the manufacturing process can be improved. In particular, when several tens of products are obtained from one lead frame LF, the effect of improving the manufacturing efficiency due to the increased effective area is large.

[0086] Here, in this process, as shown in FIG. 13, the sealing resin wraps around and adheres to the area not in close contact with the molding die 50 or the tape material TP. Therefore, the sealing body MR is formed in the thin portion LFhf formed by the half etching process. In other words, in this process, the thin portion LFhf is sealed with the resin. Therefore, in order to expose the lower surface LDb2 of the portion LDe shown in FIG. 3 from the sealing body MR, a process of removing the sealing body MR covering the lower surface LDb2 is required. In this embodiment, a laser irradiation process shown in FIG. 7 is performed as a process of removing the sealing body MR covering the lower surface LDb2.

[0087] <Laser irradiation process> In the laser irradiation process shown in FIG. 7, after removing the tape material TP shown in FIG. 13, a region of the sealing body MR covering a part of each of the leads LD is irradiated with a laser beam. FIG. 14 is an enlarged cross-sectional view showing a state in which the sealing body covering the end of the lead is irradiated with a laser beam in the laser irradiation process shown in FIG. 7. FIG. 15 is an enlarged plan view showing an example of a scanning direction of a position to be irradiated with a laser beam in the laser irradiation process shown in FIG. 7. FIG. 16 is an enlarged plan view showing an example after the sealing body is removed by the laser irradiation process shown in FIG. 7. FIG. 17 is an enlarged cross-sectional view taken along the line FF in FIG. 16. FIG. 18 is an enlarged cross-sectional view taken along the line GG in FIG. 16.

[0088] As shown in FIG. 14, in the laser irradiation step, the portions of the sealing body MR that cover the lower surfaces LDb2 of the respective leads LD are selectively irradiated with laser light LZ to expose the lower surfaces LDb2.

[0089] Focusing on the device formation part LFd1 shown in Fig. 15, the multiple leads LD are arranged adjacent to each other so as to be spaced apart from each other in the Y direction. Of the sealing body MR, the portions covering the lower surfaces LDb2 of the multiple leads LD are selectively removed. Therefore, the partial MRW described with reference to Fig. 5 is formed between the portions LDe adjacent to each other in the Y direction (in other words, between the lower surfaces LDb2 adjacent to each other in the Y direction). In the laser irradiation process, the partial MRW is not irradiated with the laser light LZ (see Fig. 14).

[0090] Note that "selectively irradiating B of A with laser light" means "at least B is irradiated with laser light, and there is a part of A that is not irradiated with laser light." Therefore, "selectively irradiating B of A with laser light" includes cases where there is a part of "B" that is not irradiated with laser light. Also, "selectively irradiating B of A with laser light" includes cases where a part of "A" is irradiated with laser light.

[0091] A method using laser irradiation is particularly effective as a method for selectively removing the portions covering the lower surface LDb2 of each of the multiple leads LD after the sealing process. This is because the laser light LZ can increase the directivity. For example, in the case of this embodiment, the laser light LZ is an ultraviolet laser with a wavelength of 355 nm. The maximum output of the laser light LZ is 20 W (100 kHz). In addition, the spot diameter of the laser light LZ (the diameter of the circularly irradiated spot) is about 30 μm to 35 μm.

[0092] On the other hand, the width WLDe of the lower surface LDb2 (the length in the Y direction in the example shown in FIG. 15) is about 250 μm. That is, the irradiation area of ​​the laser beam LZ irradiated in the laser irradiation process of the present embodiment (the area of ​​the irradiation range when the irradiation position of the laser beam LZ is fixed) is smaller than the planar area of ​​the lower surface LDb2.

[0093] Therefore, in order to expose most of the lower surface LDb2, it is necessary to scan the laser light LZ and sequentially remove the sealing body MR covering the lower surface LDb2. In the case of this embodiment, for example, as shown in FIG. 16 with an arrow, the irradiation position of the laser light LZ (see FIG. 14) is sequentially moved along the scanning track LZS.

[0094] In addition, in order to improve the connection reliability between the bonding material SD1 and the lower surface LDb2 of the lead LD shown in Fig. 6, it is necessary to reliably expose the lower surface LDb2. For this reason, in the laser irradiation step, in addition to the sealing body MR, the lower surface LDb2 of the portion LDe of the lead LD is also irradiated with the laser light LZ (see Fig. 14).

[0095] Therefore, in the laser irradiation process, a plurality of grooves LZT extending in the Y direction are formed on the lower surface LDb2. In terms of the flatness of the surface, the following state is achieved. That is, as shown in FIG. 17, after the laser irradiation process is completed, the lower surface LDb2 is rougher than the lower surface LDb. In other words, after the laser irradiation process is completed, the flatness of the lower surface LDb2 is lower than the flatness of the lower surface LDb.

[0096] When the sealing body MR is removed by laser irradiation, the portion irradiated with the laser light LZ shown in FIG. 14 and the surrounding portion are evaporated and removed. Therefore, from the viewpoint of preventing the removal of the sealing body MR other than the portion covering the lower surface LDb2, the range of the irradiated region irradiated with the laser light LZ in this process does not coincide with the range of the lower surface LDb2. Therefore, as shown in FIG. 16 and FIG. 18, it is preferable that the sealing body MR remains without being removed at the periphery of the lower surface LDb2. In other words, after the laser irradiation process is completed, a part of the lower surface LDb2 (the part LDc shown in FIG. 16 and FIG. 18) is preferably covered with the sealing body MR. In other words, it is preferable that the part LDe of the lead LD includes the part LDc covered with the sealing body MR.

[0097] On the other hand, in the metal film forming step shown in Fig. 7, in order to form the metal film SD on the side surface LDs2 of the portion LDm of the lead LD as shown in Fig. 3, it is necessary to expose the side surface LDs2 in this step. For this reason, as shown in Fig. 16, it is preferable that the scanning track LZS of the laser light LZ (see Fig. 14) is present in the vicinity of the side surface LDs2, and that the groove LZT closest to the side surface LDs2 among the multiple grooves LZT is in contact with the side surface LDs2. This allows the side surface LDs2 to be exposed from the sealing body MR in the laser irradiation step.

[0098] The above-mentioned structure of the plurality of grooves LZT, or the structure in which the portion LDe has the portion LDc that is covered by the sealing body MR, is a characteristic structure formed by removing a part of the sealing body MR by a laser irradiation process after the sealing process. Moreover, these structures remain in the completed semiconductor device PKG1 shown in Fig. 3. Therefore, with respect to the completed semiconductor device PKG1, it can be determined whether the laser irradiation process of this embodiment has been performed based on the presence or absence of the grooves LZT shown in Figs. 16 and 17, or the presence or absence of the portion LDc shown in Figs. 16 and 18.

[0099] Furthermore, no sealing body MR remains at the tip (the boundary with the side surface LDs in FIG. 3) farthest from the die pad DP of the lower surface LDb2 of the portion LDe of the lead LD shown in FIG. 3. In order to reliably remove the sealing body MR from this portion, in this embodiment, the sealing body MR is removed from an area wider than the planned area of ​​the portion LDe of the lead LD as shown in FIG.

[0100] Specifically, in the present embodiment, the lead frame LF is disposed between the tie bar LFtb and the lead LD (specifically, the portion LDe of the lead LD), and has a lead connection portion LFx having a lower surface LDb2. After the laser irradiation step is completed, a part of the lower surface LFb2 of the lead connection portion LFx is exposed from the sealing body MR, and the other part is sealed in the sealing body.

[0101] Although not shown in the drawings, by controlling the output and irradiation time of the laser irradiation, it is possible to reduce the unevenness to an extent that the grooves LZT shown in Fig. 16 and Fig. 17 cannot be visually recognized. As a modification of Fig. 16 and Fig. 18, there is a case where the entire lower surface LDb2 is exposed in the laser irradiation step (i.e., the entire portion of the sealing body MR that covers the lower surface LDb2 is removed).

[0102] Also, the scanning trajectory LZS shown in FIG. 16 is an example, and there are various modified examples of the scanning direction of the laser light LZ (see FIG. 14). For example, in the example shown in FIG. 16, the multiple grooves LZT extend in the Y direction, but as a modified example, the multiple grooves LZT may extend in the X direction. However, scanning the laser light LZ along the side surface LDs2 makes it less likely that unevenness will occur in the exposed state of the side surface LDs2 from the sealing body MR. From this viewpoint, it is preferable that the multiple grooves LZT extend along the Y direction, which is the same as the extension direction of the side surface LDs2, as shown in FIG. 16.

[0103] <Example of consideration> Incidentally, the inventors of the present application have studied a method of exposing the lower surface LDb2 by using a dicing blade instead of the laser irradiation process of the present embodiment. Fig. 19 is an enlarged cross-sectional view showing the study example corresponding to Fig. 14. Fig. 20 is an enlarged plan view showing the study example corresponding to Fig. 15.

[0104] The study example shown in Fig. 19 differs from the manufacturing method of the semiconductor device of the present embodiment in that a half dicing process is provided instead of the laser irradiation process shown in Fig. 7. In the half dicing process, a dicing blade (cutting edge) is made to travel along the dicing portion LFc to remove the sealing body MR (see Fig. 20) embedded in the step portion ST (see Fig. 10).

[0105] The dicing blade DB1 is an annular (ring-shaped) or disc-shaped cutting tool with a plurality of abrasive grains attached to a cutting portion arranged on the periphery of the circle. The cutting portion of the dicing blade DB1 with the plurality of abrasive grains attached thereto can be pressed against a workpiece to cut and remove the workpiece.

[0106] In the half dicing process, the sealing body MR is cut by a dicing blade DB1 to expose the lower surface LDb2 of the portion LDe of the lead LD. In addition, by running the dicing blade DB1 along the extending direction of the dicing portion LFc (see FIG. 20), the lower surface LDb2 of each of the leads LD can be sequentially exposed.

[0107] In this case, the dicing blade DB1 is rotated and moved linearly to cut the leads LD continuously. Therefore, compared to the laser irradiation process of the present embodiment, this has the advantage of higher manufacturing efficiency.

[0108] However, according to the study by the inventors of the present application, it was found that in the case of the method of this study example, if the distance between adjacent leads LD is narrow, there is a concern that the adjacent leads LD may be short-circuited due to the metal burr MS1 shown in Figure 20.

[0109] The metal burr MS1 shown in Fig. 20 is formed by the metal (e.g., copper in the case of the examined example) constituting the lead frame LF being dragged in the rotation direction of the dicing blade DB1 shown in Fig. 19 in the half dicing process. In the example shown in Fig. 20, the metal burr MS1 is formed from the top to the bottom of the page.

[0110] Since the metal burr MS1 itself is made of copper or a copper alloy, its wettability to solder is significantly reduced when the metal burr MS1 is oxidized, for example, by heat treatment, etc. However, in order to improve the wettability of the lead LD to solder, as shown in Figure 7, it is necessary to carry out a metal film formation process to form a metal film SD (see Figure 3) made of a metal that has a higher wettability to solder than copper.

[0111] If the metal film forming process is performed in a state where the metal burr MS1 is exposed from the sealing body MR, a metal film SD (see FIG. 3) is also formed on the surface of the metal burr MS1. Therefore, as described with reference to FIG. 6, when the semiconductor device of the study example is mounted on a mounting board MB, the solder spreads not only on the exposed surface of the lead LD from the sealing body MR but also on the metal burr MS1.

[0112] 20, in the case of the semiconductor device of the study example, the portion between the portions LDe of the adjacent leads LD is also cut by the dicing blade DB1 (see FIG. 19). Therefore, the portion MRW shown in FIG. 15 does not exist.

[0113] In this case, the solder that has spread onto the metal burr MS1 is likely to be integrated with the solder that has spread onto the adjacent lead LD, resulting in a state in which the adjacent leads LD are likely to be short-circuited via the solder.

[0114] In the case of this embodiment, the lower surface LDb2 shown in FIG. 15 is exposed by the laser irradiation process as shown in FIG. 7. Therefore, the metal burr MS1 shown in FIG. 20 is not generated. Therefore, even if the metal film formation process is performed after the laser irradiation process, the metal film SD (see FIG. 3) is formed on the lower surface LDb, the lower surface LDb2, and the side surface LDs2, and is not formed between the adjacent leads LD.

[0115] Moreover, the portion MRW shown in FIG. 5 and FIG. 15 functions as an insulating material for ensuring the insulation between adjacent leads LD.

[0116] Therefore, according to this embodiment, even if the interval between adjacent leads LD is narrow, it is possible to prevent the adjacent leads LD from being short-circuited. In other words, according to this embodiment, since it is possible to prevent the adjacent leads LD from being short-circuited, it is possible to reduce the distance between the adjacent leads LD. In other words, it is possible to reduce the planar size of the semiconductor device.

[0117] <Metal film formation process> Next, in the solder film formation step shown in Fig. 7, after the laser irradiation step, a metal film SD is formed on the lower surface LDb and the lower surface LDb2 shown in Fig. 22. Fig. 21 is an explanatory diagram that shows a schematic example of the metal film formation step shown in Fig. 7. Fig. 22 is an enlarged cross-sectional view showing a state in which a metal film is formed on the lead shown in Fig. 17.

[0118] In this process, as shown in FIG. 21, for example, the lead frame LF is immersed in a plating solution 61. The plating solution 61 is, for example, a solder solution. An anode bar 62 is immersed in the plating solution 61. In the electroplating method, the anode bar 62 is used as an anode, and the metal part of the lead frame LF is used as a cathode. For this reason, as shown in FIG. 21, the lead frame LF is connected to the negative pole of a power source 63, and the anode bar 62 is connected to the positive pole of the power source 63. When a current is applied in this state, a reduction reaction occurs on the cathode side, and a metal film SD (see FIG. 22) is formed on the surface of the metal part of the lead frame LF exposed from the sealing body MR. This method is called an electroplating method (also called an electrolytic plating method).

[0119] 22, a metal film SD is formed on the lower surface LDb, the side surface LDs2, and the lower surface LDb2 of the lead LD by electroplating. This metal film SD is made of a metal material that has higher wettability with solder than copper or copper alloy, which is the base material of the lead frame LF. In the case of this embodiment, the metal film SD is made of solder as described above.

[0120] As already described, in the case of this embodiment, the sealing body MR (see FIG. 14) embedded in the step portion ST shown in FIG. 10 is removed by irradiating it with the laser light LZ (see FIG. 14), so that the metal burr MS1 shown in FIG. 20 is not formed. Therefore, in the metal film forming step, the metal film SD is not formed between the leads LD adjacent to each other in one device formation portion LFd (see FIG. 9).

[0121] As explained at the end of the lead frame preparation process, as a modification of this embodiment, when the portion LDe is formed by half dicing, metal burrs may occur around the portion LDe. However, even if metal burrs occur in the lead frame preparation process, the metal burrs are sealed in the sealing process shown in Fig. 7. Therefore, even if the portion LDe is formed by half dicing in the lead frame preparation process, the metal film SD is not formed on the metal burrs in the metal film formation process.

[0122] As a modification of this embodiment, the metal film SD (see FIG. 22) may be formed by electroless plating. In the case of the electroplating method described as this embodiment, it is necessary to pass a current through the member on which the plating film is to be formed (the member to be plated), and therefore it is necessary to carry out this method before the singulation process described below. However, the film quality of the metal film SD is preferably formed by electroplating rather than by electroless plating.

[0123] On the other hand, in the case of electroless plating, since there is no need to pass a current through the plated member, it is also possible to carry out the metal film forming process after the singulation process described below. However, if electroless plating is carried out after the singulation process, a plating film is also formed on the surface of the metal burr MS2 (see FIG. 24 described below) described below. In this case, there is a concern that adjacent leads LD may be short-circuited via the metal burr MS2. Therefore, even when electroless plating is used, it is preferable to carry out the metal film forming process before the singulation process.

[0124] <Singulation process> Next, in the singulation step shown in Fig. 7, a dicing blade DB2 shown in Fig. 23 is run along the dicing portion LFc shown in Fig. 8 to divide and singulate each of the multiple device forming portions LFd. This step also includes a step of separating the device forming portions LFd1 and LFd2 shown in Fig. 23. Fig. 23 is an enlarged cross-sectional view showing the dicing step shown in Fig. 7. Note that Fig. 23 corresponds to the enlarged cross-section shown in Fig. 14. Fig. 24 is an enlarged side view showing one side of the semiconductor device after the dicing step shown in Fig. 7 is completed.

[0125] The dicing blade DB2 is an annular (ring-shaped) or disc-shaped cutting tool with a plurality of abrasive grains attached to a cutting portion arranged on the periphery of the circle. The cutting portion of the dicing blade DB2 with the plurality of abrasive grains attached thereto can be pressed against a workpiece to cut and remove the workpiece.

[0126] In the case of this embodiment, the portion of the sealing body MR shown in Fig. 15 that seals the tie bar LFtb of the dicing portion LFc is cut together with the tie bar LFtb. Also, the lead connection portion LFx shown in Fig. 16 is cut in this process.

[0127] 23, a side surface LDs of the lead LD and a side surface MRs of the sealing body MR are formed by this process. In the case of the present embodiment, since the lead LD and the sealing body MR are cut collectively, the side surface LDs is disposed on an extension of the side surface MRs of the sealing body MR, as already described with reference to FIG.

[0128] Incidentally, since cutting is performed using a dicing blade DB2 in this step, there is a possibility that metal burrs MS2 (see FIG. 24) may occur as described in the study example. As shown in FIG. 24, the metal burrs MS2 are formed on the side surface of the semiconductor device PKG1.

[0129] However, most of the metal burr MS2 is made of copper or copper alloy, which is the base material of the lead frame LF (see FIG. 23). The metal burr MS2 contains only a small amount of the metal film SD. Furthermore, in the case of this embodiment, the singulation process is performed after the metal film formation process, so that even if the metal burr MS2 occurs, a metal film that is highly wettable to solder will not be formed on the metal burr MS2.

[0130] For this reason, when the metal burr MS2 is oxidized by, for example, heat treatment, etc., the wettability of the metal burr MS2 with respect to solder is very low. Therefore, even if the metal burr MS2 occurs, the adjacent leads LD are unlikely to be short-circuited via the metal burr MS2.

[0131] Through the above steps, the semiconductor device PKG1 shown in Fig. 1 to Fig. 5 is obtained. After that, tests and inspections such as an electrical test and a visual inspection are performed as necessary, and those determined to be non-defective are transported to the next process, such as a packaging process for the semiconductor device.

[0132] <Variation 1> Next, a modified example of the embodiment described above will be described. Fig. 25 is an enlarged cross-sectional view showing a modified example of Fig. 14. Fig. 26 is an enlarged plan view showing a modified example of Fig. 15. In the embodiment described above, the tie bar LFtb is not irradiated with the laser light LZ (see Fig. 14) in the laser irradiation process, and the lower surface LDb2 of the tie bar LFtb remains covered with the sealing body MR at the stage when the laser irradiation process is completed.

[0133] On the other hand, in the case of this modified example, in the laser irradiation step, the laser light LZ is moved as shown in FIG. 25 to expose not only the lower surface LDb2 of the portion LDe of the lead LD, but also a part of the lower surface LDb2 of the tie bar LFtb from the sealing body MR (see FIG. 26).

[0134] In this modified example, two lead LDs adjacent to each other in the X direction can be irradiated with laser at the same time. Therefore, when irradiating a large number of lead LDs with laser, the number of times that the emission of the laser light LZ is turned off can be reduced by half. Therefore, as shown in Figs. 14 and 15, the processing efficiency of the laser irradiation process can be improved compared to the method of irradiating the laser light LZ (see Fig. 14) so ​​as to leave the sealing body MR on the tie bar LFtb.

[0135] However, from the viewpoint of suppressing the occurrence of metal burrs that are likely to occur in the dicing process, it is preferable to perform dicing in a state where the metal member is sealed in the sealing body MR. Therefore, from the viewpoint of suppressing the occurrence of metal burrs, it is preferable that the entire tie bar LFtb remains sealed in the sealing body MR at the stage where the laser irradiation process is completed, as shown in FIG.

[0136] <Variation 2> Next, another modification of the above-mentioned embodiment will be described. Although briefly described in the section on the lead frame preparation process, as a modification of the above-mentioned embodiment, there is a method in which a step portion is not formed in the lead frame preparation process, and the metal of the lead LD (see FIG. 27) is removed in the laser irradiation process shown in FIG. 7 to form the portion LDe shown in FIG. 3 and FIG. 5. FIG. 27 is an enlarged cross-sectional view showing another modification of FIG. 14. FIG. 28 is an enlarged plan view showing another modification of FIG. 15.

[0137] The lead frame LF2 shown in Figures 27 and 28 differs from the lead frame LF shown in Figures 10 and 11 in that the thin portion LFhf shown in Figures 10 and 11 (in other words, the step portion ST shown in Figure 10) is not formed in the lead frame preparation process shown in Figure 7.

[0138] In addition, in the case of this variant example 2, in the laser irradiation process shown in Figures 27 and 28, laser light LZ (see Figure 27) is irradiated onto the lower surface LDb of the lead LD to remove the metal (copper or copper alloy) of the lead frame LF2, thereby forming the portion LDe shown in Figures 3 and 5, which differs from the embodiment described using Figures 14 and 15.

[0139] In the case of the present modified example 2, in the lead frame preparation process, the process of forming the thin portion LFhf shown in FIG. 10 and FIG. 11 can be omitted.

[0140] However, in the laser irradiation process, when removing metal, the irradiation time of the laser light LZ (see FIG. 27) is longer than when removing the sealing body MR (see FIG. 28) mainly made of resin. Therefore, from the viewpoint of improving the overall manufacturing efficiency, the method described using FIGS. 14 and 15 is preferable.

[0141] The technical concept of the method for manufacturing a semiconductor device according to the second modification can be expressed as follows.

[0142] That is, the manufacturing method of the semiconductor device of this modification is as follows: (a) preparing a lead frame having a die pad with a first upper surface and a first lower surface opposite to the first upper surface, a second upper surface facing the same direction as the first upper surface, and a second lower surface opposite to the second upper surface, the lead frame having a plurality of leads spaced apart from the die pad; (b) mounting a semiconductor chip having a plurality of electrodes on the first top surface of the die pad; (c) electrically connecting the electrodes of the semiconductor chip to the leads via conductive members; (d) sealing a portion of the die pad, a portion of each of the leads, the conductive members, and the semiconductor chip with a resin made of an insulating material while a tape material is in close contact with the first lower surface of the die pad and the second lower surface of each of the leads, to form a sealed body having a third upper surface facing in the same direction as the first upper surface, and a third lower surface opposite to the third upper surface; (e) removing the tape material, and then irradiating a portion of the second lower surface of each of the plurality of leads with laser light; (f) after the step (e), forming a metal film on the second lower surface of each of the plurality of leads and on a portion of each of the plurality of leads that is exposed by the laser light; Including, After the step (e) is completed, each of the plurality of leads of the lead frame is a first portion having the second upper surface and the second lower surface; a second portion that is disposed at a position farther from the die pad than the first portion and has a thickness smaller than that of the first portion; Including, the leads of the lead frame prepared in the step (a) are arranged in a first direction; the second portion has a second upper surface and a fourth lower surface opposite the second upper surface; a distance from the second upper surface to the fourth lower surface is shorter than a distance from the second upper surface to the second lower surface; The method for manufacturing a semiconductor device, wherein in the step (e), the fourth lower surface is formed by selectively irradiating the laser light onto the portion constituting the second portion of each of the plurality of leads.

[0143] <Other Modifications> In addition to the above-mentioned modified examples, the above-mentioned technology can be applied to various modified examples. For example, in the above-mentioned embodiment and modified examples, a QFN type semiconductor device in which multiple leads are arranged on each of the four sides of the semiconductor device has been described as an example of a semiconductor device. However, the arrangement method of the multiple leads is not limited to the QFN type. For example, it can be applied to a DFN type semiconductor device in which multiple leads LD are arranged only on two sides that are opposite to each other among the four sides of the semiconductor device.

[0144] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0145] 50 Molding tool 51 Upper mold (mold) 52 Lower die (mold) 52a Support surface (mold surface, pressing surface, surface) 53 Cavity (recess) 61 Plating solution 62 Anode rod 63 Power supply BW Wire (conductive material) CP Semiconductor Chip CPb back surface (main surface, bottom surface) CPs side CPt surface (principal surface, top surface) DB Die bond material (adhesive) DB1, DB2 dicing blades (cutting blades) DP Die pad (chip mounting area, tab) DPb,LDb,LDb2,MRb Bottom surface DPs, LDs, LDs2, LDs3, MRs Side DPt,LDt,MBt,MRt Top surface LD lead (terminal, external terminal) LDc,LDe,LDm part LF, LF2 lead frame LFc, LFcX, LFcY Dicing Department LFd, LFd1, LFd2 Device Formation Section LFf Frame section (frame section, frame body) LFhf Thin section (half etching section) LFtb tie bar LFx lead connection LND, LNDa Land (Terminal) LZ laser light LZS Scanning Orbit LZT Groove MB Mounting board (motherboard, wiring board) MR sealing body (resin body) MRW part MS1, MS2 Metal burrs PD pad (electrode) PKG1 Semiconductor device SD metal film SD1 Bonding material SR1 Insulating film (solder resist film) ST Step TL Hanging Lead TP tape material (resin film)

Claims

1. (a) preparing a lead frame having a die pad having a first upper surface and a first lower surface located opposite the first upper surface, and a plurality of leads having a second upper surface facing the same direction as the first upper surface and a second lower surface located opposite the second upper surface, the leads being spaced apart from the die pad; (b) mounting a semiconductor chip having a plurality of electrodes on the first top surface of the die pad; (c) electrically connecting the electrodes of the semiconductor chip to the leads via conductive members; (d) sealing a portion of the die pad, a portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip with a resin made of an insulating material while a tape material is in close contact with the first lower surface of the die pad and the second lower surfaces of each of the plurality of leads, to form a sealed body having a third upper surface facing in the same direction as the first upper surface, and a third lower surface positioned opposite the third upper surface; (e) removing the tape material and irradiating with laser light areas of the sealing body that cover a portion of each of the plurality of leads; (f) after the step (e), forming a metal film on the second lower surface of each of the plurality of leads and on the portion of each of the plurality of leads; having Each of the plurality of leads of the lead frame prepared in the step (a) is a first portion having the second upper surface and the second lower surface; a second portion that is disposed at a position farther from the die pad than the first portion and has a thickness smaller than that of the first portion; Including, the leads of the lead frame prepared in step (a) are arranged in a first direction; the second portion includes a second upper surface and a fourth lower surface opposite the second upper surface; a distance from the second upper surface to the fourth lower surface is shorter than a distance from the second upper surface to the second lower surface; In the step (e), the laser light is selectively irradiated to the portion of the sealing body that covers the fourth lower surface of each of the plurality of leads, thereby exposing the fourth lower surface from the sealing body.

2. In claim 1, the lead frame prepared in step (a) has a first device forming section, a second device forming section disposed adjacent to the first device forming section in a second direction intersecting the first direction, and a dicing section disposed between the first device forming section and the second device forming section and extending in the first direction; The step (d) comprises: (d1) adhering one piece of the tape material to the first device formation section and the second device formation section; (d2) housing the first device forming section and the second device forming section in one cavity; (d3) supplying the resin into the cavity to collectively seal the first device forming portion and the second device forming portion; A method for manufacturing a semiconductor device comprising the steps of:

3. In claim 2, each of the first device forming section and the second device forming section includes the die pad and the plurality of leads; the dicing section includes tie bars connected to the plurality of leads of the first device forming section and the plurality of leads of the second device forming section, the tie bars extending in the first direction, (g) after the step (f), a step of separating the first device forming portion and the second device forming portion by running a dicing blade which is a rotary blade along the dicing portion, the method for manufacturing a semiconductor device further comprising the steps of:

4. In claim 1, The method for manufacturing a semiconductor device, wherein the step (a) includes the step of forming the second portion by removing a portion of each of the plurality of leads by etching.

5. In claim 1, A method for manufacturing a semiconductor device, wherein in the step (e), a plurality of grooves are formed in the fourth lower surface.

6. In claim 1, After the step (e) is completed, the fourth lower surface is rougher than the second lower surface.

7. In claim 1, After the step (e) is completed, a portion of the fourth lower surface is covered by the encapsulant.

8. In claim 1, an irradiation area of ​​the laser light irradiated in the step (e) is smaller than a planar area of ​​the fourth lower surface.

9. In claim 1, The plurality of leads arranged in the first direction include two leads adjacent to each other, a part of the sealing body made of an insulating material is interposed between the second portion of one of the two adjacent leads and the second portion of the other of the two adjacent leads; a length from the third upper surface to the third lower surface of the part in a thickness direction of the sealing body is longer than a length from the third upper surface to the fourth lower surface of the sealing body.

10. a die pad having a first upper surface and a first lower surface opposite the first upper surface; a plurality of leads including a second upper surface facing the same direction as the first upper surface and a second lower surface positioned opposite the second upper surface, the leads being spaced apart from the die pad; a semiconductor chip having a plurality of electrodes and mounted on the first top surface of the die pad; a plurality of conductive members electrically connecting the plurality of electrodes and the plurality of leads of the semiconductor chip; a third upper surface facing the same direction as the first upper surface, and a third lower surface located opposite the third upper surface, the sealing body sealing a portion of the die pad, a portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip such that the first lower surface of the die pad and the second lower surfaces of each of the plurality of leads are exposed from the third lower surface; Including, Each of the plurality of leads includes: a first portion having the second upper surface and the second lower surface; a second portion that is disposed at a position farther from the die pad than the first portion and has a thickness smaller than that of the first portion; Including, The plurality of leads are arranged in a first direction, the second portion includes a second upper surface and a fourth lower surface opposite the second upper surface; a distance from the second upper surface to the fourth lower surface is shorter than a distance from the second upper surface to the second lower surface; The plurality of leads arranged in the first direction include two leads adjacent to each other, a part of the sealing body made of an insulating material is interposed between the second portion of one of the two adjacent leads and the second portion of the other of the two adjacent leads; a length from the third upper surface to the third lower surface of the part in a thickness direction of the sealing body is longer than a length from the third upper surface to the fourth lower surface of the sealing body.

11. In claim 10, The semiconductor device, wherein a plurality of grooves are formed in the fourth lower surface.

12. In claim 10, The fourth lower surface is rougher than the second lower surface.

13. In claim 10, A semiconductor device, wherein a portion of the fourth lower surface is covered by the sealing body.

14. In claim 10, Each of the plurality of leads has a plurality of lead sides; the encapsulant has encapsulant side surfaces that intersect with each of the third upper surface and the third lower surface, A semiconductor device, wherein a first lead side surface, which is located farthest from the die pad, and the sealing body side surface among the multiple lead side surfaces are arranged in the same plane.

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