Temporarily fixed substrate

Abstract

To suppress chipping in an outer peripheral section of a temporarily fixed substrate.SOLUTION: On a temporarily fixed substrate, on which a predetermined fixing target is temporarily fixed on one principal surface, the arithmetic average roughness of a side end is greater than the arithmetic average roughness of the one principal surface and is 5 μm or less.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a temporary fixing substrate used in a manufacturing process of a semiconductor package. [Background technology]

[0002] FOWLP (Fan-out Wafer Level Package) technology is known as a semiconductor package manufacturing technology. FOWLP technology is a process of obtaining a semiconductor package with a lower height than conventional ones by performing a process of resin molding on a temporary fixing substrate on which a semiconductor chip is temporarily fixed with an adhesive, a process of grinding the resin mold to expose the electrode ends of the semiconductor chip, a process of forming a thin-film rewiring layer (multilayer wiring) and solder balls on the surface where the electrode ends are exposed, and a process of singulating each package and peeling it off from the temporary fixing substrate.

[0003] An embodiment using a translucent ceramic substrate as a temporary fixing substrate for chips in such FOWLP technology is already known (see, for example, Patent Documents 1 and 2). The translucent ceramic substrate satisfies all of the requirements required for a temporary fixing substrate, namely, high flatness required for exposing electrode ends, high rigidity and reverse warpage required for suppressing warpage during multilayer wiring formation, translucency that allows the transmission of laser light for hardening the adhesive, and chemical resistance for cleaning and reuse after use. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6430081 [Patent Document 2] Patent No. 6420023 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional temporary fixing substrates have a problem in that chipping (defects) occurs in the peripheral portion, resulting in a decrease in yield.

[0006] Furthermore, the conventional temporary fixing substrate has a problem in that peeling defects occur in which the resin portion peels off from the outer periphery, resulting in a decrease in yield.

[0007] The present invention has been made in view of the above problems, and has an object to suppress the occurrence of chipping at the outer periphery of a temporary fixing substrate.

[0008] A second object of the present invention is to provide a temporary fixing substrate that can suppress peeling defects and obtain semiconductor packages with a higher yield than ever before. [Means for solving the problem]

[0009] In order to solve the above problems, a first aspect of the present invention is a temporary fixing substrate having one main surface on which a predetermined fixing object is temporarily fixed, characterized in that the arithmetic mean roughness of a side end portion is larger than the arithmetic mean roughness of the one main surface and is 5 μm or less.

[0010] A second aspect of the present invention is a temporary fixing substrate according to the first aspect, characterized in that it has chamfered areas at the ends over the entire outer periphery of each of the one main surface and the other main surface, and the arithmetic mean roughness of the chamfered area at least on the one main surface side is 0.1 μm to 10 μm and is larger than the arithmetic mean roughness of the one main surface.

[0011] A third aspect of the present invention is a temporary fixing substrate according to the second aspect, characterized in that the chamfered region has a first chamfered portion and a second chamfered portion having different inclination angles with respect to the one main surface.

[0012] A fourth aspect of the present invention is the temporary fixing substrate according to the second or third aspect, characterized in that the one principal surface and the other principal surface have an arithmetic mean roughness of 100 nm or less.

[0013] A fifth aspect of the present invention is the temporary fixing substrate according to any one of the first to third aspects, characterized in that the arithmetic mean roughness of the side edge portion is 2 μm or less.

[0014] A sixth aspect of the present invention is a temporary fixing substrate according to any one of the first to third aspects, characterized in that the predetermined fixing objects are a plurality of electronic components or semiconductor substrates. Effect of the Invention

[0015] According to the first to sixth aspects of the present invention, it is possible to suitably suppress the occurrence of chipping at the side edge of the temporary fixing substrate during the process of temporarily fixing an object to be fixed, such as an electronic component, to the temporary fixing substrate.

[0016] In particular, according to the second to fourth aspects, it is possible to suitably suppress the occurrence of peeling between the temporary fixing substrate and the object to be fixed, the adhesive layer or the adhesive layer, other resins, or the like. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a plan view of one main surface (front surface) 1a of a temporary fixing substrate 1 according to a first embodiment. [Diagram 2] 1 is an enlarged cross-sectional view showing the state of a chamfered region 2, in the vicinity of a side end portion 1e of a temporary fixing substrate 1. FIG. [Diagram 3] 1A to 1C are schematic cross-sectional views showing stages during a process of manufacturing a semiconductor package by FOWLP technology using a temporary fixing substrate 1. [Figure 4] FIG. 2 is a flow diagram illustrating a manufacturing process of the temporary fixing substrate 1. [Diagram 5] 1 is a diagram showing a schematic view of a state in which a temporary fixing substrate 1 is chamfered using a chamfering device 100. FIG. [Figure 6] 6 is an enlarged schematic diagram of a portion A in FIG. 5, showing how chamfering is performed. [Figure 7] 1 is a schematic cross-sectional view showing a main part of a lapping polishing apparatus 200 for lapping a temporarily fixed substrate 1. FIG. [Figure 8]2 is a perspective view of a main part of the lapping polishing apparatus 200 with the upper platen 202 omitted. [Figure 9] 10 is a diagram showing a schematic view of a state in which a side end 1e of a temporary fixing substrate 1 where a chamfered region 2 is not formed is polished in a lapping and polishing apparatus 200. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] <First embodiment> <Temporary fixing board> 1 is a plan view of one main surface (front surface) 1a of a temporary fixing substrate 1 according to a first embodiment of the present invention. The temporary fixing substrate 1 is a substrate to which a semiconductor chip is temporarily fixed when a semiconductor package is manufactured by a fan-out wafer level package (FOWLP) technique.

[0019] The temporary fixing substrate 1 is a translucent ceramic substrate having a diameter of several hundred mm (e.g., 300 mm), a thickness of several hundred μm to several mm (e.g., 1 mm), an in-plane thickness difference of several μm or less (e.g., 3 μm or less), and a warpage of several hundred μm or less (e.g., 200 μm). In the present embodiment, the translucent ceramic is a ceramic having a forward total light transmittance of 20% or more in the entire wavelength range of 200 nm to 1500 nm. Examples of such translucent ceramic include alumina, silicon nitride, aluminum nitride, and silicon oxide. For example, a suitable example of the temporary fixing substrate 1 is one having alumina as the main component and a forward total light transmittance of 70% or more at a wavelength of 1500 nm. When alumina is used as the main component, it is preferable to use a high purity alumina powder of 99.9% or more (preferably 99.95% or more) as a raw material, and magnesium oxide or zirconia (ZrO 2 ) and yttria (Y 2 O 3 ) is preferably added.

[0020] The surface 1a, which is the placement surface of the semiconductor chip, and the other main surface (back surface) 1b are both flat polished surfaces with a small surface roughness by being polished in advance. More specifically, in the surface 1a and the back surface 1b, a thickness difference within the plane of several μm described above and an arithmetic mean roughness Ra of 100 nm or less (preferably 20 nm or less) are realized. More specifically, both the surface 1a and the back surface 1b are surfaces subjected to lapping and polishing. Note that there is no particular limitation on the lower limit value of the arithmetic mean roughness Ra of the surface 1a and the back surface 1b, but 1 nm is sufficient for practical use.

[0021] However, the temporary fixing substrate 1 according to the present embodiment includes a chamfered region 2 at the end over the entire outer periphery of the surface 1a. Although not shown in the figure, the chamfered region 2 is similarly provided on the back surface 1b. Therefore, strictly speaking, the arithmetic mean roughness Ra of the surface 1a and the back surface 1b of 100 nm or less described above is realized in the region excluding the chamfered region 2. Hereinafter, the surface 1a and the back surface 1b excluding the chamfered region 2 are also referred to as the flat surface 1a and the flat back surface 1b, respectively.

[0022] FIG. 2 is an enlarged cross-sectional view near the side end portion 1e of the temporary fixing substrate 1 showing the state of the chamfered region 2.

[0023] In the case shown in FIG. 2, an example is illustrated in which the chamfered region 2 has a two-stage configuration including a first chamfered portion 2a inclined at an inclination angle θ1 with respect to the flat surface 1a and a second chamfered portion 2b inclined at an inclination angle θ2 (>θ1) with respect to the flat surface 1a. The second chamfered portion 2b is provided in a range of a predetermined width b (<a) from the side end portion 1e. Similarly, on the flat back surface 1b side, a chamfered region 2 having a two-stage configuration of the first chamfered portion 2a and the second chamfered portion 2b is provided. Note that the second chamfered portion 2b may be omitted, and the chamfered region 2 may have a one-stage configuration including only the first chamfered portion 2a.

[0024] The inclination angle θ1 is preferably 5° to 55° (for example, 30°). When the chamfered region 2 has a two-stage structure, the inclination angle θ2 is preferably 35° to 85° (for example, 60°), where θ1<θ2.

[0025] By providing the chamfered region 2 satisfying the above-mentioned range of inclination angles, the occurrence of chipping is suitably suppressed in the temporary fixing substrate 1. That is, in the case of the temporary fixing substrate 1 without the chamfered region 2, chipping is likely to occur in the corners where the front surface 1a and the back surface 1b and the side end 1e are perpendicular to each other, but in the case of the temporary fixing substrate 1 according to the present embodiment, since it is provided with the chamfered region 2, it does not have such perpendicular corners, and the angles between the chamfered region 2 and the front surface 1a and the back surface 1b and the angle between the chamfered region 2 and the side end 1e are all obtuse angles, so that chipping is extremely unlikely to occur.

[0026] That is, the provision of the chamfered region 2 has the effect of suppressing the occurrence of defects due to the occurrence of chipping and increasing the manufacturing yield of the temporary fixing substrate 1. In particular, forming the chamfered region 2 into a two-stage configuration of the first chamfered portion 2a and the second chamfered portion 2b is more effective in suppressing such chipping because such an obtuse angle is provided in two stages.

[0027] <Semiconductor package manufacturing process and the effect of roughening the chamfered edge> Among the chamfered regions 2 provided on the temporary fixing substrate 1 in the above-mentioned manner, at least the chamfered region 2 provided on the front surface (one main surface) 1a side is made into a rough surface having a surface roughness larger than that of the flat surface 1a. Specifically, the arithmetic mean roughness Ra of the chamfered region 2 is 0.1 μm to 10 μm. This is intended to ensure the manufacturing yield of the semiconductor package. This point will be described below.

[0028] 3 is a schematic cross-sectional view showing a step-by-step process of manufacturing a semiconductor package by the FOWLP technique using the temporary fixing substrate 1. However, in FIG. 3, for the sake of simplicity, the chamfered region 2 is shown by diagonal lines only on the front surface 1a side.

[0029] 3(a), in the process of manufacturing a semiconductor package, a layer (adhesive layer) 3α made of an adhesive is formed on a temporary fixing substrate 1. Examples of the adhesive include double-sided tape and hot melt adhesives, and the adhesive can be formed by various known methods such as roll coating, spray coating, screen printing, and spin coating.

[0030] Next, as shown in FIG. 3(b), a plurality (a large number) of semiconductor chips 4 are placed on the adhesive layer 3α. The semiconductor chips 4 are placed in an area inside the chamfered area 2. The adhesive layer 3α is then cured to form the adhesive layer 3. The curing method is selected from heating, ultraviolet irradiation, and the like, depending on the material of the adhesive used in the adhesive layer 3α. As a result, the semiconductor chips 4 are adhesively fixed to the temporary fixing substrate 1.

[0031] When the semiconductor chip 4 is fixed to the temporary fixing substrate 1 in this manner, a molding resin is poured onto the entire upper surface of the temporary fixing substrate 1, that is, into the gaps 5 between the semiconductor chips 4 and the entire upper surface of the semiconductor chip 4. The molding resin is cured to form a resin mold 6, as shown in Fig. 3(c). Examples of the molding resin include epoxy resin, polyimide resin, polyurethane resin, and urethane resin.

[0032] Thereafter, the resin mold 6 is ground until the electrode ends of the semiconductor chip 4 are exposed, and then a rewiring layer and solder balls are formed on the ground surface. Finally, the substrate is divided into individual packages, and the temporary fixing substrate 1 is separated by laser lift-off.

[0033] The chamfered region 2 provided on the outer periphery of the temporary fixing substrate 1 has the effect of suppressing the occurrence of defects (peeling defects) in which the resin (adhesive layer 3 and resin mold 6) peels off from the temporary fixing substrate 1 (peeling suppression effect) during the semiconductor package manufacturing process described above, until the time when individualization and laser lift-off are performed.

[0034] In the case of conventional temporary fixing substrates, during the manufacturing process of the above-mentioned semiconductor package, air can get in between the temporary fixing substrate and the resin from the outside near the outer periphery of the temporary fixing substrate, forming air bubbles, which can cause peeling between the temporary fixing substrate and the resin.

[0035] However, when the temporary fixing substrate 1 according to the present embodiment is used, the adhesive and further the mold resin enter the chamfered region 2, which is provided on the outer periphery of the front surface 1a and has a surface roughness sufficiently larger than that of the front surface 1a, and an anchor effect is generated between the resin and the chamfered region 2. This anchor effect suppresses the formation of bubbles on the outer periphery of the temporary fixing substrate 1 and the peeling of the resin. The presence or absence of bubbles can be confirmed by observing the temporary fixing substrate 1 from the back surface 1b side with the naked eye or with a stereomicroscope. In this embodiment, the resin is deemed to have peeled off not only when the temporary fixing substrate 1 is visually observed from the side end 1e side and a portion where the resin and the temporary fixing substrate 1 are separated is confirmed, but also when bubbles having a size of 3 mm or more in the longitudinal or lateral direction are confirmed as a result of observing the temporary fixing substrate 1 from the back surface 1b side with the naked eye or with a stereomicroscope.

[0036] When the temporary fixing substrate 1 is provided with a chamfered region 2 having an arithmetic mean roughness Ra of 0.1 μm to 10 μm, the occurrence rate of peeling failure (peeling failure rate) counted per substrate is suppressed to 3% or less. Preferably, the arithmetic mean roughness Ra of the chamfered region 2 is 0.5 μm to 2 μm.

[0037] From the viewpoint of preventing peeling, the width a of the chamfered region 2 may be up to 1% of the radius r of the temporary fixing substrate 1 at most, and the chamfered region 2 does not need to extend further inward beyond this. For example, in the case of a temporary fixing substrate 1 having a diameter of 300 mm (r=150 mm), a width a of about 0.2 mm to 0.5 mm is preferable. The width b of the second chamfered portion 2b is preferably about 0.01 mm to 0.11 mm. The presence of the chamfered region 2 does not impede laser lift-off.

[0038] <Manufacturing process of temporary fixing substrate> Next, a description will be given of a manufacturing process of the temporary fixing substrate 1 having the chamfered region 2. Fig. 4 is a flow diagram that outlines the manufacturing process of the temporary fixing substrate 1. The temporary fixing substrate 1 is generally manufactured through a molded body preparation step (step S1), a firing step (step S2), a chamfering step (step S3), and a polishing step (step S4).

[0039] In manufacturing the temporary fixing substrate 1, first, a molded body mainly composed of a light-transmitting ceramic powder is prepared (step S1). For example, the above-mentioned alumina or other light-transmitting ceramic raw material powder, ceramic powder such as magnesium oxide or sintering aid, and organic materials such as binder and solvent are kneaded in a ball mill or the like to produce a slurry, and the slurry is molded into a tape. The obtained tape is sheared (cut) to obtain rectangular sheets of a predetermined size, which are laminated and pressed, and the pressed laminate is punched into a circle. This produces a disk-shaped molded body. Alternatively, the molded body may be obtained by a doctor blade method, an extrusion method, a gel cast method, or the like.

[0040] Next, the formed compact is fired (step S2), whereby the organic components are eliminated and a ceramic sintered body (temporarily fixed substrate 1 before chamfering and polishing) is obtained.

[0041] The firing is preferably performed by first calcining in an air furnace and then firing in a hydrogen furnace. The sintering temperature in the firing is preferably 1700°C to 1900°C, more preferably 1750°C to 1850°C, from the viewpoint of densifying the sintered body.

[0042] After the firing, the sintered body may be annealed in a hydrogen furnace to adjust (correct) the warpage. From the viewpoint of preventing deformation and abnormal grain growth while accelerating the discharge of the sintering aid, the annealing is preferably performed at a temperature within ±100°C of the maximum temperature during firing, and more preferably at 1900°C or less. The annealing time is preferably 1 to 6 hours.

[0043] When the sintered body (the temporary fixing substrate 1 before chamfering and polishing) is obtained, the entire outer periphery of the front and back surfaces (both main surfaces) of the sintered body is then chamfered (step S3). In the following description, for convenience, the temporary fixing substrate 1 before chamfering and the temporary fixing substrate 1 before polishing will also be simply referred to as the temporary fixing substrate 1.

[0044] Fig. 5 is a diagram showing a schematic diagram of chamfering of the temporary fixed substrate 1 using a chamfering device (beveling machine) 100. The chamfering device 100 includes a table 101, a table rotating mechanism 102, a grindstone holding and moving mechanism 103, and a grindstone 104. Fig. 6 is an enlarged schematic diagram of a portion A in Fig. 5, showing a state in which the chamfering is performed.

[0045] The table 101 is configured so that the temporary fixing substrate 1 to be chamfered can be placed horizontally on its upper surface, and by operating the table rotation mechanism 102, the table 101 and the temporarily fixing substrate 1 placed thereon can be rotated in a horizontal plane.

[0046] The grindstone holding and moving mechanism 103 is capable of holding a disk-shaped grindstone 104 in a horizontal position at its lower end, and is capable of rotating and moving back and forth within a horizontal plane while holding the grindstone 104.

[0047] The grindstone 104 is disk-shaped, and its outer circumferential edge portion forms a blade portion 104a having an isosceles triangular shape in cross section, as shown in Fig. 6. The grit size of the grindstone 104 (blade portion 104a) is selected so that the arithmetic mean roughness Ra of the finally formed chamfered region 2 falls within the above-mentioned range of 0.1 µm to 10 µm.

[0048] When chamfering, first, the temporarily fixed substrate 1 is placed on the upper surface of the table 101. Meanwhile, a grindstone 104 is attached to the grindstone holding and moving mechanism 103. At that time, the temporarily fixed substrate 1 and the grindstone 104 are aligned so that their respective central heights in the thickness direction (positions in the vertical direction) match.

[0049] Then, while the table 101 on which the temporary fixing substrate 1 is placed is rotated horizontally by the table rotation mechanism 102 as shown by the arrows AR1 (AR1a, AR1b), the grindstone holding and moving mechanism 103 rotates the grindstone 104 horizontally in the opposite direction to the table 101 as shown by the arrows AR2 (AR2a, AR2b), while moving it in a translational manner toward the side end 1e of the temporary fixing substrate 1 as shown by the arrows AR3 (AR3a, AR3b).

[0050] With this rotation and translational movement, the blade 104a of the grindstone 104 approaches the side end 1e of the temporary fixing substrate 1 and eventually comes into contact with the upper and lower edge portions 1ea, 1eb of the side end 1e of the temporary fixing substrate 1. As the rotation and translational movement of the grindstone 104 continues even after this contact, the side end 1e of the temporary fixing substrate 1 is gradually cut away from the edge portions 1ea, 1eb, and finally a chamfered region 2 is formed.

[0051] When the chamfering region 2 has a two-stage configuration, two types of grindstones 104 having blade portions 104a with different angles are used in sequence. Alternatively, one grindstone 104 may be provided with a plurality of blade portions 104a with different angles, and the two-stage chamfering region 2 may be formed by using these blade portions in sequence.

[0052] Since the semiconductor chip 4 is not usually mounted on the back surface 1b of the temporary fixing substrate 1 by the above process, the chamfered area 2 formed on the back surface 1b is not necessarily roughened from the viewpoint of suppressing peeling of the resin, but there is no particular inconvenience in roughening the chamfered area 2 on the back surface 1b together with the front surface 1a during chamfering in the chamfering device 100. Rather, it can be said that it is preferable in terms of symmetry of the shape of the side end portion 1e to chamfer the front surface 1a and back surface 1b in the same manner with the blade portion 104a of the same grit size.

[0053] Finally, the front and back surfaces (both main surfaces) of the chamfered temporary fixing substrate 1 are polished (step S4).

[0054] Fig. 7 is a schematic cross-sectional view showing a main part of a lapping polishing apparatus 200 that performs lapping polishing of the temporarily fixed substrate 1. The lapping polishing apparatus 200 includes a lower surface plate 201, an upper surface plate 202, and a plurality of carriers 203. Fig. 8 is a perspective view of the main part of the lapping polishing apparatus 200 with the upper surface plate 202 omitted.

[0055] The lower surface plate 201 and the upper surface plate 202 are rotatable in a horizontal plane coaxially and in opposite directions as shown by arrows AR4 and AR5. Examples of the material of the lower surface plate 201 and the upper surface plate 202 include copper, resin copper, and tin. Alternatively, a polishing pad may be attached to a metal surface plate. In such a case, examples of the polishing pad include a hard urethane pad, a nonwoven fabric pad, and a suede pad.

[0056] Each carrier 203 has a circular through hole 203h into which the temporary fixed substrate 1 to be polished is fitted, and is capable of rotating about its axis between an annular guide 204 and a central axis 205 as the lower surface plate 201 and the upper surface plate 202 rotate.

[0057] In the lapping apparatus 200, a plurality of carriers 203, each of which has a temporarily fixed substrate 1 to be polished fitted therein, are sandwiched between a lower platen 201 and an upper platen 202, and while a slurry SL is dropped between the lower platen 201 and the upper platen 202, the lower platen 201 and the upper platen 202 are rotated in opposite directions as indicated by arrows AR4 and AR5. As a result, both main surfaces of the temporarily fixed substrate 1 are polished simultaneously, and a flat front surface 1a and a flat back surface 1b with an arithmetic mean roughness Ra of 100 nm or less (preferably 20 nm or less) can be obtained. Examples of the slurry SL include water-based or oil-based diamond slurry.

[0058] Although the chamfered region 2 is also polished to some extent by the lapping, the surface roughness of the chamfered region 2, which has been roughened in advance, remains almost the same as before polishing.

[0059] Through the above steps, the temporary fixing substrate 1 according to the present embodiment having the chamfered region 2 is obtained.

[0060] As described above, according to this embodiment, by providing chamfered regions on the entire outer periphery of both main surfaces of the temporary fixing substrate used for temporarily fixing a semiconductor chip in the manufacturing process of a semiconductor package by the FOWLP technique, it is possible to suitably suppress the occurrence of chipping at the corners of the temporary fixing substrate. In addition, by making the chamfered regions on the outer periphery of the main surface to which the semiconductor chip is temporarily fixed a rough surface having a larger surface roughness than the main surface, it is possible to suitably suppress peeling between the temporary fixing substrate and the resin during the above process.

[0061] <Second embodiment> In the first embodiment described above, the chamfering area 2 is formed into a rough surface in the chamfering device 100, and then both main surfaces of the temporary fixing substrate 1 are lapped and polished by the lapping device 200, thereby forming a flat surface 1a to which the semiconductor chip 4 is temporarily fixed.

[0062] In the process of performing lapping using the lapping apparatus 200, the side end 1e is also polished to some extent due to the nature of the method. That is, the surface roughness of the side end 1e is reduced by lapping. Therefore, in addition to the flat front surface 1a and the flat back surface 1b, the surface roughness (arithmetic mean roughness Ra) of the side end 1e is also smaller than the surface roughness (arithmetic mean roughness Ra) of the chamfered region 2. Reducing the surface roughness of the side end 1e by performing lapping in this manner has the effect of suppressing the occurrence of chipping within the surface of the side end 1e. Moreover, this effect can be obtained not only in the temporary fixing substrate 1 in which the chamfered region 2 is formed, but also in the temporary fixing substrate 1 in which the chamfering process is omitted.

[0063] FIG. 9 is a diagram showing a schematic view of a state in which a side end portion 1e of a temporary fixing substrate 1 where no chamfered region 2 is formed is polished in a lapping and polishing apparatus 200. As shown in FIG.

[0064] As described above, in the lapping polishing apparatus, the slurry SL is dropped between the lower platen 201 and the upper platen 202 which sandwich the carrier 203 and the temporary fixing substrate 1, and the slurry SL also enters between the side end 1e of the temporary fixing substrate 1 and the carrier 203 as shown in Fig. 9. The side end 1e of the temporary fixing substrate 1 is polished by the slurry SL which has entered. This also applies to the case where the temporary fixing substrate 1 is provided with the chamfered region 2.

[0065] When the arithmetic mean roughness Ra of the side end 1e is 5 μm or less, the chipping occurrence rate (chipping defect rate) counted per substrate is suppressed to less than 3.0%. When the arithmetic mean roughness Ra of the side end 1e is 2 μm or less, the chipping defect rate is suppressed to 1.0% or less.

[0066] Furthermore, in the case of the temporary fixing substrate 1 having the chamfered region 2 as in the first embodiment, if the arithmetic mean roughness Ra of the side end portion 1e is 2 μm or less, the chipping defect rate is suppressed to 0.5% or less.

[0067] There is no particular limit to the lower limit of the arithmetic mean roughness Ra of the side end 1e, but in practice, 0.01 μm or more is sufficient. However, since lapping is performed mainly on the main surface of the temporary fixing substrate 1, the polishing of the side end 1e proceeds more slowly than that of the main surface. Therefore, the arithmetic mean roughness Ra of the side end 1e is usually greater than the arithmetic mean roughness Ra of the flat front surface 1a and the flat back surface 1b.

[0068] As described above, according to this embodiment, by setting the arithmetic mean roughness Ra of the side edge of the temporary fixing substrate used for temporarily fixing a semiconductor chip in the semiconductor package manufacturing process by the FOWLP technology to 5 μm or less, it is possible to suitably suppress the occurrence of chipping at the side edge.

[0069] (Modification) In the above-described embodiment, the temporary fixing substrate having a chamfered region is used as a substrate to which a plurality of semiconductor chips are temporarily fixed when a semiconductor package is manufactured by the FOWLP technique, but the use of the temporary fixing substrate is not limited thereto, and the temporary fixing substrate may be used for temporarily fixing electronic components other than semiconductor chips. That is, the temporary fixing substrate according to the above-described embodiment may be used for the purpose of suppressing peeling between the resin and the temporary fixing substrate when a resin mold is formed after a plurality of electronic components are bonded to the temporary fixing substrate with an adhesive.

[0070] Alternatively, various semiconductor substrates may be temporarily fixed to a temporary fixing substrate having a chamfered region with an adhesive, and the temporarily fixed semiconductor substrates may be subjected to a desired process, and then the temporary fixing substrate may be peeled off in the same manner as in the above-described embodiment. Examples of the semiconductor substrate include silicon substrates, compound semiconductor substrates, and further epitaxial substrates using these as base substrates, as well as other composite substrates, multilayer substrates, and multilayer substrates. In such cases, the same effects as those in the above-described embodiment can be obtained. EXAMPLES

[0071] (Confirming the effect of roughening the chamfered area) Five types of temporary fixing substrates 1 (conditions 1 to 5) were produced in quantities of 200 each, each having a different combination of the arithmetic mean roughness Ra of the flat surface 1a and the chamfered region 2. The chamfered region 2 had a two-stage configuration, with inclination angles θ1 and θ2 of 30° and 60°, respectively. For each temporary fixing substrate 1, the process up to temporary fixing of the semiconductor chip 4 by the resin mold 6 was carried out in accordance with the process illustrated in FIG.

[0072] In addition, a temporary fixing substrate was prepared in the same manner as in Conditions 1, 4, and 5, except that the chamfered region 2 was not formed (Condition 6).

[0073] For all the obtained samples (laminated bodies of the temporary fixing substrate 1, the semiconductor chip 4, and the resin), the presence or absence of peeling between the temporary fixing substrate 1 and the resin was visually confirmed, and the peeling failure rate for each example was calculated. Specifically, the temporary fixing substrate 1 was visually inspected from the side end 1e side and the back surface 1b side, and it was determined that peeling had occurred if separation between the resin mold 6 and the temporary fixing substrate 1 was confirmed at the side end 1e, or if air bubbles with a minimum size of 3 mm or more were present in at least one of the radial and circumferential directions of the temporary fixing substrate 1 when observed from the back surface 1b side.

[0074] Table 1 shows a list of the arithmetic mean roughness Ra of the flat surface 1a and the chamfered region 2, and the evaluation results of the peeling failure rate for each of the examples and comparative examples.

[0075] [Table 1]

[0076] Regarding the evaluation of the peeling failure rate, it was determined that the resin peeling was well suppressed for the temporary fixing substrate 1 produced under conditions where the peeling failure rate was 3% or less. Specifically, this applies to conditions 1 to 5. In Table 1, these conditions 1 to 5 are marked with a "〇" (circle) in the "Peeling Failure Rate" column.

[0077] On the other hand, it was determined that the resin peeling was not sufficiently suppressed for the temporary fixing substrate 1 produced under conditions where the peeling failure rate exceeded 3%. Specifically, only condition 6 fell into this category. Specifically, the peeling failure rate for condition 6 was 4.5%. In Table 1, the column for "peeling failure rate" for condition 6 is marked with an "x" (cross).

[0078] The above results show that providing a chamfered region 2 that is a sufficiently rough surface compared to the surface 1a, with an arithmetic mean roughness Ra in the range of 0.1 μm to 10 μm, is effective in suppressing peeling between the temporary fixing substrate 1 and the resin.

[0079] (Verifying the effect of polishing the side edges) While forming the chamfered region 2 in the same manner as in Condition 3, five types of temporary fixing substrates 1 (Conditions 3-1 to 3-5) were produced in 200 pieces each, each having different arithmetic mean roughnesses Ra of the side end portion 1e. The arithmetic mean roughnesses Ra were measured using a laser microscope. Furthermore, while forming the chamfered region 2 in the same manner as in Condition 4, three types of temporary fixing substrates 1 (Conditions 4-1 to 4-3) were produced in 200 pieces each, each having different arithmetic mean roughnesses Ra of the side end portion 1e. Furthermore, like in Condition 6, no chamfered region 2 was formed, and two types of temporary fixing substrates 1 (Conditions 6-1 to 6-2) were produced in 200 pieces each, each having different arithmetic mean roughnesses Ra of the side end portion 1e.

[0080] The side end 1e of each of the temporary fixing substrates 1 was observed under a stereomicroscope to check for the occurrence of chipping. When a chip having a size of 5 mm or more in the circumferential direction and a size of 1 mm or more in the radial direction of the temporary fixing substrate 1 was confirmed, it was determined that chipping had occurred.

[0081] Table 2 shows the arithmetic mean roughness Ra of the chamfered region 2 and the side edge 1e, and the evaluation results of the chipping defect rate for each example.

[0082] [Table 2]

[0083] Regarding the evaluation of the chipping defect rate, a chipping defect rate of 0.5% or less was deemed to be an extremely effective way of suppressing the occurrence of chipping. Specifically, this applies to conditions 3-1, 3-3, 4-2, and 4-3. In Table 2, these conditions are marked with a "◎" (double circle) in the "Chipping defect rate" column.

[0084] In addition, when the chipping defect rate was more than 0.5% and 1.0% or less, it was determined that the occurrence of chipping was generally well suppressed. Specifically, condition 6-2 fell into this category. In Table 2, the relevant condition is marked with a "〇" (circle) in the "Chipping defect rate" column.

[0085] Furthermore, if the chipping defect rate was greater than 1.0% and less than 3.0%, it was determined that the occurrence of chipping was suppressed to a certain degree. Specifically, this applies to conditions 3-2, 3-4, and 4-1. In Table 2, these conditions are marked with a "△" (triangle mark) in the "Chipping defect rate" column.

[0086] On the other hand, if the obtained chipping defect rate was over 3%, it was determined that chipping was not sufficiently suppressed. Specifically, this was the case for condition 3-5 and condition 6-1. In Table 2, these conditions are marked with an "X" (cross mark) in the "chipping defect rate" column. For example, the chipping defect rate for condition 6-1 was 4.0%.

[0087] The above results show that having the side end 1e with an arithmetic mean roughness Ra of 5 μm or less has a certain degree of effect in suppressing chipping at the side end 1e, specifically, the chipping occurrence rate is suppressed to less than 3%. Also, when the arithmetic mean roughness Ra of the side end 1e is 2 μm or less, the chipping occurrence rate is suppressed to 1% or less, and in addition, when the temporary fixing substrate 1 further includes the chamfered region 2, the chipping occurrence rate is suppressed to 0.5% or less. [Explanation of symbols]

[0088] 1 Temporary fixing board 1a (One main surface (front surface) of the temporary fixing substrate) 1b (the other main surface (back surface) of the temporary fixing substrate) 1e Side end (of temporary fixing board) 2 Chamfer area 3 Adhesive layer 4. Semiconductor chips 5 Gap 6 Resin mold SL Slurry 100 Chamfering device 101 Table 102 Table rotation mechanism 103 Grindstone holding and moving mechanism 104 Grindstone 104a (of a grindstone) 200 Lapping machine 201 Lower surface plate 202 Upper surface plate 203 Career 203h Through hole

Claims

1. A temporary fixing substrate on one main surface of which a predetermined fixing object is temporarily fixed, The arithmetic mean roughness of the side end portion is larger than the arithmetic mean roughness of the one main surface and is 5 μm or less. A temporary fixing substrate,

2. The temporary fixing substrate according to claim 1 , chamfered areas are provided at the ends of the one main surface and the other main surface over the entire periphery thereof; The arithmetic mean roughness of at least the chamfered region on the one main surface side is 0.1 μm to 10 μm and is larger than the arithmetic mean roughness of the one main surface; A temporary fixing substrate,

3. The temporary fixing substrate according to claim 2, The chamfered region includes a first chamfered portion and a second chamfered portion having different inclination angles with respect to the one main surface. A temporary fixing substrate,

4. The temporary fixing substrate according to claim 2 or 3, the arithmetic average roughness of the one principal surface and the other principal surface is 100 nm or less; A temporary fixing substrate,

5. The temporary fixing substrate according to any one of claims 1 to 3, The arithmetic mean roughness of the side edge is 2 μm or less. A temporary fixing substrate,

6. The temporary fixing substrate according to any one of claims 1 to 3, The predetermined object to be fixed is a plurality of electronic components or a semiconductor substrate. A temporary fixing substrate,

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