Oxide semiconductor thin film, semiconductor device, and memory

Abstract

To provide an oxide semiconductor having unprecedented characteristics, also provide a novel semiconductor device using such a novel oxide semiconductor, and further provide a semiconductor device that realizes a one-transistor memory that allows for high integration.SOLUTION: An amorphous oxide semiconductor thin film includes Sb, In, and Zn, and further includes an element X, and 10%≤Zn+X≤70%, and 30%≤In+Sb≤90% are satisfied.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present invention relates to an oxide semiconductor thin film, a semiconductor device, and a memory. [Background technology]

[0002] In recent years, various semiconductor memories have been developed in response to increases in data capacity and improvements in processing speed. For example, oxide semiconductors can be formed into films at relatively low temperatures, making it possible to stack them three-dimensionally on top of conventional circuits made of Si semiconductors, or to create 3D oxide semiconductor circuits. In addition, IGZO has the advantage of having a wide band gap, which means that the leakage current when the transistor is off is small. Taking advantage of this advantage, a 2-transistor, 0-capacitor DRAM has been proposed (see Non-Patent Document 1).

[0003] Moreover, in recent years, in order to effectively utilize big data, it has become necessary to accumulate large amounts of data on IoT devices and perform AI processing on the terminal side, rather than relying solely on cloud servers. To achieve this, storage memory with larger capacity and extremely low power consumption is required, and ferroelectric transistor (FeFET) memory with a channel made of oxide semiconductor such as IGZO has been proposed.

[0004] Furthermore, it is said that future AI technology will require high-density three-dimensional stacking (memory) technology and devices that realize ultra-long time constants on the order of seconds or more, and there is a demand for three-dimensional, highly integrated memories with a certain degree of retention time (Non-Patent Document 2).

[0005] Here, there is an IGZO charge trap memory that is composed of only one transistor with the aim of high integration (Non-Patent Document 3). However, this charge trap memory requires the addition of Pt to the gate insulating film or an additional insulating layer.

[0006] One-transistor type memories include one-transistor type FeRAM that uses a ferroelectric material (Non-Patent Document 4). This FeRAM uses a ferroelectric material for the gate insulating film, but the ferroelectric properties of ferroelectric materials generally decrease when the film is made thinner, so there is a limit to how thin the film can be made, and there is also a problem of leakage current when the gate insulating film is made thin, so there is a limit to how much it can be miniaturized. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] Belmonte et al. - 2020 - Capacitor-less, long-retention (400s) DRAM cell paving the way towards low-power and high-density monolithic 3D.pdf [Non-Patent Document 2] Applied Physics, Vol. 88, No. 7, pp. 481-485 (2019), "Neuromorphic Systems and Physical Devices" [Non-Patent Document 3] AIP Advances 5, 127203 (2015) [Non-Patent Document 4] Jpn. J. Appl. Phys., Vol. 44, No. 25 (2005) Summary of the Invention [Problem to be solved by the invention]

[0008] As mentioned above, memories using oxide semiconductors such as IGZO, which are promising as memories that can be manufactured using low-temperature processes (below 400°C), require two transistors or one transistor and one capacitor in one memory cell, and also require the use of a ferroelectric material for the gate insulating film. In any case, there are challenges in achieving high integration.

[0009] In view of the above circumstances, an object of the present invention is to provide an oxide semiconductor having unprecedented characteristics. Another object of the present invention is to realize a novel semiconductor device using such a novel oxide semiconductor. A further object of the present invention is to provide a semiconductor device that realizes a one-transistor memory that can be highly integrated. [Means for solving the problem]

[0010] As a result of extensive research conducted to achieve the above object, it was discovered that when an Sb-containing oxide semiconductor is used as an active layer of a semiconductor device, the threshold voltage Von differs greatly between a forward (negative to positive) sweep of Vg and a reverse (positive to negative) sweep of Vg, and this has led to the completion of the present invention. The present invention is as follows.

[0011] A first aspect of the present invention is an amorphous oxide semiconductor thin film containing Sb, In, and Zn, and further containing an element X, where 10%≦Zn+X≦70%, 30%≦In+Sb≦90%. A second aspect of the present invention is the oxide semiconductor thin film of the first aspect, which is composed of an oxide semiconductor containing, as the element X, at least one element selected from the group consisting of Al, Ga, Sn, Ge, Ti, W, Hf, W, and Zr. A third aspect of the present invention is the oxide semiconductor thin film of the second aspect, wherein the oxide semiconductor contains Sb, In, Zn, and at least one of Al and Ga, and 10%≦Zn+(Al,Ga)≦70%, 30%≦In+Sb≦90%. A fourth aspect of the present invention is the oxide semiconductor thin film according to the first aspect, which has a light transmittance of 70% or more at a wavelength of 500 nm. A fifth aspect is a semiconductor device that is a transistor having an active layer made of the oxide semiconductor thin film of any one of the first to fourth aspects, the semiconductor device comprising a gate electrode provided on the active layer via a gate insulating film, and a source electrode and a drain electrode connected to the active layer. A sixth aspect is the semiconductor device according to the fifth aspect, which forms a hysteresis curve with a difference in Vg of 0.5 V or more when the gate voltage is swept back and forth. A seventh aspect of the present invention is a memory using the semiconductor device of the fifth aspect. A memory using the semiconductor device of the fifth aspect as a memory cell holds state A in which a relatively low first voltage is applied to the gate electrode to perform writing, and state B in which a relatively high second voltage is applied to the gate electrode to perform writing, and in reading by applying a voltage between the source and drain to detect a current flowing between the source and drain, the memory can distinguish whether state A has been written or state B has been written based on the magnitude of the current value. Effect of the Invention

[0012] When the oxide semiconductor of the present invention is used as an active layer in a semiconductor device, the threshold voltage Von is significantly different between the forward (negative to positive) sweep of Vg and the reverse (positive to negative) sweep of Vg, and hysteresis can be formed, making it applicable to various applications. Furthermore, a semiconductor device using the oxide semiconductor of the present invention as an active layer can realize a memory cell with one transistor, and can be easily highly integrated. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view showing an example of the structure of a semiconductor device of the present invention. [Diagram 2] 1 is a cross-sectional view showing an example of the structure of a semiconductor device of the present invention. [Diagram 3] 1 is a cross-sectional view showing an example of the structure of a semiconductor device of the present invention. [Figure 4] 1 is a cross-sectional view showing an example of the structure of a semiconductor device of the present invention. [Diagram 5] 1 is a cross-sectional view showing an example of the structure of a semiconductor device of the present invention. [Figure 6] FIG. 1 is a diagram showing an example of a hysteresis curve illustrating the memory principle of the present invention. [Figure 7] FIG. 13 is a diagram showing test results of Samples 1-5 and TFT1-5 of the present invention. [Figure 8] FIG. 13 is a diagram showing the Von characteristics of TFT6. [Figure 9] FIG. 13 is a diagram showing the Von characteristics of a TFT7. [Figure 10] FIG. 13 is a diagram showing the Von characteristics of TFT8. [Figure 11] FIG. 13 is a diagram showing the Von characteristics of TFT9. [Figure 12] FIG. 1 is a diagram showing the Von characteristics of a TFT 10. [Figure 13] FIG. 13 is a diagram showing the repeatability characteristics of TFT5. [Figure 14] FIG. 13 is a diagram showing a hysteresis curve when measuring the repeated characteristics of TFT5. [Figure 15] FIG. 13 is a diagram showing a hysteresis curve when measuring the repeated characteristics of TFT5. [Figure 16] FIG. 13 is a diagram showing a hysteresis curve when measuring the repeated characteristics of TFT5. [Figure 17] FIG. 13 is a diagram showing a hysteresis curve when measuring the repeated characteristics of TFT5. [Figure 18] FIG. 1 is a diagram showing a schematic diagram of an example of a memory array according to the present invention; [Figure 19] 1 is a diagram for explaining writing and reading of a memory array according to the present invention; [Figure 20] FIG. 13 is a diagram showing the measurement results of the retention time of a written state of a transistor according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0015] [Oxide semiconductor thin film] The oxide semiconductor thin film of the present invention is an amorphous oxide semiconductor thin film containing Sb, In, and Zn, and further contains an element X, and is composed of an oxide semiconductor thin film satisfying 10%≦Zn+X≦70%, 30%≦In+Sb≦90%.

[0016] Specifically, the element X is an oxide semiconductor containing at least one element selected from the group consisting of Al, Ga, Sn, Ge, Ti, W, Hf, W, and Zr.

[0017] Furthermore, the oxide semiconductor contains Sb, In, Zn, and at least one of Al and Ga, and preferably satisfies 10%≦Zn+(Al,Ga)≦70%, 30%≦In+Sb≦90%, and more preferably satisfies 20%≦Zn+(Al,Ga)≦50%, 50%≦In+Sb≦70%.

[0018] Such an oxide semiconductor thin film has a hole mobility of 1 cm 2 / Vs or more, and the carrier concentration is 10 14 ~10 19 cm -3 and the band gap Eg is 2.4 to 4.0. Thus, the oxide semiconductor thin film of the present invention has properties that enable it to be used as an active layer of a transistor.

[0019] When the oxide semiconductor thin film of the present invention is used as the active layer of a transistor, the transistor becomes a semiconductor device having a hysteresis in which the difference in Vg when the gate voltage is swept back and forth is 0.5 V or more. The difference in Vg when the gate voltage is swept back and forth is called the hysteresis width as described later, and the hysteresis width is 0.5 V or more, and 1 V or more is more preferable.

[0020] In a particularly preferable composition range, that is, 50≦In+Sb≦70, 30≦Zn+(Al,Ga)≦50, 15≦Zn≦30, a clear hysteresis width with a Vg difference of 2 to 12 V is observed.

[0021] Such hysteresis is not lost even after 100,000 reciprocal sweeps of the gate voltage. In addition, when the gate voltage of this semiconductor device is swept in the forward or reverse direction and then held at the read voltage, the retention time of the time memory where the ratio of the drain current state after the forward sweep to the drain current state after the reverse sweep is 100 or more is 2 seconds or more.

[0022] The method for forming the oxide semiconductor thin film of the present invention is not particularly limited. For example, the film may be formed by sputtering using a sputtering target having the same composition as the composition of the film to be formed, or by atomic layer deposition (ALD) or vacuum deposition, and the film formation method is not particularly limited as long as an amorphous oxide semiconductor thin film can be formed.

[0023] Furthermore, as described above, when the oxide semiconductor thin film of the present invention is used as an active layer of a thin film semiconductor device (also simply referred to as a semiconductor device), which is a thin film semiconductor transistor such as a TFT, the above-mentioned unique effects can be achieved.

[0024] The semiconductor device including the oxide semiconductor thin film of the present invention includes an active layer made of an amorphous oxide semiconductor thin film, a gate electrode provided on the active layer via a gate insulating film, and a source electrode and a drain electrode connected to the active layer. Typically, the thin-film semiconductor device comprises an active layer made of an amorphous oxide semiconductor thin film, a gate electrode provided on one surface of the active layer via a gate insulating film, and a source electrode and a drain electrode connected to the active layer. In addition, a vertical thin film semiconductor device may be formed by providing a source electrode and a drain electrode thereon, in which a gate all around (gate all around: GAA) type or a channel all around (channel all around: CAA) type structure is formed in which a gate is arranged around a pillar-shaped active layer, and the oxide semiconductor thin film of the present invention is used as the active layer.

[0025] As a specific example of a semiconductor device, FIG. 1 shows an example of a semiconductor device having a structure in which the gate insulating film and the gate electrode are provided on the upper surface of the active layer, and the source electrode and the drain electrode are provided on the upper surface side of the active layer.

[0026] FIG. 1 shows a schematic configuration of an example of a semiconductor device according to the present invention. The thin film transistor 110 of this embodiment comprises an active layer 11, a gate insulating film 12, a gate electrode 13, and a protective film (passivation) 14 on a substrate 10, and has a source electrode 15S and a drain electrode 15D extended from the active layer 11 via the protective film 14.

[0027] The substrate 10 is typically a Si substrate or a glass substrate. The gate electrode 13 is typically made of a metal single layer or multilayer film such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), or a general gate electrode material used in semiconductor devices such as TiN, W, or WSi, and is formed by, for example, a sputtering method. In this embodiment, the gate electrode 13 is made of molybdenum. The thickness of the gate electrode 13 is not particularly limited and is, for example, 200 nm. The gate electrode 13 is formed by, for example, a sputtering method, an ALD method, a vacuum deposition method, or the like.

[0028] The active layer 11 functions as a channel layer of the thin film transistor 110. The active layer 11 has a thickness of, for example, 5 nm to 200 nm. The active layer 11 is made of the oxide semiconductor thin film of the present invention described above. The active layer 11 is formed by, for example, a sputtering method, an ALD method, a vacuum deposition method, or the like.

[0029] The gate insulating film 12 is formed between the gate electrode 13 and the active layer 11. The gate insulating film 12 is made of, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a laminated film of these. The film formation method is not particularly limited, and may be a CVD method, a sputtering method, a vapor deposition method, or the like. The thickness of the gate insulating film 12 is not particularly limited, and is, for example, 200 nm to 400 nm.

[0030] The source electrode 15S and the drain electrode 15D are drawn out from the active layer 11 and formed on the protective film 14 at a distance from each other. The source electrode 15S and the drain electrode 15D can be composed of a single metal layer film of aluminum, molybdenum, copper, titanium, or the like, or a multilayer film of these metals. As described later, the source electrode 15S and the drain electrode 15D can be simultaneously formed by patterning a metal film. The thickness of the metal film is, for example, 100 nm to 200 nm. The source electrode 15S and the drain electrode 15D are formed by, for example, a sputtering method, a vacuum deposition method, or the like.

[0031] At least one of the upper and lower surfaces of the active layer 11 of the thin film transistor 110 may be provided with a semiconductor thin film having a lower carrier density than the active layer 11 .

[0032] An example of such a thin film transistor is shown in FIG. A thin film transistor 110A in FIG. 2 has semiconductor thin films 11A and 11B, each having a low carrier density, on both the upper and lower surfaces of an active layer 11. The semiconductor thin films 11A and 11B may be, for example, InGaAl oxide (IGA) films having a high carrier concentration. Similarly to the active layer 11, the semiconductor thin films 11A and 11B are formed by, for example, a sputtering method, an ALD method, a vacuum deposition method, or the like.

[0033] The thin film transistor of the present invention is not limited to such a structure, and may have a structure as shown in FIGS.

[0034] The thin-film transistor 110B in FIG. 3 has a structure in which a gate electrode 13 is provided on the lower surface of an active layer 11, and has a structure in which the gate electrode 13, a gate insulating film 12, and an active layer 11 are laminated on a substrate 10, and a source electrode 15S and a drain electrode 15D are extended from above the gate insulating film 12 and the active layer 11.

[0035] The thin-film transistor 110C in FIG. 4 has a structure in which an etching stop layer 16 is provided on the gate insulating film 12 and the active layer 11 of the thin-film transistor 110B in FIG.

[0036] The thin-film transistor 110D in FIG. 5 is a dual-gate type TFT, and has a bottom gate electrode 13A on the lower surface side of the active layer 11 via a gate insulating layer 12A, and a top gate electrode 13B on the upper surface side via a gate insulating layer 12B. The source electrode 15S and the drain electrode 15D are led out via an n-layer 11A provided continuously with the active layer 11, i.e., an N-type layer with a low concentration of N-type impurities.

[0037] Although the specific examples described above are lateral transistors, the present invention is not limited to these, and it goes without saying that the above-mentioned vertical transistors may also be used.

[0038] As described above, the transistor having the oxide semiconductor thin film of the present invention as an active layer is a semiconductor device having a hysteresis of 0.5 V or more in difference in Vg when the gate voltage is swept back and forth. Therefore, when writing is performed by applying a predetermined voltage to the gate electrode of such a transistor and then detecting the drain current to read, the magnitude of the read current that can be detected by reading can be changed in two stages by changing the write voltage applied to the gate electrode in two stages. In other words, by changing the write voltage for one transistor, two types of writing can be performed and the data can be read out in a distinguishable manner, so that one transistor can constitute one element of a memory.

[0039] If the first write voltage is -12 to -1V, e.g., -5V, the second write voltage is 1 to 12V, e.g., +10V, and the read voltage is 0.1 to 5V, e.g., 1.5V, the magnitude of the current when writing and reading with the first write voltage differs from the magnitude of the current when writing and reading with the second write voltage. Therefore, it is possible to distinguish whether the data was written with the first write voltage or the second write voltage from the read current value, and one memory element can be configured with one transistor.

[0040] FIG. 6 shows an example of a hysteresis curve of a transistor of the present invention. Here, when writing is performed with a first write voltage, for example, Vg=-5V→0V, it is written as hysteresis state A. On the other hand, when writing is performed with a second write voltage, for example, +10V→0V, it is written as state B.

[0041] During reading, when a voltage of, for example, 5 V is applied between the source and drain while a voltage of, for example, +1.5 V is applied to the gate electrode, a current flowing between the source and drain is detected.

[0042] At this time, when state A is written, the current value is relatively high, and when state B is written, the current value is relatively low. In other words, by detecting the magnitude of the current value, it is possible to detect whether it is in state A or state B, which can be expressed as the "1" and "0" states of the memory.

[0043] Until now, for example, it was necessary to construct one memory cell from one transistor and one capacitor, and the written state had to be held in a charged state in the capacitor connected to the transistor. However, with the transistor of the present invention, by utilizing hysteresis as described above, it is possible to hold and distinguish between the state written with the first write voltage and the state written with the second write voltage without a capacitor, and to read them out. Therefore, it is possible to construct one memory cell from only one transistor.

[0044] The hysteresis curve of the transistor of the present invention is not lost even after 100,000 reciprocating sweeps of the gate voltage, and therefore has sufficient specifications for use as a memory cell.

[0045] In addition, when the gate voltage of this semiconductor device is swept in the forward or reverse direction and then held at the read voltage, the time during which the ratio of the drain current state after the forward sweep to the state after the reverse sweep is 100 or more is 2 seconds or more, which can be considered as the memory retention time, and from this point of view it is clear that it can be used as a memory. EXAMPLES

[0046] (Sample 1-5) Using one or more sputtering targets, an oxide semiconductor thin film of Sample 1-5 having the composition shown in Table 1 was formed on a glass substrate to a thickness of 50 nm. The band gap Eg (eV) and crystallinity of the oxide semiconductor thin films of Samples 1-5 were measured as follows. The results are shown in Table 1.

[0047] (Band gap measurement) The band gap was measured as follows. 1. Measure the transmittance T and reflectance R using a spectroscope. 2. Calculate the absorption coefficient α using the following formula: α=((-ln(T / (1-R)) / n) / (T / (1-R))) n: Film thickness [cm] T, R: Measurement data / 100 3. Calculate (α×hω)^(1 / 2). hω(photon energy) [eV]: 1239.8 / wavelength [nm] 4.From a graph with the horizontal axis being hω [eV] and the vertical axis being (α×hω)^(1 / 2), the band gap is the point where the tangent with the maximum slope intersects with the x-axis. Table 1 shows the band gap Eg obtained by the above measurement.

[0048] (transmittance) Table 1 shows the transmittance for light with a wavelength of 500 nm obtained by measuring the band gap. It was found that the transmittance of Sample 2-5, in which Sb was added, was similar to that of Sample 1, which did not contain Sb. The high transmittance has the advantage that it can be used in TFT devices used in displays.

[0049] (Crystalline) The crystallinity was confirmed by an X-ray diffraction device to determine whether the material was amorphous. If no broad pattern (only a halo pattern) with no significant peaks was observed, the material was deemed amorphous.

[0050] As a result, Samples 1 to 5, including Sample 1 which did not contain Sb, were found to be amorphous, which is indicated as Amo in the table.

[0051] (Device 1-5) Moreover, the semiconductor device (TFT) 1-5 shown in FIG. 3 was manufactured using the same oxide semiconductor thin film as an active layer. The base material 10 is a glass substrate, and the gate electrode 13 is made of molybdenum and is 200 nm thick. The gate insulating film 12 is made of a laminated film of a silicon oxide film (SiOx) and a silicon nitride film (SiNx) and is 200 nm to 400 nm thick. The source electrode 15S and the drain electrode 15D are metal films with thicknesses of 100 nm to 200 nm.

[0052] A power supply and an ammeter were connected to this TFT, and the change in threshold voltage Von was measured by sweeping Vg in the forward direction (negative to positive) and in the reverse direction (positive to negative). The results are shown in Figure 7. The hysteresis width is also shown in Table 1.

[0053] As a result, hysteresis with a Vg difference of 0.5 V or more was observed in Device 2-4, which contained Sb, but almost no hysteresis was observed in Device 1, which did not contain Sb. Hysteresis is formed from an upward curve, where the current rises with a forward Vg sweep, and a downward curve, where the current falls to 0 V with a reverse Vg sweep, and hysteresis was said to have been formed when the Vg at the end of the downward curve was 0.5 V or more higher than the Vg at the start of the upward curve. Here, the gate voltage at which Id=1 nA is Von, and the difference in Von depending on the sweep direction is the hysteresis width, which will be referred to as the hysteresis width hereinafter. FIG. 7 shows a ternary composition diagram of In, Al, and Sb when Zn is fixed at about 25%, and it is expected that hysteresis will be observed almost universally in compositions containing Sb.

[0054] [Table 1]

[0055] (Sample 6-10) The oxide semiconductor thin films of Samples 6-10 were formed in the same manner as the oxide semiconductor thin films of Samples 1-5, and the band gap Eg and crystallinity were measured in the same manner. The band gap Eg, transmittance, and crystallinity are shown in Tables 2 and 3.

[0056] In addition, the Hall mobility and carrier concentration were measured as follows. Each sample was set in a Hall effect measuring device (HL5500; manufactured by Toho Technology Co., Ltd.), and the Hall effect was evaluated at room temperature, and the carrier density and mobility were measured. These results are shown in Tables 2 and 3.

[0057] As a result, Sample 6-10 was amorphous, and there was no significant change in the band gap, which was within the range of 2.4 to 4.0, specifically, within the range of 2.5 to 2.9. Such an oxide semiconductor thin film has a hole mobility of 1 cm 2Above / Vs, specifically, 10 to 40 cm 2 / Vs, and the carrier concentration is 10 14 ~10 19 cm -3 within the range of, specifically, 1×10 14 ~5×10 18 cm -3 It was thus. As a result, it was found that the oxide semiconductor thin films of Samples 6 - 10 have characteristics that enable them to be used as the active layer of a transistor.

[0058] (Device 6 - 10) Similarly, a semiconductor device (TFT) 6 - 10 having the oxide semiconductor thin film of Samples 6 - 10 as the active layer was manufactured, and hysteresis was similarly observed. The results are shown in FIGS. 8 to 12. As shown in these drawings, hysteresis was similarly observed in TFT 6 - 10 as well.

[0059]

Table 2

[0060]

Table 3

[0061] (Repeated characteristics test) Using TFT5, the observation of hysteresis was repeated 100,000 times. That is, the observation of hysteresis, which results in an increasing curve of current with the sweeping of Vg in the forward direction and then a decreasing curve of current down to 0 A with the sweeping of Vg in the reverse direction, was repeated 100,000 times. The results are shown in FIG. 13. The graph in FIG. 13 shows the changes in the threshold voltage Vth in the forward sweep (Forward) and the threshold voltage Vth in the reverse sweep (Backward) in each hysteresis observation. The threshold voltage Vth is the average value of Vg when 0.5 nA < Id < 5 nA. 14 to 17 show hysteresis curves for repetitions 1-100, 900-1000, 9900-10000, and 99900-100000, respectively. As a result, it was confirmed that almost the same hysteresis curve was observed even after 100,000 cycles.

[0062] (Memory) FIG. 18 shows an example of a memory configuration using a transistor according to the present invention. As shown in Fig. 18, one transistor of the present invention is one memory cell 200, and the memory cells 200 are arranged vertically and horizontally in a matrix to form a memory chip. The transistor constituting each memory cell 200 is, for example, the transistor shown in Fig. 1, and the gate electrodes 13 of the memory cells 200 in each row aligned horizontally are connected to word lines 1 to n for each row.

[0063] The source electrodes 15S of the memory cells 200 in each row aligned vertically are connected to bit lines 1 to n for each column, and the drain electrodes 15D are connected to plate lines 1 to n for each column, so that a voltage can be applied between the source electrodes 15S and the drain electrodes 15D. A sense amplifier 300 is connected to each of the bit lines 1 to n, so that the sense amplifier 300 of each of the bit lines 1 to n can measure the value of a current flowing between the source and drain of a transistor connected to the bit lines 1 to n. At this time, a predetermined voltage is applied between the source and drain.

[0064] In addition, the memory cells 200 in each column can be selected to measure the current value corresponding to each memory cell 200 by sequentially applying a predetermined voltage to the bit lines 1 to n of each column, thereby sequentially detecting the current value flowing between the source and drain of the transistor of the memory cells 200 in each column.

[0065] Here, at the time of writing, as shown in FIG. 19(a), the voltage between the source and drain is set to 0 V, and the voltage applied to the gate electrode via the bit lines 1 to n is set to a first write voltage, for example, −5 V, or a second write voltage, for example, +10 V.

[0066] Here, when writing is performed with the first write voltage, hysteresis state A is written as shown in Fig. 6. On the other hand, when writing is performed with the second write voltage, state B is written.

[0067] During reading, as shown in FIG. 19(b), when a voltage of, for example, 5 V is applied between the source and drain while a voltage of, for example, +1.5 V is applied to the gate electrode, a current flowing between the source and drain is detected.

[0068] At this time, if state A is written, the current value is relatively high, and if state B is written, the current value is relatively low. In other words, by detecting the magnitude of the current value, it is possible to detect whether the state is A or B.

[0069] (Verification of memory write retention time) FIG. 20 shows the results of writing data into a TFT transistor for memory use and measuring the time that the recorded state can be maintained. This graph shows the change in drain current Id over time when data is written before time=0 sec (applied gate voltage Vg=-5V or +10V), the gate voltage Vg is held at 1.5V at time=0 sec, and 5V is constantly applied between the source and drain electrodes. The current value of Id+ (Vg = -5V → 1.5V) gradually decreases and Id- (Vg = +10V → 1.5V) gradually increases, but even at Time = 2 sec, the ratio of Id+ (Vg = -5V → 1.5V) to Id- (Vg = +10V → 1.5V) is 121, and it can be seen that the two Id states can be maintained for approximately 2 seconds. [Explanation of symbols]

[0070] 10 Substrate 11 Active layer 11A,B Semiconductor thin film 12 Gate insulating film 12A Gate Insulation Layer 12B Gate insulation layer 13 Gate electrode 13A Bottom gate electrode 13B Top gate electrode 14 Protective film 15D Drain electrode 15S Source Electrode 16 Etching stop layer 110 Thin-film transistor

Claims

1. 1. An amorphous oxide semiconductor thin film containing Sb, In, and Zn, and further containing an element X, wherein 10%≦Zn+X≦70%, 30%≦In+Sb≦90%.

2. The element X is an oxide semiconductor containing at least one selected from the group consisting of Al, Ga, Sn, Ge, Ti, W, Hf, W, and Zr. The oxide semiconductor thin film according to claim 1 .

3. the oxide semiconductor contains Sb, In, Zn, and at least one of Al and Ga, and 10%≦Zn+(Al,Ga)≦70%, 30%≦In+Sb≦90%; The oxide semiconductor thin film according to claim 2.

4. The light transmittance at a wavelength of 500 nm is 70% or more. The oxide semiconductor thin film according to claim 1 .

5. A transistor having an active layer made of the oxide semiconductor thin film according to any one of claims 1 to 4, comprising a gate electrode provided on the active layer via a gate insulating film, and a source electrode and a drain electrode connected to the active layer. Semiconductor device.

6. When the gate voltage is swept back and forth, a hysteresis curve is formed with a Vg difference of 0.5 V or more. The semiconductor device of claim 5.

7. A semiconductor device according to claim 5 is used. Memory.

8. A memory using the semiconductor device according to claim 5 as a memory cell, A state A in which a relatively low first voltage is applied to the gate electrode to perform programming, and a state B in which a relatively high second voltage is applied to the gate electrode to perform programming are maintained; A voltage is applied between the source and drain to detect the current flowing between the source and drain, and the magnitude of the current value can be used to distinguish whether state A or state B has been written. Memory.

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