Method for manufacturing integrated device package

Abstract

To provide an improved manufacturing process or a technique for mounting multiple semiconductor dies to form an integrated device package while meeting necessary cleanliness requirements.SOLUTION: Pre-processing for manufacturing an integrated device package is performed by forming a first non-conductive dielectric layer on a first side of a plurality of dies and forming a first non-conductive dielectric layer on a first side of a carrier. The plurality of dies are sequentially bonded to the carrier by adhering the respective non-conductive dielectric layers to each other. A filling non-conductive dielectric layer is formed on the carrier and the plurality of dies until the plurality of dies are covered by the filling non-conductive dielectric layer. A portion of the filling non-conductive dielectric layer is then removed to planarize and expose conductive contact pads located on a second side of the plurality of dies opposite the first side, to form a reconstituted die assembly electrically connectable to an external electronic device.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a process for manufacturing an integrated device package, and more particularly to a process for bonding multiple semiconductor dies to form an integrated device package. [Background technology]

[0002] Typically, an integrated device package comprises one or more semiconductor dies mounted on a package substrate. Advances in assembly and packaging technology have resulted in finer and finer pitches of the semiconductor dies, increasing the challenge of electrically connecting such semiconductor dies to corresponding high density bond pads or terminals. Furthermore, bonding of such electrical connections traditionally needs to be performed in a very clean environment to avoid contamination, resulting in reduced freedom to design manufacturing processes as a result of the spatial constraints of clean rooms.

[0003] In some applications, there may be a need to bond individual singulated semiconductor dies onto a wafer or other substrate carrier, or an entire wafer with multiple unsingulated semiconductor dies may be bonded directly onto another wafer or other substrate carrier. These semiconductor dies or wafers may be stacked in a three-dimensional configuration, with each die also typically positioned laterally relative to one another. Various combinations thereof are possible. The substrate carrier may also include one or more redistribution layers, which allow for spacing between bond pads greater than the pad pitch on the die to facilitate next-level interconnection with other electronic components.

[0004] In the prior art, it can be very difficult to bond semiconductor dies (whether they comprise the same or different types of semiconductor dies) in a clean environment as described above. In order to maintain the necessary level of cleanliness when performing the bonding operation, one conventional solution is to cluster multiple interconnected tools. Using this approach, the interconnected tools operate to perform sequential bonding of multiple semiconductor dies as wafers or substrate carriers are transferred between the clustered tools and back again. In one prior art approach, a material pre-treatment tool is used to treat the dies to be bonded and the target wafer with plasma gas to clean and activate them and prepare them for the next die bonding. The dies and the target wafer are then transferred from the material pre-treatment tool to one or more die bonding tools directly or indirectly coupled to the material pre-treatment tool using a sealed passageway in order to maintain the cleanliness of the dies and the target wafer after said cleaning and activation and during said transfer.

[0005] Clustering material pre-treatment and die bonding tools has various disadvantages. First, a multiple tool setup occupies a large footprint, which leads to high operational costs. Especially when different types of die are attached, each type of die may require a different die bonder to be bonded. Moreover, since bonding of different dies is performed consecutively in a tool cluster, it is difficult to control queue times efficiently, and time may be wasted while downstream die bonding tools wait for the completion of the preceding bonding process.

[0006] To avoid the limitations of the prior art discussed above, it would be beneficial to be able to alternatively perform integration of multiple die using a stand-alone die bonder. Summary of the Invention [Problem to be solved by the invention]

[0007] SUMMARY OF THE PRESENT EMBODIMENT It is therefore an object of the present invention to provide an improved manufacturing process or technique for mounting multiple semiconductor dies to form an integrated device package while meeting necessary cleanliness requirements. [Means for solving the problem]

[0008] Accordingly, the present invention provides a method for manufacturing an integrated device package, the method comprising the steps of: preparing a plurality of dies for bonding by forming a first non-conductive dielectric layer on a first side of the plurality of dies, preparing the carrier by forming a first non-conductive dielectric layer on the first side of the carrier, sequentially bonding the plurality of dies to the carrier by adhering the first non-conductive dielectric layer on the first side of the plurality of dies to the first non-conductive dielectric layer on the first side of the carrier, forming a filled non-conductive dielectric layer over the carrier and the plurality of dies bonded on the carrier until the plurality of dies are covered by the filled non-conductive dielectric layer, and removing a portion of the filled non-conductive dielectric layer to planarize and expose conductive contact pads located on a second side opposite the first side of the plurality of dies to form a reconstructed die assembly, such that the conductive contact pads of the reconstructed die assembly are electrically connectable to an external electronic device.

[0009] It will be convenient hereinafter to describe the invention in more detail by reference to the accompanying drawings, which show certain preferred embodiments of the invention: Particularity in the drawings and the associated description should not be understood as superseding the generality of the broad character of the invention as defined by the claims.

[0010] Hereinafter, a specific example of a process for manufacturing an integrated device package according to the present invention will be described with reference to the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1A]FIG. 1 illustrates the steps involved in a die pre-processing stage, including forming conductive bumps on the die, thinning and passivating the surface of the die, and separating the die from other dies included in the wafer. [Figure 1B] FIG. 1 illustrates the steps involved in a die pre-processing stage, including forming conductive bumps on the die, thinning and passivating the surface of the die, and separating the die from other dies included in the wafer. [Figure 1C] FIG. 1 illustrates the steps involved in a die pre-processing stage, including forming conductive bumps on the die, thinning and passivating the surface of the die, and separating the die from other dies included in the wafer. [Figure 1D] FIG. 1 illustrates the steps involved in a die pre-processing stage, including forming conductive bumps on the die, thinning and passivating the surface of the die, and separating the die from other dies included in the wafer. [Figure 1E] FIG. 1 illustrates the steps involved in a die pre-processing stage, including forming conductive bumps on the die, thinning and passivating the surface of the die, and separating the die from other dies included in the wafer. [Figure 2A] FIG. 13 shows the steps involved in the carrier preparation stage, including creating alignment marks on the surface of the carrier and passivating the surface of the carrier to prepare it for bonding. [Figure 2B] FIG. 13 shows the steps involved in the carrier preparation stage, including creating alignment marks on the surface of the carrier and passivating the surface of the carrier to prepare it for bonding. [Figure 2C] FIG. 13 shows the steps involved in the carrier preparation stage, including creating alignment marks on the surface of the carrier and passivating the surface of the carrier to prepare it for bonding. [Figure 3A] 1A-1E to the carrier preprocessed in FIGS. 2A-2C. FIG. [Figure 3B] 1A-1E to the carrier preprocessed in FIGS. 2A-2C. FIG. [Figure 4] FIG. 3C illustrates the step of passivating the surface of the bonded fully populated carrier as shown in FIG. 3B with a non-conductive dielectric layer. [Diagram 5] FIG. 5 illustrates planarization of the fully populated carrier of FIG. 4 to expose the copper bumps of the bonded die. [Figure 6A] 6 illustrates bonding of the fully populated carrier of FIG. 5 to a wafer according to one embodiment of the present invention. [Figure 6B] 6 illustrates bonding of the fully populated carrier of FIG. 5 to a wafer according to one embodiment of the present invention. [Figure 6C] 6 illustrates bonding of the fully populated carrier of FIG. 5 to a wafer according to one embodiment of the present invention. [Figure 7] FIG. 13 illustrates an integrated device package comprised of two fully populated carriers joined together according to another embodiment of the present invention. [Figure 8] 1 illustrates bonding of each separated die to a fully populated carrier according to one embodiment of the present invention. [Figure 9] 11 illustrates the further formation of fan-out interconnects on a fully populated carrier in accordance with one embodiment of the present invention. [Figure 10A] FIG. 1 illustrates the steps involved in preparing a core die for use in multi-layer die stacking. [Figure 10B] FIG. 1 illustrates the steps involved in preparing a core die for use in multi-layer die stacking. [Figure 10C] FIG. 1 illustrates the steps involved in preparing a core die for use in multi-layer die stacking. [Figure 10D] FIG. 1 illustrates the steps involved in preparing a core die for use in multi-layer die stacking. [Figure 10E] FIG. 1 illustrates the steps involved in preparing a core die for use in multi-layer die stacking. [Figure 10F] FIG. 1 illustrates the steps involved in preparing a core die for use in multi-layer die stacking. [Figure 10G] FIG. 1 illustrates the steps involved in preparing a core die for use in multi-layer die stacking. [Figure 11A] 2A-2C illustrate an example of how multiple core dies may be stacked together to form a multi-layer integrated device package, in accordance with one embodiment of the present invention. [Figure 11B] 2A-2C illustrate an example of how multiple core dies may be stacked together to form a multi-layer integrated device package, in accordance with one embodiment of the present invention. [Figure 11C] 2A-2C illustrate an example of how multiple core dies may be stacked together to form a multi-layer integrated device package, in accordance with one embodiment of the present invention. [Figure 11D] 2A-2C illustrate an example of how multiple core dies may be stacked together to form a multi-layer integrated device package, in accordance with one embodiment of the present invention. [Figure 11E] 2A-2C illustrate an example of how multiple core dies may be stacked together to form a multi-layer integrated device package, in accordance with one embodiment of the present invention. [Figure 11F] 2A-2C illustrate an example of how multiple core dies may be stacked together to form a multi-layer integrated device package, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] 1A-1E show the steps involved in the die pre-processing stage. In FIG. 1A, first, a number of dies are selected, which may consist of multiple types of dies that will be combined in an integrated device package. As an example, three types of dies are selected, referred to as die A10, die B12, and die C14, respectively. At this point, typically, these different dies 10, 12, 14 are included in a non-singulated wafer containing multiple dies to enable batch processing. Thus, the die A10, the die B12, and the die C14 are each included in a separate wafer, each of the wafers having an array of non-singulated dies.

[0013] In Figure 1B, conductive contact pads, such as copper bumps 16, are formed on the bond pads of each of the dies 10, 12, 14, typically by electroplating a copper material onto the bond pads of the dies. In Figure 1C, the underside of the first side of the wafer (opposite the top surface of the second side of the wafer on which the copper bumps 16 are formed) is ground to form a thinned wafer surface 18. Such grinding may be performed first by mechanical grinding, followed by chemical-mechanical polishing ("CMP") of the underside of the wafer.

[0014] 1D shows a non-conductive dielectric layer 20 formed on each of the ground, thinned wafer surfaces 18 to prepare the group of different dies 10, 12, 14 for mounting in fixed positions relative to one another on a carrier. The non-conductive dielectric layer 20 may comprise a non-conductive material that may include, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride, or may include carbon, such as, for example, silicon carbide, silicon oxycarbonitride, silicon carbonitride, or diamond-like carbon.

[0015] By using a suitable setup, these materials can be deposited on the wafer by thin film deposition processes, including but not limited to physical vapor deposition processes and chemical vapor deposition processes. In particular, thin film deposition of these materials by plasma enhanced chemical vapor deposition (i.e. PECVD) is preferred. Typically, thin film deposition is followed by polishing of the surface of the deposited non-conductive dielectric layer by CMP. Then, as shown in FIG. 1E, individual dies 10, 12, 14 are singulated from the wafer with them by a singulation process, for example saw blade dicing or laser dicing, so that each singulated die 10, 12, 14 has a singulated surface 22 that separates it from other dies of the same wafer.

[0016] Although the non-conductive dielectric layer 20 may comprise organic or inorganic dielectric materials, it is preferred to use only inorganic dielectric materials because the thermal expansion coefficient of inorganic dielectric materials more closely matches that of the silicon dies 10, 12, and 14. This ensures that the dies 10, 12, 14 are less likely to suffer from problems due to mismatched thermal expansion coefficients, such as warping when exposed to high temperatures.

[0017] 2A-2C show the steps involved in the carrier pre-treatment stage. In FIG. 2A, first, a carrier 24 is selected for mounting the dies 10, 12, 14 pre-treated in FIG. 1E. The carrier 24 is flat and may be made of various materials, such as silicon or glass. In FIG. 2B, after selecting the carrier 24, alignment marks 26 are made on the top surface of the carrier 24 at designated locations for alignment. These alignment marks 26 may be used later to assist in accurately mounting multiple dies 10, 12, 14 on specific locations on the carrier 24. As shown in FIG. 2C, to prepare the carrier 24 for mounting the dies 10, 12, 14 on the carrier 24, a first or top surface of the carrier 24 is passivated by forming a non-conductive dielectric layer 28 on its top surface. Such passivation may be performed using a non-conductive material similar to that used for the non-conductive dielectric layer 20 formed on the dies 10, 12, 14 described above. The surface of the deposited non-conductive dielectric layer 28 is then polished by CMP.

[0018] 3A and 3B show bonding of the die preprocessed in FIGS. 1A-1E to the carrier preprocessed in FIGS. 2A-2C. In order to avoid manufacturing defective electronic devices, only known good dies among the separated dies must be selected for bonding to the carrier 24. In FIG. 3A, the known good dies among die A 10, die B 12, and die C 14 are bonded to a predetermined position on the carrier 24. These singulated dies 10, 12, and 14 are bonded sequentially onto the carrier 24 with reference to alignment marks 26 previously fabricated on the top surface of the carrier 24.

[0019] The dies 10, 12, 14 are bonded onto the carrier 24 with their copper bumps 16 facing upward and away from the carrier 24. The non-conductive dielectric layer 20 on the dies 10, 12, 14 is thus in contact with the non-conductive dielectric layer 28 on the carrier 24, thereby achieving direct dielectric-to-dielectric bonding through the non-conductive dielectric layers 20, 28, respectively, formed during the previous die and carrier preparation steps when the dies 10, 12, 14 are mounted onto the carrier 24.

[0020] As shown in FIG. 3B, the dielectric-to-dielectric bonds are annealed in a suitable environment (e.g., at high temperature and after purging the ambient gas with nitrogen gas) to bond the respective non-conductive dielectric layers 20, 28 together, harden the bonds, and fix the positions of the dies 10, 12, 14 relative to each other.

[0021] Figure 4 illustrates the step of passivating the surface of the bonded fully populated carrier 24 as shown in Figure 3B, with a further filled non-conductive dielectric layer 30 being added over the carrier 24 and the dies 10, 12, 14. This additional filled non-conductive dielectric layer 30 not only fills any gaps between the dies 10, 12, 14 disposed on the carrier 24, but also extends to a height that covers all of the copper bumps 16 on the dies 10, 12, 14.

[0022] 5 illustrates planarization of the fully populated carrier 24 in FIG. 4 to expose the conductive contact pads or copper bumps 16 of the dies 10, 12, 14 bonded to the fully populated carrier 24. Planarization may be performed by utilizing CMP to grind the non-conductive dielectric layer to remove portions of the filled non-conductive dielectric layer 30, ultimately exposing all of the copper bumps 16 on the top surface of the ground filled non-conductive dielectric layer 30. Thus, the top surfaces of the copper bumps 16 and the top surface of the filled non-conductive dielectric layer 30 are flush with each other, which allows the so-planarized reconstructed die assembly 34 to be electrically connected to an external electrical device, as will be further described below.

[0023] It should be understood that different types of dies 10, 12, 14 have inherently different thickness tolerances, while the copper bumps 16 formed on the dies 10, 12, 14 also have height tolerances. The advantage of the planarization step in Figure 5 is that by properly designing the die thickness and bump height tolerances, this process ensures that all exposed surfaces of the copper bumps 16 are uniformly positioned at the same height, thereby facilitating subsequent bonding to other devices despite the inherent differences in thickness and height.

[0024] 6A-6C illustrate bonding of a flattened rebuilt die assembly 34 (formed from the fully populated carrier 24 of FIG. 5) to a wafer 36 in accordance with one embodiment of the present invention. In FIG. 6A, the exposed copper bumps 16 of the flattened rebuilt die assembly 34 face upward. In FIG. 6B, the flattened rebuilt die assembly 34 is flipped over so that its exposed copper bumps 16 face corresponding conductive contacts 38 formed on the wafer 36. The conductive contacts 38 of the wafer 36 may be surrounded by a non-conductive dielectric layer 39.

[0025] The exposed copper bumps 16 of the planarized rebuilt die assembly 34 are then aligned and placed in contact with the conductive contacts 38 of the wafer 36, as shown in FIG. 6C. The adhesion between the respective non-conductive dielectric layers 30, 39 is hardened by annealing. This completes the fabrication of an integrated device package 40 comprised of the planarized rebuilt die assembly 34 bonded to the wafer 36. The resulting structure may be processed through downstream processes to form a final device structure that can be electrically connected to other electronic devices.

[0026] FIG. 7 shows an integrated device package 42 constructed by two fully populated carriers in the form of two planarized rebuilt die assemblies 34, 34' similar to each other. These two planarized rebuilt die assemblies 34, 34' are bonded together according to another embodiment of the present invention. The copper bumps 16 of the two planarized rebuilt die assemblies 34, 34' are aligned and bonded to each other in the manner shown in FIG. 6C to create the integrated device package 42. The pre-processing and assembly of each planarized rebuilt die assembly 34, 34' can be performed using the same process already described above, so a detailed description of this process will not be repeated here. The resulting structure can be processed by downstream processes to provide a final device structure that can be electrically connected to other electronic devices.

[0027] 8 illustrates the bonding of each of the dies separated from the second plurality of dies, die D 44 and die E 46, to a fully populated carrier 24 in the form of a planarized rebuilt die assembly 34, according to an embodiment of the present invention. To achieve dielectric-to-dielectric bonding, the conductive contact pads or copper bumps 48 of the dies 44, 46 are surrounded by a non-conductive dielectric layer 49 that is flush with the exposed surfaces of the copper bumps 48. Known good singulated dies from the dies D 44 and die E 46 are sequentially bonded in place on the planarized rebuilt die assembly 34 by utilizing direct dielectric-to-dielectric bonding via the respective non-conductive dielectric layers 30, 49. The singulated dies 44, 46 may be bonded onto the planarized rebuilt die assembly 34 with reference to the exposed copper bumps 16 on the top surface of the planarized rebuilt die assembly 34, or separate alignment marks may be added to the planarized rebuilt die assembly 34 for alignment purposes. The integrated device package thus produced combines the planarized rebuilt die assembly 34 with the second plurality of dies 44, 46. The resulting structure may be processed by downstream processes to yield a final device structure that is electrically connectable to other electronic devices.

[0028] 9 illustrates the further formation of fan-out interconnects on a fully populated carrier in the form of a planarized rebuilt die assembly 34 according to one embodiment of the present invention. The fan-out interconnects may comprise one or more redistribution layers 52 that electrically couple the copper bumps 16 having a smaller spacing pitch to copper pillars 54 on the one or more redistribution layers 52 opposite the copper bumps 16. Additionally, each copper pillar 54 may be capped with a solder bump 56 to form electrical contacts for interconnection at the next level via the fan-out interconnect at the location of the solder bump 56. Such an integrated device package 58 produced by combining the planarized rebuilt die assembly 34, the one or more redistribution layers 52, and the electrical contacts may be electrically attached to other electronic devices.

[0029] 10A-10G illustrate the steps involved in preparing a core die 60 for use in multi-tier die stacking. A selected core die 60 as shown in FIG. 10A is part of a wafer that includes multiple integrated core dies 60 arranged in a matrix. Each core die 60 has multiple through silicon vias ("TSVs") that penetrate the entire thickness of the core die 60. Each TSV 64 is filled with a conductive material (such as copper), and conductive contact pads (such as copper bumps 62) are formed on both sides of the TSV. In FIG. 10A, the top surface of the core die 60 is marked with arrow 66.

[0030] In FIG. 10B, a non-conductive dielectric layer 70 covering the conductive bumps 62 is formed on the underside 68 of the first side of the core die 60. In FIG. 10C, each core die 60 forms part of the wafer, but is singulated from the wafer such that there is a singulated surface 72 on each core die 60. As shown in FIG. 10D, if the core die 60 is a good die and has no defects, the singulated core die 60 can be referred to as a known good core die 74. The known good core die 74 is then bonded to a carrier 76 having a corresponding non-conductive dielectric layer 78 formed thereon. Such a carrier 76 can be made of silicon, glass, or other suitable material.

[0031] Figure 10E shows a known good core die 74 bonded to a carrier 76 using direct dielectric to dielectric bonding. Figure 10F shows another non-conductive dielectric layer 80 being formed on the top surface (indicated by arrows 66) of the core die 60 to fill the gaps between each conductive bump 62 and to fill the non-conductive dielectric layer 80 so that all of the conductive bumps 62 are covered.

[0032] In FIG. 10G, the non-conductive dielectric layer 80 is ground away until the top surfaces of the conductive bumps 62 are exposed, and the surfaces of the non-conductive dielectric layer 80 and the conductive bumps 62 are flush with one another, resulting in a planarized reconstructed die assembly 82 comprising the core die 60.

[0033] 11A-11F illustrate an example of how multiple core dies 60, 94 may be stacked together to form a multi-layer integrated device package 100 according to an embodiment of the present invention. As shown in FIG. 11A, there is a second or lower rebuilt die assembly 90, which may include a lower die 92 bonded to a carrier 84 via a non-conductive dielectric layer 86. The structure of the lower rebuilt die assembly 90 is similar to that of the planarized rebuilt die assembly 82. The lower die 92 has copper bumps 88 on its lower surface covered by the non-conductive layer 86 and exposed copper bumps 88 on its upper surface.

[0034] The exposed conductive bumps 62 on the planarized rebuilt die assembly 82 with the core die 60 are aligned with the exposed conductive bumps 88 on the top surface of the lower die 92. The planarized rebuilt die assembly 82 with the core die 60 is then bonded to the top surface of the lower planarized rebuilt die assembly 90 with the lower die 92 such that the conductive bumps 62 are in electrical contact with the corresponding conductive bumps 88.

[0035] 11B shows integrated device package 82 bonded to an integrated device package that includes bottom die 92. Additionally, carrier 76 and a portion of non-conductive dielectric layer 78 of planarized reconstructed die assembly 82 have been removed to expose the top surface of conductive pads 62 of core die 60.

[0036] 11C shows a further second core die 94 having copper bumps 88 bonded and electrically connected to the top surface of the conductive pads 62 of the core die 60. A further rebuilt die assembly (not shown) comprising the second core die 94 is then bonded to the top surface of the core die 60, with the dielectric to dielectric bonding manner being similar to that described in connection with FIGS. 1A and 1B. The carrier and a portion of the non-conductive dielectric layer of the integrated device package comprising the second core die 94 are then ground away to expose the copper bumps 88 on the top surface of the package. Thus, as shown in FIG. 11C, this stacked assembly comprises three separate layers of stacked dies 92, 60, 94.

[0037] 11D, a top rebuilt die assembly 96 comprising a top die 98 mounted on a carrier 100 via a non-conductive dielectric layer 102 is flipped over so that its copper bumps 88 face the copper bumps 88 of the second core die 94. The manufacturing process utilized to form such an integrated device package 96 may be similar to the manufacturing process utilized to form an integrated device package in the form of the rebuilt die assembly 34 shown in FIG.

[0038] 11E, the top die 98 is bonded and electrically connected to the second core die 94 via a dielectric-to-dielectric bond, thereby bonding to the respective copper bumps 88. Furthermore, the carrier 100 and the non-conductive dielectric layer 102 of the top die 98 are completely ground away to expose the top surface of the top die 98. Thus, the top surfaces of the plurality of top dies 98 are removed.

[0039] 11F, a portion of the carrier 84 and the non-conductive dielectric layer 86 of the lower rebuilt die assembly 90 is removed by grinding to expose the copper bumps 88 on the underside of the lower die 92. Solder bumps 96 are then deposited on these exposed copper bumps 88 on the underside of the lower die 92. The fabricated multi-layer integrated device package 104, which includes the upper die 98 of the upper rebuilt die assembly 96, one or more core dies 60, 94, and the lower die 92 of the lower rebuilt die assembly 90, can now be singulated to separate the respective electronic devices for electrical testing. These singulated and tested electronic devices are then ready to be electrically attached to other electronic devices using the solder bumps 96 as electrical interconnects for the next level of device interconnection.

[0040] It should be appreciated that the manufacturing process according to the preferred embodiment of the present invention presents an architecture, method, and process flow that allows an effective way to integrate multiple dies to form an integrated device package. The multiple dies may be of the same type or different types, and a stand-alone die bonder may be used without the need to cluster pre-processing tools and multiple die bonders together to handle materials such as multiple dies and target wafers. This results in improved control of both material cleanliness and manufacturing queue times. The above approach avoids the need to cluster multiple tools, which in the prior art led to poor performance and unnecessarily complex operations of individual tools, especially for integrating multiple dies of different die types.

[0041] Furthermore, a much larger process window is available due to less time constraints imposed by queue times and less need for strict sequential integrated assembly lines. Thus, there is more freedom to handle single and multi-layer 3D integrated device packages using either single or multiple chiplets (active or inactive) integration and / or die stacking. The strict sequential mode of operation in the prior art is avoided by enabling parallel processing. This feasibility can significantly improve productivity.

[0042] Avoiding the use of organic dielectric materials in the non-conductive dielectric layers can further reduce thermal expansion coefficient mismatches that can cause warpage or die shift issues. Additionally, grinding planarization using CMP or other surface removal techniques on the integrated device package assists in the next level of interconnection made in downstream processing of the integrated device package by eliminating any die thickness or height discrepancies, especially in devices with multiple chiplets.

[0043] It will be understood that the invention described herein is susceptible to variations, modifications, and / or additions other than those specifically described, and the invention includes all such variations, modifications, and / or additions that fall within the spirit and scope of the foregoing description. [Explanation of symbols]

[0044] 10 silicon die, A10 die, 12 die, B12 die, 14 die, C14 die, 16 copper bumps, 18 thinned wafer surface, 20 non-conductive dielectric layer, 22 singulated surface, 24 fully populated carrier, 26 alignment marks, 28 non-conductive dielectric layer, 30 filled non-conductive dielectric layer, 34 planarized rebuilt die assembly, 36 wafer, 38 conductive contacts, 39 non-conductive dielectric layer, 40 integrated device package, 42 integrated device package, 44 die, 44D die, 46 die, E46 die, 48 copper bumps, 49 non-conductive dielectric layer, 52 redistribution layer, 54 copper pillars, 56 solder bumps, 58 integrated device package, 60 core die, 62 copper bumps, conductive bumps, conductive pads, 64 through silicon vias, TSVs, 66 top surface, 68 bottom surface, 70 non-conductive dielectric layer, 72 singulated surface, 74 core die, 76 carrier, 78 non-conductive dielectric layer, 80 non-conductive dielectric layer, 82 planarized rebuilt die assembly, integrated device package, 84 carrier, 86 non-conductive dielectric layer, 88 copper bumps, conductive bumps, 90 bottom rebuilt die assembly, 92 bottom die, 94 second core die, 96 top rebuilt die assembly, integrated device package, solder bumps, 98 top die, 100 multi-layer integrated device package, carrier, 102 non-conductive dielectric layer, 104 multi-layer integrated device package

Claims

1. 1. A method for manufacturing an integrated device package, comprising: preparing a plurality of die for bonding by forming a first non-conductive dielectric layer on a first surface of the plurality of die; preparing the carrier by forming a first non-conductive dielectric layer on a first surface of the carrier; sequentially bonding the plurality of dies to the carrier by adhering the first non-conductive dielectric layer on the first side of the plurality of dies to the first non-conductive dielectric layer on the first side of the carrier; forming a filled non-conductive dielectric layer over the carrier and the plurality of dies bonded onto the carrier until the plurality of dies are covered by the filled non-conductive dielectric layer; removing a portion of the filled non-conductive dielectric layer to planarize and expose conductive contact pads located on a second side of a plurality of the dies opposite the first side to form a rebuilt die assembly, the conductive contact pads of the rebuilt die assembly being electrically connectable to an external electronic device; A method comprising:

2. The step of pre-treating a plurality of the dies further comprises: forming the first non-conductive dielectric layer on a first side of a wafer comprising a plurality of the dies; singulating the wafer to separate a plurality of the dies; The method of claim 1 further comprising:

3. forming the conductive contact pads on a second side of the wafer opposite the first side; grinding the first side of the wafer to thin the wafer prior to forming the first non-conductive dielectric layer on the first side of the wafer; The method of claim 2 , further comprising:

4. The method of claim 2 , further comprising the step of selecting only known good dies from the separated plurality of dies for bonding onto the carrier.

5. 10. The method of claim 1, wherein the first non-conductive dielectric layer on the first surface of the plurality of dies and the carrier consists solely of an inorganic dielectric material.

6. The step of pre-treating a plurality of the dies further comprises: forming the first non-conductive dielectric layer on a first side of a plurality of wafers of different types comprising a plurality of the dies of different types; singulating a plurality of said wafers to separate a plurality of said dies of different types for bonding; The method of claim 1 further comprising:

7. The method of claim 1 , wherein the first non-conductive dielectric layer on the first surface of the plurality of dies and the carrier is deposited by plasma enhanced chemical vapor deposition.

8. 2. The method of claim 1, wherein the step of preparing the carrier further comprises creating alignment marks on the first surface of the carrier for alignment purposes during bonding of a plurality of the dies onto the carrier.

9. 2. The method of claim 1 , wherein the first non-conductive dielectric layers on a plurality of the dies are adhered to the first non-conductive dielectric layer on the carrier by annealing each of the non-conductive dielectric layers to one another to cure a dielectric-to-dielectric bond of the non-conductive dielectric layers and fix the relative positions of the non-conductive dielectric layers.

10. 2. The method of claim 1, wherein the filled non-conductive dielectric layer is planarized such that a top surface of the conductive contact pad and a top surface of the filled non-conductive dielectric layer are coplanar with one another.

11. 10. The method of claim 1, further comprising the steps of: providing the wafer with a non-conductive dielectric layer surrounding conductive contacts of the wafer; and bonding conductive pads of the rebuilt die assembly to the conductive contacts, such combination of the rebuilt die assembly and the wafer forming the integrated device package.

12. 10. The method of claim 1 , further comprising the steps of: providing a second rebuilt die assembly similar to the rebuilt die assembly; and bonding the conductive contact pads of the rebuilt die assembly to the conductive contact pads of the second rebuilt die assembly, such combination of the rebuilt die assembly and the second rebuilt die assembly forming the integrated device package.

13. 2. The method of claim 1, further comprising the steps of: providing a plurality of second separated dies having a non-conductive dielectric layer surrounding conductive contact pads of each of the plurality of second separated dies; and bonding the plurality of second separated dies to electrically connect the contact pads of the plurality of second separated dies to the conductive contact pads of the rebuilt die assembly, such combination of the rebuilt die assembly and the plurality of second separated dies forming the integrated device package.

14. 10. The method of claim 1, further comprising forming one or more redistribution layers on the planarized filled non-conductive dielectric layer to electrically couple the conductive contact pads to electrical contacts formed on one or more redistribution layers opposite the conductive contact pads, such combination of the reconstructed die assembly, the one or more redistribution layers, and the electrical contacts forming the integrated device package.

15. 2. The method of claim 1 , wherein the step of pre-processing a plurality of the die further comprises forming a plurality of through silicon vias in each die, the through silicon vias being filled with a conductive material, and forming the conductive contact pads on both sides of the through silicon vias before forming the first non-conductive dielectric layer on the first side of each die, the first non-conductive dielectric layer covering the conductive contact pads on the first side of each die for bonding each die to the carrier.

16. 16. The method of claim 15, further comprising, after forming the reconstructed die assembly, providing a second reconstructed die assembly similar to the reconstructed die assembly, and bonding the conductive contact pads of the second reconstructed die assembly to the conductive contact pads of the reconstructed die assembly.

17. 17. The method of claim 16, further comprising removing a portion of the carrier and the non-conductive dielectric layer of the rebuilt die assembly to expose the conductive contact pads of the rebuilt die assembly that are flush with a top surface of the portion of the non-conductive dielectric layer that remains unremoved.

18. 20. The method of claim 17, further comprising, after exposing the conductive contact pads of the rebuilt die assembly, providing a third rebuilt die assembly similar to the rebuilt die assembly, and bonding the conductive contact pads of the third rebuilt die assembly to the conductive contact pads of the rebuilt die assembly.

19. 20. The method of claim 17, further comprising the steps of: providing a plurality of second dies mounted on a second carrier via a second non-conductive dielectric layer; and bonding a plurality of the second dies to electrically connect conductive contacts of the plurality of second dies to the conductive contact pads of the rebuilt die assembly.

20. removing a portion of the carrier and the non-conductive dielectric layer of the second reconstructed die assembly to expose the conductive contact pads of the plurality of dies of the second reconstructed die assembly that are flush with a surface of the remaining non-conductive dielectric layer portions; removing the second carrier and the second non-conductive dielectric layer to expose surfaces of a plurality of the second dies; Further comprising:

20. The method of claim 19, wherein such combination of the rebuilt die assembly, the second rebuilt die assembly, and a plurality of the second dies forms the integrated device package.

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