Storage device and method for driving storage device

Abstract

To provide a new semiconductor device.SOLUTION: One of source or drain of a first transistor is connected to one terminal of a first capacitance element, the other of the source or drain of the first transistor is connected to a bit line, a gate of the first transistor is connected to a word line, the other terminal of the first capacitance element is connected to a first driving circuit, the first driving circuit has a function of outputting a first potential, a function of outputting a second potential in conjunction with a timing when a potential of a selection signal applied to the word line is changed, and a function of outputting a third potential in conjunction with a timing when the potential of data applied to the bit line is changed, in which the direction changed from the first potential to the second potential is opposite to a direction where the potential of the selection signal is changed and the direction changed from the first potential to the third potential is opposite to the direction the potential of the data is changed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a memory device and a method for driving the memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the present specification etc. relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). More specifically, examples of the technical field of one embodiment of the present invention disclosed in the present specification etc. include a semiconductor device, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, an arithmetic device, a control device, a storage device, an input device, an output device, an input / output device, a signal processing device, an arithmetic processing device, an electronic computer, an electronic device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] It is known that a transistor including an oxide semiconductor in a channel formation region has an extremely small off-state current. For example, Patent Document 1 discloses a low-power arithmetic processing unit (such as a CPU) that utilizes the characteristic of the transistor having a small off-state current. In addition, Patent Document 2 discloses a storage device (such as a main memory and a cache memory) that can store data for a long period of time by utilizing the characteristic of the transistor having a small off-state current.

[0004] Furthermore, for example, Patent Document 3 discloses a technique for stacking the transistors to increase the density of an integrated circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2021 / 053473 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a semiconductor device capable of increasing a retention time, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device capable of increasing the operation speed, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device capable of increasing the recording density, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device. Alternatively, an object of one embodiment of the present invention is to provide a miniaturized semiconductor device, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device. Another object of one embodiment of the present invention is to provide a novel semiconductor device, a memory device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the memory device.

[0007] The above-mentioned problem does not prevent the existence of other problems. Problems other than the above-mentioned problem will be obvious from the description of this specification, drawings, claims, etc., and it is possible to extract problems other than the above-mentioned problem from the description of this specification, drawings, claims, etc. Note that one embodiment of the present invention does not need to solve all of these problems (the above-mentioned problem and other problems). [Means for solving the problem]

[0008] (1) One embodiment of the present invention is a storage device having a memory array and a peripheral circuit, the memory array having a first memory cell, the peripheral circuit having a first drive circuit, the first memory cell having a first transistor and a first capacitance element, one of a source or a drain of the first transistor being electrically connected to one terminal of the first capacitance element, the other of the source or the drain of the first transistor being electrically connected to a bit line, a gate of the first transistor being electrically connected to a word line, and the other terminal of the first capacitance element being electrically connected to a first drive circuit, the first drive circuit having a function of outputting a first potential, a function of outputting a second potential in conjunction with a timing at which a potential of a selection signal applied to the word line changes, and a function of outputting a third potential in conjunction with a timing at which a potential of data applied to the bit line changes, wherein a direction in which the potential changes from the first potential to the second potential is opposite to a direction in which the potential of the selection signal changes, and a direction in which the potential changes from the first potential to the third potential is opposite to a direction in which the potential of the data changes.

[0009] (2) One aspect of the present invention includes a memory array and a peripheral circuit, the memory array includes a first memory cell and a second memory cell, the peripheral circuit includes a first drive circuit and a second drive circuit, the first memory cell includes a first transistor and a first capacitance element, the second memory cell includes a second transistor and a second capacitance element, one of a source or a drain of the first transistor is electrically connected to one terminal of the first capacitance element, the other of the source or the drain of the first transistor is electrically connected to a bit line, the gate of the first transistor is electrically connected to a first word line, and the other terminal of the first capacitance element is electrically connected to the first drive circuit. a first driving circuit having a function of outputting a signal whose potential changes in a direction opposite to the direction in which the potential of a selection signal applied to the first word line changes, and a second driving circuit having a function of outputting a signal whose potential changes in a direction opposite to the direction in which the potential of a selection signal applied to the second word line changes.

[0010] (3) One aspect of the present invention includes a memory array and a peripheral circuit, the memory array includes a first memory cell and a second memory cell, the peripheral circuit includes a first drive circuit and a second drive circuit, the first memory cell includes a first transistor and a first capacitance element, the second memory cell includes a second transistor and a second capacitance element, one of a source or a drain of the first transistor is electrically connected to one terminal of the first capacitance element, the other of the source or the drain of the first transistor is electrically connected to a first bit line, the gate of the first transistor is electrically connected to a word line, and the other terminal of the first capacitance element is electrically connected to the first drive circuit. a gate of the second transistor electrically connected to a first terminal of the first capacitive element, one of the source and drain of the second transistor electrically connected to one terminal of the second capacitive element, the other of the source and drain of the second transistor electrically connected to a second bit line, the gate of the second transistor electrically connected to a word line, and the other terminal of the second capacitive element electrically connected to a second drive circuit, the first drive circuit having a function of outputting a signal whose potential changes in a direction opposite to a direction in which the potential of data supplied to the first bit line changes, and the second drive circuit having a function of outputting a signal whose potential changes in a direction opposite to a direction in which the potential of data supplied to the second bit line changes.

[0011] (4) One aspect of the present invention has a memory array and a peripheral circuit. The memory array has a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The peripheral circuit has a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit. The first memory cell has a first transistor and a first capacitor element. The second memory cell has a second transistor and a second capacitor element. The third memory cell has a third transistor and a third capacitor element. The fourth memory cell has a fourth transistor and a fourth capacitor element. One of the source or drain of the first transistor is electrically connected to one terminal of the first capacitor element. The other of the source or drain of the first transistor is electrically connected to the first bit line. The gate of the first transistor is electrically connected to the first word line. The other terminal of the first capacitor element is electrically connected to the first drive circuit. One of the source or drain of the second transistor is electrically connected to one terminal of the second capacitor element. The other of the source or drain of the second transistor is electrically connected to the first bit line. The gate of the second transistor is electrically connected to the second word line. The other terminal of the second capacitor element is electrically connected to the second drive circuit. One of the source or drain of the third transistor is electrically connected to one terminal of the third capacitor element. The other of the source or drain of the third transistor is electrically connected to the second bit line. The gate of the third transistor is electrically connected to the first word line. The other terminal of the third capacitor element is electrically connected to the third drive circuit. One of the source or drain of the fourth transistor is electrically connected to one terminal of the fourth capacitor element. The other of the source or drain of the fourth transistor is electrically connected to the second bit line. The gate of the fourth transistor is electrically connected to the second word line. The other terminal of the fourth capacitor element is electrically connected to the fourth drive circuit, which is a storage device.

[0012] (5) Also, in any one of (1) to (4) above, the first transistor may contain an oxide semiconductor in the channel formation region.

[0013] (6) In any one of the above (1) to (4), the first transistor may be provided on the first capacitive element.

[0014] (7) In addition, in the above (6), the semiconductor device may have a first conductor, a second conductor on the first conductor, and a third conductor on the second conductor, wherein the first conductor includes a region that functions as the other terminal of the first capacitive element, the second conductor includes a region that functions as one terminal of the first capacitive element and a region that functions as one of the source or drain of the first transistor, and the third conductor includes a region that functions as the other of the source or drain of the first transistor.

[0015] (8) In any one of the above (1) to (4), the memory array may be provided on a peripheral circuit.

[0016] (9) One embodiment of the present invention is a method for driving a memory device having a memory cell in which one of a source or a drain of an n-channel transistor is electrically connected to one terminal of a capacitor, in which the potential of a selection signal applied to a gate of the transistor is lowered and then the potential applied to the other terminal of the capacitor is increased.

[0017] (10) One embodiment of the present invention is a method for driving a memory device having a memory cell in which one of a source or a drain of an n-channel transistor is electrically connected to one terminal of a capacitor, and the method reduces the potential applied to the other terminal of the capacitor in synchronization with the timing of increasing the potential of data applied to the other of the source or drain of the transistor. Effect of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device capable of increasing a retention time, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device can be provided. According to one embodiment of the present invention, a semiconductor device capable of increasing an operation speed, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device can be provided. According to one embodiment of the present invention, a semiconductor device capable of reducing power consumption, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device can be provided. According to one embodiment of the present invention, a semiconductor device capable of increasing a recording density, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device can be provided. According to one embodiment of the present invention, a miniaturized semiconductor device, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device can be provided. According to one embodiment of the present invention, a novel semiconductor device, a storage device including the semiconductor device, a method for driving the semiconductor device, or a method for driving the storage device can be provided.

[0019] The above effects do not preclude the existence of other effects. Effects other than the above effects will be obvious from the description of this specification, drawings, claims, etc., and it is possible to extract effects other than the above effects from the description of this specification, drawings, claims, etc. An embodiment of the present invention does not need to have all of these effects (the above effects and other effects). [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a circuit diagram illustrating an example of the configuration of a storage device. [Diagram 2] 2A and 2B are timing charts illustrating an example of the operation of the storage device. [Diagram 3]3A to 3F are circuit diagrams illustrating an operation example of the memory device. [Figure 4] 4A and 4B are timing charts illustrating an example of the operation of the storage device. [Diagram 5] 5A to 5D are circuit diagrams illustrating an operation example of the memory device. [Figure 6] 6A and 6B are timing charts illustrating an example of the operation of the storage device. [Figure 7] 7A and 7B are circuit diagrams illustrating configuration examples of a memory device. [Figure 8] FIG. 8 is a circuit diagram illustrating a configuration example of a storage device. [Figure 9] FIG. 9 is a timing chart illustrating an example of the operation of the storage device. [Figure 10] FIG. 10 is a circuit diagram illustrating an example of the configuration of a storage device. [Figure 11] FIG. 11 is a timing chart illustrating an example of the operation of the storage device. [Figure 12] FIG. 12 is a circuit diagram illustrating an example of the configuration of a storage device. [Figure 13] FIG. 13 is a timing chart illustrating an example of the operation of the storage device. [Figure 14] 14A and 14B are circuit diagrams illustrating configuration examples of a memory device. [Figure 15] FIG. 15 is a block diagram showing an example of the configuration of a storage device. [Figure 16] FIG. 16 is a block diagram showing an example of the configuration of a storage device. [Figure 17] Fig. 17A is a top view showing a configuration example of a semiconductor device, and Fig. 17B and Fig. 17C are cross-sectional views showing the configuration example of a semiconductor device. [Figure 18] 18(A) and 18(B) are cross-sectional views showing configuration examples of a semiconductor device. [Figure 19] FIG. 19 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 20]20A to 20C are cross-sectional views showing configuration examples of a semiconductor device. [Figure 21] 21A to 21D are circuit diagrams showing configuration examples of a semiconductor device. [Figure 22] 22A and 22B are top views showing configuration examples of a semiconductor device. [Figure 23] 23A and 23B are cross-sectional views showing configuration examples of a semiconductor device. [Figure 24] 24(A) and 24(B) are cross-sectional views showing configuration examples of a semiconductor device. [Diagram 25] FIG. 25 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 27] Fig. 27A is a top view showing a configuration example of a semiconductor device, and Fig. 27B and Fig. 27C are cross-sectional views showing the configuration example of a semiconductor device. [Figure 28] Fig. 28(A) is a top view showing a configuration example of a semiconductor device, Fig. 28(B) is a schematic perspective view showing a configuration example of a semiconductor device, and Figs. 28(C) to 28(E) are cross-sectional views showing a configuration example of a semiconductor device. [Figure 29] 29(A) and 29(B) are cross-sectional views showing configuration examples of a semiconductor device. [Diagram 30] Fig. 30(A) is a top view showing a configuration example of a semiconductor device, Fig. 30(B) is a schematic perspective view showing a configuration example of a semiconductor device, and Figs. 30(C) to 30(E) are cross-sectional views showing a configuration example of a semiconductor device. [Diagram 31] FIG. 31 is a cross-sectional view showing a configuration example of a semiconductor device. [Diagram 32] Fig. 32(A) is a top view showing a configuration example of a semiconductor device, Fig. 32(B) is a schematic perspective view showing a configuration example of a semiconductor device, and Figs. 32(C) to 32(E) are cross-sectional views showing a configuration example of a semiconductor device. [Diagram 33] 33(A) and 33(B) are cross-sectional views showing configuration examples of a semiconductor device. [Diagram 34] Fig. 34A is a top view showing a configuration example of a semiconductor device, and Fig. 34B to Fig. 34D are cross-sectional views showing a configuration example of a semiconductor device. [Diagram 35] FIG. 35 is a diagram showing various storage devices by hierarchical level. [Diagram 36] 36A to 36H are circuit diagrams illustrating examples of the configuration of a memory cell. [Figure 37] 37A and 37B are circuit diagrams illustrating configuration examples of a semiconductor device. [Figure 38] 38(A) and 38(B) are diagrams showing an example of an electronic component. [Figure 39] 39(A) and 39(B) are diagrams showing an example of an electronic device, and Fig. 39(C) to Fig. 39(E) are diagrams showing an example of a mainframe computer. [Diagram 40] Fig. 40(A) is a diagram showing an example of space equipment, and Fig. 40(B) is a diagram showing an example of a storage system applicable to a data center. [Diagram 41] 41(A1) to 41(B6) are diagrams explaining "electrical connection". [Diagram 42] Fig. 42A is a top view showing a configuration example of a semiconductor device, and Fig. 42B and Fig. 42C are cross-sectional views showing a configuration example of a semiconductor device. [Diagram 43] 43(A) and 43(B) are schematic perspective views showing configuration examples of a semiconductor device. [Diagram 44] 44(A) and 44(B) are cross-sectional views showing configuration examples of a semiconductor device. [Diagram 45] 45(A) and 45(B) are diagrams showing evaluation results of oxide semiconductors. [Diagram 46] 46A to 46D show evaluation results of oxide semiconductors. [Figure 47] 47A to 47H show evaluation results of oxide semiconductors. [Figure 48]48A to 48D are diagrams illustrating an evaluation method of an oxide semiconductor. [Figure 49] 49A to 49H show evaluation results of oxide semiconductors. [Figure 50] FIG. 50 is a diagram showing the evaluation results of the oxide semiconductor. [Figure 51] 51(A) and 51(B) are diagrams showing the evaluation results of oxide semiconductors. [Figure 52] 52A to 52D are diagrams showing the evaluation results of transistors. [Figure 53] 53(A) and 53(B) are diagrams showing the evaluation results of transistors. [Figure 54] 54(A) and 54(B) are diagrams showing the evaluation results of transistors. [Figure 55] FIG. 55 is a diagram showing the evaluation results of the transistors. [Figure 56] 56(A) and 56(B) are diagrams showing the evaluation results of transistors. [Figure 57] 57(A) and 57(B) are diagrams showing the evaluation results of transistors. [Figure 58] 58(A) and 58(B) are diagrams showing the evaluation results of transistors. [Figure 59] FIG. 59 is a diagram showing the evaluation results of the transistors. [Figure 60] FIG. 60 is a diagram showing the evaluation results of the transistors. [Figure 61] FIG. 61 is a diagram showing the evaluation results of the storage devices. [Figure 62] 62(A) and 62(B) are diagrams showing the evaluation results of the storage devices. [Figure 63] FIG. 63 is a diagram showing the evaluation results of the storage devices. [Figure 64] 64(A) and 64(B) are diagrams showing the evaluation results of the storage devices. [Figure 65] FIG. 65 is a diagram showing the evaluation results of the storage devices. [Figure 66] FIG. 66 is a diagram showing the evaluation results of the storage devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] In this specification, the term "semiconductor device" refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having the circuit. The term also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit including a semiconductor element, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, or an electronic device in which an electronic component is mounted are examples of semiconductor devices. In addition, for example, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, an arithmetic device, a control device, a storage device, an input device, an output device, an input / output device, a signal processing device, an electronic computer, or an electronic device may be a semiconductor device itself and may have a semiconductor device.

[0022] Hereinafter, the embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be easily understood by those skilled in the art that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments.

[0023] In this specification and the like, a configuration shown in each embodiment can be appropriately combined with a configuration shown in another embodiment to form one aspect of the present invention. In addition, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0024] In addition, in the drawings explaining the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, and the repeated description may be omitted. In addition, in the drawings, when the same functions are indicated, for example, the hatching patterns may be the same and no particular reference numerals may be attached. In addition, in the drawings, for example, in the perspective view or the top view (also called "plan view"), the illustration of some components may be omitted in order to make it easier to understand. In addition, in the drawings, for example, the illustration of some hidden lines may be omitted. In addition, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0025] Also, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Thus, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations of ideal examples, and are not limited to, for example, shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally thinned by a process such as etching, but these may not be reflected in the drawings to facilitate understanding. Also, for example, in an actual circuit operation, variations in voltage or current may occur due to noise or timing deviation, but these may not be reflected in the drawings to facilitate understanding.

[0026] In addition, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings are not limited to the explanations, and may be rephrased appropriately.

[0027] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, a distinguishing reference numeral such as "A", "b", "_1", "[n]", or "[m,n]" may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which a distinguishing reference numeral is added, or when it is not necessary to distinguish between them, the distinguishing reference numeral may not be added.

[0028] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow), etc. For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, etc. may be referred to as the "conductive state" or "on state". In addition, the "non-conductive state", "cut-off state", or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, etc. may be referred to as the "non-conductive state", "cut-off state", or "off state".

[0029] In addition, in this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the "gate voltage", the voltage between the drain and the source (drain-source) may be referred to as the "drain voltage", and the voltage between the backgate and the source (backgate-source) may be referred to as the "backgate voltage". In addition, the current flowing between the drain and the source may be referred to as the "drain current". In addition, in an n-channel transistor, descriptions such as "high gate voltage", "high drain voltage", and "high backgate voltage" may be appropriately interchangeable with descriptions such as "low gate voltage", "low drain voltage", and "low backgate voltage" in a p-channel transistor. In addition, descriptions such as "low gate voltage", "low drain voltage", and "low backgate voltage" in an n-channel transistor may be appropriately interchangeable with descriptions such as "high gate voltage", "high drain voltage", and "high backgate voltage" in a p-channel transistor.

[0030] In this specification, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification, the off-state current and the current flowing between the gate and the source and drain (also referred to as a gate leakage current) may also be referred to as leakage current.

[0031] (Embodiment 1) A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one embodiment of the present invention can be used for, for example, a memory device. The memory device includes a memory cell and a circuit for driving the memory cell. Another embodiment of the present invention is a method for driving the memory cell.

[0032] <Storage device configuration example 1> FIG. 1 is a circuit diagram illustrating a memory device of one embodiment of the present invention.

[0033] As shown in Fig. 1, the memory device 100 has a memory array 110 and a peripheral circuit 120. The memory array has a plurality of memory cells 111 arranged in a matrix. Note that Fig. 1 illustrates one memory cell 111 as a representative.

[0034] The memory cell 111 includes a transistor M11 and a capacitor C11. One of the source and drain of the transistor M11 is connected to one terminal of the capacitor C11. The other of the source and drain of the transistor M11 is connected to a wiring BL having a function as a bit line. The gate of the transistor M11 is connected to a wiring WL having a function as a word line. The other terminal of the capacitor C11 (sometimes called a plate terminal) is connected to a wiring PL having a function as a signal line. Note that a wiring in which one of the source and drain of the transistor M11 and one terminal of the capacitor C11 are connected to each other may be described as a wiring SN. Note that, as described later, after data is written to the memory cell 111, a potential corresponding to the data is held in the wiring SN. For this reason, the wiring may be called a holding node.

[0035] The peripheral circuit 120 includes a driver circuit 121 having a function of applying a data potential to the wiring BL, a driver circuit 122 having a function of applying a selection signal potential to the wiring WL, and a driver circuit 123 having a function of applying a control signal potential to the wiring PL. In other words, it can be said that the driver circuit 121 has a function of outputting a data potential, the driver circuit 122 has a function of outputting a selection signal potential, and the driver circuit 123 has a function of outputting a control signal potential.

[0036] Here, the control signal may have a first potential (corresponding to a potential Vp0 described later), a second potential (corresponding to a potential Vp1 described later), and a third potential (corresponding to a potential Vp2 described later). Furthermore, the timing at which the potential of the control signal changes from the first potential to the second potential may be linked to the timing at which the potential of the selection signal changes. Furthermore, the direction of the change from the first potential to the second potential may be opposite to the direction at which the potential of the selection signal changes. Furthermore, the timing at which the potential of the control signal changes from the first potential to the third potential may be linked to the timing at which the potential of the data changes. Furthermore, the direction of the change from the first potential to the third potential may be opposite to the direction at which the potential of the data changes.

[0037] In the memory cell 111, the transistor M11 is an n-channel transistor or a p-channel transistor. Here, the transistor M11 is described as an n-channel transistor. An n-channel transistor has a larger on-state current than a p-channel transistor. Therefore, the data read speed and data write speed of the memory cell 111 can be improved.

[0038] The transistor M11 may be, for example, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region. The semiconductor is not limited to a single element semiconductor (such as silicon or germanium) whose main component is a single element, but may be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0039] In addition, various types of transistors can be used as the transistor M11, such as a MOS field effect transistor, a junction field effect transistor, or a bipolar transistor.

[0040] In addition, transistors of various structures can be used as the transistor M11. For example, transistors of various structures can be used, such as a top-gate type (e.g., a planar type and a staggered type), a bottom-gate type (e.g., an inverted planar type and an inverted staggered type), a dual-gate type (a structure in which gates are arranged on both sides (e.g., above and below) of a channel formation region), a FIN type (fin type), a TRI-GATE type (tri-gate type), and a GAA type (gate-all-around type). In addition, for example, a vertical transistor (a transistor whose channel length direction is a vertical direction (also referred to as a height direction or a direction perpendicular to a surface on which the transistor is formed)) can be used.

[0041] In one embodiment of the present invention, an OS transistor (a transistor including an oxide semiconductor in a channel formation region) can be used as the transistor M11.

[0042] The OS transistor has a very small off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 -18 A) Below, 1zA(1×10 -21 A) or less, or 1yA (1×10 -24 In the case of a Si transistor (a transistor containing silicon in a channel formation region), the off-state current per 1 μm of channel width in a room temperature environment can be set to 1 fA (1×10 -15 A) or more and 1 pA (1 × 10 -12 A) or less. Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude smaller than the off-state current of a Si transistor. Therefore, for example, when a wiring connected to one of the source and drain of an OS transistor is floating, the charge accumulated in the wiring can be held for a long period of time. Therefore, for example, by forming a memory cell using an OS transistor, data written to the memory cell can be stored for a long period of time.

[0043] Moreover, the off-current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Moreover, the on-current of an OS transistor is unlikely to decrease even in a high-temperature environment. On the other hand, the on-current of a Si transistor decreases in a high-temperature environment. That is, the on-current of an OS transistor is larger than that of a Si transistor in a high-temperature environment. Furthermore, an OS transistor can perform a good switching operation because the ratio of the on-current to the off-current is large even in an environment of 125° C. or higher and 150° C. or lower. Thus, a semiconductor device using an OS transistor can operate stably and with high reliability even in a high-temperature environment.

[0044] In addition, the OS transistor has a high withstand voltage between the source and drain (also referred to as drain withstand voltage), so that a semiconductor device including the OS transistor can operate stably and have high reliability even when driven at high voltage.

[0045] Here, in the memory cell 111, a configuration in which an OS transistor is used as the access transistor (transistor M11) may be called DOSRAM (registered trademark). DOSRAM is an abbreviation for Dynamic Oxide Semiconductor RAM (Random Access Memory). DOSRAM can store data for a long period of time because it uses an OS transistor with an extremely small off-current. In other words, since data once written can be stored for a long period of time, the frequency of refreshing data can be reduced. In addition, since the electrostatic capacitance of the cell capacitance (C11) can be reduced, the cell size can be reduced. Therefore, by using DOSRAM, it is possible to reduce the power consumption and improve the recording density of a storage device having the DOSRAM.

[0046] A memory cell using an OS transistor can write or read data by charging or discharging an electric charge, so that data can be written or read substantially unlimited times. In addition, a memory cell using an OS transistor has excellent rewrite endurance because it does not involve structural changes at the atomic level, unlike, for example, a magnetic memory or a resistance change type memory. In addition, a memory cell using an OS transistor has excellent stability because instability due to an increase in electron trap centers, unlike a flash memory, is not observed even when data is repeatedly written.

[0047] In addition, memory cells using OS transistors can be freely arranged on, for example, a silicon substrate on which Si transistors are provided, and therefore can be easily integrated. In addition, memory cells using OS transistors can be manufactured at low cost because the same manufacturing equipment as that for Si transistors can be used to manufacture the OS transistors.

[0048] In addition, since memory cells using OS transistors can be monolithically stacked in multiple memory cells, it is possible to improve the recording density, bandwidth, and access latency of a storage device using the memory cells.

[0049] In one embodiment of the present invention, a vertical transistor can be used as the transistor M11 in the memory cell 111. This can reduce the layout area of ​​the memory cell 111. That is, the storage density of a storage device including the memory cell 111 can be improved.

[0050] Furthermore, the transistor M11 can be stacked on the capacitive element C11 and arranged to have an overlapping area, thereby further reducing the layout area of ​​the memory cell 111. That is, the storage density of the storage device having the memory cell 111 can be further improved.

[0051] In the memory cell 111, a configuration example in which the transistor M11 is stacked on the capacitor C11 and a vertical transistor is used as the transistor M11 will be described in Embodiment 2 to be described later.

[0052] Various transistors can be used as transistors included in the peripheral circuit 120. For example, n-channel transistors, p-channel transistors, or both may be used. For example, OS transistors, Si transistors, or both may be used. For example, planar transistors, vertical transistors, or both may be used. Note that a configuration example of the driver circuit 123 included in the peripheral circuit 120 of one embodiment of the present invention will be described later.

[0053] [Example 1] 2A, 2B, and 3A to 3F are a timing chart and a circuit diagram illustrating an example of a method for driving the memory cell 111. The timing chart shown in Fig. 2A illustrates an example of an operation in which data "0" is written to the memory cell 111 in which data "1" is stored, and the data "0" is stored.

[0054] In the following description, the potential corresponding to the binary data applied to the wiring BL is a high power supply potential VDD (sometimes simply referred to as VDD) for the binary data "1," and a low power supply potential VSS (sometimes simply referred to as VSS) for the binary data "0."

[0055] The potential of the signal applied to the wiring WL is either a potential H (sometimes simply referred to as H) that can turn on the transistor M11, or a potential L (sometimes simply referred to as L) that can turn off the transistor M11.

[0056] In this operation example, the case where an n-channel transistor is used as the transistor M11 is described. When a p-channel transistor is used as the transistor M11, the description regarding the magnitude relationship of voltages and potentials may be appropriately rewritten. For example, "the voltage is large" may be appropriately rewritten as "the voltage is small", and "the voltage is small" may be appropriately rewritten as "the voltage is large". Also, for example, "raising the potential" may be appropriately rewritten as "lowering the potential", and "lowering the potential" may be appropriately rewritten as "raising the potential".

[0057] Here, assuming that the threshold voltage of the transistor M11 is Vth, in the operation of the memory cell 111, in order for the transistor M11 to be in the on state, the minimum gate voltage in the on state can be determined to be greater than the threshold voltage (that is, "H - VDD > Vth") so that the potential H can be determined. Also, in order for the transistor M11 to be in the off state, the potential L can be determined so that the maximum gate voltage in the off state is less than the threshold voltage (that is, "L - VSS < Vth").

[0058] Also, the potential of the signal applied to the wiring PL is either the potential Vp0 or a potential Vp1 greater than the potential Vp0.

[0059] In the description of the operation, when the potential changes, for example, due to loads (parasitic capacitance and parasitic resistance) such as wiring, there may be rise time and fall time. Also, for example, even if it is shown that two different operations are at the same timing, it does not necessarily mean that they are exactly at the same timing. For example, even if there is a slight time difference due to signal delay in the wiring, etc., it may be regarded as being at the same timing.

[0060] Also, in the timing chart, for the sake of easy understanding of the explanation, even if each period is illustrated with the same length on the drawing, the time lengths of each period may be different.

[0061] 2A shows states of potentials applied to the wirings WL, BL, and PL in each period of operation, changes in the potential of the wiring SN, and changes in the gate voltage (also referred to as Vgs) of the transistor M11.

[0062] 3A to 3F also show the potentials of the wirings WL, BL, PL, and SN at each time point during operation. The gate voltage Vgs of the transistor M11 is shown by an arrow. In this case, a symbol indicating a potential, such as "VDD" or "VSS" (also called a potential symbol), may be enclosed next to each wiring.

[0063] In a period T11, a potential H is applied to the wiring WL, and a potential Vp0 is applied to the wiring PL. As an example, a potential "VDD" corresponding to "1" is applied to the wiring BL, and the potential of the wiring SN of the memory cell 111 is also "VDD". At this time, the gate voltage Vgs of the transistor M11 is "H-VDD", and the transistor M11 is on. This corresponds to a state after data "1" is read from and written back to the memory cell 111. The potentials of the wirings at this time are shown in FIG. 3(A). In the following description, unless otherwise specified, the previous state is maintained.

[0064] In a period T12, "VSS" corresponding to "0" is applied to the wiring BL. Then, the potential of the wiring SN gradually decreases to "VSS" through the transistor M11. That is, data "0" is written to the memory cell 111. At this time, the gate voltage Vgs of the transistor M11 becomes "H-VSS". The potentials of the wirings at this time are shown in FIG. 3B.

[0065] In a period T13, a potential L is applied to the wiring WL. Then, the gate voltage Vgs of the transistor M11 becomes "L-VSS", and the transistor M11 is turned off. That is, writing of data "0" to the memory cell 111 is completed, and "VSS" corresponding to data "0" is held in the wiring SN. The potentials of the wirings at this time are shown in FIG. 3C.

[0066] In a period T14, an intermediate potential Vpre between the potentials VDD and VSS is applied to the wiring BL. That is, the wiring BL is precharged to the intermediate potential Vpre. Then, the potential of the wiring SN becomes lower than the potential of the wiring BL, and the wiring SN functions as the source of the transistor M11. Since "VSS" is held in the wiring SN, the gate voltage Vgs of the transistor M11 remains at "L-VSS". The potentials of the wirings at this time are shown in FIG. 3(D). Note that the wiring BL may be precharged to "VDD".

[0067] In period T15, a potential Vp1 is applied to the wiring PL. That is, the potential of the wiring PL rises from the potential Vp0 to the potential Vp1. Then, the potential of the wiring SN also rises due to the capacitive coupling of the capacitor C11. At this time, if the potential of the wiring SN rises by "vp", the potential of the wiring SN becomes "VSS+vp", and the gate voltage Vgs of the transistor M11 becomes "L-(VSS+vp)". That is, the gate voltage Vgs of the transistor M11 becomes smaller by "vp". The potentials of the wirings at this time are shown in FIG. 3(E).

[0068] Thereafter, the state in which the potential of the wiring SN is "VSS+vp" is maintained.

[0069] In the period T16, a potential Vp0 is applied to the wiring PL. That is, the potential of the wiring PL drops from the potential Vp1 to the potential Vp0. Then, the potential of the wiring SN also drops by "vp" due to the capacitive coupling of the capacitor C11. At this time, the potential of the wiring SN becomes "VSS", and the gate voltage Vgs of the transistor M11 becomes "L-VSS". That is, the potential of the wiring SN returns to the state after data is written to the memory cell 111 (corresponding to the periods T13 and T14). The period T16 corresponds to, for example, the state before data is read from the memory cell 111. The potentials of the wirings at this time are shown in FIG. 3(F).

[0070] Here, the transistor M11 has a region (also called a subthreshold region) where the off-current (meaning the drain current in an off state where the gate voltage is lower than the threshold voltage) changes exponentially with respect to the gate voltage. That is, in the transistor M11 in an off state, the smaller the gate voltage Vgs is, the smaller the off-current is.

[0071] Therefore, when the transistor M11 is turned off after data is written to the memory cell 111, the smaller the gate voltage Vgs of the transistor M11 is, the longer it is possible to hold the potential of the wiring SN corresponding to the written data.

[0072] In one embodiment of the present invention, the memory cell 111 is operated as in the above-described period T15 (i.e., the potential of the selection signal applied to the wiring WL is lowered and then the potential applied to the wiring PL is increased), so that the gate voltage Vgs of the transistor M11 in an off state can be reduced. As a result, the potential of the wiring SN corresponding to data written to the memory cell 111 can be held for a long period of time. Thus, a memory device capable of storing data for a long period of time can be realized. For example, power consumption can be reduced by reducing the frequency of refreshing data.

[0073] In other words, as one embodiment of the present invention, the driver circuit 123 can have a function of outputting a signal whose potential changes in a direction opposite to the direction in which the potential of the selection signal applied to the wiring WL changes. In this case, the timing at which the potential of the signal output from the driver circuit 123 changes may be linked to the timing at which the potential of the selection signal changes. In other words, for example, the potential of the signal output from the driver circuit 123 may increase after the potential of the selection signal decreases.

[0074] Note that an OS transistor may be used as the transistor M11 of the memory cell 111. An OS transistor has a characteristic that it operates in a subthreshold region with a wider range of gate voltage Vgs than a Si transistor. Therefore, by reducing the gate voltage Vgs, the off-current can be made smaller than that of a Si transistor. For example, by making the gate voltage Vgs smaller than 0 V, the off-current can be made extremely small. That is, in the memory cell 111 using an OS transistor as the transistor M11, the potential of the wiring SN can be held for a longer period of time as the gate voltage Vgs is made smaller.

[0075] Therefore, for example, in the above-described period T15, the increase in the potential of the wiring SN, "vp", may be increased. This reduces the gate voltage Vgs, and the off-current can be reduced. For example, by increasing "vp", the gate voltage Vgs may be reduced to less than 0 V. This can significantly reduce the off-current of the transistor M11, and the potential of the wiring SN can be held for a long period of time.

[0076] Here, "vp" in the above-mentioned period T15 is "(Vp1-Vp0) x capacitance of the capacitance element C11 / (capacitance of the capacitance element C11 + parasitic capacitance of the wiring SN)".

[0077] Therefore, for example, the larger the capacitance of the capacitive element C11, the larger the "vp" becomes, and the smaller the gate voltage Vgs of the transistor M11 becomes. In other words, it can be said that the larger the capacitance of the capacitive element C11, the longer it can hold the potential of the wiring SN.

[0078] For this purpose, for example, the capacitance of the capacitive element C11 may be made larger than the capacitance between the gate (corresponding to the wiring WL) and one of the source or drain (corresponding to the wiring SN) of the transistor M11. Also, for example, the film thickness of the insulator functioning as the dielectric of the capacitive element C11 may be made thinner than the film thickness of the insulator functioning as the gate insulating film of the transistor M11. Also, for example, the relative dielectric constant of the insulator functioning as the dielectric of the capacitive element C11 may be made larger than the relative dielectric constant of the insulator functioning as the gate insulating film of the transistor M11.

[0079] Also, for example, the larger the change in the potential of the wiring PL (i.e., "Vp1-Vp0"), the larger "vp" becomes, and the smaller the gate voltage Vgs of the transistor M11 becomes. In other words, it can be said that the larger the change in the potential of the wiring PL, the longer the potential of the wiring SN can be maintained.

[0080] For this purpose, for example, the change in the potential of the wiring PL may be made larger than the change in the potential of the selection signal provided to the wiring WL (i.e., "HL"). Note that, in order to suppress an increase in power consumption due to the change in the potential of the wiring PL, the change in the potential of the wiring PL may be made smaller than the change in the potential of the selection signal.

[0081] Although an example of operation has been described here in which data "0" is written to the memory cell 111 that holds data "1" and the data "0" is held, the same applies to the case in which data "0" is written to the memory cell 111 that holds data "0". Also, the same applies to the case in which data "1" is written to the memory cell 111 that holds data "0" or "1" and the data "1" is held.

[0082] The timing chart shown in FIG. 2(B) is an example of an operation of writing "1" data into the memory cell 111 in which "0" data is held and holding the "1" data, and shows the states of the potentials applied to each of the wiring WL, the wiring BL, and the wiring PL in each period of the operation. Note that illustration of the change in the potential of the wiring SN and the change in the gate voltage Vgs of the transistor M11 are omitted. In this case, in the period T12 for writing "1" data, the potential of the wiring SN gradually rises from "VSS" to "VDD", and the gate voltage Vgs of the transistor M11 gradually drops from "H-VSS" to "H-VDD". Also, after writing "1" data, the potential of the wiring SN becomes "VDD" in the periods T13 and T14, and the gate voltage Vgs of the transistor M11 becomes "L-VDD". Further, the potential of the wiring SN becomes "VDD+vp" in the period T15, and the gate voltage Vgs of the transistor M11 becomes "L-(VDD+vp)". Also, the potential of the wiring SN becomes "VDD" in the period T16, and the gate voltage Vgs of the transistor M11 becomes "L-VDD".

[0083] That is, the gate voltage Vgs of the transistor M11 in the off state is smaller when holding "1" data than when holding "0" data. Therefore, if "0" data can be held for a long period by the operation example as described above, it can be said that "1" data can also be held for a long period.

[0084] One aspect of the present invention may be able to achieve, for example, low power consumption by operating the memory cell 111 as in the above-described period T15. That is, in the operation of the memory cell 111, from the viewpoint of low power consumption, it is preferable to reduce the amplitude of the signal in the peripheral circuit 120. For example, it is preferable to reduce the amplitude of the signal applied to the wiring WL (that is, "H-L"). For this purpose, for example, the potential L may be increased. However, by increasing the potential L, the gate voltage Vgs of the off-state transistor M11 in the periods T13 and T14 may not become sufficiently small, and it may be difficult to hold the potential of the wiring SN for a long time due to the off-current. Therefore, by operating as in the period T15, the gate voltage Vgs of the off-state transistor M11 can be reduced, and thus it may be possible to hold the potential of the wiring SN for a long time. Here, since the dynamic power consumption in the peripheral circuit 120 is proportional to the square of the amplitude of the signal, it can be said that the decrease in power consumption due to the reduction in the amplitude of the signal is larger than the increase in power consumption due to the addition of the drive circuit 123. Therefore, it may be possible to realize a storage device capable of long-term storage while achieving low power consumption. For example, low power consumption can be achieved by reducing the data refresh frequency.

[0085] In addition, in one embodiment of the present invention, by operating the memory cell 111 as in the above-described period T15, for example, a transistor used in the peripheral circuit 120 may be miniaturized. For example, a transistor used in the driver circuit 122 having a function of generating a signal supplied to the wiring WL may be miniaturized. Here, as a transistor is miniaturized, a voltage range of a circuit using the transistor is reduced, so that, for example, the amplitude (i.e., "HL") of a signal supplied to the wiring WL may be reduced. That is, for example, the potential L may be increased. However, by increasing the potential L, the gate voltage Vgs of the transistor M11 in an off state in the periods T13 and T14 may not be sufficiently reduced, and it may be difficult to hold the potential of the wiring SN for a long period of time due to off-state current. Therefore, by operating the memory cell 111 as in the period T15, the gate voltage Vgs of the transistor M11 in an off state can be reduced, so that the potential of the wiring SN may be held for a long period of time. Thus, a memory device capable of storing data for a long period of time may be realized while miniaturizing the transistors used in the peripheral circuit 120 to achieve miniaturization. For example, power consumption can be reduced by reducing the frequency of refreshing data.

[0086] [Example 2] 4(A), 4(B), and 5(A) to 5(D) are a timing chart and a circuit diagram illustrating an example of a method for driving the memory cell 111. The timing chart shown in Fig. 4(A) is an operation example in which data "1" is written to the memory cell 111 in which data "0" is stored, and the data "1" is stored.

[0087] In the following description, the description of the above-mentioned Operation Example 1 can be referred to as appropriate.

[0088] The potential of the signal applied to the wiring PL is either a potential Vp0 or a potential Vp2 which is lower than the potential Vp0.

[0089] In a period T21, a potential H is applied to the wiring WL, and a potential Vp0 is applied to the wiring PL. As an example, the wiring BL is applied with "VSS" corresponding to "0", and the potential of the wiring SN of the memory cell 111 is also "VSS". At this time, the gate voltage Vgs of the transistor M11 is "H-VSS", and the transistor M11 is in an on state. This corresponds to a state after reading and writing back data of "0" from the memory cell 111. The potentials of the wirings at this time are shown in FIG. 5(A). In the following description, unless otherwise specified, the previous state is maintained.

[0090] In period T22, "VDD" corresponding to "1" is applied to the wiring BL. At this time, a pulse of potential Vp2 is applied to the wiring PL. That is, at the same time that "VDD" is applied to the wiring BL, the potential of the wiring PL drops from potential Vp0 to potential Vp2, and then rises from potential Vp2 to potential Vp0. Then, through the operation described below, the potential of the wiring SN gradually rises to "VDD". That is, data "1" is written to the memory cell 111.

[0091] When the potential of the wiring PL drops from potential Vp0 to potential Vp2, the potential of the wiring SN drops due to capacitive coupling of the capacitor C11. At this time, if the potential of the wiring SN drops by "vp", the potential of the wiring SN becomes "VSS-vp", and the gate voltage Vgs of the transistor M11 becomes "H-(VSS-vp)". In other words, the gate voltage Vgs of the transistor M11 increases by "vp". The potentials of the wirings at this time are shown in FIG. 5B.

[0092] In this way, the on-state current of the transistor M11 can be instantaneously increased by instantaneously increasing the gate voltage Vgs at the same time that “VDD” is applied to the wiring BL, thereby increasing the rate at which the potential of the wiring SN gradually increases.

[0093] Thereafter, when the potential of the wiring PL rises from the potential Vp2 to the potential Vp0, the potential of the wiring SN rises due to the capacitive coupling of the capacitive element C11, thereby shortening the time until the potential of the wiring SN reaches "VDD".

[0094] Finally, the potential of the wiring SN becomes “VDD,” and the gate voltage Vgs of the transistor M11 becomes “H-VDD.” The potentials of the wirings at this time are shown in FIG.

[0095] In period T23, a potential L is applied to the wiring WL. Then, the gate voltage Vgs of the transistor M11 becomes "L-VDD", and the transistor M11 is turned off. That is, writing of data "1" to the memory cell 111 is completed, and "VDD" corresponding to the data "1" is held in the wiring SN. The potentials of the wirings at this time are shown in FIG. 5(D).

[0096] In one embodiment of the present invention, by operating the memory cell 111 as in the above-described period T22 (i.e., by lowering the potential applied to the wiring PL in synchronization with the timing of increasing the potential of data applied to the wiring BL), the rate at which the potential of the wiring SN gradually increases can be increased and the time required to reach "VDD" can be shortened when writing data "1" to the memory cell 111. That is, the speed at which data is written to the memory cell 111 can be improved. Furthermore, because the potential reaches "VDD" even if the speed at which data is written is increased, the speed at which data is read can also be improved. Thus, a memory device capable of increasing the operating speed can be realized.

[0097] That is, as one embodiment of the present invention, the driver circuit 123 can have a function of outputting a signal whose potential changes in a direction opposite to the direction in which the potential of data applied to the wiring BL changes. In this case, the timing at which the potential of the signal output from the driver circuit 123 changes may be linked to the timing at which the potential of the data changes. In other words, for example, the potential of the signal output from the driver circuit may decrease in synchronization with the timing at which the potential of the data increases.

[0098] Here, "vp" in the above-mentioned period T22 is "(Vp0-Vp2) x capacitance of the capacitance element C11 / (capacitance of the capacitance element C11+parasitic capacitance of the wiring SN)".

[0099] Therefore, for example, it can be said that the larger the change in the potential of the wiring PL (that is, "Vp0-Vp2") is, the larger "vp" is, and the speed at which data is written to the memory cell 111 can be increased.

[0100] For this purpose, for example, the change in the potential of the wiring PL may be made larger than the change in the potential of the data applied to the wiring BL (i.e., "VDD-VSS"). Note that, in order to suppress an increase in power consumption due to the change in the potential of the wiring PL, the change in the potential of the wiring PL may be made smaller than the change in the potential of the data.

[0101] Note that, here, an example of operation has been described in which data "1" is written to memory cell 111 that holds data "0" and the data "1" is held. However, in other cases, it is preferable not to apply an operation such as that of period T22 described above.

[0102] For example, when data "0" is written to the memory cell 111 in which data "0" is stored, the potential held in the wiring SN remains at "VSS". Also, when data "1" is written to the memory cell 111 in which data "1" is stored, the potential held in the wiring SN remains at "VDD". In such a case, it is preferable not to change the potential of the wiring PL in order to prevent the potential of the wiring SN from changing when the potential of the wiring PL is changed.

[0103] For example, when data "0" is written to the memory cell 111 in which data "1" is stored, the potential of the wiring SN gradually decreases until it reaches "VSS" in the period T22. In such a case, the potential of the wiring PL increases from the potential Vp2 to the potential Vp0, which increases the potential of the wiring SN, and therefore the effect of shortening the time it takes for the potential of the wiring SN to reach "VSS" cannot be obtained. For this reason, it is preferable not to change the potential of the wiring PL.

[0104] The timing chart shown in FIG. 4B is an example of an operation in which data “0” is written to the memory cell 111 in which data “1” is stored and the data “0” is stored, and shows the states of potentials applied to the wiring WL, wiring BL, and wiring PL in each period of the operation. Note that the illustration of the change in the potential of the wiring SN and the change in the gate voltage Vgs of the transistor M11 is omitted. In this case, in the period T22 in which data “0” is written, the potential of the wiring SN gradually drops from “VDD” to “VSS”, and the gate voltage Vgs of the transistor M11 gradually rises from “H-VDD” to “H-VSS”. At this time, since the potential of the wiring PL does not change, the potential of the wiring SN does not change due to the capacitive coupling of the capacitance element C11. After the data “0” is written, the potential of the wiring SN in the period T23 becomes “VSS”, and the gate voltage Vgs of the transistor M11 becomes “L-VSS”.

[0105] In one embodiment of the present invention, for example, low power consumption can be achieved by operating the memory cell 111 as in the above-described period T22. That is, in terms of low power consumption, it is preferable to reduce the amplitude of a signal in the peripheral circuit 120 in the operation of the memory cell 111, for example, to reduce the amplitude of a signal provided to the wiring WL (i.e., "HL"). For this purpose, for example, the potential H may be reduced. However, by reducing the potential H, the gate voltage Vgs of the transistor M11 in an on state may not be sufficiently large, the on-state current may be reduced, and the speed at which data is written to the memory cell 111 may decrease. Thus, by operating the memory cell 111 as in the period T22, it is possible to improve the write speed and the read speed. Here, since the dynamic power consumption in the peripheral circuit 120 is proportional to the square of the signal amplitude, it can be said that the decrease in power consumption caused by reducing the signal amplitude is larger than the increase in power consumption caused by adding the driver circuit 123. Therefore, it may be possible to realize a memory device that can increase the operating speed while achieving low power consumption. Alternatively, it may be possible to realize a memory device that can suppress a decrease in the operating speed while achieving low power consumption.

[0106] In addition, in one embodiment of the present invention, by operating the memory cell 111 as in the above-described period T22, for example, a transistor used in the peripheral circuit 120 can be miniaturized. For example, a transistor used in the driver circuit 122 having a function of generating a signal supplied to the wiring WL can be miniaturized. Here, as a transistor is miniaturized, a voltage range of a circuit using the transistor is reduced, so that, for example, the amplitude of a signal supplied to the wiring WL (that is, "HL") may be reduced. That is, for example, the potential H may be reduced. However, by reducing the potential H, the gate voltage Vgs of the transistor M11 in an on state may not be sufficiently large, and the on-state current may be reduced, so that the speed at which data is written to the memory cell 111 may decrease. Thus, by operating the memory cell as in the period T22, the write speed and the read speed may be improved. Thus, a memory device that can be miniaturized by miniaturizing a transistor used in the peripheral circuit 120 and can increase the operating speed may be realized. Alternatively, a memory device that can be miniaturized and can suppress a decrease in the operating speed may be realized.

[0107] [Operation example 3] 6A and 6B are timing charts illustrating an example of a method for driving the memory cell 111 of one embodiment of the present invention. The timing charts in each of FIGS. 6A and 6B are operation examples that combine the above-described Operation Example 1 and Operation Example 2. Therefore, the above description can be referred to, and detailed description thereof will be omitted here.

[0108] The timing chart shown in Fig. 6(A) is an example of an operation in which data "1" is written to the memory cell 111 in which data "0" is stored and the data "1" is stored, and is a combination of the timing chart shown in Fig. 2(B) and the timing chart shown in Fig. 4(A). The timing chart shown in Fig. 6(B) is an example of an operation in which data "0" is written to the memory cell 111 in which data "1" is stored and the data "0" is stored, and is a combination of the timing chart shown in Fig. 2(A) and the timing chart shown in Fig. 4(B).

[0109] In one embodiment of the present invention, a memory device capable of increasing the operating speed and storing data for a long period of time while achieving low power consumption and miniaturization can be realized by operating the memory cell 111 as shown in the timing charts in Figures 6(A) and 6(B). For example, low power consumption can be achieved by reducing the frequency of refreshing data.

[0110] [Drive circuit 123] 7A and 7B are circuit diagrams showing configuration examples that can be applied to the driver circuit 123. FIG.

[0111] 7A includes a transistor M2a and a transistor M2b. One of the source and the drain of the transistor M2a is connected to the wiring PL, the other of the source and the drain is connected to the wiring PLa, and the gate is connected to the wiring SEa. One of the source and the drain of the transistor M2b is connected to the wiring PL, the other of the source and the drain is connected to the wiring PLb, and the gate is connected to the wiring SEb.

[0112] 7A has a function of supplying the potential of one of the wirings PLa and PLb to the wiring PL. That is, in the driver circuit 123 shown in FIG 7A, one of the transistors M2a and M2b is turned on and the other is turned off, so that the potential of one of the wirings PLa and PLb is supplied to the wiring PL.

[0113] 7A is applied to the memory device 100, and a potential Vp1 is applied to the wiring PLa and a potential Vp0 is applied to the wiring PLb, so that the memory cell 111 can operate as in the above-described Operation Example 1. Also, for example, by applying the driver circuit 123 shown in FIG. 7A to the memory device 100, and a potential Vp2 is applied to the wiring PLa and a potential Vp0 is applied to the wiring PLb, the memory cell 111 can operate as in the above-described Operation Example 2.

[0114] 7B includes a transistor M2c in addition to the components of the driver circuit 123 shown in Fig. 7A. One of the source and the drain of the transistor M2c is connected to the wiring PL, the other of the source and the drain is connected to the wiring PLc, and the gate is connected to the wiring SEc.

[0115] 7B has a function of supplying the potential of any one of the wirings PLa to PLc to the wiring PL. That is, in the driver circuit 123 shown in FIG. 7B, the potential of any one of the wirings PLa to PLc is supplied to the wiring PL by turning on any one of the transistors M2a to M2c and turning off the others.

[0116] For example, in the memory device 100, the driver circuit 123 shown in FIG. 7B can be applied to apply a potential Vp1 to the wiring PLa, a potential Vp0 to the wiring PLb, and a potential Vp2 to the wiring PLc, so that the memory cell 111 can operate as in the above-described operation example 3.

[0117] 7A and 7B are merely examples of the driver circuit 123, and the present invention is not limited to the configuration thereof. Here, an example of a configuration using n-channel transistors is shown, but p-channel transistors or CMOS circuits may be used.

[0118] <Storage device configuration example 2> Next, a description will be given of the connection relationship between the memory cells 111 arranged in a matrix and the driving circuits 123. For ease of explanation, a case in which four memory cells 111 are arranged in a matrix of 2 rows and 2 columns will be described as an example.

[0119] [Connection example 1] FIG. 8 is a circuit diagram illustrating an example of the connection relationship between four memory cells 111 arranged in a matrix of 2 rows and 2 columns and two drive circuits 123. As shown in FIG.

[0120] 8 illustrates a memory cell 111[1,1] arranged in the first row and first column, a memory cell 111[1,2] arranged in the first row and second column, a memory cell 111[2,1] arranged in the second row and first column, and a memory cell 111[2,2] arranged in the second row and second column in the memory array 110. Also illustrated are a driving circuit 123[1] arranged in the first row and a driving circuit 123[2] arranged in the second row in the peripheral circuit 120. Note that FIG. 8 omits the illustration of the driving circuit 121[1] arranged in the first column, the driving circuit 121[2] arranged in the second column, the driving circuit 122[1] arranged in the first row, and the driving circuit 122[2] arranged in the second row.

[0121] The wiring PL[1] arranged in the first row is connected to the memory cells 111[1,1] and 111[1,2], and the driver circuit 123[1]. The wiring PL[2] arranged in the second row is connected to the memory cells 111[2,1] and 111[2,2], and the driver circuit 123[2]. The wiring BL[1] arranged in the first column is connected to the memory cells 111[1,1] and 111[2,1], and the driver circuit 121[1]. The wiring BL[2] arranged in the second column is connected to the memory cells 111[1,2] and 111[2,2], and the driver circuit 121[2]. The wiring WL[1] arranged in the first row is connected to the memory cells 111[1,1] and 111[1,2], and the driver circuit 122[1]. The wiring WL[2] arranged in the second row is connected to the memory cells 111[2,1] and 111[2,2] and the driver circuit 122[2].

[0122] FIG. 9 is a timing chart for explaining an example of a method for driving the four memory cells 111 shown in FIG. 8. Here, the first row is selected, data of “1” is written to the memory cell 111[1,1] in which data of “0” is stored, data of “0” is written to the memory cell 111[1,2] in which data of “1” is stored, and each data is stored. The above-mentioned operation example 1 is applied as a method for driving each memory cell 111. The configuration shown in FIG. 8 is suitable for applying the above-mentioned operation example 1 as a method for driving the memory cells 111, since the wiring PL is connected to the drive circuit 123 for each memory cell 111 arranged in each row. The explanation of the above-mentioned operation example 1 can be appropriately referred to.

[0123] The period T1a is a period during which data is held in the four memory cells 111. At this time, the wirings WL[1] and WL[2] are at the potential L, the wirings BL[1] and BL[2] are at an intermediate potential between the potentials VDD and VSS, and the wirings PL[1] and PL[2] are at the potential Vp1.

[0124] The period T1b is a period immediately before the start of reading and writing back data from and to the memory cells 111 in the first row, and corresponds to the period T16. Here, the potential of the wiring PL[1] is lowered from the potential Vp1 to the potential Vp0.

[0125] The period T1c is a period immediately after the start of reading and writing back data from and to the memory cells 111 in the first row. Here, a potential H is applied to the wiring WL[1]. At this time, the potential of the wiring BL[1] drops from the intermediate potential, and the potential of the wiring BL[2] rises from the intermediate potential. This change is amplified by a sense amplifier, thereby reading out the data. Note that since the potential held in the memory cells 111 changes due to the reading out of data (i.e., because of destructive reading), the data is then written back.

[0126] The period T1d is a period immediately after the end of reading and writing back data from and to the memory cells 111 in the first row, and corresponds to the period T11.

[0127] Period T1e is a period during which data is written to the memory cell 111[1,1], and corresponds to period T12.

[0128] The period T1f is a period during which data is written to the memory cell 111[1,2], and corresponds to the period T12.

[0129] A period T1g is a period immediately after writing of data to the memory cells 111 in the first row is completed, and corresponds to the period T13. Here, a potential L is applied to the wiring WL[1].

[0130] The period T1h is a period in which the wirings BL[1] and BL[2] are precharged to the intermediate potential Vpre, and corresponds to the period T14.

[0131] The period T1i is a period during which the potential of the wiring PL[1] is increased in order to hold the data written in the memory cells 111 in the first row for a long period, and corresponds to the period T15. Here, the potential of the wiring PL[1] is increased from the potential Vp0 to the potential Vp1.

[0132] In this way, when a plurality of memory cells 111 arranged in a matrix are connected to a plurality of driving circuits 123 as shown in Fig. 8, data written in the memory cells 111 can be held for a long period of time by applying a driving method as shown in Fig. 9. Thus, a storage device capable of storing data for a long period of time can be realized. For example, power consumption can be reduced by reducing the frequency of refreshing data.

[0133] [Connection example 2] FIG. 10 is a circuit diagram illustrating another example of the connection relationship between four memory cells 111 arranged in a matrix of 2 rows and 2 columns and two drive circuits 123. In FIG.

[0134] 10 illustrates a memory cell 111[1,1] arranged in the first row and first column, a memory cell 111[1,2] arranged in the first row and second column, a memory cell 111[2,1] arranged in the second row and first column, and a memory cell 111[2,2] arranged in the second row and second column in the memory array 110. Also illustrated are a driving circuit 123[1] arranged in the first column and a driving circuit 123[2] arranged in the second column in the peripheral circuit 120. Note that FIG. 10 omits the illustration of the driving circuit 121[1] arranged in the first column, the driving circuit 121[2] arranged in the second column, the driving circuit 122[1] arranged in the first row, and the driving circuit 122[2] arranged in the second row.

[0135] The wiring PL[1] arranged in the first column is connected to the memory cell 111[1,1], the memory cell 111[2,1], and the driver circuit 123[1]. The wiring PL[2] arranged in the second column is connected to the memory cell 111[1,2], the memory cell 111[2,2], and the driver circuit 123[2]. The wiring BL[1] arranged in the first column is connected to the memory cell 111[1,1], the memory cell 111[2,1], and the driver circuit 121[1]. The wiring BL[2] arranged in the second column is connected to the memory cell 111[1,2], the memory cell 111[2,2], and the driver circuit 121[2]. The wiring WL[1] arranged in the first row is connected to the memory cell 111[1,1], the memory cell 111[1,2], and the driver circuit 122[1]. The wiring WL[2] arranged in the second row is connected to the memory cells 111[2,1] and 111[2,2] and the driver circuit 122[2].

[0136] FIG. 11 is a timing chart for explaining an example of a method for driving the four memory cells 111 shown in FIG. 10. Here, the first row is selected, data of “1” is written to the memory cell 111[1,1] in which data of “0” is stored, data of “0” is written to the memory cell 111[1,2] in which data of “1” is stored, and each data is stored. The above-mentioned operation example 2 is applied as a method for driving each memory cell 111. The configuration shown in FIG. 10 is suitable for applying the above-mentioned operation example 2 as a method for driving the memory cells 111, since the wiring PL is connected to the drive circuit 123 for each memory cell 111 arranged in each column. The explanation of the above-mentioned operation example 2 can be appropriately referred to.

[0137] The period T2b is a period during which data is held in the four memory cells 111. At this time, the wirings WL[1] and WL[2] are at the potential L, the wirings BL[1] and BL[2] are at an intermediate potential between the potentials VDD and VSS, and the wirings PL[1] and PL[2] are at the potential Vp0.

[0138] The periods T2c, T2d, T2g, and T2h are similar to the above-mentioned periods T1c, T1d, T1g, and T1h, respectively.

[0139] The period T2e is a period during which data is written to the memory cell 111[1,1], and corresponds to the period T22. Here, a pulse of a potential Vp2 is applied to the wiring PL[1] in order to write data “1” to the memory cell 111[1,1] that holds data “0”.

[0140] The period T2f is a period during which data is written to the memory cell 111[1,2], and corresponds to the period T22. Here, in order to write data “0” to the memory cell 111[1,2] in which data “1” is stored, the potential of the wiring PL[2] is not changed.

[0141] In this way, when a plurality of memory cells 111 arranged in a matrix and a plurality of driving circuits 123 are connected as shown in Fig. 10, the speed at which data is written to the memory cells 111 can be improved by applying a driving method as shown in Fig. 11. In addition, since the voltage reaches "VDD" even if the data writing speed is increased, the data reading speed can also be improved. Thus, a memory device capable of increasing the operating speed can be realized.

[0142] [Connection example 3] FIG. 12 is a circuit diagram illustrating an example of the connection relationship between four memory cells 111 arranged in a matrix of 2 rows and 2 columns and four driving circuits 123 arranged in a matrix of 2 rows and 2 columns.

[0143] 12 illustrates the memory cell 111[1,1] arranged in the first row and first column, the memory cell 111[1,2] arranged in the first row and second column, the memory cell 111[2,1] arranged in the second row and first column, and the memory cell 111[2,2] arranged in the second row and second column in the memory array 110. Also, in the peripheral circuit 120, the driving circuit 123[1,1] arranged in the first row and first column, the driving circuit 123[1,2] arranged in the first row and second column, the driving circuit 123[2,1] arranged in the second row and first column, and the driving circuit 123[2,2] arranged in the second row and second column are illustrated. Note that in FIG. 12, the driving circuit 121[1] arranged in the first column, the driving circuit 121[2] arranged in the second column, the driving circuit 122[1] arranged in the first row, and the driving circuit 122[2] arranged in the second row are omitted from the illustration.

[0144] The wiring PL[1,1] arranged in the first row and first column is connected to the memory cell 111[1,1] and the driving circuit 123[1,1]. The wiring PL[1,2] arranged in the first row and second column is connected to the memory cell 111[1,2] and the driving circuit 123[1,2]. The wiring PL[2,1] arranged in the second row and first column is connected to the memory cell 111[2,1] and the driving circuit 123[2,1]. The wiring PL[2,2] arranged in the second row and second column is connected to the memory cell 111[2,2] and the driving circuit 123[2,2]. The wiring BL[1] arranged in the first column is connected to the memory cell 111[1,1], the memory cell 111[2,1], and the driving circuit 121[1]. The wiring BL[2] arranged in the second column is connected to the memory cells 111[1,2] and 111[2,2], and the driver circuit 121[2]. The wiring WL[1] arranged in the first row is connected to the memory cells 111[1,1] and 111[1,2], and the driver circuit 122[1]. The wiring WL[2] arranged in the second row is connected to the memory cells 111[2,1] and 111[2,2], and the driver circuit 122[2].

[0145] FIG. 13 is a timing chart for explaining an example of a method for driving the four memory cells 111 shown in FIG. 12. Here, the first row is selected, data of “1” is written to the memory cell 111[1,1] in which data of “0” is stored, data of “0” is written to the memory cell 111[1,2] in which data of “1” is stored, and each data is stored. The above-mentioned operation example 3 is applied as a method for driving each memory cell 111. The configuration shown in FIG. 12 is suitable for applying the above-mentioned operation example 3 as a method for driving the memory cell 111 because the wiring PL is connected to the drive circuit 123 for each memory cell 111. Note that the timing chart shown in FIG. 13 can be said to be a combination of the example of the driving method shown in FIG. 9 and the example of the driving method shown in FIG. 11. Therefore, the above description can be referred to, and detailed description will be omitted here.

[0146] FIG. 14A is a circuit diagram showing a configuration example of four drive circuits 123 arranged in a matrix of 2 rows and 2 columns in the connection example shown in FIG.

[0147] Figure 14(A) shows a driving circuit 123[1,1] arranged in the first row and first column, a driving circuit 123[1,2] arranged in the first row and second column, a driving circuit 123[2,1] arranged in the second row and first column, and a driving circuit 123[2,2] arranged in the second row and second column in the peripheral circuit 120.

[0148] The wiring PBL[1] arranged in the first column is connected to the driving circuit 123[1,1] and the driving circuit 123[2,1]. The wiring PBL[2] arranged in the second column is connected to the driving circuit 123[1,2] and the driving circuit 123[2,2]. The wiring PWL[1] arranged in the first row is connected to the driving circuit 123[1,1] and the driving circuit 123[1,2]. The wiring PWL[2] arranged in the second row is connected to the driving circuit 123[2,1] and the driving circuit 123[2,2].

[0149] Each driver circuit 123 includes a transistor M21. One of the source and the drain of the transistor M21 is connected to the wiring PL, the other of the source and the drain is connected to the wiring PBL, and the gate is connected to the wiring PWL.

[0150] 14A, a desired potential can be applied to the wiring PL arranged in any row and any column by applying a potential to each of the wirings PWL[1] and PWL[2] and a potential to each of the wirings PBL[1] and PBL[2]. That is, in the memory array 110, the potential of the wiring PL can be changed for each memory cell 111. Thus, the driving method shown in FIG. 13 can be realized.

[0151] Fig. 14(B) is a circuit diagram showing another configuration example of the drive circuit 123. The drive circuit 123 shown in Fig. 14(B) differs from the drive circuit 123 shown in Fig. 14(A) in that it has a NAND circuit X21 instead of the transistor M21. One of a pair of input terminals of the NAND circuit X21 is connected to the wiring PBL, the other of the pair of input terminals is connected to the wiring PWL, and the output terminal is connected to the wiring PL. Note that a NAND gate prepared in a standard circuit library can be used as the NAND circuit X21.

[0152] Note that the driver circuit 123 shown in FIGS. 14A and 14B is just an example, and the invention is not limited to this configuration.

[0153] 12, the memory cells 111 may be stacked on the driver circuits 123. That is, for example, when the driver circuit 123 has the configuration shown in FIG. 14A, the transistor M11 and the capacitor C11 included in the memory cells 111 may be stacked on the transistor M21 included in the driver circuit 123. By stacking the transistor M11 and the capacitor C11 on the transistor M21, an increase in the area occupied by providing the driver circuit 123 can be suppressed.

[0154] <Storage device configuration example 3> A storage device 700 according to one embodiment of the present invention will be described.

[0155] 15 and 16 are block diagrams illustrating configuration examples of a memory device 700. The memory device 700 shown in each of FIGS.

[0156] The memory array unit 721 has a plurality of memory cells 111. The plurality of memory cells 111 are arranged in a matrix of M rows and N columns, where M is an integer of 1 or more, and N is an integer of 1 or more.

[0157] In addition, in each of Figures 15 and 16, as representative examples, memory cell 111[1,1] arranged in the first row and first column, memory cell 111[1,N] arranged in the first row and Nth column, memory cell 111[M,1] arranged in the Mth row and first column, and memory cell 111[M,N] arranged in the Mth row and Nth column are shown.

[0158] Figure 15 also illustrates wiring WL[1] and wiring PL[1] connected to N memory cells 111 arranged in the first row, wiring WL[M] and wiring PL[M] connected to N memory cells 111 arranged in the Mth row, wiring BL[1] connected to M memory cells 111 arranged in the first column, and wiring BL[N] connected to M memory cells 111 arranged in the Nth column.

[0159] Figure 16 also illustrates wiring WL[1] connected to N memory cells 111 arranged in the first row, wiring WL[M] connected to N memory cells 111 arranged in the Mth row, wiring BL[1] and wiring PL[1] connected to M memory cells 111 arranged in the first column, and wiring BL[N] and wiring PL[N] connected to M memory cells 111 arranged in the Nth column.

[0160] Here, the memory array unit 721 corresponds to the memory array 110 described above. Note that the configuration example of the memory array unit 721 shown in FIG. 15 corresponds to the connection example shown in FIG. 8 described above. Also, the configuration example of the memory array unit 721 shown in FIG. 16 corresponds to the connection example shown in FIG. 10 described above.

[0161] The peripheral circuit unit 722 includes a power switch 761, a power switch 762, and a peripheral circuit 771. The peripheral circuit 771 includes a peripheral circuit 781, a control circuit 772, and a voltage generation circuit 773.

[0162] In one aspect of the present invention, for example, an Si transistor can be used as the transistor constituting the peripheral circuit unit 722. Therefore, a CMOS circuit (for example, a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit, etc.) configured by connecting, for example, the gate of an n-channel type Si transistor and the gate of a p-channel type Si transistor to the peripheral circuit unit 722 can be used.

[0163] Also, for example, by using an OS transistor as the transistor constituting the memory cell 111, the memory array unit 721 can be stacked on the peripheral circuit unit 722 using Si transistors. Therefore, the size of the storage device 700 can be reduced. Also, the wiring distance between the peripheral circuit unit 722 and the memory array unit 721 can be shortened. Therefore, improvements in the read speed and write speed of the storage device 700 can be achieved.

[0164] Although not shown, in the storage device 700, the memory array unit 721 may have a plurality of sense amplifiers arranged in a matrix, and a plurality of memory cells 111 may be stacked on the sense amplifiers. With such a configuration, by accessing the plurality of sense amplifiers simultaneously, the data stored in the memory array unit 721 can be read out in ultra-parallel.

[0165] For example, a signal is provided to each of the terminal BW, the terminal CE, the terminal GW, the terminal MCK, the terminal WAKE, the terminal ADDR, the terminal WDA, the terminal PON1, and the terminal PON2 from outside the storage device 700. In addition, for example, a signal is output from the terminal RDA to outside the storage device 700.

[0166] For example, a clock signal is applied to the terminal MCK. Furthermore, a control signal is applied to each of the terminals BW, CE, and GW. A chip enable signal is applied to the terminal CE. A global write enable signal is applied to the terminal GW. A byte write enable signal is applied to the terminal BW. An address signal is applied to the terminal ADDR. Write data is applied to the terminal WDA. Read data is applied to the terminal RDA. A power gating control signal is applied to the terminals PON1 and PON2. The signals applied to the terminals PON1 and PON2 may be generated by, for example, the control circuit 772.

[0167] The control circuit 772 has a function of controlling the operation of the memory device 700. The control circuit 772 has a function of, for example, performing a logical operation on signals provided to each of the terminals CE, GW, and BW to determine an operation mode (for example, a write operation or a read operation) of the memory device 700. The control circuit 772 also has a function of generating a signal that controls the peripheral circuit 781 so that the operation mode is executed.

[0168] The voltage generation circuit 773 has a function of generating an arbitrary potential for operating the peripheral circuit unit 722. For example, the voltage generation circuit 773 has a function of generating an arbitrary potential by inputting a clock signal provided to a terminal MCK in response to a signal provided to a terminal WAKE. For example, a signal that controls whether or not the clock signal provided to the terminal MCK is input to the voltage generation circuit 773 is provided to the terminal WAKE.

[0169] The peripheral circuit 781 has a function of writing and reading data to and from the memory cells 111. The peripheral circuit 781 has a function of generating various signals for controlling the operation of the memory cells 111, etc. The peripheral circuit 781 has a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

[0170] The row decoder 782 and the column decoder 784 have a function of decoding an address signal applied to a terminal ADDR. The row decoder 782 has a function of specifying a row to be accessed. The column decoder 784 has a function of specifying a column to be accessed. The row driver 783 has a function of selecting a row specified by the row decoder 782 and applying a desired signal to, for example, the corresponding memory cell 111. The column driver 785 has a function of selecting a column specified by the column decoder 784 and applying a desired signal to, for example, the corresponding memory cell 111.

[0171] The data driver 786 has a function of writing and reading data to and from the memory cell 111 selected by the row driver and the column driver. The input circuit 787 has a function of holding data provided to a terminal WDA from outside the memory device 700. The data (data Din) held in the input circuit 787 is written to the memory cell 111 via the data driver 786. The data stored in the memory cell 111 is read out to the output circuit 788 via the data driver 786. The output circuit 788 has a function of holding the read out data (data Dout). In addition, the output circuit 788 has a function of outputting the held data from a terminal RDA to outside the memory device 700.

[0172] The peripheral circuit 781 can have a function corresponding to the above-mentioned peripheral circuit 120. That is, the peripheral circuit 781 can have a function corresponding to the driving circuit 121, a function corresponding to the driving circuit 122, and a function corresponding to the driving circuit 123.

[0173] In the memory device 700 shown in FIG. 15, for example, the row driver 783 may have functions corresponding to the driving circuit 122 and the driving circuit 123, and the column driver 785 and the data driver 786 may have a function corresponding to the driving circuit 121. That is, the row driver 783 has a function of applying a desired signal to the wirings WL[1] to WL[M] and a function of applying a desired potential to the wirings PL[1] to PL[M], and the column driver 785 and the data driver 786 may have a function of exchanging data with the wirings BL[1] to BL[N].

[0174] Also, in the memory device 700 shown in FIG. 16, for example, the row driver 783 may have a function corresponding to the driving circuit 122, and the column driver 785 and the data driver 786 may have functions corresponding to the driving circuit 121 and the driving circuit 123. That is, the row driver 783 has a function of applying a desired signal to the wirings WL[1] to WL[M], and the column driver 785 and the data driver 786 may have a function of exchanging data with the wirings BL[1] to BL[N] and a function of applying a desired potential to the wirings PL[1] to PL[M].

[0175] The power switch 761 has a function of controlling whether to supply the potential applied to the terminal VMD to the peripheral circuit 771. The power switch 762 has a function of controlling whether to supply the potential applied to the terminal VMH to the row driver 783. Here, for example, a high power supply potential (e.g., potential VDD) for operating the peripheral circuit section 722 is applied to the terminal VMD, and a low power supply potential (e.g., potential VSS) is applied to the terminal VMS. Also, for example, a high power supply potential (e.g., a potential higher than the potential VDD) for operating the memory cell 111 etc. is applied to the terminal VMH. The power switch 761 is controlled to be in a conductive state or a non-conductive state by the signal applied to the terminal PON1. The power switch 762 is controlled to be in a conductive state or a non-conductive state by the signal applied to the terminal PON2.

[0176] In the peripheral circuit section 722, each circuit and each terminal can be appropriately selected or discarded. Further, other circuits and other terminals may be appropriately added.

[0177] Note that one aspect of the present invention is not limited to the configuration examples, operation examples, etc. described in the present embodiment. At least a part of the configuration examples, operation examples, and the corresponding drawings etc. illustrated in the present embodiment can be appropriately combined with other configuration examples, other operation examples, other drawings, and other embodiments etc. described in this specification etc.

[0178] (Embodiment 2) In the present embodiment, a configuration example of a memory cell that can be used in the memory device shown in Embodiment 1 described above will be described. Further, a configuration example of a transistor that can be used in the memory device shown in Embodiment 1 described above will be described.

[0179] <Configuration Example of Memory Cell> FIGS. 17(A) to 17(C) are a top view and a cross-sectional view for explaining a configuration example of a semiconductor device 200 having a transistor 600 and a capacitor element 690. At least a part of the semiconductor device 200 can be used for a memory cell of one aspect of the present invention. For example, it can be used for the memory cell 111 shown in Embodiment 1 described above.

[0180] FIG. 17(A) is a top view of the semiconductor device 200. FIG. 17(B) is a cross-sectional view of the portion indicated by the one-dot chain line A1 - A2 in FIG. 17(A). Further, FIG. 17(C) is a cross-sectional view of the portion indicated by the one-dot chain line A3 - A4 in FIG. 17(A). Note that in the top view of FIG. 17(A), some elements are omitted for clarity of the figure. Also, FIG. 43(A) shows a perspective schematic view of the semiconductor device 200 with some elements omitted. Further, in FIG. 43(A), an example is shown where the outer edge shape in the top view of each of the conductor 630, the conductor 634, and the oxide 650 is circular.

[0181] 17(A) to 17(C) illustrate an insulator 612, a conductor 610 on the insulator 612, a transistor 600 and a capacitor 690 on the conductor 610, an insulator 620 on the conductor 610, an insulator 640 on the insulator 620, and an insulator 678 on the transistor 600 and the capacitor 690. The insulator 612, the insulator 620, the insulator 640, and the insulator 678 function as interlayer films. The conductor 610 functions as a wiring.

[0182] 17A to 17C, the transistor 600 is provided so as to overlap with the capacitor 690. An opening 648 in which part of the structure of the transistor 600 is provided has a region overlapping with an opening 628 in which part of the structure of the capacitor 690 is provided. In particular, the conductor 630 functions as one of a source electrode and a drain electrode of the transistor 600 and as one of a pair of electrodes of the capacitor 690; therefore, the transistor 600 and the capacitor 690 share part of their structures. With this structure, the transistor 600 and the capacitor 690 can be provided without significantly increasing the area occupied in a top view.

[0183] [Capacitive element 690] The capacitance element 690 has a conductor 634 on the conductor 610, an insulator 632 on the conductor 634, and a conductor 630 on the insulator 632. The conductor 630 functions as one of a pair of electrodes (may be referred to as an upper electrode), the conductor 634 functions as the other of the pair of electrodes (may be referred to as a lower electrode), and the insulator 632 functions as a dielectric. In other words, the capacitance element 690 constitutes a MIM (Metal-Insulator-Metal) capacitance.

[0184] As shown in FIGS. 17(B) and 17(C), the insulator 620 has an opening 628 reaching the conductor 610. At least a portion of the conductor 634 is disposed in the opening 628. Note that the conductor 634 has a region in contact with the upper surface of the conductor 610 in the opening 628, a region in contact with a side surface of the insulator 620 in the opening 628, and a region in contact with at least a portion of the upper surface of the insulator 620. The insulator 632 is disposed such that at least a portion of it is located in the opening 628. The conductor 630 is disposed such that at least a portion of it is located in the opening 628. Note that the conductor 630 is preferably provided so as to fill the opening 628 as shown in FIGS. 17(B) and 17(C).

[0185] The capacitance element 690 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them not only at the bottom but also on the side of the opening 628, and the capacitance per unit area can be increased. Therefore, the deeper the opening 628 is made, the greater the capacitance of the capacitance element 690 can be made.

[0186] The side surface of the opening 628 (sometimes referred to as the side surface of the opening 628 of the insulator 620) is preferably perpendicular to the upper surface of the conductor 610. In other words, the insulator 620 can be said to have the opening 628 extending in a direction perpendicular to the upper surface of the conductor 610. In this case, the opening 628 has a cylindrical shape.

[0187] Although an example in which the opening 628 is circular in top view has been described in this embodiment, one embodiment of the present invention is not limited thereto. For example, the opening 628 may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view. In this case, the maximum width of the opening 628 can be calculated as appropriate according to the shape of the topmost part of the opening 628 in top view.

[0188] For example, when the opening 628 is rectangular in a top view, the maximum width of the opening 628 may be the length of the diagonal of the rectangle. Alternatively, for example, when the opening 628 is a substantially circular shape such as an ellipse, a polygonal shape, or a shape in which the corners of a polygon are rounded in a top view, the maximum width of the opening 628 may be the maximum width of the shape of the opening 628 in the top view.

[0189] The portions of the conductor 634, the insulator 632, and the conductor 630 disposed in the opening 628 are provided to reflect the shape of the opening 628. Thus, the conductor 634 is provided along the opening 628, the insulator 632 is provided so as to cover the conductor 634, and the conductor 630 is provided so as to fill the recess of the insulator 632 reflecting the shape of the opening 628.

[0190] That is, a part of the dielectric (corresponding to the insulator 632) of the capacitor element 690 is provided along the side surface of the opening 628. That is, it is provided in a direction perpendicular to the upper surface of the conductor 610. In other words, it can also be said that each of the surface where the upper electrode and the dielectric of the capacitor element 690 are in contact and the surface where the lower electrode and the dielectric are in contact has a component in a direction perpendicular to the upper surface of the conductor 610.

[0191] In FIGS. 17(B) and 17(C), the opening 628 is provided such that the side surface of the opening 628 is perpendicular to the upper surface of the conductor 610, but one aspect of the present invention is not limited to this. For example, the side surface of the opening 628 may have a tapered shape.

[0192] In this specification and the like, the tapered shape refers to a shape in which at least a part of the side surface of the structure is provided inclined with respect to the substrate surface. Also, the angle formed by the inclined side surface and the substrate surface is called the taper angle. In particular, in this specification and the like, a tapered shape having a taper angle exceeding 0° and less than 90° may be referred to as a forward taper shape, and a tapered shape having a taper angle exceeding 90° and less than 180° may be referred to as a reverse taper shape.

[0193] A conductor 634 and an insulator 632 are laminated along the side surface of the opening 628 and the upper surface of the conductor 610. A conductor 630 is provided on the insulator 632 so as to fill the opening 628. In this specification and the like, a capacitance element 690 having such a configuration may be referred to as a trench type capacitance, a trench capacitance, a deep hole laminated capacitance, or the like.

[0194] The insulator 640 is disposed on the capacitor 690. That is, the insulator 640 is disposed above the conductor 634, the insulator 632, and the conductor 630. In other words, the conductor 630 is disposed below the insulator 640.

[0195] The conductor 610 is provided below the conductor 634. The conductor 634 has a region in contact with the conductor 610.

[0196] The conductor 610 is provided on an insulator 612. The conductor 610 can be provided, for example, in a planar form.

[0197] The insulator 612 may be, for example, a material that can be used for the insulator 514 described below.

[0198] It is preferable to use a conductive material having high conductivity as the conductor 610. Note that the conductor 610 may have a single-layer structure or a structure in which different materials are stacked. For example, a material that can be used for the conductor 503 or the conductor 560 described later may be used as the conductor 610. For example, tungsten or the like can be used.

[0199] The conductor 634 is preferably made of a single layer or a multilayer of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing diffusion of oxygen. In this way, when an oxide insulator is used for the insulator 632, the insulator 632 can suppress oxidation of the conductor 634. In addition, when an oxide insulator is used for the insulator 620, the insulator 620 can suppress oxidation of the conductor 634.

[0200] The conductor 634 may be, for example, a material that can be used for the conductor 503 or the conductor 560 described later. For example, titanium nitride or indium tin oxide with added silicon may be used. For example, a structure in which titanium nitride is stacked on tungsten may be used. For example, a structure in which tungsten is stacked on a first titanium nitride, and a second titanium nitride is stacked on the tungsten may be used.

[0201] The insulator 632 is provided on the conductor 634. The insulator 632 is provided so as to contact the upper surface and side surfaces of the conductor 634. In other words, the insulator 632 is preferably structured to cover the side end portions of the conductor 634. This can prevent the conductor 634 and the conductor 630 from shorting out.

[0202] As shown in FIGS. 17B and 17C, the insulator 632 may be provided extending so as to be in contact with the upper surface of the insulator 620.

[0203] Alternatively, a structure may be used in which a side end of the insulator 632 coincides with a side end of the conductor 634. With such a structure, the insulator 632 and the conductor 634 can be formed using the same mask, and the manufacturing process can be simplified.

[0204] It is preferable to use a material with a high dielectric constant, a so-called high-k material, as the insulator 632. By using a high-k material as the insulator 632, the insulator 632 can be made thick enough to suppress the gate leakage current and the capacitance of the capacitor 690 can be sufficiently ensured.

[0205] As the high dielectric constant material insulator, for example, an oxide, an oxynitride, a nitriding oxide, or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, gallium, etc. can be used. These materials may also be used by containing silicon. Insulators made of these materials can also be used by stacking them.

[0206] Furthermore, as an insulator of a high dielectric constant material, for example, aluminum oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, an oxide having silicon and zirconium, an oxynitride having silicon and zirconium, an oxide having hafnium and zirconium, or an oxynitride having hafnium and zirconium can be used.

[0207] Insulators made of the above materials may be laminated for use. In this case, it is preferable to use a structure in which a high dielectric constant material and a material having a higher dielectric strength than the high dielectric constant material are laminated.

[0208] As such an insulator, for example, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used. Also, for example, an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. Also, for example, an insulator in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used. By using an insulator having a relatively high dielectric strength, such as aluminum oxide, in a laminated state as the insulator, the dielectric strength is improved and electrostatic breakdown of a capacitor having the insulator can be suppressed.

[0209] The conductor 630 is provided in contact with a part of the upper surface of the insulator 632. Moreover, the side end of the conductor 630 is preferably located inside the side end of the conductor 634 in both the X direction and the Y direction. Note that in a structure in which the insulator 632 covers the side end of the conductor 634, the side end of the conductor 630 may be located outside the side end of the conductor 634.

[0210] A single layer or a multilayer of a conductive material can be used as the conductor 630. For example, a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion is preferably used as the conductor 630.

[0211] The conductor 630 may be made of, for example, a material that can be used for the conductor 503, the conductor 560, or the conductor 542 described below. For example, titanium nitride or tantalum nitride may be used.

[0212] Since the insulator 620 functions as an interlayer film, it is preferable that the insulator 620 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulator 620, an insulator containing a material with a low dielectric constant can be used in a single layer or a multilayer structure.

[0213] For example, a material that can be used for the insulator 516 described later may be used as the insulator 620. For example, it is preferable to use silicon oxide or silicon oxynitride because of their thermal stability.

[0214] [Transistor 600] The transistor 600 includes a conductor 630, a conductor 660 on an insulator 640, an oxide 650, an insulator 672 on the oxide 650, and a conductor 670 on the insulator 672. The oxide 650 functions as a semiconductor film including a channel formation region, the conductor 670 functions as a gate electrode, the insulator 672 functions as a gate insulating film, the conductor 630 functions as one of a source electrode and a drain electrode, and the conductor 660 functions as the other of the source electrode and drain electrode.

[0215] In the transistor 600, a metal oxide that functions as an oxide semiconductor is used for the oxide 650 including a channel formation region. For example, the oxide 650 may be any metal oxide that can be used for the oxide 530 described later.

[0216] Note that a semiconductor that can be used as the oxide 650 including the channel formation region is not limited to a metal oxide that functions as an oxide semiconductor. The same applies to the oxide 530 and the oxide 830 described later. Thus, in this specification and the like, the term "oxide" may be replaced with the term "semiconductor," "semiconductor layer," or "semiconductor film" as appropriate.

[0217] As shown in FIGS. 17B and 17C, the insulator 640 and the conductor 660 have an opening 648 that reaches the conductor 630. At least a part of the oxide 650 is disposed in the opening 648. Note that the oxide 650 has a region that contacts the upper surface of the conductor 630 in the opening 648, a region that contacts the side surface of the conductor 660 in the opening 648, and a region that contacts at least a part of the upper surface of the conductor 660. The insulator 672 is disposed so that at least a part of it is located in the opening 648. The conductor 670 is disposed so that at least a part of it is located in the opening 648. Note that the conductor 670 is preferably provided so as to fill the opening 648 as shown in FIGS. 17B and 17C.

[0218] The conductor 630 may have a structure in which, for example, tantalum nitride is laminated on titanium nitride. In this case, the titanium nitride may be in contact with the insulator 632, and the tantalum nitride may be in contact with the oxide 650. With such a structure, the conductor 630 can be prevented from being excessively oxidized by the oxide 650. Furthermore, when an oxide insulator is used for the insulator 632, the insulator 632 can be prevented from being excessively oxidized. The conductor 630 may have a structure in which, for example, tungsten is laminated on titanium nitride.

[0219] Moreover, since the conductor 630 has a region in contact with the oxide 650, it is preferable to use a conductive material containing oxygen. With such a structure, the conductor 630 can maintain its conductivity even if it absorbs oxygen. Even when a material containing oxygen is used for the insulator 632, the conductivity of the conductor 630 can be maintained.

[0220] Furthermore, as the conductor 630, for example, indium tin oxide (also referred to as ITO), indium tin oxide doped with silicon (also referred to as ITSO), or indium zinc oxide (also referred to as IZO (registered trademark)) can be used in a single layer or in a stacked layer.

[0221] The oxide 650 has a region in contact with the side surface of the conductor 660 in the opening 648 and a region in contact with a part of the top surface of the conductor 660. In this way, the oxide 650 contacts not only the side surface but also the top surface of the conductor 660, so that the area in which the oxide 650 and the conductor 660 contact each other can be increased.

[0222] 17C shows a structure in which the side end of the oxide 650 is located inside the side end of the conductor 660. Note that one embodiment of the present invention is not limited to this. For example, a structure in which the side end of the oxide 650 and the side end of the conductor 660 coincide with each other in the Y direction may be used. Alternatively, a structure in which the side end of the oxide 650 is located outside the side end of the conductor 660 may be used.

[0223] 17A to 17C, it is preferable that the conductor 670 extends in the Y direction and the conductor 660 extends in the X direction. With such a structure, the conductor 670 and the conductor 660 cross each other. Although the conductor 610 is provided in a planar shape in FIG. 17A, one embodiment of the present invention is not limited to this. For example, the conductor 610 may be provided parallel to the conductor 670 or parallel to the conductor 660.

[0224] The side surface of the opening 648 (sometimes referred to as the side surface of the opening 648 of the insulator 640) is preferably perpendicular to the upper surface of the conductor 610. In other words, the insulator 640 can be said to have the opening 648 extending in a direction perpendicular to the upper surface of the conductor 610. In this case, the opening 648 has a cylindrical shape.

[0225] Although the opening 648 has a circular shape in top view in this embodiment, one embodiment of the present invention is not limited to this. For example, the opening 648 may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view. In this case, the maximum width of the opening 648 can be calculated as appropriate according to the shape of the topmost part of the opening 648 in top view.

[0226] For example, if opening 648 is a rectangle when viewed from above, the maximum width of opening 648 may be the length of the diagonal of the rectangle. Alternatively, for example, if opening 648 is a substantially circular shape such as an ellipse, a polygonal shape, or a polygonal shape with rounded corners when viewed from above, the maximum width of opening 648 may be the maximum width of the shape of opening 648 when viewed from above.

[0227] The portions of the oxide 650, the insulator 672, and the conductor 670 that are disposed in the opening 648 are provided to reflect the shape of the opening 648. Thus, the oxide 650 is provided along the opening 648, the insulator 672 is provided to cover the oxide 650, and the conductor 670 is provided to fill the recess of the insulator 672 that reflects the shape of the opening 648.

[0228] That is, a part of the semiconductor film (corresponding to the oxide 650) including the channel formation region of the transistor 600 is provided along the side surface of the opening 648. That is, the part is provided perpendicular to the top surface of the conductor 610. In other words, it can be said that the channel length direction of the transistor 600 has a component perpendicular to the top surface of the conductor 610. That is, it can be said that the channel length direction has a component in the vertical direction (the Z direction in FIGS. 17A to 17C, which is also referred to as the height direction or the direction perpendicular to the formation surface). That is, it can be said that the source electrode and the drain electrode are located at different heights and the drain current flows in the vertical direction. Thus, the transistor of one embodiment of the present invention is a transistor whose channel length direction has a vertical component (that is, a transistor in which the drain current flows vertically), and can be called, for example, a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or a vertical channel transistor.

[0229] Here, the conductor 660 may be, for example, a material that can be used for the conductor 630. The conductor 670 may be, for example, a material that can be used for the conductor 630. The insulator 672 may be, for example, a material that can be used for the insulator 522, the insulator 524, or the insulator 545 described later. The insulator 640 may be, for example, a material that can be used for the insulator 620. The insulator 678 may be, for example, a material that can be used for the insulator 514 described later or the insulator 612 described above.

[0230] 17B and 17C, the opening 648 is provided so that the side surface of the opening 648 is perpendicular to the top surface of the conductor 610; however, this is not limited to this embodiment of the present invention. For example, the side surface of the opening 648 may be tapered.

[0231] 17B and 17C, the oxide 650 is shown as a single layer, but one embodiment of the present invention is not limited to this. The oxide 650 may have a stacked structure of multiple oxide layers having different chemical compositions.

[0232] Here, an enlarged view of the oxide 650 and its vicinity in Fig. 17B is shown in Fig. 18A. Also, a cross-sectional view in the XY plane including the conductor 660 is shown in Fig. 18B.

[0233] As shown in FIG. 18A, the oxide 650 has a region 650i, and regions 650na and 650nb that are provided so as to sandwich the region 650i.

[0234] The region 650na is a region of the oxide 650 in contact with the conductor 630. At least a portion of the region 650na functions as one of the source region and drain region of the transistor 600. The region 650nb is a region of the oxide 650 in contact with the conductor 660. At least a portion of the region 650nb functions as the other of the source region and drain region of the transistor 600. As shown in FIG. 18(B), the conductor 660 is in contact with the entire outer periphery of the oxide 650. Thus, the other of the source region and drain region of the transistor 600 can be formed on the entire outer periphery of a portion of the oxide 650 that is formed in the same layer as the conductor 660.

[0235] Region 650i is a region between regions 650na and 650nb of the oxide 650. At least a part of region 650i functions as a channel formation region of the transistor 600. That is, the channel formation region of the transistor 600 is located in a region of the oxide 650 between the conductor 630 and the conductor 660. It can also be said that the channel formation region of the transistor 600 is located in a region of the oxide 650 that is in contact with the insulator 640 or in the vicinity of the region.

[0236] The channel length of the transistor 600 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 600 is determined by the thickness of the insulator 640 on the conductor 630. In FIG. 18(A), the channel length L of the transistor 600 is indicated by a dashed double-headed arrow. The channel length L is the distance between the end of the region where the oxide 650 and the conductor 630 contact each other and the end of the region where the oxide 650 and the conductor 660 contact each other in a cross-sectional view. In other words, the channel length L corresponds to the length of the side surface of the insulator 640 on the opening 648 side in a cross-sectional view.

[0237] In a planar transistor, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in one embodiment of the present invention, the channel length can be set by the film thickness of the insulator 640. Thus, the channel length of the transistor 600 can be made to be an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 600, and improves the frequency characteristics.

[0238] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 648. This allows the area occupied by the transistor 600 to be reduced compared to a planar type transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane.

[0239] Also, in the XY plane including the channel formation region of the oxide 650, the oxide 650, the insulator 672, and the conductor 670 are arranged concentrically, as in FIG. 18(B). Therefore, the side of the conductor 670 arranged at the center faces the side of the oxide 650 through the insulator 672. That is, in the top view, the entire circumference of the oxide 650 becomes the channel formation region. In this case, for example, the channel width of the transistor 600 is determined by the outer periphery length of the oxide 650. That is, it can be said that the channel width of the transistor 600 is determined by the size of the maximum width of the opening 648 (the maximum diameter when the opening 648 is circular in the top view). In FIG. 18(A) and FIG. 18(B), the maximum width D of the opening 648 is indicated by a double-headed arrow of a two-dot chain line. In FIG. 18(B), the channel width W of the transistor 600 is indicated by a double-dot chain line arrow of a one-dot chain line. By increasing the size of the maximum width D of the opening 648, the channel width per unit area can be increased, and the on-current can be increased.

[0240] When the opening 648 is formed by using a photolithography method, the maximum width D of the opening 648 is limited by the exposure limit of photolithography, and further miniaturization is difficult. In addition, the maximum width D of the opening 648 is set by the film thickness of each of the oxide 650, the insulator 672, and the conductor 670 provided in the opening 648. The maximum width D of the opening 648 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that, when the opening 648 is circular in top view, the maximum width D of the opening 648 corresponds to the diameter of the opening 648, and the channel width W can be calculated as "D x π".

[0241] The channel length L of the transistor 600 of one embodiment of the present invention is preferably smaller than at least the channel width W of the transistor 600. The channel length L of the transistor 600 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 600. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0242] In addition, by forming the opening 648 to have a circular shape in top view, the oxide 650, the insulator 672, and the conductor 670 are arranged concentrically. This makes the distance between the conductor 670 and the oxide 650 uniform, so that the gate electric field of the oxide 650 can be applied uniformly.

[0243] In one embodiment of the present invention, at least a part of the semiconductor device 200 can be used for the memory cell 111 described in the above-described embodiment 1. That is, the transistor 600 corresponds to the transistor M11, and the capacitor 690 corresponds to the capacitor C11. That is, it can be said that the conductor 670 includes a region that functions as the gate of the transistor M11, the conductor 660 includes a region that functions as the other of the source and drain of the transistor M11, the conductor 630 includes a region that functions as one of the source and drain of the transistor M11 and a region that functions as one terminal of the capacitor C11, and the conductor 610 includes a region that functions as the other terminal of the capacitor C11. The conductor 670 corresponds to the wiring WL, the conductor 660 corresponds to the wiring BL, the conductor 610 corresponds to the wiring PL, and the conductor 630 corresponds to the wiring SN. 17A to 17C, the transistor M11, the capacitor C11, the wiring WL, the wiring BL, the wiring PL, and the wiring SN are denoted by reference characters in parentheses.

[0244] Note that the transistor 600 and the capacitor 690 illustrated in FIGS. 17A to 17C are just examples and are not limited to these structures.

[0245] [Transistor 600B] In one embodiment of the present invention, a transistor having a back gate may be used in the semiconductor device 200 described above.

[0246] FIG. 19 is a cross-sectional view for explaining a configuration example of a transistor having a back gate as one aspect of the present invention. The transistor 600B shown in FIG. 19 is a modified example of the transistor 600 described above. The transistor 600B has two corresponding gates (a gate and a back gate) sandwiching a channel formation region.

[0247] The transistor 600B differs from the transistor 600 in that it has a conductor 680 and an insulator 682. In the transistor 600B, an insulator 682 is provided between the insulator 640 and the oxide 650 on the side surface of the opening 648, and a conductor 680 is provided on a part of the insulator 640 so as to surround the outer periphery of the oxide 650 via the insulator 682.

[0248] Here, the conductor 670 may function as a first gate (also simply referred to as a gate) electrode, and the conductor 680 may function as a second gate (also referred to as a back gate) electrode. In that case, the insulator 672 functions as a first gate insulating film, and the insulator 682 functions as a second gate insulating film.

[0249] The transistor 600B also differs from the transistor 600 in that the conductor 630 has a recess at a position overlapping the opening 648. In the transistor 600B, a part of the oxide 650 and a part of the insulator 682 are provided in the recess of the conductor 630. At that time, the lower surface of the oxide 650 is provided so as to be lower than the lower surface of the insulator 682.

[0250] By adopting such a configuration, the area where the oxide 650 and the conductor 630 are in contact with each other can be increased. Therefore, the contact resistance between the oxide 650 and the conductor 630 can be reduced.

[0251] Here, as the conductor 680, for example, a material that can be used for the conductor 670 may be used. Also, as the insulator 682, for example, a material that can be used for the insulator 672 may be used.

[0252] Here, in a transistor having a back gate, the threshold voltage is shifted by the back gate voltage. In addition, the back gate of the transistor may be connected to the gate, one of the source and the drain, or the other of the source and the drain.

[0253] 20A is a cross-sectional view showing an example of a configuration in which a backgate (corresponding to the conductor 680) of the transistor 600B is connected to a gate (corresponding to the conductor 670) of the transistor 600B via an insulator 672 and a conductor 684 embedded in the insulator 640. FIG. 20B is a cross-sectional view showing an example of a configuration in which a backgate (corresponding to the conductor 680) of the transistor 600B is connected to the other of the source and drain (corresponding to the conductor 660) of the transistor 600B via a conductor 684 embedded in the insulator 640. FIG. 20C is a cross-sectional view showing an example of a configuration in which a backgate (corresponding to the conductor 680) of the transistor 600B is connected to one of the source and drain (corresponding to the conductor 630) of the transistor 600B via a conductor 684 embedded in the insulator 640.

[0254] The conductor 684 functions as a plug or a wiring. The details of the conductor having a function as a plug or a wiring will be described later.

[0255] 21A and 21B are examples of circuit diagrams in which the transistors included in the memory cell 111 described in the above-described embodiment 1 are replaced with transistors having a backgate. In FIG. 21A, as an example, the backgate of the transistor M11 is connected to the gate. In FIG. 21B, as an example, the backgate of the transistor M11 is connected to the wiring BGL1.

[0256] 21C and 21D are examples of circuit diagrams in which the transistors included in the driver circuit 123 described in the above-described embodiment 1 are replaced with transistors having backgates. In FIG. 21C, as an example, the backgates of the transistors M2a and M2b are connected to the gates of the transistors M2a and M2b. In FIG. 21D, as an example, the backgates of the transistors M2a and M2b are connected to the wiring BGL2.

[0257] Here, by connecting the back gate of a transistor to the gate, the on-state current of the transistor can be increased, and by applying an arbitrary potential to the back gate of the transistor, the threshold voltage of the transistor can be changed.

[0258] In one embodiment of the present invention, the memory cell 111 can have the structure shown in FIG. 21B in the memory device described in Embodiment 1. In this case, a potential that increases the threshold voltage of the transistor M11 may be applied to the wiring BGL1. This can reduce the off-state current of the transistor M11, and data written to the memory cell 111 (i.e., the potential of the wiring SN) can be held for a long period of time. Furthermore, when writing or reading data, the potential applied to the wiring BGL1 may be changed so that the threshold voltage of the transistor M11 is reduced. This can increase the on-state current of the transistor, and improve the writing and reading speeds.

[0259] 21C can be applied to the driver circuit 123. This can increase the on-state currents of the transistors M2a and M2b, thereby improving the operation speed when the memory cell 111 is driven. This can also be applied to the driver circuit 123. The configuration shown in FIG. 21D can be applied to the driver circuit 123. In this case, a potential that reduces the threshold voltages of the transistors M2a and M2b may be applied to the wiring BGL2. This can increase the on-state currents of the transistors M2a and M2b, thereby improving the operation speed when the memory cell 111 is driven.

[0260] [Modifications of the semiconductor device 200] A semiconductor device including a transistor and a capacitor that can be used in one embodiment of the present invention is not limited to the structure of the semiconductor device 200 shown in Figures 17(A) to 17(C) and 43(A). For example, the structure of the semiconductor device 200A shown in Figures 42(A) to 42(C) and 43(B) may be used.

[0261] FIG. 42(A) is a top view of the semiconductor device 200A. FIG. 42(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 42(A). FIG. 42(C) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 42(A). Note that in the top view of FIG. 42(A), some elements are omitted for clarity. FIG. 43(B) is a perspective schematic view of the semiconductor device 200A, with some elements omitted. FIG. 43(B) illustrates an example in which the outer edge shapes of the conductor 630, the conductor 634, and the oxide 650 in top view are each circular.

[0262] The semiconductor device 200A differs from the semiconductor device 200 in that it has an insulator 676. The insulator 676 is provided on the insulator 672, and an opening is provided so as to overlap with the opening 648. A region that functions as a wiring for the conductor 670 is provided so as to contact the side and top surface of the insulator 676 in the opening. As the insulator 676, for example, a material that can be used for the insulator 620 or the insulator 640 described above may be used.

[0263] In the semiconductor device 200A, in the region where the conductor 670 and the conductor 660 overlap, an insulator 672 and an insulator 676 are provided between the conductor 670 and the conductor 660. Therefore, the distance between the conductor 670 and the conductor 660 can be made larger than that in the semiconductor device 200. This can reduce the parasitic capacitance between the conductor 660 and the conductor 670. In addition, since the thickness of the conductor 670 can be easily increased, the resistance can be reduced. Therefore, for example, when the semiconductor device 200A is used in a memory cell, the write speed and the read speed can be improved.

[0264] [Modifications of the transistor 600 and the capacitor 690] A transistor and a capacitor that can be used in one embodiment of the present invention are not limited to the transistor 600 and the capacitor 690 illustrated in Figures 17A to 17C. For example, a transistor 600 having a structure illustrated in Figure 44A and a capacitor 690 having a structure illustrated in Figure 44B may be used.

[0265] 44(A) and 44(B) show a layered structure of a conductor 630_1 and a conductor 630_2 over the conductor 630_1 as the conductor 630. The conductor 630_1 functions as one of a pair of electrodes of the capacitor 690, and the conductor 630_2 functions as one of the source electrode and drain electrode of the transistor 600.

[0266] Also, a stacked layer structure of a conductor 660_1 and a conductor 660_2 over the conductor 660_1 is illustrated as the conductor 660. For example, the conductor 660_1 can function as a wiring, and the conductor 660_2 can function as the other of the source electrode and drain electrode of the transistor 600.

[0267] 44A, the conductor 630_2 has a recess at a position overlapping with the opening 648, and part of the oxide 650, part of the insulator 672, and part of the conductor 670 are provided in the recess of the conductor 630_2. In this case, the bottom surface of the conductor 670 in the recess can be provided lower than the top surface of the conductor 630_2 outside the recess.

[0268] By providing the oxide 650 in the recess of the conductor 630_2, the area where the oxide 650 and the conductor 630_2 are in contact with each other can be increased, and thus the contact resistance between the oxide 650 and the conductor 630_2 can be reduced.

[0269] Furthermore, by reducing the height of the bottom surface of the conductor 670, a gate electric field can be easily applied to the channel formation region of the oxide 650. This can improve the electrical characteristics of the transistor 600. In addition, a gate electric field can be easily applied to a region of the oxide 650 in contact with the conductor 630_2. This can increase the on-state current of the transistor 600. Furthermore, regardless of whether the conductor 630 or the conductor 660 functions as a drain electrode, the electrical characteristics of the transistor 600 can be improved.

[0270] 44(A), the oxide 650 may have a region 650p with a rounded corner in the recess of the conductor 630_2. This can suppress electric field concentration on the insulator 672 near the region 650p, compared to when the region 650p has a right angle or an acute angle (has a corner). In this way, by suppressing the electric field concentration on the insulator 672, dielectric breakdown of the insulator 672 can be suppressed, and a highly reliable semiconductor device can be provided.

[0271] 44B, the conductor 610 has a recess at a position overlapping with the opening 628, and part of the conductor 634, part of the insulator 632, and part of the conductor 630_1 are provided in the recess of the conductor 610. In this case, the bottom surface of the conductor 630_1 in the recess can be provided so as to be lower than the top surface of the conductor 610 outside the recess.

[0272] By providing the conductor 634 in a recessed portion of the conductor 610, it is possible to increase the area where the conductor 634 and the conductor 610 are in contact with each other. Therefore, the contact resistance between the conductor 634 and the conductor 610 can be reduced.

[0273] Here, as shown in FIG. 44(B), the conductor 634 may have a region 634p with a rounded corner in the recess of the conductor 610. This can suppress electric field concentration on the insulator 632 near the region 634p more than when the region 634p is a right angle or an acute angle (having a corner), for example. Also, the end 634q of the conductor 634 may be provided so as to be located below the upper surface of the insulator 620. This can suppress electric field concentration on the insulator 632 near the end 634q more than when the end 634q is located on the insulator 620. In this way, by suppressing the electric field concentration on the insulator 632, it is possible to suppress dielectric breakdown of the insulator 632 and provide a highly reliable semiconductor device.

[0274] <Memory array layout example> Here, an example of a layout in which the semiconductor devices 200 are arranged in a matrix will be described.

[0275] 22(A) and 22(B) are top views showing an example of a layout in the case where the semiconductor device 200 is arranged in a matrix shape. That is, for example, it can be said that this is an example of the layout of the memory array 110 that can be applied when the semiconductor device 200 is used as the memory cell 111 shown in the above-described first embodiment.

[0276] 22(A) and 22(B), nine semiconductor devices 200 are arranged in a matrix of three rows and three columns. Here, the semiconductor device 200 arranged in the first row and first column is indicated as semiconductor device 200[1,1], the semiconductor device 200 arranged in the first row and third column is indicated as semiconductor device 200[1,3], the semiconductor device 200 arranged in the third row and first column is indicated as semiconductor device 200[3,1], and the semiconductor device 200 arranged in the third row and third column is indicated as semiconductor device 200[3,3].

[0277] In addition, as a representative example, the oxide 650, conductor 634, opening 648, and opening 628 of the semiconductor device 200[3,3] are shown with the symbols oxide 650[3,3], conductor 634[3,3], opening 648[3,3], and opening 628[3,3], respectively.

[0278] The three semiconductor devices 200 arranged in the first row are connected to a conductor 670[1] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the second row are connected to a conductor 670[2] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the third row are connected to a conductor 670[3] extending in the row direction (Y direction).

[0279] The three semiconductor devices 200 arranged in the first row are connected to a conductor 660[1] extending in the row direction (X direction). The three semiconductor devices 200 arranged in the second row are connected to a conductor 660[2] extending in the row direction (X direction). The three semiconductor devices 200 arranged in the third row are connected to a conductor 660[3] extending in the row direction (X direction).

[0280] Here, Fig. 22(A) is a layout example that can be applied to the connection example shown in Fig. 8 of the above-mentioned first embodiment. Therefore, in Fig. 22(A), the three semiconductor devices 200 arranged in the first row are connected to the conductor 610[1] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the second row are connected to the conductor 610[2] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the third row are connected to the conductor 610[3] extending in the row direction (Y direction).

[0281] FIG. 23(A) is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[1,2], and the semiconductor device 200[1,3] in the column direction (X direction) in the layout shown in FIG. 22(A). As shown in FIG. 23(A), the conductor 660[1] extending in the column direction (X direction) is shared by the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1]. Also, FIG. 23(B) is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1] in the row direction (Y direction). As shown in FIG. 23(B), the conductor 610[1] and the conductor 670[1] extending in the row direction (Y direction) are shared by the semiconductor device 200[1,1], the semiconductor device 200[1,2], and the semiconductor device 200[1,3].

[0282] That is, the direction in which conductors 610[1] to 610[3] extend is parallel to the direction in which conductors 670[1] to conductors 670[3] extend, and is perpendicular to the direction in which conductors 660[1] to conductors 660[3] extend.

[0283] In addition, when viewed from above, the conductor 610[1] and the conductor 670[1] have an overlapping region, the conductor 610[2] and the conductor 670[2] have an overlapping region, and the conductor 610[3] and the conductor 670[3] have an overlapping region. In addition, when viewed from above, the ends of the conductor 610[1] and the conductor 670[1] do not have to be aligned, the ends of the conductor 610[2] and the conductor 670[2] do not have to be aligned, and the ends of the conductor 610[3] and the conductor 670[3] do not have to be aligned.

[0284] Also, Fig. 22(B) is a layout example that can be applied to the connection example shown in Fig. 10 of the above-mentioned first embodiment. Therefore, in Fig. 22(B), the three semiconductor devices 200 arranged in the first row are connected to the conductor 610[1] extending in the row direction (X direction). The three semiconductor devices 200 arranged in the second row are connected to the conductor 610[2] extending in the row direction (X direction). The three semiconductor devices 200 arranged in the third row are connected to the conductor 610[3] extending in the row direction (X direction).

[0285] FIG. 24(A) is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[1,2], and the semiconductor device 200[1,3] in the column direction (X direction) in the layout shown in FIG. 22(B). As shown in FIG. 24(A), the conductor 610[1] and the conductor 660[1] extending in the column direction (X direction) are shared by the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1]. Also, FIG. 24(B) is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1] in the row direction (Y direction). As shown in FIG. 24(B), the conductor 670[1] extending in the row direction (Y direction) is shared by the semiconductor device 200[1,1], the semiconductor device 200[1,2], and the semiconductor device 200[1,3].

[0286] That is, the direction in which conductors 610[1] to 610[3] extend is parallel to the direction in which conductors 660[1] to conductors 660[3] extend and perpendicular to the direction in which conductors 660[1] to conductors 660[3] extend.

[0287] In addition, when viewed from above, the conductor 610[1] and the conductor 660[1] have an overlapping region, the conductor 610[2] and the conductor 660[2] have an overlapping region, and the conductor 610[3] and the conductor 660[3] have an overlapping region. In addition, when viewed from above, the ends of the conductor 610[1] and the conductor 660[1] do not have to be aligned, the ends of the conductor 610[2] and the conductor 660[2] do not have to be aligned, and the ends of the conductor 610[3] and the conductor 660[3] do not have to be aligned.

[0288] In this manner, in one embodiment of the present invention, by applying the semiconductor device 200 arranged in a matrix to the memory array 110 shown in the above-described embodiment 1, a conductor 670 corresponding to the wiring WL and a conductor 610 corresponding to the wiring PL can be provided so as to overlap each other as shown in Fig. 22A. In addition, a conductor 660 corresponding to the wiring BL and a conductor 610 corresponding to the wiring PL can be provided so as to overlap each other as shown in Fig. 22B. Thus, the area occupied by the memory cell 111 can be reduced, and the recording density can be improved.

[0289] In this embodiment, nine semiconductor devices 200 are arranged in a matrix of three rows and three columns, but the arrangement is not limited to this. The semiconductor devices 200 may be arranged in two rows, or in four or more rows. The semiconductor devices 200 may also be arranged in two columns, or in four or more columns.

[0290] <Example of transistor stacking> In the memory device of one embodiment of the present invention, transistors having various structures can be used, and a structure in which transistors having various structures are stacked can be used.

[0291] 25 is a cross-sectional view of a semiconductor device including a transistor 550, a transistor 500, a transistor 600, and a capacitor 690 (i.e., the semiconductor device 200). Note that FIG. 25 illustrates a cross-sectional view of the transistor 550 in the channel length direction.

[0292] 25, the transistor 500 is provided above a transistor 550. The semiconductor device 200 (four representative ones are shown here) is provided above the transistor 500.

[0293] The conductor 328 on the transistor 550 may be connected to the conductor 548 on the transistor 500 via the conductor 330, the conductor 356, the conductor 518, the conductor 546, etc. The conductor 548 may be connected to the conductor 670 via the conductor 616, the conductor 610, the conductor 626, the conductor 630, the conductor 646, etc. Note that these conductors may be formed of conductors having a function as a plug or a wiring.

[0294] In this specification and the like, a conductor having a function as a plug or wiring may be collectively designated by the same reference symbol for multiple components. Also, the wiring and the plug may be integrated. That is, a part of the conductor may function as a wiring and a part of the conductor may function as a plug.

[0295] For each plug or wiring, for example, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer.

[0296] In particular, it is preferable to use a high melting point material that has both heat resistance and conductivity for each plug or wiring. For example, tungsten or molybdenum can be used as such a material. It is also preferable to use a low resistance conductive material that can reduce the wiring resistance for each plug or wiring. For example, aluminum or copper can be used as such a material.

[0297] [Transistor 550] The transistor 550 will now be described.

[0298] As shown in Figure 25, the transistor 550 is provided over a substrate 311 and has a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulating film, a semiconductor region 313 functioning as a channel formation region, a low-resistance region 314a functioning as one of the source region or drain region, and a low-resistance region 314b functioning as the other of the source region or drain region.

[0299] The transistor 550 may be either a p-channel type or an n-channel type. For example, by connecting the gate of the n-channel transistor 550 and the gate of the p-channel transistor 550, a CMOS circuit (for example, a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured.

[0300] Therefore, for example, when the transistor 550 is applied to a memory device, it may be used as a transistor constituting a peripheral circuit for operating the memory device. That is, for example, in the memory device 100 described in the above-described embodiment 1, the transistor 550 may be used as at least a part of the transistors constituting the peripheral circuit 120. Also, for example, in the memory device 700 described in the above-described embodiment 1, the transistor 550 may be used as at least a part of the transistors constituting the peripheral circuit portion 722.

[0301] 26, the transistor 550 can have a so-called fin type structure in which the upper surface and the side surface in the channel width direction of a semiconductor region 313 made of a part of a substrate 311 are covered with a conductor 316 via an insulator 315. This increases the effective channel width, thereby improving the on-characteristics of the transistor 550. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 550.

[0302] The transistor 550 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single crystal silicon, in, for example, a region where a channel of the semiconductor region 313 is formed, a region nearby the region, a low resistance region 314a which is one of the source region and the drain region, and a low resistance region 314b which is the other of the source region and the drain region. Alternatively, the transistor 550 may be formed of a material having, for example, germanium, silicon germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 550 may be configured using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide, gallium aluminum arsenide, or the like.

[0303] The low resistance regions 314a and 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0304] A semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, can be used as the conductor 316. Also, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0305] Note that the work function is determined depending on the material of a conductor; therefore, the threshold voltage of a transistor can be adjusted by selecting the material of the conductor.

[0306] It is preferable to use a material such as titanium nitride or tantalum nitride as the conductor 316. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum in a laminated state. In particular, it is preferable to use a tungsten in a laminated state in terms of heat resistance.

[0307] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order over the transistor 550.

[0308] It is preferable to use, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like as the insulators 320, 322, 324, and 326. In particular, it is preferable to use silicon oxide or silicon oxynitride in terms of their thermal stability.

[0309] In this specification, silicon oxynitride refers to a material that contains more oxygen than nitrogen, silicon nitride oxide refers to a material that contains more nitrogen than oxygen, aluminum oxynitride refers to a material that contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material that contains more nitrogen than oxygen.

[0310] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0311] As the insulator 324, it is preferable to use an insulator having barrier properties that prevent impurities such as hydrogen from diffusing from the substrate 311 located below the insulator 324 or the transistor 550 to a region located above the insulator 324.

[0312] As an insulator having a barrier property against hydrogen, for example, silicon nitride formed by a chemical vapor deposition (CVD) method can be used. Also, for example, metal oxides such as aluminum oxide, hafnium oxide, or tantalum oxide can be used.

[0313] Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor, such as the transistor 600, the characteristics of the semiconductor element may deteriorate. Therefore, an insulator that suppresses the diffusion of hydrogen is preferably used between a region where the transistor 600 is provided and a region where the transistor 550 is provided. Specifically, the insulator that suppresses the diffusion of hydrogen is an insulator from which the amount of hydrogen released is small.

[0314] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0315] A conductor 328 is embedded in the insulators 320 and 322. A conductor 330 is embedded in the insulators 324 and 326.

[0316] Each of the conductor 328 and the conductor 330 functions as a plug or a wiring.

[0317] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in Fig. 25, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is embedded in the insulator 350, the insulator 352, and the insulator 354.

[0318] The conductor 356 functions as a plug or wiring. For example, the same material as the conductor 328 or the conductor 330 can be used as the conductor 356. In particular, it is preferable to use a conductor having a barrier property against hydrogen.

[0319] The insulators 350, 352, and 354 can be made of materials similar to those of the insulators 324, 322, and 326. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0320] Here, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the region in which the transistor 550 is provided can be separated from the outside of the region by the conductor having a barrier property against hydrogen. Therefore, diffusion of hydrogen to the outside of the region in which the transistor 550 is provided can be suppressed.

[0321] For example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. Alternatively, tantalum nitride and tungsten having high conductivity may be stacked. By using a stack of tantalum nitride and tungsten as the conductor, the conductor can suppress the diffusion of hydrogen while maintaining the conductivity as a wiring.

[0322] That is, by forming the conductor 356 as a stack of tantalum nitride and tungsten, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer of the conductor 356 having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0323] Note that although the wiring layer including the conductor 356 has been described here, the present invention is not limited to this. A wiring layer including the conductor 356 does not necessarily have to be provided, and two or more wiring layers similar to the wiring layer including the conductor 356 may be provided.

[0324] Note that the transistor 550 illustrated in FIG. 25 is just an example and is not limited to this configuration.

[0325] [Transistor 500] The transistor 500 will now be described.

[0326] Fig. 27(A) is a top view of the transistor 500. Fig. 27(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Fig. 27(A), and is also a cross-sectional view of the transistor 500 in the channel length direction (illustrated as the X direction). Fig. 27(C) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Fig. 27(A), and is also a cross-sectional view of the transistor 500 in the channel width direction (illustrated as the Y direction). Note that some elements are omitted from the top view of Fig. 27(A) for clarity.

[0327] The transistor 500 is a so-called planar type transistor, and has a structure that makes it easier to increase the channel length compared to a vertical transistor such as the above-mentioned transistor 600. Therefore, for example, the structure makes it easy to reduce short channel effects such as drain induced barrier lowering (DIBL). In other words, the structure makes it easy to realize a transistor with high saturation (small change in drain current with respect to drain voltage in the saturation region of the transistor).

[0328] Therefore, for example, when the transistor 500 is applied to a memory device, it may be used as a transistor constituting a sense amplifier for reading data from a memory cell included in the memory device. That is, for example, in the memory device 100 described in the above-described embodiment 1, the transistor may be used as at least a part of the transistors constituting the peripheral circuit 120. Also, for example, in the memory device 700 described in the above-described embodiment 1, the transistor may be used as at least a part of the transistors constituting the peripheral circuit portion 722.

[0329] As shown in FIGS. 27B and 27C, an insulator 514 and an insulator 516 are stacked in this order on an insulator 512.

[0330] It is preferable that any one of the insulators 512, 514, and 516 be an insulator that has barrier properties against oxygen, hydrogen, and the like.

[0331] The insulator 514 is preferably an insulator having a barrier property that prevents impurities such as hydrogen from diffusing from the outside of the region where the transistor 500 is provided to the region where the transistor 500 is provided. The insulator 514 can be, for example, a material similar to the above-described insulator 324.

[0332] As an insulator having a barrier property against hydrogen, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0333] In particular, aluminum oxide has a high barrier property against both oxygen and impurities such as hydrogen and water. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 500 during and after the transistor manufacturing process, and can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0334] By applying a material with a relatively low dielectric constant to the insulators 512 and 516, the parasitic capacitance generated between the wirings can be reduced. For the insulators 512 and 516, for example, the same material as the above-described insulator 326 can be used.

[0335] As shown in FIGS. 27(B) and 27(C), the transistor 500 includes a conductor 503 disposed so as to be embedded in the insulators 514 and 516, an insulator 522 disposed on the insulators 516 and the conductor 503, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an insulator 545 disposed along the opening, and a conductor 560 disposed on the formation surface of the insulator 545.

[0336] Note that the oxides 530a and 530b may be collectively referred to as an oxide 530.

[0337] The oxide 530 functions as a semiconductor film including the channel formation region of the transistor 500.

[0338] The conductor 503 is disposed so as to overlap with the oxide 530 and the conductor 560.

[0339] Here, the conductor 503 preferably has a conductor 503a provided in contact with the insulator 514 and the insulator 516, and a conductor 503b provided so as to be embedded inside the conductor 503a. It is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545, and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable that an insulator 582 is disposed over the insulator 580, the conductor 560, and the insulator 545.

[0340] 27B and 27C, the conductor 503 has a two-layer structure including the conductor 503a and the conductor 503b, but the present invention is not limited to this structure. For example, the conductor 503 may have a single-layer structure or a stacked structure including three or more layers.

[0341] Although the configuration in which the ends of the conductor 542a and the conductor 542b are aligned with the end of the oxide 530 is shown, the present invention is not limited to this. For example, the conductor 542a and the conductor 542b may extend beyond the end of the oxide 530.

[0342] Although the oxide 530 has a structure in which two layers, the oxide 530a and the oxide 530b, are stacked, the present invention is not limited thereto. For example, the oxide 530 may have a single layer structure or a structure in which three or more layers are stacked.

[0343] Although the conductor 560 has a configuration in which two layers, conductor 560a and conductor 560b, are stacked, the present invention is not limited to this. For example, the conductor 560 may have a single layer configuration, or may have a configuration in which three or more layers are stacked.

[0344] Here, in the transistor 500, the conductor 560 functions as a gate electrode, the insulator 545 functions as a gate insulating film, and the conductor 542a and the conductor 542b function as one or the other of a source electrode or a drain electrode, respectively.

[0345] As described above, the conductor 560 is formed so as to be embedded in an opening (sometimes called an opening of the insulator 580) formed in a region of the insulator 580 between the conductor 542a and the conductor 542b. Thus, the arrangement of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. With this configuration, the conductor 560 can be formed without providing a margin for alignment. Therefore, the area occupied by the transistor 500 can be reduced. Thus, the semiconductor device can be miniaturized and highly integrated.

[0346] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a and the conductor 542b. This makes it possible to reduce parasitic capacitance formed between the conductor 560 and the conductor 542a and the conductor 542b. As a result, the switching speed of the transistor 500 can be improved. As a result, the frequency characteristics of the semiconductor device can be improved.

[0347] Furthermore, in miniaturizing a semiconductor device, it is necessary to shorten the gate length of the transistor 500, but at the same time, it is necessary to prevent the conductivity of the conductor 560 from decreasing. If the thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. Thus, by providing the conductor 560 so as to be embedded in the opening of the insulator 580, the conductor 560 with a shape with a high aspect ratio can be formed without collapsing during the process.

[0348] Here, the conductor 560 may function as a first gate (also simply referred to as a gate) electrode, and the conductor 503 may function as a second gate (also referred to as a back-gate) electrode. In this case, the insulator 545 functions as a first gate insulating film, and the insulators 522 and 524 function as second gate insulating films.

[0349] As described above, the conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.

[0350] In this case, in the transistor 500, for example, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-current can be reduced. Therefore, for example, by applying a negative potential to the conductor 503, the drain current (sometimes referred to as cutoff current) when the potential applied to the conductor 560 is 0 V can be reduced.

[0351] In this specification, the structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification can be said to have a structure different from the Fin type structure and the planar type structure. On the other hand, the S-channel structure disclosed in this specification can be regarded as a type of Fin type structure or a type of planar type structure. In this specification, the Fin type structure refers to a structure in which the gate electrode is arranged so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the Fin type structure and the S-channel structure, a transistor with improved resistance to the short channel effect can be obtained. In other words, a transistor in which the short channel effect is unlikely to occur can be obtained.

[0352] By making the transistor have the above-mentioned S-channel structure, the channel formation region can be electrically surrounded by the electric field of the gate electrode. Since the S-channel structure is a structure in which the channel formation region is electrically surrounded by the electric field of the gate electrode, it can be said that the S-channel structure is substantially the same as a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. By making the transistor have the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the semiconductor film and the gate insulating film can be the entire bulk of the semiconductor film. Therefore, it is possible to improve the density of the current flowing through the transistor, and therefore it is possible to improve the on-current of the transistor or the field effect mobility of the transistor.

[0353] As described above, the conductor 503 has the conductor 503a formed in contact with the insulators 514 and 516, and the conductor 503b formed further inside.

[0354] The conductor 503a is preferably made of a conductive material that has barrier properties against impurities such as hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules), water, and copper (has the function of suppressing the diffusion of the impurities; in other words, the impurities are unlikely to permeate). The conductor 503a is preferably made of a conductive material that has barrier properties against oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (has the function of suppressing the diffusion of oxygen; in other words, the impurities are unlikely to permeate). In other words, the conductor 503a preferably has barrier properties against any one or all of the above impurities and the above oxygen.

[0355] In this way, since the conductor 503a has a barrier property against oxygen, for example, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 503b, and thus the conductor 503 can also function as a wiring.

[0356] In this case, it is preferable to use a conductive material having high conductivity as the conductor 503b, for example, a conductive material containing tungsten, copper, or aluminum as a main component.

[0357] Note that the transistor 500 may have a structure without the conductor 503 (that is, a structure without a backgate).

[0358] Here, it is preferable to use an insulator containing more oxygen than the amount of oxygen required for the stoichiometric composition as the insulator in contact with the oxide 530. The oxygen is easily released from the insulator by heating. Note that in this specification and the like, oxygen released by heating may be referred to as "excess oxygen."

[0359] The insulator 524 is in contact with the oxide 530. Therefore, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region").

[0360] In this way, by providing an insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O :oxygen vacancy) can be reduced, thereby improving the reliability of the transistor 500.

[0361] Here, an oxide semiconductor that can be used for the oxide 530 will be described. The oxide semiconductor includes a metal oxide.

[0362] The metal oxide preferably contains at least one of indium and zinc. For example, it is preferable to have indium, M (wherein M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, it is preferable that M is one or more selected from gallium, aluminum, yttrium, and tin.

[0363] In particular, as the metal oxide, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO"). Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used. Alternatively, an oxide containing indium (In), tin (Sn), and zinc (Zn) (also referred to as "ITZO (registered trademark)") may be used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (also referred to as "IGZTO") may be used.

[0364] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in a metal oxide, a transistor using the metal oxide for a semiconductor film including a channel formation region can have excellent characteristics, such as a large on-state current, high field-effect mobility, and high frequency characteristics.

[0365] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of the atomic ratio of metal elements in such In-M-Zn oxides include a composition of In:M:Zn=1:1:1 or thereabout, In:M:Zn=1:1:1.2 or thereabout, In:M:Zn=2:1:3 or thereabout, In:M:Zn=3:1:2 or thereabout, In:M:Zn=4:2:3 or thereabout, In:M:Zn=4:2:4.1 or thereabout, In:M:Zn=5:1:3 or thereabout, In:M:Zn=5:1:6 or thereabout, In:M:Zn=5:1:7 or thereabout, In:M:Zn=5:1:8 or thereabout, In:M:Zn=6:1:6 or thereabout, or In:M:Zn=5:2:5 or thereabout, etc. In the In-M-Zn oxide, the atomic ratio of In may be smaller than the atomic ratio of M. The atomic ratio of metal elements in such an In-M-Zn oxide may be, for example, In:M:Zn=1:3:2 or a composition close thereto, or In:M:Zn=1:3:4 or a composition close thereto, etc. Note that a composition close thereto includes a range of plus or minus 30% of the desired atomic ratio.

[0366] For example, when describing a composition with an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, it includes cases where, when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When describing a composition with an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, it includes cases where, when In is 5, Ga is more than 0.1 and 2 or less, and Zn is more than 5 and 7 or less. When describing a composition with an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, it includes cases where, when In is 1, Ga is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0367] In addition, when metal oxides are used in a laminated structure, for example, a three-layer laminate structure may be used in which the first layer is a metal oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1, the second layer is a metal oxide having an atomic ratio of metal elements of In:Zn=4:1, and the third layer is a metal oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1. Note that it is preferable to configure the band gaps of the metal oxides of the first and third layers to be larger than the band gap of the metal oxide of the second layer. This configuration allows the main current path to be the metal oxide of the second layer, resulting in a so-called buried channel structure.

[0368] For the analysis of the composition of the metal oxide, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, these methods may be combined in multiple ways for analysis. Note that for elements with low content, due to the influence on the analysis accuracy, the actual content and the content obtained by analysis may be different. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0369] For the formation of the metal oxide, a sputtering method or an atomic layer deposition (ALD) method can be used. Note that when the metal oxide is formed by the sputtering method, the composition of the formed metal oxide may be different from the composition of the sputtering target. In particular, for zinc, the content in the formed metal oxide may decrease to about 50% compared with the sputtering target.

[0370] The oxide semiconductor preferably has crystallinity. Examples of the oxide semiconductor having crystallinity include c-axis aligned crystalline oxide semiconductor (CAAC-OS), nanocrystalline oxide semiconductor (nc-OS), polycrystalline oxide semiconductor, or single crystal oxide semiconductor. As the oxide semiconductor, it is preferable to use CAAC-OS or nc-OS, and it is particularly preferable to use CAAC-OS.

[0371] The CAAC-OS preferably has multiple layered crystal regions with c-axes oriented in the normal direction to the surface on which it is formed. For example, the oxide semiconductor preferably has layered crystals parallel to the surface on which it is formed. With this structure, the layered crystals of the oxide semiconductor are formed parallel to the channel length direction of the transistor, and therefore the on-state current of the transistor can be increased.

[0372] Note that in one embodiment of the present invention, in a method for forming an oxide semiconductor, the CAAC-OS, which is an oxide semiconductor with high crystallinity, can be used as a nucleus or seed to increase the crystallinity of oxide semiconductors formed above and below the CAAC-OS. This can increase the crystallinity of the entire oxide semiconductor. In other words, the oxide semiconductors formed above and below the CAAC-OS can be grown in a solid phase using the CAAC-OS as a nucleus or seed to form an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can be referred to as an axial growth CAAC (AG CAAC).

[0373] By increasing the crystallinity of an oxide semiconductor, a transistor including the oxide semiconductor in a semiconductor film including a channel formation region can have excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), and a transistor with high reliability).

[0374] Note that a treatment for improving the crystallinity of the oxide semiconductor is preferably performed during or after the formation of the oxide semiconductor. Examples of the treatment for improving the crystallinity of the oxide semiconductor include a heat treatment, a plasma treatment, a microwave (typically, 2.45 GHz) treatment, a microwave plasma treatment, and a light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or in sequence. For example, a heat treatment and a microwave plasma treatment can be performed simultaneously. Alternatively, a microwave plasma treatment can be performed after the heat treatment.

[0375] In this specification, microwave refers to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Also, microwave plasma processing refers to processing using a device having a power source that generates high-density plasma using microwaves, for example. Also, microwave plasma processing can be called microwave-excited high-density plasma processing.

[0376] It is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor several times during the formation of the oxide semiconductor. For example, when the oxide semiconductor film is formed by an ALD method, it is preferable to perform the microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor film having a thickness in a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that there is no particular limitation on the method for forming the first oxide semiconductor film and the second oxide semiconductor film, and the ALD method or the sputtering method may be used, respectively. In particular, it is preferable to form the first oxide semiconductor film by an ALD method, in order to prevent elements of a layer constituting a surface to be formed from being mixed (also referred to as mixing) into the first oxide semiconductor film and the second oxide semiconductor film. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Although a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is illustrated here, the present invention is not limited to this. The same treatment can be applied to the oxide semiconductor film having a single layer or a stacked structure of three or more layers.

[0377] Treatment for increasing the crystallinity of an oxide semiconductor may be performed after the oxide semiconductor is formed. Specifically, the treatment may be performed directly on the oxide semiconductor after the formation, or may be performed through another film, such as an insulating film, formed on the oxide semiconductor. For example, a microwave plasma treatment may be performed after the oxide semiconductor is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor is formed, and then a heat treatment or a microwave plasma treatment may be performed on the oxide semiconductor through the insulating film.

[0378] Note that the above-described treatment for improving the crystallinity of an oxide semiconductor can also serve as a treatment for removing impurities contained in the oxide semiconductor. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor can be preferably removed. Alternatively, by performing the treatment for improving the crystallinity of an oxide semiconductor in an oxygen gas atmosphere, oxygen vacancies (V O It can reduce oxygen vacancy.

[0379] When the treatment to enhance the crystallinity of the oxide semiconductor is performed, the temperature of the substrate is preferably set to room temperature (for example, 25° C.) or higher, or to a range of from 100° C. to 600° C., or from 300° C. to 450° C. The temperature of the heat treatment is preferably set to a range of from 100° C. to 700° C., or from 300° C. to 450° C.

[0380] By increasing the crystallinity of an oxide semiconductor, a highly reliable transistor can be provided.

[0381] The crystallinity of the oxide semiconductor can be analyzed by, for example, an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern, or by a combination of these techniques.

[0382] Note that it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Hydrogen in the oxide semiconductor combines with oxygen vacancies to form defects in which hydrogen enters the oxygen vacancies (also referred to as V O H), which may deteriorate transistor characteristics (for example, the Id-Vg characteristics of an initial transistor or the Id-Vg characteristics in a long-term reliability test). Therefore, as a material surrounding the oxide semiconductor, for example, a material used for an insulator in contact with the oxide semiconductor, it is preferable to use a material with little hydrogen emission. Examples of the material with little hydrogen emission include silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and the like. Thereby, the incorporation of hydrogen into the oxide semiconductor can be suppressed. In particular, when silicon nitride is used for at least one of the insulators in contact with the oxide semiconductor, the reliability of the transistor can be improved. Note that a material with little hydrogen emission may have a function of capturing or fixing hydrogen inside the insulator (also referred to as gettering).

[0383] Note that in the oxide 530, V O H may function as a donor and electrons as carriers may be generated. Also, in some cases, a part of hydrogen combines with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat or an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, it is preferable to reduce V O H in the oxide 530 as much as possible to make it highly pure intrinsic or substantially highly pure intrinsic.

[0384] Thus, in order to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as hydrogen and water in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygen addition treatment"). For example, V OBy using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0385] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a barrier property against oxygen. When the insulator 522 has a barrier property against oxygen, for example, the insulator 522 can prevent oxygen contained in the oxide 530 from diffusing toward the insulator 516. In addition, for example, the conductor 503 can be prevented from reacting with oxygen contained in the insulator 524, the oxide 530, and the like.

[0386] In a transistor using an oxide semiconductor for a semiconductor film, it is preferable that a channel formation region of the transistor has fewer oxygen vacancies or a lower impurity concentration (for example, the concentration of hydrogen, nitrogen, metal elements, and the like) than the source and drain regions. O H may be formed and electrons may be generated as carriers, so V O It is also preferable that H is small. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0387] In addition, the source and drain regions of the transistor have more oxygen vacancies than the channel formation region. O It is preferable that the amount of H is large or the impurity concentration is high. In this manner, the source region and the drain region of the transistor are n-type regions having a higher carrier concentration and a lower resistance than the channel formation region.

[0388] The band gap of the metal oxide used as the oxide semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap as the oxide semiconductor, the off-state current of the transistor can be reduced.

[0389] The insulator 522 is preferably made of a high dielectric constant (high-k) material (material with a high relative dielectric constant).

[0390] As transistors become more miniaturized and highly integrated, problems such as gate leakage current can occur due to thinner gate insulating films. By using high-k materials as the insulators that function as gate insulating films, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0391] Examples of insulators that function as gate insulating films include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO 3 ), or an insulator including barium strontium titanate (BST), is preferably used in a single layer or a laminated layer.

[0392] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, in terms of the insulator having a barrier property against oxygen, impurities, etc. As the insulator, it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0393] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Furthermore, these insulators may be used after being subjected to a nitriding treatment. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on these insulators.

[0394] By forming the insulator 522 using such a material, the insulator 522 can function as an insulator that prevents oxygen from being released from the oxide 530 and prevents impurities such as hydrogen from being mixed into the oxide 530 from the periphery of the transistor 500.

[0395] 27B and 27C show a structure in which two layers of the insulator 522 and the insulator 524 are stacked as the second gate insulating film; however, the present invention is not limited to this. For example, the second gate insulating film may have a single-layer structure or a stacked structure of three or more layers. In this case, the second gate insulating film may have a structure in which the same materials are stacked, or a structure in which different materials are stacked.

[0396] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used as a single layer or a stacked layer for the oxide 530 including a channel formation region. For example, any of the semiconductors that can be used for the oxide 650 described above may be used for the oxide 530. Note that the semiconductor that can be used for the oxide 530 is not limited to a metal oxide.

[0397] In the oxide 530, by providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0398] The oxide 530 preferably has a configuration of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0399] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0400] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b may be lowered.

[0401] Specifically, by having (as a main component) a common element other than oxygen in the oxide 530a and the oxide 530b, a mixed layer with a low defect level density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, an In-Ga-Zn oxide, a Ga-Zn oxide, or gallium oxide may be used as the oxide 530a.

[0402] At this time, the main path of carriers becomes the oxide 530b. By configuring the oxide 530a as described above, the defect level density at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-current of the transistor 500 can be increased.

[0403] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode or a drain electrode are provided.

[0404] As the conductor 542a and the conductor 542b, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, an alloy containing these metal elements, or an alloy combining these metal elements, can be used. In particular, it is preferable to use, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, in that it has a barrier property against oxygen and hydrogen, for example, a metal nitride film such as tantalum nitride is used.

[0405] 27B and 27C show a structure in which the conductor 542a and the conductor 542b are single layers, but the present invention is not limited to this structure. For example, the conductor 542a and the conductor 542b may each have a stacked structure of two or more layers.

[0406] The conductor 542a and the conductor 542b may be, for example, a configuration in which a tantalum nitride film and a tungsten film are stacked, a configuration in which a titanium film and an aluminum film are stacked, a configuration in which an aluminum film is stacked on a tungsten film, a configuration in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a configuration in which a copper film is stacked on a titanium film, or a configuration in which a copper film is stacked on a tungsten film.

[0407] In addition, for example, a three-layer structure in which an aluminum film or copper film is laminated on a titanium film or titanium nitride film, and a titanium film or titanium nitride film is further laminated on that, or a three-layer structure in which an aluminum film or copper film is laminated on a molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further laminated on that, etc. may be used.

[0408] Note that the conductor 542a and the conductor 542b may be formed using a transparent conductive material containing, for example, indium oxide, tin oxide, or zinc oxide.

[0409] 27B, in the oxide 530, a region 543a may be formed as a low-resistance region at the interface with the conductor 542a and in its vicinity. In addition, in the oxide 530, a region 543b may be formed as a low-resistance region at the interface with the conductor 542b and in its vicinity. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. In addition, a channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0410] In this manner, by providing the conductor 542a and the conductor 542b so as to be in contact with the oxide 530, the oxygen concentration in the regions 543a and the regions 543b may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a and the conductor 542b and a component of the oxide 530 may be formed in the regions 543a and the regions 543b. In such a case, the carrier concentration in the regions 543a and the regions 543b increases, and the regions 543a and the regions 543b become low-resistance regions.

[0411] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover a side surface of the oxide 530 and a side surface of the insulator 524 and to be in contact with the insulator 522.

[0412] For example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used as the insulator 544. In addition, for example, silicon nitride oxide or silicon nitride can also be used.

[0413] Alternatively, an insulator containing an oxide of one or both of aluminum and hafnium may be used. For example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) may be used. In particular, it is preferable to use hafnium aluminate, for example, in that it has high heat resistance and is unlikely to crystallize in a heat treatment in a later process.

[0414] Note that when the conductor 542a and the conductor 542b are made of a material that is resistant to oxidation or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not necessarily provided.

[0415] The insulator 544 can prevent impurities such as hydrogen and water contained in the insulator 580 from diffusing into the oxide 530b. The insulator 580 can also prevent the conductor 542a and the conductor 542b from being oxidized by excess oxygen contained in the insulator 580.

[0416] It is preferable to use an insulator that contains excess oxygen and releases oxygen when heated, similar to the above-described insulator 524, as the insulator 545. In this way, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b.

[0417] Specifically, for example, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies can be used as the insulator 545. In particular, it is preferable to use silicon oxide or silicon oxynitride in terms of their thermal stability.

[0418] As the insulator 545, an insulator with a reduced concentration of impurities such as hydrogen and water is preferably used, similar to the above-described insulator 524. Note that the thickness of the insulator 545 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

[0419] Here, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably has a barrier property against oxygen. This suppresses diffusion of excess oxygen from the insulator 545 to the conductor 560. Thus, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, for example, a material that can be used for the insulator 544 may be used.

[0420] 27B and 27C show a structure in which the insulator 545 is a single layer; however, the present invention is not limited thereto. For example, the insulator 545 functioning as the first gate insulating film may have a stacked structure of two or more layers, similar to the insulators 522 and 524 functioning as the second gate insulating films. For example, the insulator 545 may have a stacked structure of a high-k material and a thermally stable material. This makes it possible to reduce the gate voltage during operation of the transistor 500 while maintaining the physical film thickness of the insulator 545.

[0421] The conductor 560a of the conductor 560 may be, for example, hydrogen, water, nitrogen, or nitrogen oxide (e.g., N 2 O, NO, or NO2 It is preferable to use a conductive material that has a barrier property against impurities such as copper and the like. It is also preferable to use a conductive material that has a barrier property against oxygen. When the conductor 560a has a barrier property against oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and the conductivity from decreasing.

[0422] As the conductive material having a barrier property against oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

[0423] The conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making the conductor 560a a conductor. This can be called an OC (Oxide Conductor) electrode.

[0424] The conductor 560 can also function as a wiring. Therefore, it is preferable to use a conductive material with high conductivity as the conductor 560b, similar to the conductor 503b. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used.

[0425] The conductor 560b may be configured by laminating different materials, for example, by laminating titanium or titanium nitride and the above-mentioned conductive material.

[0426] An insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween.

[0427] The insulator 580 preferably has regions of excess oxygen.

[0428] As the insulator 580, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin can be used. In particular, it is preferable to use silicon oxide or silicon oxynitride in terms of thermal stability. Furthermore, it is preferable to use silicon oxide or silicon oxide having voids in terms of an excess oxygen region that can be easily formed in a later step.

[0429] By providing the insulator 580 having an excess oxygen region, oxygen is released by heating, and the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the insulator 580 preferably has a reduced concentration of impurities such as hydrogen and water.

[0430] The insulator 582 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 545. By forming the insulator 582 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0431] The insulator 582 may be, for example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0432] In particular, aluminum oxide has high barrier properties against impurities such as hydrogen, and even a thin film of 0.5 nm to 3.0 nm can suppress the diffusion of impurities such as hydrogen. Therefore, aluminum oxide formed by sputtering not only functions as an oxygen source, but also functions as an insulator with barrier properties against impurities such as hydrogen.

[0433] It is preferable to provide an insulator 584 that functions as an interlayer film on the insulator 582. The insulator 584 preferably has a reduced concentration of impurities such as hydrogen and water, similar to the insulator 524, for example.

[0434] Conductors 540a and 540b are provided in the openings formed in the insulator 584, the insulator 582, the insulator 580, and the insulator 544. At this time, the conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductor 546 described later.

[0435] An insulator 586 is provided on the insulator 584.

[0436] As the insulator 586, it is preferable to use an insulating material having barrier properties against oxygen and hydrogen. As the insulator 586, for example, the same material as the insulator 514 can be used.

[0437] An insulator 588 is provided on the insulator 586.

[0438] By using, for example, a material having a relatively low dielectric constant as the insulator 588, the parasitic capacitance generated between the wirings can be reduced. As the insulator 588, for example, the same material as the insulator 512 or the insulator 516 can be used.

[0439] For example, a conductor 546 or the like is embedded in the insulator 580, the insulator 582, the insulator 584, and the insulator 586. Also, for example, a conductor 548 or the like is embedded in the insulator 588.

[0440] Each of the conductor 546 and the conductor 548 has a function as a plug or a wiring.

[0441] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator having a high barrier property against hydrogen and water may be formed to cover the opening. By surrounding the transistor 500 with the insulator having the high barrier property, hydrogen and water can be prevented from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by an insulator having a high barrier property against hydrogen and water. When an opening is formed to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 may be formed, and the insulator having a high barrier property may be formed to be in contact with the insulator 522 or the insulator 514. In this way, the manufacturing process of the transistor 500 can be performed as a part of the manufacturing process. As the insulator having a high barrier property against hydrogen and water, for example, a material similar to the insulator 522 or the insulator 514 may be used.

[0442] Note that the transistor 500 illustrated in FIGS. 27A to 27C is just an example and is not limited to this structure.

[0443] [Transistor 500F] 28 to 32, examples of the configuration of a transistor different from that of the transistor 500 will be described. FIG. 28(A) is a top view of the transistor 500F. FIG. 28(B) is a perspective schematic view of the transistor 500F. FIG. 28(C) to FIG. 28(E) are cross-sectional views of the transistor 500F. FIG. 28(C) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 28(A), and is also a cross-sectional view of the transistor 500F in the channel width direction (Y direction here). FIG. 28(D) is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 28(A), and is also a cross-sectional view of the transistor 500F in the channel width direction. FIG. 28(E) is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 28(A), and is also a cross-sectional view of the transistor 500F in the channel length direction (X direction here). Here, the dashed line A5-A6 is perpendicular to the dashed line A1-A2 and the dashed line A3-A4, and the dashed line A1-A2 and the dashed line A3-A4 are parallel to each other. Note that some components are omitted in the top view of FIG. 28(A) and the schematic perspective view of FIG. 28(B). FIG. 29(A) shows an enlarged view of the vicinity of the conductor 560 in FIG. 28(E). FIG. 29(B) shows an enlarged view of the vicinity of the oxide 530 in FIG. 28(C).

[0444] The transistor 500F has a configuration that allows the channel width to be increased without significantly increasing the occupation area compared to the transistor 500. That is, the on-current can be increased without significantly increasing the occupation area.

[0445] Therefore, for example, by applying the transistor 500F to a memory device, the operation speed of the memory device can be improved, such as by improving the speed at which data is read from and written to memory cells in the memory device. That is, for example, the transistor 500F may be used for at least a part of the transistors constituting the peripheral circuit 120 in the memory device 100 described in the above-described embodiment 1. Also, for example, the transistor 500F may be used for at least a part of the transistors constituting the peripheral circuit portion 722 in the memory device 700 described in the above-described embodiment 1.

[0446] The transistor 500F includes an insulator 514 on a substrate (not shown), an insulator 516 on the insulator 514, an insulator 521 on the insulator 516, an insulator 522 on the insulator 521, an oxide 530 on the insulator 522, a conductor 542a and a conductor 542b on the oxide 530 and the insulator 522, an insulator 545 on the oxide 530, and a conductor 560 (conductor 560a and conductor 560b) on the insulator 545. Note that in this specification and the like, the conductor 542a and the conductor 542b may be collectively referred to as the conductor 542.

[0447] An insulator 544 is provided on the conductor 542, and an insulator 580 is provided on the insulator 544. The insulator 545 and the conductor 560 are provided inside a first opening that penetrates the insulator 580 and the insulator 544 and reaches the oxide 530. The first opening has a region that overlaps with the oxide 530 and a region that extends along the channel width direction beyond the end of the oxide 530 in a top view. Therefore, the insulator 545 and the conductor 560 provided inside the first opening also have a region that overlaps with the oxide 530 and a region that extends along the channel width direction beyond the end of the oxide 530 in a top view. The conductor 560 also functions as a wiring. The insulator 545 has a region that contacts the oxide 530 in the first opening. In addition, an insulator 582 is provided on the insulator 580 and the conductor 560. In addition, an insulator 584 is provided on the insulator 582.

[0448] Further, insulator 541a is provided in contact with the side surface of the second opening which penetrates insulator 584, insulator 582, insulator 580, and insulator 544 to reach conductor 542a, and conductor 540a is provided in contact with insulator 541a. Conductor 540a has a region in contact with conductor 542a at the bottom of the first opening.

[0449] Furthermore, insulator 541b is provided in contact with the side surface of a third opening which penetrates insulator 584, insulator 582, insulator 580, and insulator 544 to reach conductor 542b, and conductor 540b is provided in contact with insulator 541b. Conductor 540b has a region in contact with conductor 542b at the bottom of the second opening.

[0450] In this specification and the like, conductor 540a and conductor 540b may be collectively referred to as conductor 540. Furthermore, insulator 541a and insulator 541b may be collectively referred to as insulator 541.

[0451] The oxide 530 includes a channel formation region of the transistor 500F. The conductor 560 has a region that functions as a gate electrode of the transistor 500F. The insulator 545 has a region that functions as a gate insulating film of the transistor 500F. In the transistor 500F, a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region. A region of the conductor 560 that overlaps with the oxide 530 functions as a gate electrode. A region of the insulator 545 where the insulator 545 and the oxide 530 overlap and where the insulator 545 and the conductor 560 overlap functions as a gate insulating film.

[0452] The conductor 542a has a region that functions as one of the source electrode or drain electrode of the transistor 500F. The conductor 540a functions as a plug that connects to the conductor 542a. The conductor 542b has a region that functions as the other of the source electrode or drain electrode of the transistor 500F. The conductor 540b functions as a plug that connects to the conductor 542b.

[0453] The oxide 530 is formed on the insulator 522. The oxide 530 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction, as shown in Fig. 29(B) . Therefore, the oxide 530 can also be said to have a fin-like shape.

[0454] In this specification, the maximum value of the length of the oxide 530 in the channel formation region in the channel width direction is defined as length Lx, and the maximum value of the length of the oxide 530 in the channel formation region in the direction perpendicular to the surface on which the oxide 530 is formed (for example, the upper surface of the insulator 522) (here, the Z direction) is defined as length H. In this case, the ratio of the length H to the length Lx is called the aspect ratio of the oxide 530. In addition, the fin-like shape means that the oxide 530 has a high aspect ratio (a shape in which the length H is large relative to the length Lx) in a cross-sectional view in the channel width direction. Here, a transistor in which a semiconductor layer including a channel formation region is fin-shaped may be called a fin transistor, a fin transistor, a fin transistor, or the like.

[0455] The length Lx can also be regarded as the maximum width of the oxide 530 in the channel formation region. Therefore, "length Lx" can be read as "width Lx." The length H can also be regarded as the maximum height of the oxide 530 in the channel formation region. Therefore, "length H" can be read as "height H."

[0456] The aspect ratio of the oxide 530 is preferably as large as possible within a range in which the oxide 530 does not collapse during the manufacturing process of the transistor 500F. The aspect ratio of the oxide 530 may be greater than 1 and less than 400, preferably greater than 2 and less than 100, more preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the oxide 530, the height H of the oxide 530 is preferably at least longer than the length Lx of the oxide 530. The height H of the oxide 530 may be greater than 1 and less than 400 times the length Lx of the oxide 530, preferably greater than 2 and less than 100 times, more preferably greater than 5 and less than 40 times, and even more preferably greater than 10 and less than 20 times. Also, for example, the height H may be greater than 2 and less than 10 times the length Lx. For example, the length Lx may be greater than 5 nm and less than 100 nm, preferably greater than 5 nm and less than 50 nm, and even more preferably greater than 10 nm and less than 30 nm. For example, the height H may be 50 nm or more and 2000 nm or less, and preferably 100 nm or more and 1000 nm or less. For example, the height H may be 50 nm or more and 100 nm or less.

[0457] Furthermore, as shown in FIG. 29B, in a cross-sectional view in the channel width direction, the angle θ between the formation surface of the oxide 530 on the insulator 522 and the side surface of the oxide 530 is preferably perpendicular.

[0458] The insulator 545, the conductor 560, and the conductor 542 are provided to cover the oxide 530 having such an aspect ratio. In the transistor 500F, as shown in FIG. 29B, the insulator 545 and a part of the conductor 560 are provided so as to sandwich the oxide 530 in two. As a result, in a cross-sectional view in the channel width direction, the oxide 530 and the conductor 560 are provided to face each other with the insulator 545 sandwiched between them at the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide 530. In other words, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide 530 function as channel formation regions. Therefore, the channel width of the transistor 500F is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide 530 compared to the case where the oxide 530 is formed in a planar shape.

[0459] By increasing the channel width in this way, the on-current, mutual conductance, frequency characteristics, etc. of the transistor 500F can be improved. As a result, a semiconductor device with a high operating speed can be provided. Also, in the structure of the transistor 500F, the channel width can be increased without increasing the occupied area by providing the oxide 530. Thereby, miniaturization or high integration of the semiconductor device can be achieved.

[0460] Also, as shown in FIG. 29(B) etc., the upper part of the oxide 530 may have a curved shape. By having such a curved shape, it is possible to prevent the formation of defects such as voids in the insulator 545 and the conductor 542 in the vicinity of the upper part of the oxide 530. In FIG. 29(B) etc., a symmetric structure is shown in which a curved shape is provided on both the A1 side and the A2 side of the upper part of the oxide 530, but one aspect of the present invention is not limited to this. For example, there may be an asymmetric structure in which a curved shape is provided on either the A1 side or the A2 side of the upper part of the oxide 530.

[0461] Here, a configuration example is shown in which the oxide 530 has the oxide 530a, the oxide 530b in contact with the oxide 530a, and the oxide 530c in contact with the oxide 530b.

[0462] In this case, for example, the films to be the oxide 530a and the oxide 530c may be formed by atomic layer deposition (ALD), and the film to be the oxide 530b may be formed by sputtering. Specifically, the film to be the oxide 530a may be formed to have a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto. Alternatively, indium oxide may be used for the film to be the oxide 530a. Also, the film to be the oxide 530b may be formed using an oxide target having a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition close thereto. Also, the film to be the oxide 530c may be formed to have a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto. Alternatively, indium oxide may be used for the film to be the oxide 530c.

[0463] Next, a heat treatment is preferably performed in a temperature range in which the oxide 530 is not polycrystallized.

[0464] For example, the heat treatment can be performed at a flow rate ratio of nitrogen gas and oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0465] By forming the oxide 530 by the above method and then performing heat treatment, the oxide 530 can be converted into AG CAAC. As a result, the on-state current, S value, field-effect mobility, frequency characteristics, and the like of the transistor 500F can be improved, and a semiconductor device having favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0466] 29A and 29B, in the case where an oxide semiconductor is used as the oxide 530, the insulator 545 preferably has a stacked structure of an insulator 545a in contact with the oxide 530, an insulator 545b on the insulator 545a, an insulator 545c on the insulator 545b, and an insulator 545d on the insulator 545c. In this case, the insulator 545a and the insulator 545c preferably have a function of capturing hydrogen or fixing hydrogen.

[0467] Examples of insulators having a function of capturing or fixing hydrogen include metal oxides having an amorphous structure. As the insulators 545a and 545c, it is preferable to use metal oxides such as magnesium oxide, or oxides containing one or both of aluminum and hafnium. In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have a property of capturing or fixing hydrogen. That is, it can be said that a metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0468] In addition, it is preferable to use a high-k material for the insulators 545a and 545c. As an example of the high-k material, there is an oxide containing one or both of aluminum and hafnium. By using a high-k material as the insulators 545a and 545c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating film. In addition, it is possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulating film.

[0469] As the insulators 545a and 545c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0470] As the insulator 545a, for example, an aluminum oxide film can be used. Further, the aluminum oxide preferably has an amorphous structure. Here, by providing the insulator 545a in contact with the oxide 530, hydrogen contained in the oxide 530 and the like can be more effectively captured and fixed by the insulator 545a.

[0471] As the insulator 545c, for example, hafnium oxide can be used. Here, by providing the insulator 545c between the insulator 545b and the insulator 545d, hydrogen contained in the insulator 545b or the like can be more effectively captured and fixed.

[0472] Next, it is preferable to use a heat-stable insulator such as silicon oxide or silicon oxynitride for the insulator 545b. The silicon oxide film used as the insulator 545b is preferably formed using the PEALD method.

[0473] In order to suppress the oxidation of the conductor 542a, the conductor 542b, and the conductor 560, it is preferable to provide an oxygen barrier insulator in the vicinity of each of the conductor 542a, the conductor 542b, and the conductor 560. For example, an oxygen barrier insulator may be provided in the insulator 545a, the insulator 545d, the insulator 545c, and the insulator 544.

[0474] In this specification and the like, the barrier insulator refers to an insulator having barrier properties. In this specification and the like, having barrier properties means having a property of preventing the permeation of the corresponding substance (also referred to as low permeability). For example, an insulator having barrier properties has a property that the corresponding substance is difficult to diffuse into the insulator. Also, for example, an insulator having barrier properties has a function of capturing or fixing the corresponding substance inside the insulator (also referred to as gettering).

[0475] Examples of the barrier insulator against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of the oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 545a, 545c, 545d, and 544 are each preferably a single-layer structure or a multilayer structure of a barrier insulator against oxygen.

[0476] The insulator 545a preferably has a barrier property against oxygen. The insulator 545a is preferably at least less permeable to oxygen than the insulator 580. The insulator 545a has a region in contact with the side surface of the conductor 542a and the side surface of the conductor 542b. The insulator 545a having a barrier property against oxygen can suppress the side surfaces of the conductor 542a and the conductor 542b from being oxidized and the formation of an oxide film on the side surface. This can suppress a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500F.

[0477] The insulator 545a is provided in contact with the top surface and side surface of the oxide 530 and the top surface of the insulator 522. The insulator 545a has a barrier property against oxygen, which can suppress desorption of oxygen from a channel formation region of the oxide 530 during heat treatment or the like. Thus, formation of oxygen vacancies in the oxide 530 can be reduced.

[0478] Furthermore, by providing the insulator 545a, an excessive amount of oxygen can be prevented from being supplied from the insulator 580 to the oxide 530, and an appropriate amount of oxygen can be supplied to the oxide 530. As a result, the source and drain regions can be prevented from being excessively oxidized, and a decrease in the on-state current or the field-effect mobility of the transistor 500F can be prevented.

[0479] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen and is therefore suitable as the insulator 545a.

[0480] It is preferable that the insulator 545d also has a barrier property against oxygen. The insulator 545d is provided between the channel formation region of the oxide 530 and the conductor 560 and between the insulator 580 and the conductor 560. With this structure, oxygen contained in the channel formation region of the oxide 530 can be prevented from diffusing to the conductor 560 and forming oxygen vacancies in the channel formation region of the oxide 530. In addition, it is possible to prevent oxygen contained in the oxide 530 and oxygen contained in the insulator 580 from diffusing to the conductor 560 and oxidizing the conductor 560. It is preferable that the insulator 545d is at least less permeable to oxygen than the insulator 580. For example, it is preferable to use a silicon nitride film as the insulator 545d. In this case, the insulator 545d is an insulator containing at least nitrogen and silicon.

[0481] The insulator 545d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the oxide 530.

[0482] It is preferable that the insulator 544 also has a barrier property against oxygen. The insulator 544 is provided between the insulator 580 and the conductor 542a and between the insulator 580 and the conductor 542b. The insulator 544 is provided in contact with the side surface of the conductor 542, the side surface of the oxide 530, and the upper surface of the insulator 522. This configuration can suppress the oxygen contained in the insulator 580 from diffusing into the conductor 542. Therefore, it is possible to suppress the conductor 542 from being oxidized by the oxygen contained in the insulator 580 and the increase in resistivity. It is preferable that the insulator 544 is at least less permeable to oxygen than the insulator 580. For example, it is preferable to use silicon nitride as the insulator 544. In this case, the insulator 544 is an insulator having at least nitrogen and silicon.

[0483] To prevent the hydrogen concentration in the source and drain regions from decreasing in the oxide 530, it is preferable to provide a hydrogen barrier insulator near each of the source and drain regions. For example, the insulator 544 may be provided with a hydrogen barrier insulator.

[0484] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 544 is preferably a single layer or a multilayer structure of a barrier insulator against hydrogen.

[0485] By providing the insulator 544 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, and therefore to suppress a decrease in the hydrogen concentration in the source and drain regions, thereby making it possible to make the source and drain regions n-type.

[0486] By adopting the above-mentioned configuration, the channel formation region can be made i-type or substantially i-type, and the source region and the drain region can be made n-type, and a semiconductor device having good electrical characteristics can be provided. Furthermore, by adopting the above-mentioned configuration, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, by miniaturizing the transistor 500F, high-frequency characteristics can be improved. Specifically, the cutoff frequency can be improved.

[0487] The insulators 545a to 545d function as part of a gate insulating film. The insulators 545a to 545d are provided in an opening formed in the insulator 580 together with the conductor 560. To miniaturize the transistor 500F, the thicknesses of the insulators 545a to 545d are preferably small. The thicknesses of the insulators 545a to 545d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that at least a part of the insulators 545a to 545d may have a region having the above thickness.

[0488] The thickness of the silicon oxide film used as the insulator 545 is preferably 0.7 nm or more and 3 nm or less.

[0489] In order to thin the film thicknesses of the insulators 545a to 545d as described above, it is preferable to form the insulators 545a to 545d by an ALD method. Also, in order to provide the insulators 545a to 545d in openings such as the insulator 580, it is preferable to form the insulators 545 by an ALD method. By forming the insulator 545 by the ALD method, it is possible to form the insulator 545 with good coverage on the side surface of the first opening formed in the insulator 580, the side end of the conductor 542a, and the side end of the conductor 542b, and the like.

[0490] Note that although the insulator 545 has a four-layer structure of insulators 545a to 545d, one embodiment of the present invention is not limited to this. The insulator 545 can have a structure including at least one of the insulators 545a to 545d. When the insulator 545 has a one-layer, two-layer, or three-layer structure of the insulators 545a to 545d, the manufacturing process of the transistor 500F can be simplified and the productivity of a semiconductor device including the transistor 500F can be improved.

[0491] As shown in FIG. 28A, the oxide 530 preferably has a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) in a top view. That is, the oxide 530 preferably has a structure including a portion extending in the channel width direction and a portion extending in the channel length direction. This can prevent the oxide 530 from falling during a manufacturing process of a transistor when the aspect ratio of the oxide 530 is increased. Note that the oxide 530 shown in FIG. 28A can also be referred to as having a shape having an opening in the center. In FIG. 28A, the shape of the oxide 530 in a top view is line-symmetrical about A1-A2, but one embodiment of the present invention is not limited thereto. For example, the shape of the oxide 530 in a top view may be asymmetrical.

[0492] The structure shown in Fig. 28(A) has two peripheral oxides 530 formed in the channel width direction. As shown in Fig. 28(A), it is preferable that the oxide 530 overlaps with the conductor 560 at two or more points when viewed from above. Therefore, it is preferable that the conductor 560 has two or more regions that overlap with the oxide 530. In other words, it is preferable that the oxide 530 and the conductor 560 have two or more regions that overlap with each other.

[0493] With such a structure, as shown in FIG. 28B, a plurality of fin-shaped oxides 530 are formed in a cross-sectional view in the channel width direction. Each of the plurality of fin-shaped oxides 530 includes a channel formation region. That is, the transistor 500F functions as a multi-channel transistor. Therefore, the channel width of the transistor 500F can be further increased, and the on-current can be increased. Therefore, the operating speed of a semiconductor device including the transistor 500F can be increased.

[0494] Note that, although the structure in which two peripheral oxides 530 are provided has been described here, one embodiment of the present invention is not limited thereto. For example, a structure in which one or three or more peripheral oxides 530 are provided may be used. Furthermore, the peripheral oxides 530 may be combined to form an oxide 530 having a shape with a plurality of openings. Moreover, a lattice-shaped oxide 530 may be used when viewed from above.

[0495] It is preferable that the insulators 584, 582, 522, and 521 each have an insulator having a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable that the insulators 584 and 521 use silicon nitride or the like having a higher hydrogen barrier property. For example, it is preferable that the insulator 582 use aluminum oxide or the like having a high ability to capture or fix hydrogen. For example, it is preferable that the insulator 522 use hafnium oxide or the like which is a high-k material and has a high ability to capture or fix hydrogen.

[0496] At least one of the insulators 521 and 522 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulator 521 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 522 can have a stacked structure of hafnium oxide and silicon oxide.

[0497] With such a structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 584 to the transistor 500F. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 521 to the transistor 500F. Furthermore, hydrogen contained in the insulator 580, the insulator 545, and the like can be captured and fixed to the insulator 582 or the insulator 522. Furthermore, the insulators 582 and 584 can prevent oxygen contained in the insulator 580 and the like from diffusing upward from the transistor 500F. Furthermore, the insulators 522 and 521 can prevent oxygen contained in the oxide 530 and the like from diffusing downward from the transistor 500F. In this way, the structure in which the transistor 500F is surrounded from above and below by insulators having a function of preventing the diffusion of impurities such as water and hydrogen and oxygen can reduce the diffusion of excess oxygen and hydrogen to the oxide semiconductor. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0498] The insulators 516 and 580 preferably have a dielectric constant lower than that of the insulator 522. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0499] For example, insulator 516 and insulator 580 each preferably include one or more of silicon oxide, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, and silicon oxide with vacancies.

[0500] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form a region containing oxygen that is desorbed by heating.

[0501] Additionally, the top surfaces of the insulators 516 and 580 may each be planarized.

[0502] The insulator 580 preferably has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 580 preferably has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0503] 30(A) to 30(E), the transistor 500F may be configured to include an insulator 524 under the oxide 530. The planar shape of the insulator 524 (here, the shape when viewed from the Z direction) is similar to that of the oxide 530, and the insulator 524 overlaps with the oxide 530 when viewed from above. The lower surface of the insulator 524 is in contact with the insulator 522, the side surface of the insulator 524 is in contact with the insulator 545 and the conductor 542a, and the upper surface of the insulator 524 is in contact with the lower surface of the oxide 530. The insulator 524 may be formed using an insulating material that can be used for the insulator 545b. For example, silicon oxide can be used as the insulator 524. Here, FIGS. 30(A) to 30(E) correspond to FIGS. 28(A) to 28(E). FIG. 31 corresponds to FIG. 29(B). Regarding the configurations relating to Figures 30(A) to 30(E) and 31 that are not explained below, reference may be made to the explanations relating to Figures 28(A) to 28(E) and 29(B) above.

[0504] 31, it is preferable that film thickness t2 of insulator 545 at the bottom of the first opening be thinner than film thickness t1 (the length in the direction perpendicular to the surface on which insulator 524 is formed) of insulator 524. With this configuration, the lower surface of conductor 560 (conductor 560a) located in the first opening can be positioned lower than the lower surface of oxide 530 by the difference (t1-t2) between film thickness t1 and film thickness t2.

[0505] By disposing the lower surface of the conductor 560 below the lower surface of the oxide 530, a gate electric field can be applied sufficiently from the upper end to the lower end of the oxide 530. In other words, in an opening of the insulator 580 or the like, the entire oxide 530 can be electrically surrounded by the electric field of the conductor 560 and can function as a channel formation region. With this configuration, the lower end of the oxide 530 can be prevented from functioning as a parasitic channel, and the off current between the source electrode and the drain electrode can be reduced. In addition, the normally-on state of the transistor due to the parasitic channel can be suppressed. In other words, the electrical characteristics of the transistor 500F can be improved.

[0506] In addition, as described above, the oxide 530 functions as a channel formation region from the top to the bottom, so that the channel width can be increased. This can improve the on-state current, mutual conductance, frequency characteristics, and the like of the transistor 500F.

[0507] In this specification and the like, the structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is called a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0508] Note that the S-channel structure is a structure that electrically surrounds the channel formation region, and therefore it can be said to be substantially equivalent to a GAA (gate all around) structure or a LGAA (lateral gate all around) structure. By forming the transistor 500F in the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the insulator 545 that functions as a gate insulating film can be the entire bulk of the oxide 530. Therefore, it is possible to improve the current density flowing through the transistor, and therefore it is possible to improve the on-current of the transistor or the field-effect mobility of the transistor. In addition, in one embodiment of the present invention, the oxide 530 has a CAAC structure and a fin-shaped structure. With this structure, the current path flowing through the source and drain of the transistor can be parallel to the ab plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-shaped structure has a conduction path equivalent to that of a two-dimensional semiconductor material. In addition, by using such an oxide semiconductor, a device having two-dimensional conduction can be manufactured.

[0509] 32(A) to 32(E), the transistor 500F may have a structure in which a conductor 503 is provided under an insulator 521. Note that Figures 32(A) to 32(E) correspond to Figures 28(A) to 28(E). For matters not described below regarding the structures in Figures 32(A) to 32(E), the above description of Figures 28(A) to 28(E) can be referred to.

[0510] The conductor 503 has a region that functions as a gate electrode, similar to the conductor 560. The conductor 560 may be referred to as a first gate electrode (upper gate electrode) of the transistor 500F, and the conductor 503 may be referred to as a second gate electrode (lower gate electrode) of the transistor 500F. When the conductor 560 is referred to as a gate electrode of the transistor 500F, the conductor 503 may be referred to as a backgate electrode of the transistor 500F.

[0511] When the transistor 500F has the conductor 503 under the insulator 521, each of the insulators 522 and 521 has a region that functions as a gate insulating film, similar to the insulator 545. Specifically, a region of each of the insulators 522 and 521 that overlaps with the conductor 503 functions as a gate insulating film. The insulator 545 may be referred to as a first gate insulating film (upper gate insulating film), and the insulators 522 and 521 may be referred to as a second gate insulating film (lower gate insulating film).

[0512] In the transistor 500F, the conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. In FIGS. 32C and 32E, the conductor 503 is provided inside the fourth opening that penetrates the insulator 516 and reaches the insulator 514. The fourth opening has a region that overlaps with the oxide 530 and a region that extends along the channel width direction beyond the end of the oxide 530 in a top view. Thus, the conductor 503 provided inside the fourth opening also has a region that overlaps with the oxide 530 and a region that extends along the channel width direction beyond the end of the oxide 530 in a top view. The conductor 503 also functions as a wiring.

[0513] As shown in Figures 32(C) and 32(E), it is preferable that the conductor 503 has a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom and side surfaces of the fourth opening. The conductor 503b is provided so as to fill in a recess of the conductor 503a formed along the bottom and side surfaces of the fourth opening. Here, the height of the upper surface of the conductor 503 coincides with the height of the upper surface of the insulator 516.

[0514] Here, the conductor 503a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 It is preferable to have a conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0515] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 516 or the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 503a, it is possible to suppress the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials having a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 503a can have a single-layer structure or a multilayer structure of the conductive materials described above. For example, the conductor 503a preferably has titanium nitride.

[0516] The conductor 503b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum, for example, the conductor 503b preferably contains tungsten.

[0517] As described above, the conductor 503 can function as the second gate electrode. In this case, the threshold voltage of the transistor 500F can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500F and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential of the conductor 560 is 0 V, compared to not applying a negative potential.

[0518] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match the electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 thin within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, and therefore the diffusion of the impurities into the oxide 530 can be suppressed.

[0519] Note that, although a layered structure of the conductor 503a and the conductor 503b is described here, one embodiment of the present invention is not limited thereto, and the conductor 503 may have a single-layer structure or a layered structure of three or more layers. For example, when the conductor 503 has a layered structure of three layers, in addition to the layered structure of the conductor 503a and the conductor 503b as described above, a conductor having a material similar to that of the conductor 503a may be provided on the conductor 503b. In this case, the conductor described above may be formed so that the top surface of the conductor 503b is lower than the top of the conductor 503a and the recess formed by the conductor 503a and the conductor 503b are filled.

[0520] [Transistor 800] 33A and 33B are cross-sectional views illustrating another transistor that can be used in the memory device of one embodiment of the present invention.

[0521] 33A and 33B illustrate a transistor 800 over an insulator 810, an insulator 880, an insulator 881 over the insulator 880, and the semiconductor device 200 (the transistor 600 and the capacitor 690) over the transistor 800. The insulator 810, the insulator 880, and the insulator 881 function as interlayer films.

[0522] The figure also illustrates a conductor 820, an oxide 830, an insulator 850, and a conductor 860 included in the transistor 800. In the transistor 800, the oxide 830 functions as a semiconductor film including a channel formation region, the conductor 860 functions as a gate electrode, the insulator 850 functions as a gate insulating film, the conductor 820 functions as one of a source electrode and a drain electrode, and the conductor 610 functions as the other of the source electrode and drain electrode. The conductor 610 also functions as the other of the pair of electrodes of the capacitor 690. The conductor 820 and the conductor 860 also function as wirings.

[0523] 33(A) and 33(B) can be applied to, for example, the case where the configuration shown in FIG. 14(A) is used as the driver circuit 123 in the connection example shown in FIG. 12 of the above-mentioned embodiment 1. In this case, the transistor 600 corresponds to the transistor M11, the capacitor 690 corresponds to the capacitor C11, and the transistor 800 corresponds to the transistor M21. In other words, it can be said that the conductor 670 includes a region that functions as the gate of the transistor M11, the conductor 660 includes a region that functions as the other of the source and drain of the transistor M11, the conductor 630 includes a region that functions as one of the source and drain of the transistor M11 and a region that functions as one terminal of the capacitor C11, the conductor 610 includes a region that functions as the other terminal of the capacitor C11 and a region that functions as one of the source and drain of the transistor M21, the conductor 860 includes a region that functions as the gate of the transistor M21, and the conductor 820 includes a region that functions as the other of the source and drain of the transistor M21. 33A to 33B, the conductor 670 corresponds to the wiring WL, the conductor 660 corresponds to the wiring BL, the conductor 610 corresponds to the wiring PL, the conductor 630 corresponds to the wiring SN, the conductor 860 corresponds to the wiring PWL, and the conductor 820 corresponds to the wiring PBL. Note that in Figures 33A to 33B, the parts corresponding to the transistor M11, the capacitor C11, the transistor M21, the wiring WL, the wiring BL, the wiring PL, the wiring SN, the wiring PWL, and the wiring PBL are indicated with reference characters in parentheses.

[0524] 33(A) and 33(B) is a configuration in which the capacitor C11 is stacked on the transistor M21, and the transistor M11 is stacked on the capacitor C11. That is, it can be said that the transistor M21, the capacitor C11, and the transistor M11 are arranged to have overlapping regions when viewed from above. Therefore, for example, in the connection example shown in FIG. 12 of the above-mentioned embodiment 1, when the configuration shown in FIG. 14(A) is used as the driver circuit 123, the configuration shown in FIG. 33(A) and 33(B) can be applied to suppress an increase in the area occupied by providing the driver circuit 123.

[0525] The following describes the transistor 800. Note that the above description of the transistor 600 and the capacitor 690 can be referred to, and therefore description thereof will be omitted here.

[0526] FIG. 34(A) is a top view of a transistor 800. FIG. 34(B) is a cross-sectional view of the transistor 800 corresponding to the portion indicated by the dashed line A1-A2 in FIG. 34(A). FIG. 34(C) is a cross-sectional view of the transistor 800 corresponding to the portion indicated by the dashed line A3-A4 in FIG. 34(A). Note that the dashed line A1-A2 is a straight line parallel to the X direction in the figure, and the dashed line A3-A4 is a straight line parallel to the Y direction in the figure. In the top view, some elements are omitted for clarity. In the subsequent top views, some elements may also be omitted.

[0527] 34B to 34C illustrate the transistor 800 over an insulator 810, an insulator 880, and an insulator 881 over the insulator 880. The insulator 810, the insulator 880, and the insulator 881 function as interlayer films.

[0528] Transistor 800 includes a conductor 820 on an insulator 810, an oxide 830 on the conductor 820, an insulator 850 on an insulator 880, a conductor 860 on the insulator 850, and a conductor 610 on the oxide 830, the insulator 850, and the insulator 881.

[0529] The insulator 880 is provided over the conductor 820 and the insulator 810. The insulator 881 is provided over the insulator 850 and the conductor 860.

[0530] The side surface of the oxide 830 is preferably perpendicular to the top surface of the insulator 810. With such a structure, the transistor 800 can be miniaturized or highly integrated. In this case, the films provided on the outside of the oxide 830 are preferably formed by the ALD method. The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed, films can be formed on structures with high aspect ratios, films can be formed with fewer defects such as pinholes, films can be formed with excellent coverage, and films can be formed at low temperatures. Thus, the film can be formed on the side surface of the oxide 830 with good coverage. For example, the insulator 850 and the conductor 860 are preferably formed by the ALD method.

[0531] When the side surface of the oxide 830 is perpendicular to the upper surface of the insulator 810, the oxide 830 has a cylindrical shape as shown in FIG. 34(B) and FIG. 34(C). The oxide 830 is provided extending in the Z direction. That is, the normal line of the lower surface and the normal line of the upper surface of the oxide 830 are parallel to the Z direction. The lower surface of the oxide 830 contacts a part of the upper surface of the conductor 820, the upper surface of the oxide 830 contacts a part of the lower surface of the conductor 610, and at least a part of the side surface of the oxide 830 contacts the insulator 850. In the configuration shown in FIG. 34(B) and FIG. 34(C), another part of the side surface of the oxide 830 contacts the insulator 880.

[0532] The height of the top surface of oxide 830 coincides with the height of the top surface of insulator 850 and the height of the top surface of insulator 881, respectively.

[0533] The insulator 850 covers at least a part of the side surface of the oxide 830. The insulator 850 has a region in contact with the conductor 610. The insulator 850 has a first region between the oxide 830 and the conductor 860, and a second region between the conductor 820 and the conductor 860. It can be said that the second region is located between the insulator 880 and the conductor 860. In FIG. 34(B), the width of the first region of the insulator 850 in the direction from the oxide 830 toward the conductor 860 (X direction or Y direction) is indicated as W850. Also, the width of the second region of the insulator 850 in the direction from the conductor 820 toward the conductor 860 (Z direction) is indicated as H850. For example, when the insulator 850 is formed by using the ALD method, the width W850 is the same as the width H850.

[0534] The upper surface of the portion of the conductor 860 that runs along the side surface of the oxide 830 is located below (on the insulator 810 side) the upper surface of the oxide 830. The conductor 860 has a first region that faces the side surface of the oxide 830 via the insulator 850, and a second region that overlaps with the conductor 820 via the insulator 850. For example, when the conductor 860 is formed using the ALD method, the width of the first region of the conductor 860 in the X direction or Y direction is the same as the width of the second region of the conductor 860 in the Z direction.

[0535] In the transistor 800 shown in FIGS. 34B and 34C, the conductor 860 is provided to extend in the Y direction, and the conductor 820 is provided to extend in the X direction.

[0536] In transistor 800, oxide 830 functions as a semiconductor film including a channel formation region, conductor 860 functions as a gate electrode, insulator 850 functions as a gate insulating film, conductor 820 functions as one of a source electrode and a drain electrode, and conductor 610 functions as the other of the source electrode and drain electrode.

[0537] The transistor 800 has a configuration in which one of the source electrode and drain electrode (here, the conductor 820) is located on the lower side and the other of the source electrode and drain electrode (here, the conductor 610) is located on the upper side, so that a current flows in the vertical direction. That is, a channel is formed along the side surface of the oxide 830. The transistor 800 also has a structure in which the gate electrode surrounds the channel formation region. Therefore, the transistor 800 can be said to have a GAA (Gate-All-Around) structure.

[0538] The transistor 800 preferably includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in the oxide 830 including a channel formation region. For example, any of the metal oxides that can be used for the oxide 650 described above may be used as the oxide 830. Note that a semiconductor that can be used for the oxide 830 is not limited to a metal oxide.

[0539] Here, the insulator 850 may be, for example, a material that can be used for the insulator 672 described above. The conductor 860 may be, for example, a material that can be used for the conductor 610 described above. The conductor 820 may be, for example, a material that can be used for the conductor 610 described above. The insulator 810 may be, for example, a material that can be used for the insulator 612 described above. The insulators 880 and 881 may be, for example, a material that can be used for the insulator 620 or the insulator 640 described above.

[0540] In the transistor 800, a region of the oxide 830 that is covered by the conductor 860 with the insulator 850 interposed therebetween functions as a channel formation region. A region of the oxide 830 in contact with the conductor 820 functions as one of the source region and the drain region, and a region of the oxide 830 in contact with the conductor 610 functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0541] When the oxide 830 comes into contact with the conductor 820, a metal compound or oxygen vacancy is formed, and the region of the oxide 830 in contact with the conductor 820 has a low resistance. This makes it possible to reduce the contact resistance between the oxide 830 and the conductor 820. Similarly, when the oxide 830 comes into contact with the conductor 610, the region of the oxide 830 in contact with the conductor 610 has a low resistance. This makes it possible to reduce the contact resistance between the oxide 830 and the conductor 610.

[0542] When the conductor 860 functions as a gate electrode, the channel length of the transistor 800 is the length of a region of the oxide 830 that overlaps with the conductor 860 via the insulator 850 in a cross-sectional view. In other words, it can be said that the channel length of the transistor 800 is determined by the height of the conductor 860. In Figure 34(B), the channel length L of the transistor 800 is indicated by a dashed double-headed arrow.

[0543] In the transistor 800, the channel length can be set by the height of the conductor 860. Thus, the channel length L of the transistor 800 can be made to be an extremely fine structure equal to or less than the exposure limit of photolithography (e.g., 0.1 nm to 100 nm, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm). This increases the on-state current of the transistor 800, thereby improving the frequency characteristics.

[0544] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the oxide 830. As a result, the area occupied by the transistor 800 can be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Thus, the transistor 800 can be highly integrated. Furthermore, when the transistor 800 of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased.

[0545] The height of the oxide 830 needs to be greater than the channel length L of the transistor 800. On the other hand, the height of the oxide 830 needs to be large enough so that the oxide 830 processed into a cylindrical shape does not collapse. Therefore, the height of the oxide 830 is, for example, preferably 20 nm to 200 nm, more preferably 50 nm to 200 nm, more preferably 80 nm to 200 nm, more preferably 80 nm to 150 nm, and even more preferably 80 nm to 120 nm.

[0546] Here, FIG. 34(D) shows an enlarged cross-sectional view in the XY plane including the oxide 830, the insulator 850, the conductor 860, and the insulator 881. Note that FIG. 34(D) can also be said to be a cross-sectional view in the XY plane including the channel formation region of the oxide 830. As shown in FIG. 34(D), the insulator 850 and the conductor 860 are provided concentrically. Therefore, the side surface of the oxide 830 provided at the center faces the side surface of the conductor 860 through the insulator 850. That is, in a top view, the entire circumference of the oxide 830 becomes a channel formation region. In this case, for example, the channel width of the transistor 800 is determined by the outer periphery length of the oxide 830. That is, it can be said that the channel width of the transistor 800 is determined by the width of the oxide 830 (the diameter when the oxide 830 is circular in a top view). In FIG. 34(B) and FIG. 34(D), the width D of the oxide 830 is indicated by a double-headed arrow of a two-dot chain line. 34D, the channel width W of the transistor 800 is indicated by a dashed line with a double-headed arrow. By increasing the width D of the oxide 830, the channel width can be increased, and the on-current can be increased.

[0547] When the oxide 830 is formed by photolithography, the width D of the oxide 830 is set by the exposure limit of photolithography. The width D of the oxide 830 can be 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, or 5 nm to 40 nm. When the oxide 830 is circular in top view, the width D of the oxide 830 corresponds to the diameter of the oxide 830, and the channel width W can be calculated as "D x π".

[0548] Thus, the ratio of the height of the oxide 830 to the width D of the oxide 830 can be 0.2 to 40, or 1 to 40, for example.

[0549] The height of the oxide 830 is preferably larger than the width D of the oxide 830. In other words, the width D of the oxide 830 is preferably smaller than the height of the oxide 830. With such a configuration, the transistor 800 can be miniaturized or highly integrated. In addition, when the height of the oxide 830 is increased to increase the channel length L of the transistor 800, the variation in the threshold voltage of the transistor 800 can be reduced. When the height of the oxide 830 is increased to increase the physical distance between the conductor 860 and the conductor 610, the parasitic capacitance generated between the conductor 860 and the conductor 610 can be reduced. Note that the height of the oxide 830 can be set to be the same as the width D of the oxide 830 or smaller than the width D of the oxide 830.

[0550] The channel length L of the transistor 800 can be made shorter than the channel width W of the transistor 800. The channel length L of the transistor 800 is preferably 0.1 to 0.99 times, and more preferably 0.5 to 0.8 times, the channel width W of the transistor 800. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0551] In this embodiment, the oxide 830 has a circular shape when viewed from above, but the present invention is not limited to this. For example, the oxide 830 may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners when viewed from above.

[0552] The insulator 880 is in contact with another part of the side surface of the oxide 830. The insulator 880 is in contact with the top surface and side surface of the conductor 820. The insulator 880 has a region located between the conductor 820 and the insulator 850. The film thickness of the insulator 880 on the conductor 820 is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 30 nm or less, and further preferably 10 nm or more and 20 nm or less. With this configuration, the physical distance between the conductor 820 and the conductor 860 can be increased, and the parasitic capacitance generated between the conductor 820 and the conductor 860 can be reduced.

[0553] The insulator 881 has a region located between the upper surface of the portion of the conductor 860 along the side surface of the oxide 830 and the lower surface of the conductor 610. This configuration can prevent the conductor 860 and the conductor 610 from shorting out. In addition, by increasing the height of the region (the shortest distance from the upper surface of the portion of the conductor 860 along the side surface of the oxide 830 to the lower surface of the conductor 610), the parasitic capacitance generated between the conductor 860 and the conductor 610 can be reduced. The height of the region can be, for example, 5 nm to 50 nm, 5 nm to 30 nm, or 5 nm to 20 nm. The height (film thickness) of the insulator 881 in the region not overlapping with the conductor 860 is the sum of the height of the region and the height (channel length L) of the conductor 860.

[0554] Note that the transistor 800 illustrated in FIGS. 34A to 34D is just an example and is not limited to this structure.

[0555] <Materials that make up the memory device> A material that can be used for a semiconductor device having a transistor and a capacitor is not limited to the above-described examples. In one embodiment of the present invention, in addition to the above-described materials, the following materials can also be used as appropriate.

[0556] 〔substrate〕 Examples of the substrate on which the semiconductor device of one embodiment of the present invention and a memory device including the semiconductor device can be provided include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, or a substrate having tungsten foil), a semiconductor substrate (e.g., a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), or a silicon on insulator (SOI) substrate. A heat-resistant plastic substrate may be used as the substrate. Examples of the glass substrate include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Other examples of the glass substrate include crystallized glass.

[0557] Also, as the substrate, for example, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used. For example, as the flexible substrate, the laminated film, or the base film, there is plastic represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or polytetrafluoroethylene (PTFE). There is also synthetic resin such as acrylic. There is also polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. There is also polyamide, polyimide, aramid resin, epoxy resin, inorganic deposition film, or paper. In particular, by manufacturing a transistor using, for example, a semiconductor substrate, a single crystal substrate, or an SOI substrate, it is possible to manufacture a transistor with less variation in characteristics, size, or shape, high current capacity, and small size. When a circuit is constructed using such transistors, it is possible to reduce the power consumption of the circuit or to increase the integration of the circuit.

[0558] Alternatively, a flexible substrate may be used as the substrate, and one or more of, for example, a transistor, a resistor, and a capacitor may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and one or more of, for example, a transistor, a resistor, and a capacitor. The peeling layer can be used to separate the semiconductor device from the substrate after a part or all of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate. In this case, one or more of the transistor, the resistor, and the capacitor can be transferred to a substrate having poor heat resistance or a flexible substrate. The peeling layer may be, for example, a structure in which an inorganic film of a tungsten film and a silicon oxide film are stacked, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0559] That is, the semiconductor device may be formed on a certain substrate, and then the semiconductor device may be transferred to another substrate. In addition to the substrate on which the transistors described above can be formed, the substrate on which the semiconductor device is transferred may be, for example, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including, for example, natural fibers (silk, cotton, or hemp), synthetic fibers (nylon, polyurethane, or polyester), or regenerated fibers (acetate, cupra, rayon, or regenerated polyester), etc.), a leather substrate, or a rubber substrate. By using these substrates, it is possible to manufacture a semiconductor device having flexibility or to manufacture a semiconductor device that is not easily broken. It is also possible to impart heat resistance to the semiconductor device. It is also possible to reduce the weight or thickness of the semiconductor device.

[0560] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0561] [Ferroelectrics] As an insulator (such as insulator 632) that functions as a dielectric and can be used in a semiconductor device according to one aspect of the present invention, a material that may have ferroelectricity may be used. Examples of materials that may have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, or HfZrO X (where X is a real number greater than 0). Further, examples of materials that may have ferroelectricity include materials obtained by adding element J1 (here, element J1 is one or more selected from, for example, zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium) to hafnium oxide. Note that the ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or in the vicinity thereof. Further, examples of materials that may have ferroelectricity include materials obtained by adding element J2 (here, element J2 is one or more selected from, for example, hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium) to zirconium oxide. Note that the ratio of the number of zirconium atoms to the number of element J2 atoms can be set as appropriate. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or in the vicinity thereof. Further, as a material that may have ferroelectricity, for example, piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0562] In addition, examples of materials that can have ferroelectricity include metal nitrides having an element M1, an element M2, and nitrogen. Here, the element M1 is, for example, one or more selected from aluminum, gallium, and indium. In addition, the element M2 is, for example, one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. The ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be set appropriately. In addition, metal nitrides having the element M1 and nitrogen may have ferroelectricity even if they do not contain the element M2. In addition, examples of materials that can have ferroelectricity include materials in which the element M3 is added to the above metal nitride. Here, the element M3 is, for example, one or more selected from magnesium, calcium, strontium, zinc, and cadmium. The ratio between the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0563] Examples of materials that can have ferroelectricity include SrTaO 2 N, BaTaO 2 Perovskite-type oxynitrides such as N, or GaFeO with a κ-alumina structure 3 etc.

[0564] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0565] Moreover, as the material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, an insulator using a material capable of having ferroelectricity can be made to have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also on various processes. Therefore, in this specification, not only a material that exhibits ferroelectricity is called a ferroelectric, but also a material capable of having ferroelectricity may be called a ferroelectric.

[0566] Metal oxides containing either or both of hafnium and zirconium are preferred because they can have ferroelectricity even in a thin film of a few nm. Here, the film thickness of an insulator using a material capable of having ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). For example, it is preferable to set the film thickness of the insulator to 8 nm or more and 12 nm or less. By making the insulator that functions as the dielectric of the capacitance into a ferroelectric layer that can be thinned, for example, the capacitance can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In this specification, etc., a layer of a material capable of having ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification, etc.

[0567] In addition, a metal oxide containing either or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a small area. 2 Below, 10μm 2 Below, 1μm 2 Less than or equal to 0.1μm 2 Even if the thickness is less than 10,000 nm, the material can have ferroelectric properties. 2or less than 1000nm 2 Even if the thickness is less than 100 nm, the ferroelectric layer may have ferroelectricity. By making the ferroelectric layer small in area, the area occupied by the capacitor can be made small.

[0568] Ferroelectrics are insulators, and have the property that polarization occurs inside when an electric field is applied from the outside, and the polarization remains even when the electric field is made zero. For this reason, a nonvolatile memory element can be formed by using a capacitance element (hereinafter, sometimes referred to as a ferroelectric capacitor) using this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called, for example, a FeRAM (Ferroelectric Random Access Memory) or a ferroelectric memory. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor.

[0569] It is said that ferroelectricity is expressed by displacing oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an externally applied electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for an insulator using a material that can have ferroelectricity to express ferroelectricity, the insulator needs to contain crystals. In particular, it is preferable for the insulator to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulator may be any one or more selected from a cubic crystal system, a tetragonal crystal system, an orthorhombic crystal system, a monoclinic crystal system, and a hexagonal crystal system. The insulator may have an amorphous structure. In this case, the insulator may be a composite structure having an amorphous structure and a crystalline structure.

[0570] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, etc. described in this embodiment. At least a part of the configuration examples, operation examples, and drawings corresponding thereto described in this embodiment can be appropriately combined with other configuration examples, other operation examples, other drawings, and other embodiments described in this specification, etc.

[0571] (Embodiment 3) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) will be briefly described.

[0572] [OS Transistor] For the OS transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of a channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 Less than or equal to 1×10 17 cm -3 less than 1×10 16 cm -3 less than 1×10 13 cm -3 less than 1×10 10 cm -3 Less than or equal to 1 x 10 -9 cm -3 The above is the case. Note that when the carrier concentration in an oxide semiconductor is reduced, the density of defect states in the oxide semiconductor may be reduced by reducing the impurity concentration in the oxide semiconductor. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0573] In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor may have a low density of trap states because of its low density of defect states. In addition, charges trapped in the trap states of the oxide semiconductor take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0574] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0575] In addition, when impurities or oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and the reliability may be reduced. In addition, an OS transistor is prone to have defects in which hydrogen enters an oxygen vacancy in an oxide semiconductor (hereinafter referred to as V O H) in the channel formation region, generating electrons that serve as carriers. O When H is formed, the donor concentration in the channel formation region may increase. As a result, the threshold voltage of the OS transistor may vary as the donor concentration in the channel formation region increases. For this reason, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics (drain current flows when the gate voltage is 0 V). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible.

[0576] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of a transistor can be reduced.

[0577] Furthermore, in Si transistors, a short channel effect (SCE) occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, since OS transistors use an oxide semiconductor, which is a semiconductor material with a large band gap, the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.

[0578] The short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced). Specific examples of the short channel effect include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0579] Additionally, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, meaning that the device is more resistant to the short channel effect.

[0580] The OS transistor is an accumulation-type transistor, and the Si transistor is an inversion-type transistor. Therefore, the OS transistor has a smaller characteristic length between the source region and the channel formation region and between the drain region and the channel formation region than the Si transistor. Therefore, the OS transistor is more resistant to the short-channel effect than the Si transistor. That is, when it is desired to manufacture a transistor with a short channel length, the OS transistor is more suitable than the Si transistor.

[0581] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, in a short-channel transistor, the conduction band minimum of the channel formation region is lowered due to the Conduction-Band-Lowering (CBL) effect, so that the energy difference between the conduction band minimum of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. As a result, in an OS transistor, the channel formation region is n - The source and drain regions are each an n-type region. + The domain of type, n + / n - / n + accumulation-type junction-less transistor structure, or + / n - / n + It can also be regarded as an accumulation-type non-junction transistor structure.

[0582] By adopting the above structure, the OS transistor can have good electrical characteristics even when miniaturized or highly integrated. For example, the OS transistor can have good electrical characteristics even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, it may be difficult to make the gate length of a Si transistor 20 nm or less or 15 nm or less because of the short channel effect. Therefore, the OS transistor is preferably used as a transistor having a short channel length compared to a Si transistor. The gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode when viewed from above the transistor.

[0583] Furthermore, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within any of the above ranges, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher, for example, in a room temperature environment.

[0584] As described above, the OS transistor has excellent advantages over the Si transistor in that it has a smaller off-state current and can be manufactured as a transistor with a short channel length.

[0585] The structure, configuration, method, or the like described in this embodiment can be used in appropriate combination with the structure, structure, method, or the like described in other embodiments.

[0586] (Embodiment 4) In this embodiment, application examples of a storage device according to one embodiment of the present invention will be described.

[0587] <Example of hierarchical structure of storage device> Generally, various storage devices are used in computers and the like depending on the purpose. FIG. 35 shows various storage devices by hierarchy. The higher the storage device is located, the faster the operating speed is required, and the lower the storage device is located, the larger the storage capacity and the higher the recording density are required. FIG. 35 shows, from the top layer, a register, a cache memory, a main memory, and a storage. The cache memory may also have, from the top layer, a first cache (L1), a second cache (L2), and a third cache (L3). Although an example having a third cache is shown here, a lower cache memory may also be included. The lowest cache memory may also be called a Last Level Cache (LLC) or a Final Level Cache (FLC). For example, a storage class memory may be included between the main memory and the storage.

[0588] Registers embedded in arithmetic processing devices (also called processors) such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Processing Units), and TPUs (Tensor Processing Units) are used for temporarily storing the results of calculations performed by the cores. They also have the function of retaining setting information of the arithmetic processing devices. For this reason, they are frequently accessed by the arithmetic processing devices. Thus, high operating speeds are required of the registers.

[0589] For example, a static random access memory (SRAM) is used as a cache memory. A cache memory has a function of duplicating and storing a portion of the data stored in the main memory. By storing a copy of frequently used data, the speed of accessing the data can be increased. A cache memory is required to operate at a higher speed than the main memory.

[0590] The main memory may be, for example, a dynamic random access memory (DRAM). The main memory has a function of holding programs and data read from storage. The main memory is required to have a larger storage capacity and higher recording density than the cache memory.

[0591] Storage has a function of holding data that needs to be stored for a long time and various programs used in a processing unit. Therefore, storage is required to have a large storage capacity and a high recording density. For example, a hard disk drive (HDD) and a solid state drive (SSD) located on an upper layer of a HDD can be used as the storage. For example, a large-capacity, non-volatile storage device such as a NAND type flash memory (e.g., 3D NAND) can be used as the SSD.

[0592] A memory device according to one embodiment of the present invention (for example, a memory device using an oxide semiconductor) is excellent in that it has a high operating speed and is capable of retaining data for a long period of time, as well as in that it has high rewrite endurance and can be driven at a low voltage.

[0593] A storage device according to an embodiment of the present invention is suitable as a storage device located in an area target1 including a hierarchical level where a cache memory is located, a hierarchical level where a main memory is located, and a hierarchical level where a storage is located, because it is capable of retaining data for a long period of time. In other words, a storage device according to an embodiment of the present invention is suitable for use in an area target1 including a boundary area between the main memory and the storage, and a boundary area between the main memory and the cache memory, in addition to the area where the main memory is located.

[0594] Therefore, for example, it is preferable to replace the DRAM used in the main memory with a storage device according to one embodiment of the present invention. Here, since the DRAM requires a refresh operation and is a destructive read storage device, it consumes more power than other storage devices. Therefore, by not using the DRAM, it is possible to reduce power consumption. Note that, for example, it is also preferable to replace a part of the SRAM used in the cache memory and a part of the 3D NAND used in the storage with a storage device according to one embodiment of the present invention.

[0595] Furthermore, the storage device according to one embodiment of the present invention is suitable as a storage device located in the area target2 including the hierarchy where the cache memory is located and the hierarchy where the register is located, because the storage device according to one embodiment of the present invention has a high operating speed and can realize excellent write and read operations. In other words, it is suitable to use the storag...

Claims

1. A memory array and a peripheral circuit, The memory array has a first memory cell; the peripheral circuit includes a first drive circuit; the first memory cell includes a first transistor and a first capacitance element; one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitive element; the other of the source and the drain of the first transistor is electrically connected to a bit line; a gate of the first transistor electrically connected to a word line; the other terminal of the first capacitive element is electrically connected to the first drive circuit; the first drive circuit has a function of outputting a first potential, a function of outputting a second potential in conjunction with a timing at which a potential of a selection signal applied to the word line changes, and a function of outputting a third potential in conjunction with a timing at which a potential of data applied to the bit line changes; a direction in which the potential of the selection signal changes from the first potential to the second potential is opposite to a direction in which the potential of the selection signal changes; a direction in which the potential changes from the first potential to the third potential is opposite to a direction in which the potential of the data changes; storage device.

2. A memory array and a peripheral circuit, The memory array includes a first memory cell and a second memory cell, the peripheral circuit includes a first drive circuit and a second drive circuit; the first memory cell includes a first transistor and a first capacitance element; the second memory cell includes a second transistor and a second capacitive element; one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitive element; the other of the source and the drain of the first transistor is electrically connected to a bit line; a gate of the first transistor electrically connected to a first word line; the other terminal of the first capacitive element is electrically connected to the first drive circuit; one of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitive element; the other of the source and the drain of the second transistor is electrically connected to the bit line; a gate of the second transistor electrically connected to a second word line; the other terminal of the second capacitive element is electrically connected to the second drive circuit; the first drive circuit has a function of outputting a signal whose potential changes in a direction opposite to a direction in which a potential of a selection signal applied to the first word line changes; the second drive circuit has a function of outputting a signal whose potential changes in a direction opposite to a direction in which a potential of a selection signal applied to the second word line changes; storage device.

3. A memory array and a peripheral circuit, The memory array includes a first memory cell and a second memory cell, the peripheral circuit includes a first drive circuit and a second drive circuit; the first memory cell includes a first transistor and a first capacitance element; the second memory cell includes a second transistor and a second capacitive element; one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitive element; the other of the source and the drain of the first transistor is electrically connected to a first bit line; a gate of the first transistor electrically connected to a word line; the other terminal of the first capacitive element is electrically connected to the first drive circuit; one of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitive element; the other of the source and the drain of the second transistor is electrically connected to a second bit line; a gate of the second transistor electrically connected to the word line; the other terminal of the second capacitive element is electrically connected to the second drive circuit; the first drive circuit has a function of outputting a signal whose potential changes in a direction opposite to a direction in which a potential of data applied to the first bit line changes; the second drive circuit has a function of outputting a signal whose potential changes in a direction opposite to a direction in which a potential of data applied to the second bit line changes; storage device.

4. A memory array and a peripheral circuit, the memory array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; the peripheral circuit includes a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit; the first memory cell includes a first transistor and a first capacitance element; the second memory cell includes a second transistor and a second capacitive element; the third memory cell includes a third transistor and a third capacitive element; the fourth memory cell includes a fourth transistor and a fourth capacitive element; one of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitive element; the other of the source and the drain of the first transistor is electrically connected to a first bit line; a gate of the first transistor electrically connected to a first word line; the other terminal of the first capacitive element is electrically connected to the first drive circuit; one of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitive element; the other of the source and the drain of the second transistor is electrically connected to the first bit line; a gate of the second transistor electrically connected to a second word line; the other terminal of the second capacitive element is electrically connected to the second drive circuit; one of a source and a drain of the third transistor is electrically connected to one terminal of the third capacitive element; the other of the source and the drain of the third transistor is electrically connected to a second bit line; a gate of the third transistor electrically connected to the first word line; the other terminal of the third capacitive element is electrically connected to the third drive circuit; one of a source and a drain of the fourth transistor is electrically connected to one terminal of the fourth capacitive element; the other of the source and the drain of the fourth transistor is electrically connected to the second bit line; a gate of the fourth transistor electrically connected to the second word line; The other terminal of the fourth capacitive element is electrically connected to the fourth drive circuit. storage device.

5. In any one of claims 1 to 4, the first transistor includes an oxide semiconductor in a channel formation region; storage device.

6. In any one of claims 1 to 4, The first transistor is provided on the first capacitive element. storage device.

7. In claim 6, a first conductor, a second conductor on the first conductor, and a third conductor on the second conductor; the first conductor includes a region that functions as the other terminal of the first capacitive element, the second conductor includes a region that functions as one terminal of the first capacitive element and a region that functions as one of a source and a drain of the first transistor; the third conductor includes a region that functions as the other of the source or the drain of the first transistor; storage device.

8. In any one of claims 1 to 4, the memory array is provided on the peripheral circuitry; storage device.

9. A method for driving a memory device having a memory cell in which one of a source and a drain of an n-channel transistor is electrically connected to one terminal of a capacitance element, comprising the steps of: lowering the potential of a selection signal applied to the gate of the transistor, and then increasing the potential applied to the other terminal of the capacitance element; A method for driving a storage device.

10. A method for driving a memory device having a memory cell in which one of a source and a drain of an n-channel transistor is electrically connected to one terminal of a capacitance element, comprising the steps of: a potential applied to the other terminal of the capacitance element is reduced in synchronization with a timing at which a potential of data applied to the other of the source and drain of the transistor is increased; A method for driving a storage device.

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