A / d converter, digital output temperature sensor, circuit arrangement, and oscillator

Abstract

To provide an A / D converter and so on, the A / D converter being capable of achieving reduced noise and A / D conversion at a resolution more accurate than that of an A / D conversion circuit.SOLUTION: An A / D converter 30 includes: a D / A conversion circuit 40 that performs D / A conversion of a DAC input digital value to output a DAC output signal; a difference output circuit 50 that outputs a differential signal based on a difference between an input signal and the DAC output signal; an A / D conversion circuit 60 that performs A / D conversion of the difference signal to output an ADC output digital value; and a control circuit 70. The control circuit 70 outputs a first DAC input digital value and a second DAC input digital value, performs filter processing on the difference between a first ADC output digital value obtained in correspondence with the first DAC input digital value and a second ADC output digital value obtained in correspondence with the second DAC input digital value, and determines ADC result data on the basis of the first ADC output digital value, a digital value after the filter processing, and the DAC input digital value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an A / D converter, a digital output temperature sensor, a circuit device, an oscillator, and the like. [Background technology]

[0002] There is a demand for higher accuracy in A / D converters that convert input signals into digital values. For example, Patent Document 1 discloses an A / D converter that performs A / D conversion multiple times and achieves higher resolution A / D conversion based on the obtained A / D conversion results. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-130998 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, it was discovered that this A / D converter had an issue in that noise dependent on the difference between the input voltage and the DAC output voltage occurred in the A / D conversion results. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to an A / D converter that performs A / D conversion on an input signal and outputs ADC result data, the A / D converter including: a D / A conversion circuit that performs D / A conversion on a DAC input digital value and outputs a DAC output signal; a differential output circuit that outputs a differential signal based on a difference between the input signal and the DAC output signal; an A / D conversion circuit that performs A / D conversion on the differential signal and outputs an ADC output digital value; and a control circuit that outputs the DAC input digital value based on the ADC output digital value, the control circuit outputting a first DAC input digital value and a second DAC input digital value different from the first DAC input digital value as the DAC input digital value, performs filtering on a difference between a first ADC output digital value which is the ADC output digital value obtained corresponding to the first DAC input digital value and a second ADC output digital value which is the ADC output digital value obtained corresponding to the second DAC input digital value, and obtains the ADC result data based on the first ADC output digital value, the digital value after filtering, and the DAC input digital value.

[0006] Another aspect of the present disclosure includes the A / D converter described above and a temperature sensor circuit that detects temperature and outputs a temperature detection voltage, and the differential output circuit is related to a digital output temperature sensor to which the temperature detection voltage is input as the input voltage.

[0007] Another aspect of the present disclosure relates to a digital output temperature sensor including the A / D converter described above and a temperature sensor circuit that detects temperature and outputs a temperature detection current, the differential output circuit including the digital output temperature sensor receiving the temperature detection current as the input current.

[0008] Another aspect of the present disclosure relates to a circuit device that includes the digital output temperature sensor described above and an oscillator circuit that oscillates an oscillator, wherein the digital output temperature sensor detects the temperature of the oscillator and outputs the ADC result data as temperature detection data.

[0009] Another aspect of the present disclosure relates to an oscillator including the circuit device described above and the resonator. [Brief description of the drawings]

[0010] [Figure 1] 2 shows an example of the configuration of an A / D converter according to the present embodiment. [Diagram 2] An example of an A / D converter configuration that has an amplifier circuit as a differential output circuit. [Diagram 3] An explanatory diagram of the operation of an A / D converter. [Figure 4] Example of output noise characteristics. [Diagram 5] 3 shows a detailed configuration example of an A / D converter according to the present embodiment. [Figure 6] A diagram explaining the detailed operation of the A / D converter. [Figure 7] FIG. 4 is a diagram showing an example of a relationship between an input voltage and an ADC input voltage. [Figure 8] 13 shows an example of the configuration of a filter processing unit. [Figure 9] Example of noise characteristics of dg when filter coefficient a=0.5. [Figure 10] Example of output noise characteristics when the filter coefficient is a=0.5. [Figure 11] Example of noise characteristics of dg when filter coefficient a=0.25. [Figure 12] Example of output noise characteristics when the filter coefficient is a=0.25. [Figure 13] Example of output noise characteristics when the filter coefficient is a = 0.125 and 0.25. [Figure 14] Example of a digital output temperature sensor configuration. [Figure 15] Example of noise characteristics of a digital output temperature sensor. [Figure 16] 1 is a first configuration example of a circuit device including a digital output temperature sensor. [Figure 17] 2 shows a second example configuration of a circuit device including a digital output temperature sensor. [Figure 18] An example of oscillator structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential configurations.

[0012] 1.A / D converter Fig. 1 shows an example of the configuration of an A / D converter 30 of this embodiment. The A / D converter 30 performs A / D conversion on an input signal VIN and outputs ADC result data DQ. In Fig. 1, the A / D converter 30 includes a D / A conversion circuit 40, a differential output circuit 50, an A / D conversion circuit 60, and a control circuit 70. Note that the A / D converter 30 of this embodiment is not limited to the configuration shown in Fig. 1, and various modifications are possible, such as omitting some of the components, adding other components, or changing the components to other types of components.

[0013] The D / A conversion circuit 40 performs D / A conversion on the DAC input digital value n and outputs a DAC output signal VN. It is desirable to use, for example, a resistor ladder type D / A conversion circuit as the D / A conversion circuit 40. However, in this embodiment, it is also possible to use other types of D / A conversion circuits, such as a capacitance array type, a delta sigma type, or a current output type, as the D / A conversion circuit 40. In the following, an example will be described in which the input signal VIN and the DAC output signal VN are voltage signals, but the input signal VIN and the DAC output signal VN may be current signals.

[0014] The differential output circuit 50 outputs a differential signal DS based on the difference between the input signal VIN and the DAC output signal VN. The differential output circuit 50 receives the input signal VIN at a first input terminal of the differential input, receives the DAC output signal VN at a second input terminal of the differential input, and outputs a differential signal DS between the input signal VIN and the DAC output signal VN at a differential output terminal. The first input terminal is, for example, a non-inverting input terminal, and the second input terminal is, for example, an inverting input terminal. The differential signal DS is composed of, for example, a first differential signal corresponding to VIN-VN and a second differential signal corresponding to VN-VIN.

[0015] The A / D conversion circuit 60 performs A / D conversion on the differential signal DS and outputs an ADC output digital value d. For example, the A / D conversion circuit 60 receives a first differential signal of the differential signal DS at a first input terminal of the differential input, receives a second differential signal of the differential signal DS at a second input terminal of the differential input, and outputs an ADC output digital value d obtained by A / D converting the difference between the first differential signal and the second differential signal. It is preferable to use, for example, a successive approximation type A / D conversion circuit as the A / D conversion circuit 60. However, in this embodiment, it is also possible to use, for example, an A / D conversion circuit of another type other than the successive approximation type, such as a pipeline type or a delta sigma type, as the A / D conversion circuit 60.

[0016] The control circuit 70 outputs a DAC input digital value n. For example, the control circuit 70 outputs the DAC input digital value n based on the ADC output digital value d from the A / D conversion circuit 60. For example, the control circuit 70 performs arithmetic processing based on the ADC output digital value d and outputs the DAC input digital value n to the D / A conversion circuit 40. The control circuit 70 also outputs final ADC result data DQ. In other words, it outputs the digital value of the ADC result data DQ. The control circuit 70 can be realized by a logic circuit.

[0017] Specifically, the control circuit 70 outputs, as the DAC input digital value n, a DAC input digital value n1 and a DAC input digital value n2 different from the DAC input digital value n1. The DAC input digital value n1 is the first DAC input digital value, and the DAC input digital value n2 is the second DAC input digital value. The control circuit 70 then performs a filter process on d1-d2, which is the difference between the ADC output digital value d1, which is the ADC output digital value d obtained corresponding to the DAC input digital value n1, and the ADC output digital value d2, which is the ADC output digital value d obtained corresponding to the DAC input digital value n2, to obtain a digital value dg after the filter process. The filter process is a digital filter process. The control circuit 70 then obtains the ADC result data DQ based on the ADC output digital value d1, the digital value dg after the filter process, and the DAC input digital value n. For example, the control circuit 70 obtains d=d1 / dg from dg obtained by filtering d1-d2, and obtains ADC result data DQ based on d1 / dg and the DAC input digital value n. For example, when one of the DAC input digital values ​​n1 and n2 is obtained from the other, the control circuit 70 obtains ADC result data DQ from the ADC output digital value d1, the digital value dg after filtering, and the DAC input digital value n1 or the DAC input digital value n2. For example, the control circuit 70 obtains ADC result data DQ from d1 / dg and the DAC input digital value n1 or n2. The ADC output digital value d1 is the first ADC output digital value, and the ADC output digital value d2 is the second ADC output digital value.

[0018] For example, when the control circuit 70 outputs a DAC input digital value n1, the D / A conversion circuit 40 performs D / A conversion of the DAC input digital value n1 to output a DAC output signal VN=Vn1. Then, the differential output circuit 50 outputs a differential signal DS based on the difference between the input signal VIN and the DAC output signal Vn1, and the A / D conversion circuit 60 performs A / D conversion of the differential signal DS to output an ADC output digital value d=d1 to the control circuit 70. Also, when the control circuit 70 outputs a DAC input digital value n2, the D / A conversion circuit 40 performs D / A conversion of the DAC input digital value n2 to output a DAC output signal VN=Vn2. Then, the differential output circuit 50 outputs a differential signal DS based on the difference between the input signal VIN and the DAC output signal Vn2, and the A / D conversion circuit 60 performs A / D conversion of the differential signal DS to output an ADC output digital value d=d2 to the control circuit 70. The control circuit 70 then obtains ADC result data DQ based on the ADC output digital values ​​d1 and d2 and the DAC input digital value n. For example, the control circuit 70 performs a filter process on d1-d2, which is the difference between the ADC output digital values ​​d1 and d2, to obtain a digital value dg after the filter process. The control circuit 70 then obtains the ADC result data DQ based on the ADC output digital value d1, the digital value dg after the filter process, and the DAC input digital value n1 or the DAC input digital value n2, and outputs the ADC result data DQ as the digital value of the final ADC result.

[0019] In this manner, the A / D converter 30 of the present embodiment performs, for example, two A / D conversions, one based on the DAC input digital value n1 and the other based on the DAC input digital value n2. Then, the final ADC result data DQ is calculated based on the ADC output digital value d1, which is the A / D conversion result based on the DAC input digital value n1, and the ADC output digital value d2, which is the A / D conversion result based on the DAC input digital value n2. The ADC output digital value d1 is obtained by A / D converting the difference between the input signal VIN and the DAC output signal Vn1 obtained by D / A converting the DAC input digital value n1 by the D / A conversion circuit 40, using the A / D conversion circuit 60. The ADC output digital value d2 is obtained by A / D converting the difference between the input signal VIN and the DAC output signal Vn2 obtained by D / A converting the DAC input digital value n2 by the D / A conversion circuit 40, using the A / D conversion circuit 60. In this way, it is possible to realize an A / D converter 30 capable of A / D conversion with a higher accuracy than the resolution of the A / D conversion circuit 60 by using the A / D conversion circuit 60 and the D / A conversion circuit 40. As an example, when the resolution of the A / D conversion circuit 60 is, for example, 15 to 16 bits, the resolution can be improved by, for example, about 2 bits, and an A / D converter 30 with a resolution of, for example, 17 to 18 bits can be realized. And according to this embodiment, it is possible to realize an A / D converter 30 with a higher accuracy than the resolution of the A / D conversion circuit 60 by using, for example, one A / D conversion circuit 60, without using two A / D conversion circuits such as a coarse ADC and a fine ADC. For example, by changing the settings of the A / D conversion circuit 60 and the D / A conversion circuit 40 and performing conversion twice, it is possible to alleviate the accuracy requirement of the analog gain, which is an issue in a Two-Step ADC using a coarse ADC and a fine ADC, and it is possible to realize, for example, improvement of linearity and prevention of missing codes.

[0020] In the A / D converter 30 of this embodiment, a filter process such as a low-pass filter process is performed on d1-d2, which is the difference between the ADC output digital values ​​d1 and d2, to obtain a digital value dg after the filter process, and the ADC result data DQ is calculated using this digital value dg. For example, a process is performed in which the ADC output digital value d1 is divided by the digital value dg after the filter process to obtain d1 / dg, and the ADC result data DQ is obtained based on this d1 / dg and the DAC input digital value n1 or n2. In this way, the quantization noise contained in d1-d2 can be reduced by the filter process, and the noise in the ADC result data DQ can be reduced.

[0021] For example, in the above-mentioned Patent Document 1, d1 / (d1-d2) is calculated from ADC output digital values ​​d1 and d2, and ADC result data DQ is calculated from this d1 / (d1-d2) and the DAC input digital value n1 or n2. However, in the method of Patent Document 1, quantization noise occurs in the A / D conversion circuit 60 in the numerator and denominator of d1 / (d1-d2), and it was found that noise dependent on the input signal VIN occurs in the ADC result data DQ.

[0022] In contrast, in this embodiment, quantization noise in d1-d2 is reduced by performing a filter process on d1-d2, so that noise in the ADC result data DQ can be reduced compared to Patent Document 1. For example, in this embodiment, d1 / dg is obtained by dividing the ADC output digital value d1 by the digital value dg after the filter process, and the ADC result data DQ is obtained based on this d1 / dg and n1 or n2. Therefore, compared to the method of Patent Document 1 in which the ADC result data DQ is obtained based on d1 / (d1-d2) and n1 or n2, noise in the ADC result data DQ can be reduced, and for example, generation of noise dependent on the input signal VIN can be effectively suppressed.

[0023] FIG. 2 shows a configuration example of the A / D converter 30 of this embodiment when an amplifier circuit 51 is provided as the differential output circuit 50. In FIG. 2, the input signal VIN is the input voltage. The D / A conversion circuit 40 outputs the DAC output voltage obtained by D / A converting the DAC input digital value n as the DAC output signal VN. Specifically, the D / A conversion circuit 40 outputs the DAC output voltage obtained by D / A converting the DAC input digital value n=n1 as the DAC output signal VN=Vn1, and outputs the DAC output voltage obtained by D / A converting the DAC input digital value n=n2 as the DAC output signal VN=Vn2. The differential output circuit 50 includes an amplifier circuit 51 that differentially amplifies the input signal VIN, which is the input voltage, and the DAC output signal VN, which is the DAC output voltage. In FIG. 2, the amplifier circuit 51 differentially amplifies the input signal VIN and the DAC output signal VN with an amplification factor G, and outputs the differential signal DS, which is a differential voltage signal, to the A / D conversion circuit 60. By providing such an amplifier circuit 51, the difference signal DS obtained by amplifying the difference between the input signal VIN and the DAC output signal VN by the amplifier circuit 51 can be input to the A / D conversion circuit 60. Therefore, the A / D conversion circuit 60 can perform A / D conversion, for example, at full scale, on the difference signal DS having a wide amplitude range amplified by the amplifier circuit 51, and can realize high-precision A / D conversion. For example, by A / D converting the signal amplified by the amplifier circuit 51 by the A / D conversion circuit 60, it is possible to realize an A / D converter 30 with a higher resolution than the resolution of the A / D conversion circuit 60. The amplification factor G, which is the gain of the signal of the amplifier circuit 51, can be, for example, about 10 to 20 times.

[0024] FIG. 3 is a diagram for explaining the basic operation of the A / D converter 30 of this embodiment. A1 in FIG. 3 shows the relationship between the input voltage and the DAC output voltage. The input voltage is the voltage of the input signal VIN, and the DAC output voltage is the voltage of the DAC output signal VN. The DAC input digital value n on the horizontal axis of A1 in FIG. 3 is a digital value input to the D / A conversion circuit 40, and the digital value is also called a digital code. As shown in A1 in FIG. 3, when a DAC input digital value n1 is input, the D / A conversion circuit 40 outputs a DAC output voltage of Vn1 to the amplifier circuit 51, and when a DAC input digital value n2 is input, the D / A conversion circuit 40 outputs a DAC output voltage of Vn2 to the amplifier circuit 51. In A1 in FIG. 3, the input voltage VIN of the A / D converter 30 is, for example, a voltage between the DAC output voltages Vn1 and Vn2. In this embodiment, the input signal VIN is appropriately described as an input voltage, the D / A conversion circuit 40 is appropriately described as a DAC, and the A / D conversion circuit 60 is appropriately described as an ADC.

[0025] A2 in Fig. 3 shows the relationship between the input voltage after amplification by the amplifier circuit 51 and the ADC input voltage. The ADC input voltage is a differential voltage, which is the voltage of the differential signal DS. In A2 in Fig. 3, the amplifier circuit 51 amplifies the signal by G times (G>1).

[0026] As shown in A1 of Fig. 3, when a DAC input digital value n1 is input, the D / A conversion circuit 40 outputs an output voltage of Vn1. Then, as shown in A2 of Fig. 3, the amplifier circuit 51 amplifies VIN-Vn1, which is a differential voltage between the input voltage of VIN and the DAC output voltage of Vn1, by G times and outputs it to the A / D conversion circuit 60, which then A / D converts the voltage of (VIN-Vn1) x G and outputs an ADC output digital value d1 to the control circuit 70. Also, as shown in A1 of Fig. 3, when a DAC input digital value n2 is input, the D / A conversion circuit 40 outputs an output voltage of Vn2. Then, as shown by A2 in FIG. 3, the amplifier circuit 51 amplifies VIN-Vn2, which is the differential voltage between the input voltage of VIN and the output voltage of Vn2, by G times and outputs it to the A / D conversion circuit 60, and the A / D conversion circuit 60 A / D converts the voltage of (VIN-Vn2)×G and outputs the ADC output digital value d2 to the control circuit 70.

[0027] The control circuit 70 obtains the ADC result data DQ based on the ADC output digital value d1 input from the A / D conversion circuit 60 when the DAC input digital value n1 is output to the D / A conversion circuit 40, and the ADC output digital value d2 input from the A / D conversion circuit 60 when the DAC input digital value n2 is output to the D / A conversion circuit 40. For example, the differential voltage shown at A3 in FIG. 3 is expressed as (VIN-Vn1)×G, which corresponds to the ADC output digital value d1. The differential voltage shown at A4 is expressed as (VIN-Vn2)×G, which corresponds to the ADC output digital value d2. The differential voltage shown at A5 is expressed as (Vn2-Vn1)×G=(VIN-Vn1)×G-(VIN-Vn2)×G, which corresponds to d1-d2, which is the difference between the ADC output digital values ​​d1 and d2. Therefore, the input voltage VIN of the A / D converter 30 can be determined from the ratio of the differential voltage of A3 and the differential voltage of A4 to the differential voltage of A5. Specifically, VIN can be determined as shown in the following formula (1).

[0028]

number

[0029] Therefore, the control circuit 70 can calculate and output the ADC result data DQ according to the following equation (2).

[0030]

number

[0031] For example, when VIN is a voltage between Vn1 and Vn2, VIN is a voltage expressed by the ratio of d1 / (d1-d2) between Vn1 and Vn2. For example, when d1 / (d1-d2) is 0.5, VIN=Vn1+(Vn2-Vn1)×0.5, and VIN is a voltage at the center between Vn1 and Vn2. When d1 / (d1-d2) is 0.6, VIN=Vn1+(Vn2-Vn1)×0.6, and VIN is a voltage expressed by the ratio of 60% between Vn2 and Vn1. Note that even when VIN is not a voltage between Vn1 and Vn2, VIN can be specified by the above formula (1), and the control circuit 70 can obtain and output the ADC result data DQ as in the above formula (2).

[0032] According to this embodiment, even if the amplifier circuit 51 is provided in front of the A / D conversion circuit 60 to improve the resolution of the A / D conversion, the circuit characteristics of the amplifier circuit 51, which is an amplifier circuit, are unlikely to affect the result of the A / D conversion. For example, as shown in the above formulas (1) and (2), the amplification factor G of the amplifier circuit 51 theoretically has no effect on the result of the A / D conversion. In addition, in this embodiment, the control circuit 70 generates the DAC input digital value n based on the ADC output digital value d from the A / D conversion circuit 60. For example, the control circuit 70 generates the DAC input digital value n by feedback control. By performing such feedback control, it is possible to bring VN, which is the DAC output voltage of the D / A conversion circuit 40, closer to VIN, which is the input voltage. For example, if VN and VIN are too far apart, it is difficult to obtain an accurate A / D conversion result, but by bringing VN closer to VIN, it is possible to improve the accuracy of the result of the A / D conversion.

[0033] Now, the ADC output digital values ​​d1 and d2 in the above equations (1) and (2) have a quantization error in the A / D conversion circuit 60. Therefore, if the quantization error in d1 is Q1 and the quantization error in d2 is Q2, d1 and d2 can be expressed as in the following equations (3) and (4).

[0034]

number

[0035] And from the above equation (1) and the above equations (3) and (4), if the output noise is Noise, VIN+Noise can be expressed as in the following equation (5).

[0036]

number

[0037] Therefore, from the above equation (5), the output noise, Noise, can be expressed as the following equation (6), and by solving the below equation (6), Noise can be obtained as the below equation (7).

[0038]

number

[0039] In the Noise in the above equation (7), the denominator includes the term VIN-Vn1. Therefore, the output noise of the A / D converter 30 depends on the input signal VIN, which causes a problem that the noise changes depending on the input signal VIN.

[0040] In this embodiment, a filter process is performed on the difference between the ADC output digital values ​​d1 and d2, d1-d2, as shown in the following formula (8), to obtain a digital value dg after the filter process. Here, a is a filter coefficient, and Z -1 means a delay of one cycle.

[0041] [Number]

[0042] When dg is expressed as in the following formula (9), Noise is expressed as in the following formula (10).

[0043] [Number]

[0044] When the quantization noises of d1 and d2 are Q1 and Q2, in the above formula (7) without performing filter processing, the quantization noise appearing in the denominator of Noise is Q2 - Q1. On the other hand, by performing filter processing, as shown in the above formula (10), the quantization noise appearing in the denominator of Noise is reduced to Qg < Q2 - Q1, so that the output noise can be reduced.

[0045] For example, C1 in FIG. 4 is the noise characteristic when no filter processing is performed, and the output noise changes depending on VIN - Vn1. That is, as shown in C2 of FIG. 4, ideally, the output noise should not depend on VIN - Vn1, but in C1, for example, when VIN - Vn1 increases, the output noise also increases.

[0046] On the other hand, C3 in FIG. 4 is the noise characteristic when filter processing is performed on d1 - d2 as in the present embodiment. By performing filter processing on d1 - d2 in this way, as shown in C3, the dependence on VIN - Vn1 can be sufficiently reduced compared to C1, and the noise characteristic of the A / D converter 30 can be improved. The unit of the output noise is, for example, V / sqHz.

[0047] For example, in d1 / (d1-d2) in the above formulas (1) and (2), quantization noise occurs in both the numerator d1 and the denominator d1-d2. The noise in d1 / (d1-d2) is the largest when the numerator d1 becomes large due to quantization noise and the denominator d1-d2 becomes small due to quantization noise, or when d1 becomes small due to quantization noise and d1-d2 becomes large due to quantization noise. Therefore, the noise in d1 / (d1-d2) can be reduced by performing a filter process on the denominator d1-d2 to reduce the quantization noise in d1-d2.

[0048] In this case, as a method of a comparative example of this embodiment, a method of performing a filter process not only on d1-d2 of the denominator of d1 / (d1-d2) but also on d1 of the numerator is considered. However, according to this method, the filter process is performed on d1 that changes according to VIN, and the A / D conversion process described in FIG. 3 cannot be performed properly, and appropriate ADC result data DQ cannot be obtained. On the other hand, as described in FIG. 3, d1-d2, which is the difference between the ADC output digital values ​​d1 and d2, corresponds to n1-n2, which is the difference between the DAC input digital values ​​n1 and n2. And since n2 is generated by adding a predetermined value such as +1 to n1, the true value of d1-d2 corresponding to n1-n2 also becomes a predetermined value. Therefore, even if the filter process is performed on d1-d2 whose true value becomes a predetermined value, the above-mentioned problem caused by performing a filter process on d1 does not occur. And, an error Qg occurs in d1-d2, which is an error corresponding to the quantization error of Q1 and Q2 as explained in the above equation (9). However, by reducing this Qg by low-pass filter processing, it becomes possible to improve the noise characteristics of the A / D converter 30.

[0049] Fig. 5 shows a detailed configuration example of the A / D converter 30 of this embodiment. Fig. 5 shows a specific configuration example of the control circuit 70. Fig. 6 shows a detailed explanatory diagram of the operation of the A / D converter 30. Here, it is assumed that, for example, VIN of 0.88 V is input as shown in Fig. 5. For simplicity of explanation, first, the operation will be explained when the arithmetic circuit 72 in Fig. 4 does not perform filter processing on d1-d2.

[0050] In the k-th process (k is an integer equal to or greater than 1) shown in B1 of FIG. 6, the delay unit 76 of the control circuit 70 of FIG. 5 outputs n=20. Then, the selector 78 of the control circuit 70 outputs n=20 to the D / A conversion circuit 40 the first time as shown in B2 and B3, and outputs n=21 to the D / A conversion circuit 40 the second time. When n=20 is input to the D / A conversion circuit 40, for example, +0.08V is input to the A / D conversion circuit 60, and the A / D conversion circuit 60 outputs a digital value of, for example, 80. Here, 1 LSB is, for example, 1 mV. Also, when n=21 is input to the D / A conversion circuit 40, for example, -0.02V is input to the A / D conversion circuit 60, and the A / D conversion circuit 60 outputs a digital value of, for example, -20. Then, the arithmetic circuit 72 of the control circuit 70 performs the arithmetic process of d=d1 / (d1-d2) and outputs d=80 / {80-(-20)}=0.8. In reality, the arithmetic circuit 72 performs a filter process on d1-d2 and calculates d=d1 / dg using dg obtained by this filter process, but in order to explain the basic operation of this embodiment, the arithmetic circuit 72 will be described here as performing the arithmetic process of d=d1 / (d1-d2).

[0051] The gain multiplier 73 of the control circuit 70 multiplies d=0.8 by a gain of, for example, a1=0.5, and 0.8×0.5=0.4 is input to the integrator 74 of the control circuit 70. At this time, the integrator 74 outputs 21.1 as the integration result, and the quantizer 75 of the control circuit 70 quantizes this 21.1 to an integer, and outputs n=21 as n used in the k+1th processing, as shown in B4. Also, as shown in B5, the adder 77 of the control circuit 70 adds n=20 used in the kth processing and d=0.8, which is the output of the arithmetic circuit 72 in the kth processing, and outputs DQ=20.8 as the ADC result data.

[0052] Also, as shown in B4, in the k+1th processing, the delay unit 76 outputs n=21 obtained by quantization in the kth processing. Then, the selector 78 outputs n=21 to the D / A conversion circuit 40 in the first processing as shown in B6 and B7, and outputs n=22 to the D / A conversion circuit 40 in the second processing. When n=21 is input to the D / A conversion circuit 40, for example, -0.02V is input to the A / D conversion circuit 60, and the A / D conversion circuit 60 outputs a digital value of -20, for example. When n=22 is input to the D / A conversion circuit 40, for example, -0.12V is input to the A / D conversion circuit 60, and the A / D conversion circuit 60 outputs a digital value of -120, for example. Then, the calculation circuit 72 performs a calculation process of d=d1 / (d1-d2) and outputs d=-20 / {-20-(-120)}=-0.2. The gain multiplier 73 multiplies this d=-0.2 by a gain of a1=0.5, and the integrator 74 inputs -0.2×0.5=-0.1. At this time, the integrator 74 outputs 21.5, which is the sum of 21.1, which is the k-th integration result, and 0.4, which is the k-th integrator input. The quantizer 75 then quantizes this 21.5 to an integer, and outputs n=22 as n to be used in the k+2-th processing, as shown in B8. Also, as shown in B9, the adder 77 adds n=21 used in the k+1-th processing and d=-0.2, which is the output of the arithmetic circuit 72 in the k+1-th processing, and outputs DQ=20.8 as the ADC result data.

[0053] In this embodiment, as shown by B1, B4, B8, B10, and B11 in FIG. 6, the DAC input digital value n is modulated by delta-sigma modulation or the like, and the modulated DAC input digital value n is input to the D / A conversion circuit 40. Then, as shown by B5, B9, B12, B12, B13, and B14, the ADC result data DQ corresponding to the input voltage of VIN=0.88V in FIG. 7 is output from the control circuit 70. For example, in FIG. 3, when the voltage difference between the DAC output voltage corresponding to the DAC input digital value n and the input voltage of VIN increases, the differential voltage of the differential signal DS input to the A / D conversion circuit 60 increases. If the voltage difference exceeds the full-scale range of the A / D conversion circuit 60, a problem occurs in which accurate A / D conversion cannot be performed. In this regard, in FIG. 5 and FIG. 6, when the voltage difference between the DAC output voltage and the input voltage of VIN is large, feedback control is performed by the integrator 74 or the like to make the voltage difference between the DAC output voltage and the input voltage of VIN closer, and the DAC input digital value n is output from the control circuit 70. Therefore, it is possible to prevent the differential voltage of the differential signal DS from becoming large and exceeding the full-scale range of the A / D conversion circuit 60, and it is possible to realize a high accuracy of the A / D converter 30.

[0054] As described above, in this embodiment, the control circuit 70 includes the arithmetic circuit 72 that performs an arithmetic operation based on the ADC output digital value d1 and the ADC output digital value d2, the integrator 74 that performs an integration process on the output of the arithmetic circuit 72, and the quantizer 75 that performs a quantization process on the result of the integration process and outputs a DAC input digital value n. In this way, it is possible to perform modulation such as delta-sigma modulation on the DAC input digital value n. As a result, the DAC input digital value n to the D / A conversion circuit 40 is not fixed to one value, and the linearity and differential characteristics of the D / A conversion circuit 40 can be improved. In addition, the DAC input digital value n can be determined autonomously and automatically.

[0055] 5, modulation corresponding to first-order delta-sigma modulation is performed, but the modulation process in this embodiment is not limited to this. For example, various modifications such as modulation corresponding to second-order delta-sigma modulation can be performed.

[0056] The control circuit 70 also outputs a DAC input digital value n2 obtained by adding a predetermined value to the DAC input digital value n1. For example, in FIG. 5, the control circuit 70 outputs a DAC input digital value n2 obtained by adding a predetermined value, +1, to the DAC input digital value n1. Here, the predetermined value is not limited to +1, and may be a value of 2 or more, or may be a negative value. In this way, the simple process of adding a predetermined value makes it possible to output the DAC input digital values ​​n1 and n2 to the D / A conversion circuit 40, and to cause the A / D conversion circuit 60 to output the ADC output digital value d1 corresponding to the DAC input digital value n1 and the ADC output digital value d2 corresponding to the DAC input digital value n2.

[0057] In this embodiment, as shown in Fig. 5, the calculation circuit 72 performs a filter process on d1-d2, which is the denominator in d=d1 / (d1-d2). This d1-d2 corresponds to n1-n2, and since n1-n2 is a predetermined value of 1 in Fig. 5, the true value of d1-d2 is a predetermined value. The calculation circuit 72 calculates dg=(1-a)dgZ for this d1-d2, as explained in the above equation (8). -1 +a(d1-d2) is performed to obtain a digital value dg after the filter processing. Then, the arithmetic circuit 72 performs a process of dividing d1 by dg, and outputs d=d1 / dg to the gain multiplier 73. In this way, it is possible to reduce the dependency on the input signal as described in FIG. 4, and it is possible to reduce the output noise of the A / D converter 30.

[0058] 8 shows an example of the configuration of a filter processing unit 92 that performs the filter processing. This filter processing unit 92 is provided in the arithmetic circuit 72. The filter processing unit 92 includes adders 93 and 94, a multiplier 95 that multiplies the filter coefficient, and a delay unit 96. The filter processing unit 92 configured in this way outputs dg=(1-a)dgZ -1 +a(d1-d2). Note that the filter processing of this embodiment is not limited to this filter processing, and various modifications are possible, and various low-pass filter processing that reduces noise by averaging d1-d2, etc., can be adopted.

[0059] Fig. 9 shows an example of noise characteristics of a digital value dg. E1 in Fig. 9 shows the noise characteristics of dg when no filter processing is performed, and shows the noise characteristics when the filter coefficient is a=1. This corresponds to the case of Patent Document 1 mentioned above. E2 in Fig. 9 shows the noise characteristics of dg when the filter coefficient is a=0.5. By setting a=0.5, low-pass filter processing with a cutoff frequency corresponding to a=0.5 is performed on dg.

[0060] 10, F1 is the output noise characteristic of the A / D converter 30 when no filter processing is performed, and F2 is the output noise characteristic when filter processing with a = 0.5 is performed. The output noise is reduced by performing the filter processing.

[0061] E1 in Figure 11 is the noise characteristic of dg when no filtering is performed and when the filter coefficient is a = 1. E3 is the noise characteristic of dg when the filter coefficient is a = 0.25. And F1 in Figure 12 is the output noise characteristic when no filtering is performed and F3 is the output noise characteristic when filtering with a = 0.25 is performed. By setting the filter coefficient to a = 0.25, the cutoff frequency of dg is lower than when a = 0.5, making it possible to further reduce the output noise.

[0062] F1 in FIG. 13 represents the output noise characteristics when no filtering process is performed, F3 represents the output noise characteristics when a = 0.25, and F4 represents the output noise characteristics when a = 0.125. The smaller the value of a, which is the filter coefficient, the more the output noise can be reduced. However, when the filter coefficient is, for example, a = 0.125 or less, the reduction of the output noise reaches a saturation point, and for example, the effect of reducing the output noise is the same between a = 0.125 and a = 0.25.

[0063] As described above, in this embodiment, when the first ADC output digital value is d1, the second ADC output digital value is d2, the digital value after the filtering process is dg, and the filter coefficient is a, the control circuit 70 performs, as the filtering process, dg=(1 - a)dgZ -1 +a(d1 - d2), which represents a low-pass filter process. By doing so, it is possible to perform a filtering process on d1 - d2, which is the difference between the ADC output digital values, and obtain the digital value dg that has undergone a low-pass filter process with a cut-off frequency set by the filter coefficient a as shown in FIGS. 9 and 11. Then, based on the ADC output digital value d1, the digital value dg after the filtering process, and the DAC input digital values n1 and n2, the ADC result data DQ is obtained. As a result, as shown in FIGS. 10, 12, and 13, it becomes possible to output the ADC result data DQ with reduced noise.

[0064] Also, the filter coefficient a is, for example, 0.5 or less. By doing so, it becomes possible to obtain the digital value dg that has undergone a low-pass filter process with a cut-off frequency set by the filter coefficient a of a = 0.5 or less. As a result, as shown in FIG. 9, it is possible to obtain a digital value dg with reduced noise compared to d1 - d2 where no filtering process is performed. And by using the digital value dg with reduced noise in this way, as shown in FIG. 10, it becomes possible to reduce the output noise of the A / D converter 30 compared to the case of using d1 - d2 where no filtering process is performed.

[0065] It is more preferable that the filter coefficient a is, for example, 0.25 or less. In this way, a digital value dg that has been subjected to low-pass filtering at a cutoff frequency set by a filter coefficient of a=0.25 or less can be obtained. As a result, as shown in FIG. 11, it is possible to obtain a digital value dg in which noise is sufficiently reduced compared to d1-d2 that has not been subjected to filtering. By using the digital value dg in which noise is sufficiently reduced in this way, it is possible to sufficiently reduce the output noise of the A / D converter 30 compared to the case in which d1-d2 that has not been subjected to filtering is used, as shown in FIG. 12.

[0066] Moreover, the filter coefficient a is, for example, 0.125 or more. In this way, the output noise of the A / D converter 30 can be sufficiently reduced, and the deterioration of the responsiveness due to the filter processing can be suppressed. For example, by lowering the filter coefficient, it is possible to obtain a digital value dg with sufficiently reduced noise, and the output noise of the A / D converter 30 can be reduced. However, if the filter coefficient is made too low, the cutoff frequency is too low, and the responsiveness is reduced. As shown in FIG. 13, when the filter coefficient is, for example, a=0.125 or less, the reduction of the output noise reaches a plateau, and only the responsiveness deteriorates. In this regard, if the filter coefficient is, for example, 0.5≧a≧0.125, it is possible to optimally achieve both the reduction of the output noise of the A / D converter 30 and the suppression of the deterioration of the responsiveness.

[0067] Furthermore, when the first DAC input digital value is n1, the second DAC input digital value is n2, the first ADC output digital value is d1, the digital value after filtering is dg, and the ADC result data is DQ, the control circuit 70 obtains the ADC result data DQ by DQ=n1+(n2-n1)×(d1 / dg). That is, the control circuit 70 obtains the ADC result data DQ by performing the arithmetic process of DQ=n1+(n2-n1)×(d1 / dg) based on the DAC input digital values ​​n1 and n2, the ADC output digital value d1, and the digital value after filtering dg. In this way, the A / D conversion circuit 60 and the D / A conversion circuit 40 perform conversion based on the DAC input digital value n1 and conversion based on the DAC input digital value n2, and the control circuit 70 performs arithmetic processing of DQ=n1+(n2-n1)×(d1 / dg), thereby realizing an A / D converter 30 with higher accuracy than the resolution of the A / D conversion circuit 60. In addition, since the control circuit 70 performs arithmetic processing using the filtered digital value dg instead of d1-d2, it is possible to reduce noise in the ADC result data DQ compared to the case where d1-d2 is used.

[0068] In addition, in this embodiment, unlike the Two-step ADC, which uses two A / D conversion circuits to achieve high accuracy, the A / D converter 30 is realized using the A / D conversion circuit 60 and the D / A conversion circuit 40, and has a high accuracy with a resolution higher than that of the A / D conversion circuit 60. That is, as described in FIG. 5 and the like, the A / D conversion circuit 60 and the D / A conversion circuit 40 are used to perform two conversions by changing the DAC input digital value n, thereby alleviating the requirement for accuracy of the analog gain, which is a problem in the Two-step ADC, and improving linearity and preventing missing codes. For example, in this embodiment, even if the amplifier circuit 51 is provided in front of the A / D conversion circuit 60 to improve the resolution of the A / D conversion, the amplification factor G of the amplifier circuit 51 does not affect the result of the A / D conversion, as described in the above formulas (1) and (2), and therefore high accuracy can be achieved. In addition, since there is no need to provide two A / D conversion circuits such as a Coarse ADC and a Fine ADC as in the conventional technology, there is no error caused by mismatch between the two A / D conversion circuits. In addition, since the Zoom ADC uses a delta-sigma A / D conversion circuit, it is difficult to achieve a wide bandwidth. In contrast, the A / D converter 30 of this embodiment has the advantage that it is easy to achieve a wide bandwidth because it can use an A / D conversion circuit capable of wideband operation, such as a successive approximation type A / D conversion circuit, as the A / D conversion circuit 60.

[0069] In this embodiment, the D / A conversion circuit 40 is preferably a resistor ladder type D / A conversion circuit. For example, as is clear from the above formulas (1) and (2) and FIG. 3, if the linearity characteristics such as INL (Integral Non-Linearity) of the D / A conversion circuit 40 are poor, the accuracy of the A / D converter 30 will decrease. For example, in this embodiment, the ADC result data is calculated by the arithmetic formula DQ=n1+(n2-n1)×(d1 / dg), but if the linearity characteristics of the D / A conversion circuit 40 are poor, the premise of this arithmetic formula will collapse, making it difficult to realize a high-precision A / D converter 30. In this respect, the resistor ladder type D / A conversion circuit performs D / A conversion based on the ratio of resistance values ​​of multiple resistors, so that the linearity characteristics such as INL are better than those of other types of D / A conversion circuits. For example, by properly adjusting the layout arrangement of multiple resistors, good linearity characteristics can be realized. Therefore, by using a resistor ladder type D / A conversion circuit as the D / A conversion circuit 40, accurate conversion becomes possible, and a highly accurate A / D converter 30 can be realized.

[0070] Furthermore, in this embodiment, it is desirable to use a successive approximation type A / D conversion circuit as the A / D conversion circuit 60. If a successive approximation type A / D conversion circuit is used as the A / D conversion circuit 60 in this manner, wideband A / D conversion becomes possible, and it becomes easier to realize a wideband A / D converter 30.

[0071] 2. Digital Output Temperature Sensor 14 shows an example of the configuration of a digital output temperature sensor 80 of this embodiment. The digital output temperature sensor 80 includes the A / D converter 30 of this embodiment and a temperature sensor circuit 90 that detects temperature and outputs a temperature detection signal. The temperature detection signal from the temperature sensor circuit 90 is input to the A / D converter 30, which performs A / D conversion of the temperature detection signal and outputs ADC result data DQ. In this way, a digital output temperature sensor 80 can be realized that can output the temperature detection result of the temperature sensor circuit 90 as ADC result data DQ in a digital value.

[0072] In this case, the temperature detection signal output by the temperature sensor circuit 90 after detecting the temperature may be a temperature detection voltage or a temperature detection current. When the temperature detection signal is a temperature detection voltage, the temperature detection voltage is input as an input voltage, which is an input signal VIN, to the differential output circuit 50 of the A / D converter 30 of this embodiment in FIG. 1. This allows for the realization of a digital output temperature sensor 80 that can convert the temperature detection voltage, which is the temperature detection result of the temperature sensor circuit 90, into digital ADC result data DQ and output the data. On the other hand, when the temperature detection signal is a temperature detection current, the temperature detection current is input as an input current, which is an input signal VIN, to the differential output circuit 50 of the A / D converter 30 of this embodiment in FIG. 1. This allows for the realization of a digital output temperature sensor 80 that can convert the temperature detection current, which is the temperature detection result of the temperature sensor circuit 90, into digital ADC result data DQ and output the data.

[0073] The A / D converter 30 of this embodiment is suitable as an A / D converter used in such a digital output temperature sensor 80. For example, the digital output temperature sensor 80 needs to output a highly accurate temperature detection result. In this regard, the A / D converter 30 of this embodiment is capable of A / D conversion with a higher accuracy than the resolution of the A / D conversion circuit 60, and therefore can meet the demand for such a highly accurate temperature detection result output. Furthermore, the digital output temperature sensor 80 needs to output a highly accurate temperature detection result in a wide band, but the A / D converter 30 of this embodiment can easily be made to have a wide band as described above, and therefore can also meet the demand for a highly accurate temperature detection result output in a wide band.

[0074] Specifically, the temperature sensor circuit 90 outputs a temperature detection voltage as a temperature detection signal. The temperature detection voltage is input as an input signal VIN to the amplifier circuit 51 in FIG. 2, which is the differential output circuit 50 of the A / D converter 30. The amplifier circuit 51 performs a differential amplification operation between the DAC output voltage, which is the DAC output signal VN of the D / A conversion circuit 40, and the temperature detection voltage VTP, and outputs a differential signal DS to the A / D conversion circuit 60. This realizes a digital output temperature sensor 80 that can A / D convert the temperature detection voltage, which is the temperature detection signal of the temperature sensor circuit 90, by the A / D converter 30 and output the ADC result data DQ in a digital value.

[0075] In this embodiment, the temperature sensor circuit 90 may detect the temperature and output a temperature detection current, and the temperature detection current may be input to the differential output circuit 50 as an input current. This realizes a digital output temperature sensor 80 that can convert the temperature detection current, which is the temperature detection result of the temperature sensor circuit 90, into digital ADC result data DQ and output it. For example, the input signal VIN is an input current, and the D / A conversion circuit 40 outputs the DAC output current obtained by D / A converting the DAC input digital value n as the DAC output signal VN. The differential output circuit 50 outputs the difference between the input current and the DAC output current as the differential signal DS. In this way, even if the input signal VIN is an input current such as a temperature detection current, the value of this input current can be A / D converted with high resolution and output as the ADC result data DQ.

[0076] Furthermore, in the digital output temperature sensor 80 of this embodiment, a filter process is performed on d1-d2, which is the difference between the ADC output digital values ​​d1 and d2, and a temperature detection signal is output based on the digital value dg after the filter process, thereby making it possible to reduce noise in the temperature detection signal. For example, G1 in Fig. 15 is the output noise characteristic of the digital output temperature sensor 80 when no filter process is performed on d1-d2, and G2 is the output noise characteristic when filter process is performed on d1-d2.

[0077] In G1 and G2 in Fig. 15, the regions where the output noise increases correspond to the step-like change points of the output voltage of the D / A conversion circuit 40 of A1 in Fig. 3. For example, by performing delta-sigma modulation as explained in Fig. 5 and Fig. 6, the increase in the output noise can be suppressed, but in G1 in Fig. 15 where no filtering is performed on d1-d2, temperatures at which the output noise increases significantly occur discretely, and the output noise changes significantly depending on the temperature. In other words, the output noise becomes temperature dependent.

[0078] In contrast, in this embodiment, filtering is performed on d1-d2, so that the change in output noise according to temperature, as shown in G2, can be sufficiently reduced compared to G1, and the temperature dependency of the output noise can be suppressed.

[0079] 3.Circuit device 16 shows a first configuration example of the circuit device 20 of this embodiment. The circuit device 20 includes a digital output temperature sensor 80 of this embodiment and an oscillation circuit 21 that oscillates the resonator 10. The circuit device 20 can also include an output circuit 23 that outputs a clock signal CK based on an oscillation signal OSC from the oscillation circuit 21. The oscillator 4 of this embodiment also includes the resonator 10 and the circuit device 20. The resonator 10 is electrically connected to the circuit device 20. For example, the resonator 10 and the circuit device 20 are electrically connected to each other using internal wiring, bonding wires, metal bumps, or the like of a package that houses the resonator 10 and the circuit device 20.

[0080] The vibrator 10 is an element that generates mechanical vibration by an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a quartz crystal vibrating piece that vibrates in a thickness shear manner such as an AT cut or SC cut cut angle, a tuning fork type quartz crystal vibrating piece, or a double tuning fork type quartz crystal vibrating piece. For example, the vibrator 10 may be a vibrator built in a temperature compensated crystal oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built in an oven-controlled crystal oscillator (OCXO) that has a thermostatic oven. Alternatively, the vibrator 10 may be a vibrator built in an oscillator of an SPXO (Simple Packaged Crystal Oscillator). Note that the vibrator 10 of this embodiment can also be realized by various vibrating pieces such as a vibrating piece other than a thickness shear vibration type, a tuning fork type, or a double tuning fork type, or a piezoelectric vibrating piece formed of a material other than quartz. For example, the vibrator 10 may be a surface acoustic wave (SAW) resonator or a micro electro mechanical systems (MEMS) vibrator as a silicon vibrator formed using a silicon substrate.

[0081] The circuit device 20 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. In FIG. 16, the circuit device 20 includes an oscillator circuit 21, an output circuit 23, and a digital output temperature sensor 80.

[0082] The oscillator circuit 21 is a circuit that oscillates the vibrator 10. The oscillator circuit 21 is electrically connected to the vibrator 10 via, for example, a first terminal and a second terminal for connecting the vibrator, and generates an oscillation signal OSC by oscillating the vibrator 10. The first terminal and the second terminal are, for example, pads of the circuit device 20. For example, the oscillator circuit 21 can be realized by a drive circuit for oscillation provided between the first terminal and the second terminal for connecting the vibrator, and passive elements such as a capacitor and a resistor. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is a core circuit of the oscillator circuit 21, and the drive circuit drives the vibrator 10 with voltage or current to oscillate the vibrator 10. As the oscillator circuit 21, various types of oscillator circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be via a passive element or the like.

[0083] The output circuit 23 outputs a clock signal CK based on the oscillation signal OSC. For example, the output circuit 23 buffers the oscillation signal OSC and outputs it to the outside as a clock signal CK. For example, the output circuit 23 outputs the clock signal CK in a single-ended CMOS signal format. Note that the output circuit 23 may output the clock signal CK in a signal format other than CMOS. For example, the output circuit 23 may output a differential clock signal to the outside in a signal format such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed ​​Current Steering Logic), or differential CMOS (Complementary MOS).

[0084] The digital output temperature sensor 80 detects, for example, the ambient temperature of the resonator 10 and outputs the ADC result data DQ as temperature detection data. For example, the digital output temperature sensor 80 detects the ambient temperature of the resonator 10 by detecting the ambient temperature, and outputs the ADC result data DQ to the outside as temperature detection data. In this way, it is possible to realize a circuit device 20 that can detect the ambient temperature of the resonator 10 and output it as temperature detection data. In this case, for example, a PLL loop or the like may be set up by an external system to perform temperature compensation of the oscillation frequency of the resonator 10 based on the temperature detection data, thereby realizing temperature compensation of the clock signal CK.

[0085] 17 shows a second configuration example of the circuit device 20. In FIG. 17, the circuit device 20 includes a processing circuit 24 that outputs frequency control data DFC based on temperature detection data, which is the ADC result data DQ of the digital output temperature sensor 80. The oscillation circuit 21 then outputs an oscillation signal OSC having an oscillation frequency corresponding to the frequency control data DFC. In this way, it becomes possible to detect the ambient temperature of the resonator 10 using the temperature detection data of the digital output temperature sensor 80 and control the oscillation frequency of the oscillation circuit 21. For example, it becomes possible to perform temperature compensation for the oscillation frequency of the resonator 10 and realize temperature compensation of the clock signal CK, etc.

[0086] Specifically, the processing circuit 24 includes a temperature compensation circuit 25. The temperature compensation circuit 25 performs temperature compensation processing based on temperature detection data, which is the ADC result data DQ from the digital output temperature sensor 80, and outputs frequency control data DFC. The temperature compensation processing is, for example, processing for suppressing and compensating for fluctuations in the oscillation frequency due to temperature fluctuations. That is, the temperature compensation circuit 25 performs temperature compensation processing for the oscillation frequency of the oscillation circuit 21 so that the frequency is constant even when there is a temperature fluctuation. For example, the temperature compensation circuit 25 performs temperature compensation processing to obtain the frequency control data DFC from the temperature detection data using a lookup table that indicates the correspondence between the temperature detection data and the frequency control data DFC. Specifically, the oscillation circuit 21 includes a variable capacitance circuit 22, and the capacitance value of the variable capacitance circuit 22 is adjusted based on the frequency control data DFC from the processing circuit 24, thereby realizing temperature compensation processing for the oscillation frequency of the oscillation circuit 21. Here, the variable capacitance circuit 22 includes, for example, a capacitor array having a plurality of capacitors and a switch array having a plurality of switches, and each of the plurality of capacitors and each of the plurality of switches are connected in series between a node of a first terminal or a second terminal for connecting a vibrator and, for example, a ground node. The capacitance values ​​of the plurality of capacitors in the capacitor array are weighted in binary. The plurality of switches in the switch array are turned on and off based on frequency control data DFC from the processing circuit 24. This controls the capacitance value of the variable capacitance circuit 22, adjusts the oscillation frequency of the oscillation circuit 21, and realizes temperature compensation processing.

[0087] FIG. 18 shows an example of the structure of the oscillator 4 of this embodiment. The oscillator 4 of this embodiment includes a circuit device 20 and a resonator 10. Specifically, the oscillator 4 has the resonator 10, the circuit device 20, and a package 15 that houses the resonator 10 and the circuit device 20. The package 15 is made of, for example, ceramics, and has an accommodation space inside, in which the resonator 10 and the circuit device 20 are accommodated. The accommodation space is hermetically sealed, and is preferably in a reduced pressure state that is close to a vacuum. The package 15 can suitably protect the resonator 10 and the circuit device 20 from impact, dust, heat, moisture, and the like.

[0088] The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of the base 16 that supports the vibrator 10 and the circuit device 20, and the lid 17 that is joined to the upper surface of the base 16 so as to form a storage space between the base 16 and the lid 17. The vibrator 10 is supported via a terminal electrode on a step portion provided on the inside of the base 16. The circuit device 20 is also arranged on the inner bottom surface of the base 16. Specifically, the circuit device 20 is arranged so that the active surface faces the inner bottom surface of the base 16. The active surface is a surface on which the circuit elements of the circuit device 20 are formed. Furthermore, bumps BMP are formed on pads that are terminals of the circuit device 20. The circuit device 20 is supported on the inner bottom surface of the base 16 via the conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, and the vibrator 10 and the circuit device 20 are electrically connected via the bumps BMP, the internal wiring of the package 15, the terminal electrodes, and the like. Furthermore, the circuit device 20 is electrically connected to external terminals 18, 19, which are external connection terminals of the oscillator 4, via bumps BMP and internal wiring of the package 15. The external terminals 18, 19 are formed on the outer bottom surface of the package 15. The external terminals 18, 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. This makes it possible to output a clock signal, etc. to the external device.

[0089] In FIG. 18, the circuit device 20 is flip-mounted so that the active surface of the circuit device 20 faces downward, but the present embodiment is not limited to such mounting. For example, the circuit device 20 may be mounted so that the active surface of the circuit device 20 faces upward. That is, the circuit device 20 is mounted so that the active surface faces the resonator 10. Alternatively, the oscillator 4 may be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes a semiconductor substrate, a base having a through electrode penetrating between the first surface and the second surface of the semiconductor substrate, the resonator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding member such as a metal bump, and an external terminal provided on the second surface side of the semiconductor substrate via an insulating layer such as a relocation wiring layer. An integrated circuit that becomes the circuit device 20 is formed on the first surface or the second surface of the semiconductor substrate. In this case, a first semiconductor wafer having a plurality of bases on which the resonators 10 and integrated circuits are arranged is attached to a second semiconductor wafer having a plurality of lids, thereby bonding the plurality of bases and the plurality of lids, and then the oscillators 4 are diced into individual pieces by a dicing saw or the like. In this way, it becomes possible to realize a wafer-level packaged oscillator 4, and it becomes possible to manufacture the oscillators 4 with high throughput and at low cost.

[0090] As described above, the A / D converter of this embodiment performs A / D conversion on an input signal and outputs ADC result data. The A / D converter includes a D / A conversion circuit that performs D / A conversion on a DAC input digital value and outputs a DAC output signal, a differential output circuit that outputs a differential signal based on the difference between the input signal and the DAC output signal, an A / D conversion circuit that performs A / D conversion on the differential signal and outputs an ADC output digital value, and a control circuit that outputs a DAC input digital value based on the ADC output digital value. The control circuit outputs a first DAC input digital value and a second DAC input digital value different from the first DAC input digital value as the DAC input digital value. The control circuit also performs filtering on the difference between a first ADC output digital value, which is an ADC output digital value obtained corresponding to the first DAC input digital value, and a second ADC output digital value, which is an ADC output digital value obtained corresponding to the second DAC input digital value, to obtain a digital value after filtering. The control circuit obtains ADC result data based on the first ADC output digital value, the digital value after filtering, and the DAC input digital value.

[0091] According to this embodiment, A / D conversion is performed based on the first DAC input digital value and A / D conversion is performed based on the second DAC input digital value. Then, final ADC result data is obtained based on the first ADC output digital value, which is the A / D conversion result based on the first DAC input digital value, and the second ADC output digital value, which is the A / D conversion result based on the second DAC input digital value. Then, the first ADC output digital value is obtained by A / D converting the difference between the input signal and the DAC output signal obtained by D / A converting the first DAC input digital value. Also, the second ADC output digital value is obtained by A / D converting the difference between the input signal and the DAC output signal obtained by D / A converting the second DAC input digital value. In this way, it is possible to realize an A / D converter that can perform A / D conversion with higher accuracy than the resolution of the A / D conversion circuit by using the A / D conversion circuit and the D / A conversion circuit, and it is possible to realize a high-precision A / D converter.

[0092] In this case, in this embodiment, a filter process is performed on the difference between the first ADC output digital value and the second ADC output digital value to obtain a digital value after the filter process, and the ADC result data is calculated using the digital value after the filter process. In this way, the quantization noise included in the difference between the first ADC output digital value and the second ADC output digital value can be reduced, so that the noise in the ADC result data can be reduced.

[0093] In this embodiment, when the first ADC output digital value is d1, the second ADC output digital value is d2, the digital value after the filter processing is dg, and the filter coefficient is a, the control circuit performs the filter processing as follows: dg=(1-a)dgZ -1 A low-pass filter process represented by +a(d1-d2) may be performed.

[0094] In this way, it is possible to perform filtering on d1-d2, which is the difference between the first ADC output digital value and the second ADC output digital value, to obtain a digital value dg that has been subjected to low-pass filtering with a cutoff frequency set by the filter coefficient a.

[0095] In this embodiment, the filter coefficient a may be equal to or smaller than 0.5.

[0096] In this way, it is possible to obtain a filtered digital value dg with reduced noise compared to d1-d2 that has not been subjected to filtering. By using the digital value dg with reduced noise in this way, it is possible to reduce the output noise of the A / D converter compared to the case where d1-d2 that has not been subjected to filtering is used.

[0097] In this embodiment, the filter coefficient a may be equal to or greater than 0.125.

[0098] In this way, the output noise of the A / D converter can be reduced, and the decrease in responsiveness caused by the filtering process can also be suppressed.

[0099] Furthermore, in this embodiment, when the first DAC input digital value is n1, the second DAC input digital value is n2, the first ADC output digital value is d1, the digital value after filtering is dg, and the ADC result data is DQ, the control circuit may determine the ADC result data by DQ=n1+(n2-n1)×(d1 / dg).

[0100] In this way, the A / D conversion circuit and the D / A conversion circuit perform conversion based on the first DAC input digital value and conversion based on the second DAC input digital value, and the control circuit performs arithmetic processing of DQ = n1 + (n2 - n1) x (d1 / dg), thereby realizing an A / D converter with higher accuracy than the resolution of the A / D conversion circuit. Also, because the control circuit performs arithmetic processing using the filtered digital value dg rather than d1 - d2, it is possible to reduce noise in the ADC result data DQ compared to when d1 - d2 is used.

[0101] In this embodiment, the input signal is an input voltage, the D / A conversion circuit outputs a DAC output voltage obtained by D / A converting a DAC input digital value as a DAC output signal, and the differential output circuit may be an amplifier circuit that differentially amplifies the input voltage and the DAC output voltage.

[0102] By providing such an amplifier circuit, the difference between the input signal and the DAC output signal can be amplified by the amplifier circuit and the amplified differential signal can be input to the A / D conversion circuit. Therefore, the A / D conversion circuit can perform A / D conversion on the differential signal with a wide amplitude range amplified by the amplifier circuit, enabling high-precision A / D conversion to be realized.

[0103] In this embodiment, the input signal is an input current, the D / A conversion circuit outputs a DAC output current obtained by D / A converting the DAC input digital value as a DAC output signal, and the differential output circuit outputs the difference between the input current and the DAC output current as a differential signal.

[0104] In this way, even when the input signal is an input current, the value of this input current can be A / D converted with high resolution and output as ADC result data.

[0105] This embodiment also relates to a digital output temperature sensor that includes the A / D converter described above and a temperature sensor circuit that detects temperature and outputs a temperature detection voltage, and the differential output circuit receives the temperature detection voltage as an input voltage.

[0106] In this way, it is possible to realize a digital output temperature sensor that can convert the temperature detection voltage, which is the temperature detection result of the temperature sensor circuit, into ADC result data of a digital value and output it.

[0107] This embodiment also relates to a digital output temperature sensor that includes the A / D converter described above and a temperature sensor circuit that detects temperature and outputs a temperature detection current, and the differential output circuit receives the temperature detection current as an input current.

[0108] In this way, it is possible to realize a digital output temperature sensor that can convert the temperature detection current, which is the temperature detection result of the temperature sensor circuit, into ADC result data of a digital value and output it.

[0109] This embodiment also relates to a circuit device that includes the digital output temperature sensor described above and an oscillation circuit that causes an oscillator to oscillate, and the digital output temperature sensor detects the ambient temperature of the oscillator and outputs the ADC result data as temperature detection data.

[0110] In this way, a circuit device can be realized that can detect the ambient temperature of the vibrator and output the detected temperature data.

[0111] The present embodiment also relates to an oscillator including the circuit device described above and a resonator.

[0112] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy may be replaced with that different term anywhere in the specification or drawings. All combinations of the present embodiment and modifications are also included in the scope of the present disclosure. Furthermore, the configurations and operations of the A / D converter, digital output temperature sensor, circuit device, and oscillator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0113] 4...oscillator, 10...resonator, 15...package, 16...base, 17...lid, 18, 19...external terminal, 20...circuit device, 21...oscillator circuit, 22...variable capacitance circuit, 23...output circuit, 24...processing circuit, 25...temperature compensation circuit, 30...A / D converter, 40...D / A conversion circuit, 50...differential output circuit, 51...amplifier circuit, 60...A / D conversion circuit, 70...control circuit, 72...arithmetic circuit, 73...gain multiplier, 74...integrator, 75...quantizer, 76...delay element, 77...adder, 78...selector, 80...digital output temperature sensor, 90...temperature sensor circuit, 92...filter processing section, 93, 94...adder, 95...multiplier, 96...delay unit, BMP...bump, CK...clock signal, DFC...frequency control data, DQ...ADC result data, DS...differential signal, OSC...oscillation signal, VIN...input signal, VN...DAC output signal, VTP...temperature detection voltage, Vn, Vn2...DAC output signal, a...filter coefficient, d, d1, d2...ADC output digital value, n, n1, n2...DAC input digital value

Claims

1. An A / D converter that performs A / D conversion on an input signal and outputs ADC result data, a D / A conversion circuit that performs D / A conversion on a DAC input digital value and outputs a DAC output signal; a differential output circuit that outputs a differential signal based on a difference between the input signal and the DAC output signal; an A / D conversion circuit that performs A / D conversion on the differential signal and outputs an ADC output digital value; a control circuit that outputs the DAC input digital value based on the ADC output digital value; Including, The control circuit includes: outputting a first DAC input digital value and a second DAC input digital value different from the first DAC input digital value as the DAC input digital value; performing a filter process on a difference between a first ADC output digital value, which is the ADC output digital value obtained corresponding to the first DAC input digital value, and a second ADC output digital value, which is the ADC output digital value obtained corresponding to the second DAC input digital value, to obtain a digital value after the filter process; an A / D converter that determines the ADC result data based on the first ADC output digital value, the filtered digital value, and the DAC input digital value.

2. 2. The A / D converter according to claim 1, When the first ADC output digital value is d1, the second ADC output digital value is d2, the filtered digital value is dg, and a filter coefficient is a, The control circuit performs the filtering process by: dg=(1-a)dgZ －１ +a(d1-d2) is a low-pass filter processing method according to the present invention.

3. 3. The A / D converter according to claim 2, 13. An A / D converter according to claim 12, wherein the filter coefficient a is 0.5 or less.

4. 4. The A / D converter according to claim 3, 13. An A / D converter, wherein the filter coefficient a is 0.125 or greater.

5. 2. The A / D converter according to claim 1, When the first DAC input digital value is n1, the second DAC input digital value is n2, the first ADC output digital value is d1, the filtered digital value is dg, and the ADC result data is DQ, The control circuit includes: The A / D converter is characterized in that the ADC result data is calculated by DQ=n1+(n2-n1)×(d1 / dg).

6. 2. The A / D converter according to claim 1, the input signal is an input voltage; the D / A conversion circuit outputs a DAC output voltage obtained by D / A converting the DAC input digital value as the DAC output signal; The A / D converter, wherein the differential output circuit is an amplifier circuit that differentially amplifies the input voltage and the DAC output voltage.

7. 2. The A / D converter according to claim 1, the input signal is an input current; the D / A conversion circuit outputs a DAC output current obtained by D / A converting the DAC input digital value as the DAC output signal; The A / D converter, wherein the differential output circuit outputs a difference between the input current and the DAC output current as the differential signal.

8. An A / D converter according to claim 6; a temperature sensor circuit that detects a temperature and outputs a temperature detection voltage; Including, The digital output temperature sensor is characterized in that the temperature detection voltage is input to the differential output circuit as the input voltage.

9. An A / D converter according to claim 7; a temperature sensor circuit that detects a temperature and outputs a temperature detection current; Including, A digital output temperature sensor, wherein the temperature detection current is input to the differential output circuit as the input current.

10. A digital output temperature sensor according to claim 8 or 9; An oscillator circuit for oscillating the oscillator; Including, The circuit device, wherein the digital output temperature sensor detects an ambient temperature of the vibrator and outputs the ADC result data as temperature detection data.

11. A circuit arrangement according to claim 10; The oscillator; 16. An oscillator comprising:

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