Semiconductor device and electronic apparatus

Abstract

To solve a problem that there is room for further examination regarding communication speed in a semiconductor device.SOLUTION: A semiconductor device (100) includes a transmission circuit (200) and a receiving circuit (300). The transmission circuit (200) has: a first communication mode (MD1) which transmits, as a communication mode, a first communication signal (SD1) of a first bit width as a communication signal (SD); and a second communication mode (MD2) which transmits, as a communication signal (SD), at least a second communication signal (SD2) among the first communication signal (SD1) and the second communication signal (SD2) having a second bit width shorter than the first bit width. The receiving circuit (300) is configured to discriminate the first communication mode (MD1) and the second communication mode (MD2) on the basis of mode setting parameters (SD1c and SD1p) contained in the first communication signal (SD1).SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor device and an electronic device. [Background technology]

[0002] Traditionally, communication between two chips has relied on a relatively slow communications protocol.

[0003] As an example of the related art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-106134 A

[0005] [overview] The semiconductor device disclosed in Patent Document 1 leaves room for further consideration in terms of communication speed.

[0006] The semiconductor device disclosed in this specification includes a transmitting circuit and a receiving circuit. The transmitting circuit is configured to transmit a communication signal. The receiving circuit is configured to receive the communication signal. The transmitting circuit includes, as communication modes, a first communication mode in which a first communication signal having a first bit width is transmitted as the communication signal, and a second communication mode in which at least a second communication signal out of the first communication signal and a second communication signal having a second bit width shorter than the first bit width is transmitted as the communication signal. The receiving circuit is configured to distinguish between the first communication mode and the second communication mode based on a mode setting parameter included in the first communication signal.

[0007] The electronic device disclosed in this specification includes the semiconductor device having the above-described configuration. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a configuration of a semiconductor device 100 according to the present disclosure. [Diagram 2] FIG. 2 is a diagram showing the logic level of the chip select line CSB, the logic level of the clock line CLK, and the configuration of the communication signal SD. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of the slave side internal circuit 302. As shown in FIG. [Figure 4] FIG. 4 is a timing chart showing the timing of emergency internal control. [Diagram 5] FIG. 5 is a diagram showing the voltage level of the chip select line CSB, the voltage level of the clock line CLK, and the configuration of the second communication signal SD2 in the second communication mode MD2. [Figure 6] FIG. 6 is a diagram showing a manner in which the first communication signal SD1 is sent during the second communication mode MD2. [Figure 7] FIG. 7 is a diagram showing a mode in which a first communication signal SD1 of four bytes in total is transmitted. [Figure 8] FIG. 8 is a diagram showing a mode in which a first communication signal SD1 of three bytes in total is transmitted. [Figure 9] FIG. 9 is a diagram showing the configuration of the communication signal SD when switching from the first communication mode MD1 to the second communication mode MD2. [Figure 10] FIG. 10 is a diagram showing the configuration of the communication signal SD when switching from the second communication mode MD2 to the first communication mode MD1. [Figure 11] FIG. 11 is a diagram showing a control flow when the LIN Auto Addressing function is executed. [Figure 12] FIG. 12 is a diagram showing a detailed aspect of step St20 shown in FIG.

[0009] [Detailed Description] <Basic Configuration of Semiconductor Device 100> Fig. 1 is a block diagram showing a configuration of a semiconductor device 100 according to the present disclosure. As shown in Fig. 1, the semiconductor device 100 is mounted on an electronic device 500 such as an in-vehicle network device. The semiconductor device 100 includes a master chip 200 (transmitting circuit) and a slave chip 300 (receiving circuit).

[0010] The master chip 200 is also called a host device and is a microcomputer or the like. The slave chip 300 includes an analog circuit that operates under the control of the master chip 200. Each of the master chip 200 and the slave chip 300 is a chip that integrates a plurality of circuit elements and the like, which will be described later. The semiconductor device 100 is a semiconductor integrated circuit (LSI [Large Scale Integration]) configured by sealing the master chip 200 and the slave chip 300 in a single package.

[0011] The master chip 200 and the slave chip 300 are connected via a plurality of signal lines (in accordance with FIG. 1, a clock line CLK, data lines SDI and SDO, and a chip select line CSB).

[0012] The master chip 200 has a number of terminals (MCLK terminal, MCSB terminal, MSDI terminal, and MSDO terminal in reference to FIG. 1) as means for establishing communication with the outside of the chip. The MCLK terminal is connected to a clock line CLK. The MCSB terminal is connected to a chip select line CSB. The MSDI terminal is connected to a data line SDI. The MSDO terminal is connected to a data line SDO.

[0013] The master chip 200 and the slave chip 300 are configured to be able to exchange communication signals SD (see FIG. 2) by serial communication (for example, SPI communication) via a clock line CLK, data lines SDI, SDO, and a chip select line CSB.

[0014] When the communication signal SD is transmitted from the master chip 200 to the slave chip 300, it passes through the data line SDO, and when it is transmitted from the slave chip 300 to the master chip 200, it passes through the data line SDI.

[0015] The master chip 200 transmits the first communication signal SD1 to the slave chip 300 as the communication signal SD.

[0016] 2 is a diagram showing the logic level of the chip select line CSB, the logic level of the clock line CLK, and the configuration of the communication signal SD. As shown in FIG. 2, the communication signal SD includes at least one (two in this figure) first communication signal SD1.

[0017] The first communication signal SD1 is composed of a bit group including a plurality of bits. Here, the first communication signal SD1 is 9 bits wide. The first communication signal SD1 is composed of a 1-bit command / data determination bit D / C and 8-bit parameter bits D0 to D7. The command / data determination bit D / C stores a logical value of high level (=1) or low level (=0). The parameter bits D0 to D7 store a logical value of 1 or 0.

[0018] The first communication signal SD1 includes a command signal SD1c or a parameter signal SD1p.

[0019] The command signal SD1c is the first communication signal SD1 that specifies the type of command to be executed by the slave chip 300. In the command signal SD1c, a low-level logical value is stored in the command / data determination bit D / C. Each of the parameter bits D0 to D7 of the command signal SD1c stores a logical value according to the type of command to be executed by the slave chip 300.

[0020] The parameter signal SD1p is the first communication signal SD1 that specifies parameters used for a predetermined control (for example, parameters used when executing a command specified in the immediately preceding command signal SD1c). The parameter signal SD1p has a high-level logical value stored in the command / data determination bit D / C. Each of the parameter bits D0 to D7 of the parameter signal SD1p stores a logical value corresponding to the parameter used for the predetermined control.

[0021] 1 again, the master chip 200 includes a master side control circuit 202 and a master side interface 210. The master side control circuit 202 generates a communication signal SD. Specifically, this is as follows.

[0022] When generating a command signal SD1c, the master side control circuit 202 stores a low-level logical value in the command / data determination bit D / C, and stores a parameter defining the type of command in the parameter bits D0 to D7. When generating a parameter signal SD1p, the master side control circuit 202 stores a high-level logical value in the command / data determination bit D / C, and stores a parameter value to be passed to the slave chip 300 in the parameter bits D0 to D7. The master side control circuit 202 inputs the generated communication signal SD to the master side interface 210.

[0023] The master side interface 210 is a serial interface for transmitting and receiving signals. The master side interface 210 is connected to an MCLK terminal, an MCSB terminal, an MSDI terminal, and an MSDO terminal. The master side interface 210 transmits a communication signal SD input from the master side control circuit 202 to the slave chip 300 (more specifically, a slave side interface 310 described later) via each signal line.

[0024] The slave chip 300 has a number of terminals (SCLK terminal, SCSB terminal, SSDI terminal, and SSDO terminal in reference to FIG. 1) as means for establishing communication with the outside of the chip. The SCLK terminal is connected to a clock line CLK. The SCSB terminal is connected to a chip select line CSB. The SSDO terminal is connected to a data line SDI. The SSDI terminal is connected to a data line SDO.

[0025] The slave chip 300 includes a slave side interface 310 and a slave side internal circuit 302 (an internal control circuit).

[0026] The slave side interface 310 is a serial interface for transmitting and receiving signals. The slave side interface 310 is connected to an SCLK terminal, an SCSB terminal, an SSDI terminal, and an SSDO terminal. The slave side interface 310 receives a communication signal SD from the master chip 200 (more specifically, the master side interface 210) via each signal line.

[0027] The slave side interface 310 inputs the received communication signal SD to the slave side internal circuit 302. The slave chip 300 may also employ a configuration including a register. In this case, the slave side interface 310 writes at least a part of the communication signal SD to a specified address of the register based on parameter bits D0 to D7 of an address bit group (not shown) included in the received communication signal SD. Furthermore, in this case, the slave side interface 310 may directly input the communication signal SD to the slave side internal circuit 302, or may temporarily store the communication signal SD in a register and input the communication signal SD (or a part of the communication signal SD) stored in the register to the slave side internal circuit 302.

[0028] The slave side internal circuit 302 is configured to be able to execute a predetermined internal control in response to the received communication signal SD. A specific example of the internal control will be described.

[0029] Fig. 3 is a block diagram showing an example of the configuration of the slave-side internal circuit 302. As shown in Fig. 3, the slave-side internal circuit 302 includes a switch control circuit 305, a comparator C1, an operational amplifier OP1, current sources CS1 and CS2, a transistor T1, diodes d1 to d4, resistors R1 to R5, switches SW1 to SW3, and a drive control circuit A1. Note that only the main parts of the configuration of the slave-side internal circuit 302 that are relevant to the configuration of the present disclosure will be described here, and descriptions of other parts will be omitted.

[0030] The switch control circuit 305 generates internal control signals S1-S3 in response to the communication signal SD (more specifically, the command / data determination bit D / C and the parameter bits D0-D7) input from the slave side interface 310, and inputs them to the switches SW1-SW3. The switches SW1-SW3 are on / off controlled in response to the internal control signals S1-S3.

[0031] Predetermined control signals S4, S5 are output from the comparator C1 and the operational amplifier OP1 in accordance with the on / off control states of SW1 to SW3. The slave side internal circuit 302 performs predetermined internal control in accordance with the control signals S4, S5.

[0032] <Normal communication protocol> Next, a normal communication protocol of the communication signal SD will be described. The semiconductor device 100 can execute a first communication mode MD1. The first communication mode MD1 is defined as a communication protocol of the communication signal SD in the semiconductor device 100 in normal operation. In the first communication mode MD1, the master chip 200 transmits at least one first communication signal SD1 to the slave chip 300. Specifically, it is as follows.

[0033] First, the master-side interface 210 outputs the communication signal SD one bit at a time in sequence, starting from the first bit (in reference to FIG. 2, this is the command / data determination bit D / C of the first communication signal SD1) via the MSDO terminal. Each bit output from the MSDO terminal is input to the SSDI terminal one bit at a time in sequence, via the SDO line. The slave-side interface 310 inputs the bits input to SSDI to the slave-side internal circuit 302 one bit at a time.

[0034] At this time, the slave-side internal circuit 302 detects the logic level of the command / data determination bit D / C input from the slave-side interface 310. Then, depending on the detection result, the slave-side internal circuit 302 determines whether the input first communication signal SD1 is a command signal SD1c or a parameter signal SD1p, and performs predetermined internal control.

[0035] <Considerations on communication protocols in emergencies> Incidentally, regarding the internal control of the slave chip 300 (more specifically, the slave side internal circuit 302) by the master chip 200 using the communication signal SD, there is a demand for emergency internal control in addition to the basic control in the first communication mode MD1 as described above. One example of such control is the LIN Auto Addressing function conforming to the LIN standard [Local Interconnect Network].

[0036] Fig. 4 is a timing chart showing the timing of emergency internal control. As shown in Fig. 4, the above-mentioned emergency internal control is performed, for example, when the internal control of the slave side internal circuit 302 (for example, ON / OFF control of the switches SW1 to SW3) is performed at multiple times (five times at times t1, t2, t3, t4, and t5 in this figure) in a relatively short period (a period of 26 TBit from time t1 to time t5 in this figure). Specifically, it is as follows.

[0037] As shown in FIG. 3 and FIG. 4, when time t1 arrives, the switches SW2 and SW3 are turned off to turn off the current supply from the current sources CS1 and CS2. When time t2 arrives, the switch SW2 is turned on to turn on the current supply from the current source CS1. When time t4 arrives, the switches SW2 and SW3 are turned on to turn on the current supply from the current sources CS1 and CS2. At time t5, the switches SW2 and SW3 are turned off to turn off the current supply from the current sources CS1 and CS2 (not shown). Depending on the control state of the slave side internal circuit 302, the switches SW2 and SW3 may be turned off at time t3 to turn off the current supply from the current sources CS1 and CS2. In this case, no new control is performed at time t4, and the same control state is maintained from time t3 to time t5.

[0038] Here, as described above, the time t1 to time t5 is set to a relatively short time. However, the first communication signal SD1 as described above has a relatively wide bit width for the period from time t1 to time t5 (here, a period of 26 TBit). Thus, if an emergency control as described above is to be performed by transmitting the first communication signal SD1 in the first communication mode MD1, there is a risk that the internal control of the slave side internal circuit 302 will not be able to keep up with each timing from time t1 to time t5.

[0039] In a conventional general semiconductor device, the communication signal SD is transmitted from the master chip 200 to the slave chip 300 only in the first communication mode MD1 described above. In such a general semiconductor device, it is difficult to realize the emergency internal control of the slave side internal circuit 302 as described above.

[0040] In response to such problems, the master chip 200 according to the semiconductor device 100 of the present disclosure is configured to be capable of executing a second communication mode MD2, in addition to the first communication mode MD1 described above, as a communication mode. The second communication mode MD2 is defined as an emergency communication protocol for urgently controlling the slave chip 300. The semiconductor device 100 can execute the emergency internal control of the slave-side internal circuit 302 as described above by transmitting the communication signal SD from the master chip 200 to the slave chip 300 in the second communication mode MD2. Hereinafter, the configuration related to the second communication mode MD2 according to the semiconductor device 100 of the present disclosure will be described in detail.

[0041] <Configuration related to the second communication mode MD2> FIG. 5 is a diagram showing the voltage level of the chip select line CSB, the voltage level of the clock line CLK, and the configuration of the second communication signal SD2 during the second communication mode MD2. The master-side control circuit 202 generates a second communication signal SD2 as shown in FIG. 5 in addition to the first communication signal SD1 described above.

[0042] The second communication signal SD2 is composed of a bit group including a plurality of bits. The bit width of the second communication signal SD2 is set shorter than that of the first communication signal SD1 (= command signal SD1c or parameter signal SD1p). Here, the bit width of the second communication signal SD2 is 4 bits. The second communication signal SD2 includes an emergency determination bit EC with a 1-bit width and emergency parameter bits ED0 to ED2 with a 3-bit width.

[0043] The emergency determination bit EC stores a logical value of high level (=1) or low level (=0). The logical value of the emergency determination bit EC specifies whether the first communication signal SD1 or the second communication signal SD2 is arranged following the second communication signal SD2 in the communication signal SD. Specifically, when the logical value of the emergency determination bit EC is high level, the second communication signal SD2 is further arranged following the second communication signal SD2. When the logical value of the emergency determination bit EC is low level, the first communication signal SD1 is arranged following the second communication signal SD2.

[0044] The emergency parameter bits ED0 to ED2 store logical values ​​of 1 or 0. The emergency parameter bits ED0 to ED2 correspond to the switches SW1 to SW3 of the slave-side internal circuit 302, respectively. Specifically, the emergency parameter bit ED0 specifies the on / off state of the switch SW1, the emergency parameter bit ED1 specifies the on / off state of the switch SW2, and the emergency parameter bit ED2 specifies the on / off state of the switch SE3.

[0045] In the second communication mode MD2, the master chip 200 transmits a communication signal SD including at least the second communication signal SD2 of the first communication signal SD1 and the second communication signal SD2 to the slave chip 300. In other words, during the second communication mode MD2, the master chip 200 can transmit the second communication signal SD2 and transmit the first communication signal SD1 without switching to the first communication mode MD1.

[0046] When the master side control circuit 202 transmits the second communication signal SD2 consecutively, it sets the logical level of the emergency determination bit EC of the second communication signal SD2 transmitted first to a high level and stores a predetermined logical value in the emergency parameter bits ED0 to ED2. Conversely, when the first communication signal SD1 is transmitted immediately after the second communication signal SD2, the master side control circuit 202 sets the logical level of the emergency determination bit EC of the second communication signal SD2 to a low level. In this case, the master side control circuit 202 does not store a logical value in the emergency parameter bits ED0 to ED2.

[0047] The slave-side internal circuit 302 determines whether to receive the first communication signal SD1 or the second communication signal SD2 next, depending on the logic level of the emergency determination bit EC of the received second communication signal SD2.

[0048] Specifically, when the logical level of the emergency determination bit EC of the received second communication signal SD2 is high, the slave-side internal circuit 302 determines that the slave chip 300 will next receive the second communication signal SD2. In this case, the slave-side internal circuit 302 detects the emergency parameter bits ED0-ED2 following the emergency determination bit EC. Then, the slave-side internal circuit 302 generates internal control signals S1-S3 according to the logical values ​​of the detected emergency parameter bits ED0-ED2 to control the on / off of the switches SW1-SW3.

[0049] Conversely, when the logic level of the emergency determination bit EC of the received second communication signal SD2 is low, the slave-side internal circuit 302 determines that the slave chip 300 will next receive the first communication signal SD1.

[0050] <Regarding the mode in which the first communication signal SD1 is sent during the second communication mode MD2> Fig. 6 is a diagram showing a state in which the first communication signal SD1 is sent during the second communication mode MD2. In Fig. 6, the second communication mode MD2 is executed throughout the entire area of ​​the figure. As shown in Fig. 6, the master chip 200 can send the first communication signal SD1 during the second communication mode MD2 without switching to the first communication mode MD1.

[0051] Specifically, the master chip 200 transmits the second communication signal SD2 in which a low-level logical value is stored in the emergency determination bit EC immediately before transmitting the first communication signal SD1 (time t10 in this figure). No logical value is stored in the emergency parameter bits ED0 to ED2 of this second communication signal SD2.

[0052] The number of bytes of the first communication signal SD1 to be transmitted after transmitting this second communication signal SD2 (the second communication signal SD2 with a low-level logical value stored in the emergency determination bit EC) can be set to any number in advance. This set number is hereinafter referred to as the "set byte number." Here, an example in which the set byte number is 2 bytes will be described.

[0053] After transmitting the second communication signal SD2 (the second communication signal SD2 with a low-level logical value stored in the emergency determination bit EC) (after time t10), the master chip 200 transmits the first communication signal SD1 of a set number of bytes (here, 2 bytes). The first communication signal SD1 includes a command signal SD1c that specifies a command to be executed by the slave chip 300, and a parameter signal SD1p that specifies parameters required for executing this command.

[0054] After time t11 when the first communication signal SD1 of the set number of bytes (here, 2 bytes) is transmitted, the master chip 200 again transmits the second communication signal SD2.

[0055] When the slave chip 300 detects that the logical value of the emergency determination bit EC of the received second communication signal SD2 is at a low level, it then receives the set number of bytes of the first communication signal SD1 and the second communication signal SD2 in that order.

[0056] Fig. 7 is a diagram showing a state when a first communication signal SD1 of 4 bytes in total is transmitted. In the second communication mode MD2, when a first communication signal SD1 of a number of bytes (here, 4 bytes) that is a multiple of the set number of bytes (here, 2 bytes) is transmitted, it is as follows. Note that the state before time t11 in this figure is the same as the state explained using Fig. 6.

[0057] As shown in FIG. 7, the master chip 200 transmits the first communication signal SD1 of the set number of bytes immediately after time t10 (after time t11 in this figure), and then transmits the second communication signal SD2 in which a low-level logical value is stored in the emergency determination bit EC. Then, the master chip 200 transmits the first communication signal SD1 of the set number of bytes (2 bytes in this case) again immediately after time t12. As a result, the master chip 200 transmits the first communication signal SD1 of 4 bytes in total. When transmitting the first communication signal SD1 again after this (for example, when transmitting the first communication signal SD1 of 6 bytes in total), the master chip 200 similarly transmits the second communication signal SD2 in which a low-level logical value is stored in the emergency determination bit EC, and then transmits the first communication signal SD1 of the set number of bytes.

[0058] Fig. 8 is a diagram showing a state when a total of three bytes of the first communication signal SD1 are transmitted. In the second communication mode MD2, when a first communication signal SD1 with a number of bytes (here, three bytes) that is not a multiple of the set number of bytes (here, two bytes) is transmitted, it is as follows. Note that the state before time t11 is the same as the state described using Fig. 6.

[0059] As shown in FIG. 8, the master chip 200 transmits the first communication signal SD1 of the set number of bytes immediately after time t10 (after time t11 in this figure), and then transmits the second communication signal SD2 in which a low-level logical value is stored in the emergency determination bit EC. Then, the master chip 200 transmits the first communication signal SD1 of the set number of bytes (here, 2 bytes) again immediately after time t12. At this time, the master chip 200 responds to unnecessary first communication signals SD1 other than the necessary first communication signals SD1 with a NOP [No Operation] command (a command in which the logical values ​​of the parameter bits D0 to D7 are 0). In accordance with FIG. 8, the master chip 200 transmits a NOP command in which the logical values ​​of the parameter bits D0 to D7 are 0 in the fourth byte after the parameter signal SD1p, which is the third byte.

[0060] <Switching between the first communication mode MD1 and the second communication mode MD2> The semiconductor device 100 normally transmits and receives a communication signal SD between the master chip 200 and the slave chip 300 in the first communication mode MD1. Then, at a predetermined timing (for example, the timing immediately before time t1 shown in FIG. 4) specified by the master chip 200 (more specifically, the master side control circuit 202), the first communication mode MD1 is switched to the second communication mode MD2 to transmit and receive the communication signal SD. Control when switching from the first communication mode MD1 to the second communication mode MD2 and control when switching from the second communication mode MD2 to the first communication mode MD1 will be described in detail.

[0061] When switching the communication mode to the first communication mode MD1 or the second communication mode MD2, the master chip 200 transmits a predetermined first communication signal SD1 to the slave chip 300. Specifically, this first communication signal SD1 is a command signal SD1c that defines a switching command, and a parameter signal SD1p (mode setting parameter) that defines the type of the mode to which the communication mode is to be switched.

[0062] The logical value "10101010" ("AAh" in hexadecimal) is stored in the parameter bits D0 to D7 of the command signal SD1c that specifies the mode switching.

[0063] For the parameter bits D0 to D7 of the parameter signal SD1p, the parameter bits D0 to D7 that define the first communication mode MD1 store a logical value of "01010101" ("55h" in hexadecimal). The parameter bits D0 to D7 that define the second communication mode MD2 store a logical value of "10101010" ("AAh" in hexadecimal).

[0064] The slave chip 300 detects that the communication mode is to be switched by receiving the command signal SD1c in which the logical value "10101010" is stored in the parameter bits D0 to D7. The switching to each mode will be described in detail below.

[0065] <Switching from the first communication mode MD1 to the second communication mode MD2> Fig. 9 is a diagram showing the configuration of the communication signal SD when switching from the first communication mode MD1 to the second communication mode MD2. In Fig. 9, the communication mode switches from the first communication mode MD1 to the second communication mode MD2 at time t20. The communication mode before time t20 is the first communication mode MD1. The communication mode after time t20 is the second communication mode MD2.

[0066] As shown in FIG. 9, when switching from the first communication mode MD1 to the second communication mode MD2, the master chip 200 transmits a predetermined command signal SD1c and parameter signal SD1p at the end of the first communication mode MD1 (just before the second communication mode MD2, or just before time t20 in this figure).

[0067] At this time, the parameter bits D0 to D7 of the command signal SD1c store the logical value "10101010" that specifies the mode switching. Also, the parameter bits D0 to D7 of the parameter signal SD1p store the logical value "10101010" that specifies the switching to the second communication mode MD2.

[0068] The slave chip 300 detects that the communication mode is switched by receiving the command signal SD1c in which the logical value "10101010" is stored in the parameter bits D0 to D7, and then detects that the communication mode has been switched from the first communication mode MD1 to the second communication mode MD2 by receiving the parameter signal SD1p in which the logical value "10101010" is stored in the parameter bits D0 to D7.

[0069] <Switching from the second communication mode MD2 to the first communication mode MD1> FIG. 10 is a diagram showing the configuration of the communication signal SD when switching from the second communication mode MD2 to the first communication mode MD1. In FIG. 10, at time t30 as a boundary, the communication mode is switched from the second communication mode MD2 to the first communication mode MD1. The communication mode before time t30 is the second communication mode MD2. The communication mode after time t30 is the first communication mode MD1.

[0070] As shown in FIG. 10, when the master chip 200 switches from the second communication mode MD2 to the first communication mode MD1, first, the second communication signal SD2 in which a low-level logical value is stored in the emergency determination bit EC is transmitted. In the emergency parameter bits ED0 to ED2 of this second communication signal SD2, no logical value is stored. Subsequently, the command signal SD1c and the parameter signal SD1p are transmitted.

[0071] At this time, the logical value "10101010" that defines the mode switch is stored in the parameter bits D0 to D7 of the command signal SD1c. Also, at this time, the logical value "01010101" that defines the switch to the first communication mode MD1 is stored in the parameter bits D0 to D7 of the parameter signal SD1p.

[0072] The slave chip 300 detects that the communication mode is switched by receiving the command signal SD1c in which the logical value "10101010" is stored in the parameter bits D0 to D7. Then, by subsequently receiving the parameter signal SD1p in which the logical value "01010101" is stored in the parameter bits D0 to D7, it is detected that the communication mode has been switched from the second communication mode MD2 to the first communication mode MD1.

[0073] <Regarding the LIN Auto Addressing function> The switching between the first communication mode MD1 and the second communication mode MD2 in the LIN Auto Addressing function will be described. FIG. 11 is a diagram showing the control flow when the LIN Auto Addressing function is executed.

[0074] As shown in FIG. 11, when the LIN Auto Addressing function is executed, first, in step St1, a BSM Initialization command is executed. Then, the communication mode is switched from the first communication mode MD1 to the second communication mode MD2. In steps St2 to St8, the communication mode is in the second communication mode MD2. In steps St2 to St8, the first communication signal SD1 and the second communication signal SD2 are transmitted from the master chip 200 to the slave chip 300 while remaining in the second communication mode MD2. In step St9, a BSM Finished command is executed. Then, the communication mode is switched from the second communication mode MD2 to the first communication mode MD1.

[0075] Next, the controls executed in each of steps St1 to St9 will be described in detail. Fig. 12 is a diagram showing detailed aspects of each of steps St1 to St9 shown in Fig. 11.

[0076] In addition, steps St1 to St9 are configured to include a common execution phase of the first control CTL1 and an execution phase of the second control CTL2. Each of steps St1 to St9 is assigned a predetermined control as the first control CTL1 and the second control CTL2. Hereinafter, when steps St1 to St9 are not distinguished from each other, steps St1 to St9 will be referred to as step Stn.

[0077] As shown in FIG. 12, step Stn includes steps Stn1 to Stn4. Step Stn1 is a phase in which the first control CTL1 is executed. Steps Stn2 to Stn4 are phases in which the second control CTL2 is executed. In the first control CTL1, the master chip 200 controls the slave chip 300 urgently using the second communication signal SD2. In the second control CTL2, the master chip 200 controls the slave chip 300 in the same manner as in a normal mode, not in an emergency mode, using the first communication signal SD1.

[0078] The first control CTL1 is assigned with the control of Auto Addressing in any of steps St1 to St9. When the first control CTL1 (control of Auto Addressing) is executed, the second communication signal SD2 is transmitted from the master chip 200 to the slave chip 300.

[0079] A different command is assigned to the second control CTL2 for each of steps St1 to St9. Specifically, in step St1, the above-mentioned BSM Initialization command is assigned to the second control CTL2. In steps St3, St5, and St7, the Next NAD command is assigned to the second control CTL2. In steps St2, St4, St6, and St8, the LIN massages command is assigned to the second control CTL2. In step St9, the above-mentioned BSM Finished command is assigned to the second control CTL2. When the second control CTL2 is executed, the first communication signal SD1 is transmitted from the master chip 200 to the slave chip 300.

[0080] The BSM Initialization command is a command for switching the communication mode from the first communication mode MD1 to the second communication mode MD2.

[0081] The Next NAD command is a command that performs a predetermined internal control using an address acquired by the Auto Addressing control after determining that the address is valid. When the Next NAD command is executed, the internal control of the slave side internal circuit 302 described with reference to Figures 3 and 4 is performed. That is, the second communication signal SD2 is transmitted from the master chip 200 to the slave chip 300.

[0082] The LIN massages command is a command that performs a predetermined internal control that is not related to the LIN Auto Addressing function. Therefore, when the LIN massages command is executed in steps St2, St4, St6, and St8, the address acquired by the first control CTL1 is invalidated, and the predetermined internal control is performed in the master chip 200 and the slave chip 300.

[0083] The BSM Finished command is a command for switching the communication mode from the second communication mode MD2 to the first communication mode MD1.

[0084] In step St1, unlike the other steps (steps St2 to St9), step Stn1 is omitted, and command execution starts from step Stn2. That is, the Auto Addressing control of the first control CTL1 is not executed, and the BSM Initialization command of the second control CTL2 is executed.

[0085] In step St9, control is executed from step Stn1 in the same manner as in steps other than step St1 (steps St2 to St8). That is, in step St9, the Auto Addressing control is executed as the first control CTL1 to obtain an address, and then the BSM Finished command is executed while invalidating this address.

[0086] Therefore, in steps Stn2 to Stn4 of steps St2 to St9, respectively, the first communication signal SD1 is transmitted from the master chip 200 to the slave chip 300 in the second communication mode MD2. Also, in step Stn1 of steps St2 to St9, the second communication signal SD2 is transmitted from the master chip 200 to the slave chip 300 in the second communication mode MD2.

[0087] It should be noted that steps St2, St4, and St6 to St8 indicated by dashed lines in FIG. 11 are set as options, and the steps themselves may be omitted.

[0088] As described above, the master chip 200 can execute the second communication mode MD2 as a communication mode in addition to the first communication mode MD1. In the second communication mode MD2, the master chip 200 transmits the second communication signal SD2. The second communication signal SD2 is set to have a shorter bit width than the first communication signal SD1. Therefore, the master chip 200 can urgently control the slave chip 300 by the second communication mode MD2.

[0089] As described above, the slave chip 300 detects that the communication mode has been switched to the first communication mode MD1 or the second communication mode MD2 from the logical values ​​stored in the command signal SD1c and the parameter bits D0 to D7 of the parameter signal SD1p. This allows the slave chip 300 to perform appropriate internal control based on the first communication signal SD1 and the second communication signal SD2 received from the master chip 200.

[0090] As described above, the parameter bits D0 to D7 of the command signal SD1c and the parameter signal SD1p transmitted when switching the communication mode are set to a logical value of "10101010" ("55h" in hexadecimal) or a logical value of "01010101" ("AAh" in hexadecimal). The parameter bits D0 to D7 of the command signal SD1c and the parameter signal SD1p are set to logical values ​​that intentionally repeat a high level (=1) and a low level (=0). Therefore, even if noise or the like occurs, the command signal SD1c and the parameter signal SD1p are unlikely to be erroneously inserted. This makes it possible to prevent the communication mode from being unintentionally switched.

[0091] As described above, the master chip 200 can transmit the first communication signal SD1 without switching to the first communication mode MD1 in the second communication mode MD2. This makes it possible to transmit the second communication signal SD2 of the required number of bytes in the second communication mode MD2 and to transmit the first communication signal SD1 by utilizing the surplus period. The first communication signal SD1 has a longer bit width than the second communication signal SD2 and can specify more complex commands or parameters. This makes it possible to transmit a wider variety of communication signals SD from the master chip 200 to the slave chip 300 during the second communication mode MD2.

[0092] Furthermore, the emergency parameter bits ED0 to ED2 correspond to the switches SW1 to SW3, respectively. Therefore, the slave-side internal circuit 302 can control the on / off states of the switches SW1 to SW3 by directly detecting the values ​​of the emergency parameter bits ED0 to ED2. This allows the internal control of the slave-side internal circuit 302 by the second communication signal SD2 to be simplified. In other words, the slave-side internal circuit 302 can be internally controlled at higher speed by the second communication signal SD2.

[0093] <Modification> The present invention is not limited to the above-mentioned embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, the semiconductor device 100 has been described as including one slave chip 300, but it may be configured such that a plurality of slave chips 300 are connected to one master chip 200. In this case, a CSB line is provided for each slave chip 300.

[0094] Also, although the emergency parameter bits ED0 to ED2 are respectively associated with the switches SW1 to SW3 of the slave-side internal circuit 302, this is not limiting. For example, it is possible to configure so that one second communication signal SD2 can control more control targets than the number of bits of the emergency parameter bits ED0 to ED2 (three in this case).

[0095] Also, the communication between the master chip 200 and the slave chip 300 in the semiconductor device 100 in one package has been described, but it can also be used for communication between semiconductor devices 100 in different packages.

[0096] Furthermore, although serial communication has been described as an example of the communication standard, the configuration of the semiconductor device 100 of the present disclosure is also applicable to cases where other communication standards are adopted.

[0097] Also, the bit width of the first communication signal SD1 is 9 bits (1-bit command / data determination bit D / C and 8-bit parameter bits D0 to D7), but is not limited to this. For example, the bit width of the parameter bits D0 to D7 can be a multiple of 8 (e.g., 16 bits, 24 bits, 32 bits, etc.). In other words, the bit width of the first communication signal SD1 can be 8n+1 bits (n is a natural number equal to or greater than 1).

[0098] <Additional Notes> The semiconductor device (100) disclosed in the specification includes a transmitting circuit (200) configured to transmit a communication signal (SD) and a receiving circuit (300) configured to receive the communication signal (SD). The transmitting circuit (200) includes a first communication mode (MD1) for transmitting a first communication signal (SD1) of a first bit width as the communication signal (SD), and a second communication mode (MD2) for transmitting at least a second communication signal (SD2) of the first communication signal (SD1) and a second communication signal (SD2) of a second bit width shorter than the first bit width as the communication signal (SD). The receiving circuit (300) is configured to distinguish between the first communication mode (MD1) and the second communication mode (MD2) based on mode setting parameters (SD1c, SD1p) included in the first communication signal (SD1) (first configuration).

[0099] In addition, in the semiconductor device (100) of the first configuration, the second communication signal (SD2) includes a decision bit (EC) and parameter bits (ED0 to ED2), and the transmission circuit (200) is configured such that, in the second communication mode (MD2), when sending data as the second communication signal (SD2), the decision bit (EC) is set to a first logical value and values ​​are stored in the parameter bits (ED0 to ED2), and when transmitting the second communication signal (SD2) followed by the first communication signal (SD1), the decision bit (EC) of the second communication signal (SD2) is set to a second logical value (second configuration).

[0100] In addition, in a semiconductor device (100) according to a second configuration, the transmitting circuit (200) may be configured to transmit a first communication signal (SD1) storing a first parameter (10101010) as a mode setting parameter (SD1c, SD1p) when switching from the first communication mode (MD1) to the second communication mode (MD2), and to transmit a first communication signal (SD1) storing a second parameter (01010101) as the mode setting parameter (SD1p) when switching from the second communication mode (MD2) to the first communication mode (MD1), and the receiving circuit (300) may be configured to detect whether the mode setting parameter (SD1c, SD1p) included in the received first communication signal (SD1) is the first parameter (10101010) or the second parameter (01010101) and determine the first communication mode (MD1) or the second communication mode (MD2) (third configuration).

[0101] In addition, in the semiconductor device (100) relating to the second or third configuration, the receiving circuit (300) may be configured to include an internal control circuit (302) configured to perform internal control in response to the second communication signal (SD2) (fourth configuration).

[0102] Furthermore, in a semiconductor device (100) according to a fourth configuration, the second communication signal (SD2) includes at least one parameter bit (ED0 to ED2), the internal control circuit (302) includes at least one switch (SW1 to SW3) corresponding to each of the parameter bits (ED0 to ED2) included in the second communication signal (SD2), the transmission circuit (200) stores a third logic value or a fourth logic value in each parameter bit (ED0 to ED2) when transmitting data as the second communication signal (SD2), and the internal control circuit (302) performs internal control upon receiving the second communication signal (SD2) to turn off the switches (SW1 to SW3) corresponding to the parameter bits (ED0 to ED2) in which the third logic value is stored and turn on the switches (SW1 to SW3) corresponding to the parameter bits (ED0 to ED2) in which the fourth logic value is stored (fifth configuration).

[0103] In a semiconductor device (100) of any of the first to fifth configurations, the parameter bits (ED0 to ED2) are second communication parameter bits (ED0 to ED2) indicating parameters of a second communication signal (SD2), the first communication signal (SD1) includes first communication parameter bits (D0 to D7) indicating parameters of the first communication signal (SD1), and the first bit width is a bit width of the first communication signal configured so that the first parameter bits have a bit width that is a multiple of 8 (sixth configuration).

[0104] In any one of the first to sixth configurations of the semiconductor device (100), a first chip (200) on which the circuit elements of the transmission circuit (200) are integrated and a second chip (300) on which the circuit elements of the reception circuit (300) are integrated may be sealed in a single package (seventh configuration).

[0105] The electronic device (500) disclosed in the specification includes a semiconductor device (100) of any one of the first to seventh configurations (eighth configuration).

[0106] The semiconductor device (100) according to the first configuration can transmit a second communication signal (SD2) having a second bit width shorter than the first bit width using the second communication mode (MD2). Therefore, when a predetermined control signal needs to be transmitted from the transmitting circuit (200) to the receiving circuit (300) in a short time, the control signal can be transmitted at a specified timing. In other words, the receiving circuit (300) can perform internal control as specified.

[0107] According to the semiconductor device (100) of the second configuration, when the communication signal (SD) including both the first communication signal (SD1) and the second communication signal (SD2) is sent in the second communication mode (MD2), it becomes possible to suitably determine whether the signal received by the receiving circuit (300) is the first communication signal (SD1) or the second communication signal (SD2). Therefore, suitable internal control can be performed on the receiving circuit (300) side.

[0108] According to the semiconductor device (100) of the third configuration, the receiving circuit (300) can determine switching between the first communication mode (MD1) and the second communication mode (MD2). This enables more suitable internal control on the receiving circuit (300) side.

[0109] According to the semiconductor device (100) of the fourth configuration, a predetermined internal control can be performed on the receiving circuit (300) side in response to a signal generated on the transmitting circuit (200) side.

[0110] According to the semiconductor device (100) of the fifth configuration, the receiving circuit (300) can directly control the on / off of each switch (SW1 to SW3) based on the logical value stored in each parameter bit (ED0 to ED2). This simplifies the control on the receiving circuit (300) side, and can suppress a decrease in the speed of internal control.

[0111] According to the sixth configuration, it becomes possible to transmit a communication signal (SD) from the transmitting circuit (200) to the receiving circuit (300) so as to comply with an 8-bit wide communication protocol.

[0112] According to the seventh configuration, in a semiconductor device (100) sealed in a single package, when it is necessary to transmit a predetermined control signal from a transmitting circuit (200) to a receiving circuit (300) within a short period of time, it becomes possible to transmit the control signal at a specified timing.

[0113] According to the eighth configuration, when it is necessary to transmit a predetermined control signal from the transmitting circuit (200) to the receiving circuit (300) within a short period of time, an electronic device (500) can be provided that can transmit the control signal at a specified timing. [Explanation of symbols]

[0114] 100 Semiconductor device 200 Master Chip 202 Master side control circuit 210 Master side interface 300 Slave Chips 302 Slave side internal circuit 305 Switch control circuit 310 Slave side interface 500 Electronic equipment A1 Drive control circuit C1 Comparator CS1, CS2 current source D1~D4 Diodes OP1 Operational Amplifier R1~R5 Resistors SW1~SW3 Switches T1 Transistor S1~S3 Internal control signals S4, S5 control signals CLK Clock line CSB Chip Select Line CTL1 First control CTL2 Second control SDI, SDO data lines D / C command data check bit D0~D7 Parameter bits EC Urgent judgment bit ED0~ED2 Emergency parameter bits MD1 1st communication mode MD2 Second communication mode SD1 First communication signal SD1c command signal SD1p Parameter Signal SD2 Second communication signal NOP NOP command

Claims

1. a transmitter circuit configured to transmit a communication signal; a receiver circuit configured to receive the communication signal; Equipped with The transmission circuit is configured to: a first communication mode in which a first communication signal having a first bit width is transmitted as the communication signal; a second communication mode in which at least the second communication signal is transmitted as the communication signal, out of the first communication signal and a second communication signal having a second bit width shorter than the first bit width; Equipped with The receiving circuit is a semiconductor device that distinguishes between the first communication mode and the second communication mode based on a mode setting parameter included in the first communication signal.

2. the second communication signal includes decision bits and parameter bits; In the second communication mode, the transmission circuit When transmitting data as the second communication signal, the decision bit is set to a first logical value and a value is stored in the parameter bit; 2 . The semiconductor device according to claim 1 , wherein when the first communication signal is transmitted consecutively to the second communication signal, the decision bit of the second communication signal is set to a second logical value.

3. The transmission circuit includes: transmitting the first communication signal storing a first parameter as the mode setting parameter when switching from the first communication mode to the second communication mode; transmitting the first communication signal storing a second parameter as the mode setting parameter when switching from the second communication mode to the first communication mode; 3. The semiconductor device according to claim 2, wherein the receiving circuit detects whether the mode setting parameter included in the received first communication signal is the first parameter or the second parameter, and determines whether the communication mode is the first communication mode or the second communication mode.

4. 3. The semiconductor device according to claim 2, wherein the receiving circuit includes an internal control circuit configured to perform internal control in response to the second communication signal.

5. the second communication signal includes at least one of the parameter bits; the internal control circuit includes at least one switch corresponding to each of the parameter bits included in the second communication signal; the transmitting circuit stores a third logic value or a fourth logic value in each of the parameter bits when transmitting the data as the second communication signal; When the internal control circuit receives the second communication signal, turning off the switch corresponding to the parameter bit in which the third logic value is stored; 5. The semiconductor device according to claim 4, wherein the switch corresponding to the parameter bit in which the fourth logic value is stored is internally controlled to be turned on.

6. the parameter bits are second communication parameter bits indicating parameters of the second communication signal; the first communication signal includes first communication parameter bits indicative of a parameter of the first communication signal; 4. The semiconductor device according to claim 1, wherein the first bit width is a bit width of the first communication signal configured so that the first parameter bits have a bit width that is a multiple of eight.

7. a first chip on which circuit elements of the transmission circuit are integrated; a second chip on which circuit elements of the receiving circuit are integrated; 4. The semiconductor device according to claim 1, wherein the first and second electrodes are sealed in a single package.

8. 4. An electronic device comprising the semiconductor device according to claim 1.

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