Semiconductor device

Abstract

To provide a semiconductor device that can improve the characteristics.SOLUTION: According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a compound member. The first semiconductor layer includes Alx1Ga1-x1N (0≤x1<1). The first semiconductor layer includes first through fifth partial regions. The second semiconductor layer includes Alx2Ga1-x2N (0<x2<1, x1<x2). The compound member includes Alz1Ga1-z1N (0<z1≤1, x2<z1). The compound member includes first through third regions. The first absolute value of the first difference between the (10-10) face spacing in the first region and the (10-10) face spacing in the fourth partial region is greater than the third absolute value of the third difference between the (10-10) face spacing in the third region and the (10-10) face spacing in the third partial region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, in semiconductor devices such as transistors, improvements in characteristics are desired. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2011-529639 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of improving characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a compound member. The third electrode includes a first electrode portion. The position of the third electrode in a first direction from the first electrode to the second electrode is between the position of the first electrode in the first direction and the position of the second electrode in the first direction. The first semiconductor layer is made of Al x1 Ga 1-x1It includes N(0≦x1<1). The first semiconductor layer includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second direction from the first partial region to the first electrode intersects the first direction. The direction from the second partial region to the second electrode is along the second direction. The direction from the third partial region to the first electrode portion is along the second direction. The position of the fourth partial region in the first direction is between the position of the first partial region in the first direction and the position of the third partial region in the first direction. The position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and the position of the second partial region in the first direction. The second semiconductor layer is Al x2 Ga 1-x2 It includes N(0<x2<1, x1<x2). The second semiconductor layer includes a first semiconductor portion and a second semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The direction from the fifth partial region to the second semiconductor portion is along the second direction. The compound member is Al z1 Ga 1-z1 It includes N(0<z1≦1, x2<z1). The compound member includes a first region, a second region, and a third region. The first region is between the fourth partial region and the first electrode portion in the first direction. The second region is between the first electrode portion and the fifth partial region in the first direction. The third region is between the third partial region and the first electrode portion in the second direction. The absolute value of the first difference between the (10-10) plane spacing in the first region and the (10-10) plane spacing in the fourth partial region is greater than the absolute value of the third difference between the (10-10) plane spacing in the third region and the (10-10) plane spacing in the third partial region.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Diagram 2]2A and 2B are schematic cross-sectional views illustrating evaluation positions of a semiconductor device. [Diagram 3] 3(a) to 3(d) are graphs illustrating the characteristics of the semiconductor device. [Figure 4] 4(a) to 4(d) are graphs illustrating the characteristics of the semiconductor device. [Diagram 5] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first semiconductor layer 10, a second semiconductor layer 20, and a compound member 31.

[0009] The third electrode 53 includes a first electrode portion 53a. A first direction D1 from the first electrode 51 to the second electrode 52 is defined as an X-axis direction. A direction perpendicular to the X-axis direction is defined as a Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is defined as a Y-axis direction.

[0010] The position of the third electrode 53 in the first direction D1 is between the position of the first electrode 51 in the first direction D1 and the position of the second electrode 52 in the first direction D1. For example, the third electrode 53 is between the first electrode 51 and the second electrode 52 in the first direction D1. The first electrode 51, the second electrode 52, and the third electrode 53 may extend along the third direction D3 (e.g., the Y-axis direction), for example.

[0011] The first semiconductor layer 10 is Al x1 Ga 1-x1 N (0≦x1<1). The composition ratio x1 is, for example, 0 or more and 0.05 or less. The first semiconductor layer 10 may be, for example, a GaN layer. The first semiconductor layer 10 may not include, for example, impurities that impart conductivity.

[0012] The first semiconductor layer 10 includes a first partial region 11, a second partial region 12, a third partial region 13, a fourth partial region 14, and a fifth partial region 15. A second direction D2 from the first partial region 11 to the first electrode 51 intersects with the first direction D1. The second direction D2 is, for example, the Z-axis direction. The third direction D3 intersects with, for example, a plane including the first direction D1 and the second direction D2.

[0013] The direction from the second partial region 12 to the second electrode 52 is along the second direction D2. The direction from the third partial region 13 to the first electrode portion 53a is along the second direction D2.

[0014] The position of the fourth partial region 14 in the first direction D1 is between the position of the first partial region 11 in the first direction D1 and the position of the third partial region 13 in the first direction D1. The position of the fifth partial region 15 in the first direction D1 is between the position of the third partial region 13 in the first direction D1 and the position of the second partial region 12 in the first direction D1.

[0015] The second semiconductor layer 20 is Al x2 Ga 1-x2It includes N(0 < x2 < 1, x1 < x2). The composition ratio x2 is, for example, 0.15 or more and 0.35 or less. The second semiconductor layer 20 may be, for example, an AlGaN layer. The second semiconductor layer 20 may not contain impurities that provide conductivity, for example.

[0016] The second semiconductor layer 20 includes a first semiconductor portion 21 and a second semiconductor portion 22. The direction from the fourth partial region 14 to the first semiconductor portion 21 is along the second direction D2. The direction from the fifth partial region 15 to the second semiconductor portion 22 is along the second direction D2.

[0017] The compound member 31 contains Al z1 Ga 1-z1 It includes N(0 < z1 ≤ 1, x2 < z1). The composition ratio z1 may be, for example, 0.9 or more and 1 or less. The composition ratio z1 may be, for example, substantially 1. The compound member 31 may be, for example, an AlN layer.

[0018] The compound member 31 includes a first region 31a, a second region 31b, and a third region 31c. The first region 31a is between the fourth partial region 14 and the first electrode portion 53a in the first direction D1. The second region 31b is between the first electrode portion 53a and the fifth partial region 15 in the first direction D1. The third region 31c is between the third partial region 13 and the first electrode portion 53a in the second direction D2.

[0019] The first semiconductor layer 10, the second semiconductor layer 20, and the compound member 31 include crystals.

[0020] In an embodiment, the current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be a potential based on the potential of the first electrode 51. The first electrode 51 functions as a source electrode, for example. The second electrode 52 functions as a drain electrode, for example. The third electrode 53 functions as a gate electrode, for example. The semiconductor device 110 is a transistor, for example.

[0021] 1, the first semiconductor layer 10 includes a region facing the second semiconductor layer 20. A carrier region 10C is formed in this region. The carrier region 10C is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0022] As shown in FIG. 1, the first electrode portion 53a is between the fourth partial region 14 and the fifth partial region 15 in the first direction D1. For example, a recess (e.g., a trench) is formed in a semiconductor member including the first semiconductor layer 10 and the second semiconductor layer 20. A compound member 31 or the like is formed inside the recess, and the third electrode 53 is formed in the remaining space. The third electrode 53 is, for example, a recessed gate electrode. For example, a high threshold voltage is obtained. For example, a normally-off operation is obtained.

[0023] For example, the first region 31a and the fourth partial region 14 correspond to a side surface of the recess, the second region 31b and the fifth partial region 15 correspond to another side surface of the recess, and the third partial region 13 and the third region 31c correspond to the bottom of the recess.

[0024] In the embodiment, the difference between the (10-10) interfacial spacing in the first region 31a and the (10-10) interfacial spacing in the fourth partial region 14 is defined as a first difference Δa1. The difference between the (10-10) interfacial spacing in the third region 31c and the (10-10) interfacial spacing in the third partial region 13 is defined as a third difference Δa3. In the embodiment, a first absolute value of the first difference Δa1 is greater than a third absolute value of the third difference Δa3. The description of "(10-10) interfacial spacing" indicates that a "bar" is added to the number after "-".

[0025] In a portion corresponding to the side surface of the recess, the difference in the (10-10) interplanar spacing (first difference Δa1) is large between the compound member 31 and the first semiconductor layer 10. In a portion corresponding to the bottom of the recess, the difference in the (10-10) interplanar spacing (third difference Δa3) is small between the compound member 31 and the first semiconductor layer 10.

[0026] The difference in crystal lattice length is small in the portion corresponding to the bottom of the recess. This allows high crystallinity to be obtained, for example, in the third partial region 13. This makes it easy to obtain high mobility. For example, low on-resistance can be obtained. According to the embodiment, a semiconductor device with improved characteristics can be provided.

[0027] On the other hand, there is a large difference in crystal lattice length in the portion corresponding to the side surface of the recess. For example, the (10-10) interplanar spacing is not consistent on the side surface of the recess. This suppresses carrier generation on the side surface of the recess. This makes it easier to obtain a high threshold voltage. For example, it makes it easier to obtain a stable high threshold voltage. According to the embodiment, it is possible to provide a semiconductor device with improved characteristics.

[0028] In the embodiment, the second direction D2 intersects with the (0001) plane of the crystal included in the first semiconductor layer 10. The angle between the second direction D2 and the (0001) plane is, for example, not less than 85 degrees and not more than 95 degrees. The first direction D1 may intersect with, for example, the (10-10) plane of the crystal included in the first semiconductor layer 10. The angle between the first direction D1 and the (10-10) plane is, for example, not less than 85 degrees and not more than 95 degrees.

[0029] 1, the compound member 31 may further include a fourth region 31d and a fifth region 31e. The fourth region 31d is between the first semiconductor portion 21 and the first electrode portion 53a in the first direction D1. The fifth region 31e is between the first electrode portion 53a and the second semiconductor portion 22 in the first direction D1. For example, the fourth region 31d contacts the first semiconductor portion 21. The fifth region 31e contacts the second semiconductor portion 22.

[0030] The compound member 31 may further include a sixth region 31f and a seventh region 31g. The first semiconductor portion 21 is provided between the fourth partial region 14 and the sixth region 31f. The second semiconductor portion 22 is provided between the fifth partial region 15 and the seventh region 31g.

[0031] 1, the semiconductor device 110 may further include a first insulating member 41. The first insulating member 41 includes a first insulating region 41a, a second insulating region 41b, and a third insulating region 41c. The first insulating region 41a is provided between the first region 31a and the first electrode portion 53a in the first direction D1. The second insulating region 41b is provided between the first electrode portion 53a and the second region 31b in the first direction D1. The third insulating region 41c is provided between the third region 31c and the first electrode portion 53a in the second direction D2.

[0032] The first insulating member 41 may further include a fourth insulating region 41d and a fifth insulating region 41e. The fourth insulating region 41d is provided between the fourth region 31d and the first electrode portion 53a in the first direction D1. The fifth insulating region 41e is provided between the first electrode portion 53a and the fifth region 31e in the first direction D1.

[0033] The first insulating member 41 may further include a sixth insulating region 41f and a seventh insulating region 41g. The sixth region 31f is provided between the first semiconductor portion 21 and the sixth insulating region 41f. The seventh region 31g is provided between the second semiconductor portion 22 and the seventh insulating region 41g.

[0034] Examples of the characteristics of the semiconductor device will now be described. 2A and 2B are schematic cross-sectional views illustrating evaluation positions of a semiconductor device. 2(a), the fourth partial region 14 includes a first position 14p and a second position 14q. The first position 14p is located between the second position 14q and the first region 31a in the first direction D1. The distance between the first position 14p and the first region 31a in the first direction D1 is 1 nm. The distance between the second position 14q and the first region 31a in the first direction D1 is 10 nm.

[0035] 2(b), the third partial region 13 includes a third position 13p and a fourth position 13q. The third position 13p is between the fourth position 13q and the third region 31c in the second direction D2. The distance between the third position 13p and the third region 31c in the second direction D2 is 1 nm. The distance between the fourth position 13q and the third region 31c in the second direction D2 is 10 nm.

[0036] 3(a) to 3(d) are graphs illustrating the characteristics of the semiconductor device. These figures illustrate the evaluation results of the first sample SPL1. The vertical axis of these figures is the lattice spacing LS. FIG. 3(a) shows the measurement results of the (10-10) lattice spacing in the first region 31a, the first position 14p, and the second position 14q. FIG. 3(b) shows the measurement results of the (10-10) lattice spacing in the third region 31c, the third position 13p, and the fourth position 13q. FIG. 3(c) shows the measurement results of the (0001) lattice spacing in the first region 31a, the first position 14p, and the second position 14q. FIG. 3(d) shows the measurement results of the (0001) lattice spacing in the third region 31c, the third position 13p, and the fourth position 13q. The lattice spacing is obtained by electron diffraction.

[0037] 3(a) and 3(c), the interplanar spacing value in the first region 31a is a value at a position 1 nm from the boundary between the fourth partial region 14 and the first region 31a. In Fig. 3(b) and 3(d), the interplanar spacing value in the third region 31c is a value at a position 1 nm from the boundary between the third partial region 13 and the third region 31c. The first sample SPL1 corresponds to the semiconductor device 110 according to the embodiment.

[0038] As shown in Fig. 3(a), in the first sample SPL1, the value of the (10-10) interplanar spacing is substantially constant at the first position 14p and the second position 14q. As shown in Fig. 3(b), in the first sample SPL1, the value of the (10-10) interplanar spacing is substantially constant at the third position 13p and the fourth position 13q. As shown in Fig. 3(c), in the first sample SPL1, the value of the (0001) interplanar spacing is substantially constant at the first position 14p and the second position 14q. As shown in Fig. 3(d), in the first sample SPL1, the value of the (0001) interplanar spacing is substantially constant at the third position 13p and the fourth position 13q.

[0039] 3(a), in the first sample SPL1, the (10-10) interplanar spacing in the first region 31a is smaller than the (10-10) interplanar spacing in the fourth partial region 14 (the first position 14p and the second position 14q). The difference between the (10-10) interplanar spacing in the first region 31a and the (10-10) interplanar spacing in the fourth partial region 14 corresponds to the first difference Δa1.

[0040] 3(b), in the first sample SPL1, the (10-10) interplanar spacing in the third region 31c is substantially the same as the (10-10) interplanar spacing in the third partial region 13 (the third position 13p and the fourth position 13q). The difference between the (10-10) interplanar spacing in the third region 31c and the (10-10) interplanar spacing in the third partial region 13 corresponds to the third difference Δa3.

[0041] Thus, in the first sample SPL1, the first absolute value of the first difference Δa1 is larger than the third difference Δa3. This makes it easier to obtain high mobility. For example, a low on-resistance is obtained. For example, a high threshold voltage is easily obtained in a stable manner.

[0042] 3(c), in the first sample SPL1, the (0001) interplanar spacing in the first region 31a is smaller than the (0001) interplanar spacing in the fourth partial region 14 (the first position 14p and the second position 14q). The difference between the (0001) interplanar spacing in the first region 31a and the (0001) interplanar spacing in the fourth partial region 14 corresponds to the difference Δc1.

[0043] 3(d), in the first sample SPL1, the (0001) interplanar spacing in the third region 31c is smaller than the (0001) interplanar spacing in the third partial region 13 (the third position 13p and the fourth position 13q). The difference between the (0001) interplanar spacing in the third region 31c and the (0001) interplanar spacing in the third partial region 13 corresponds to the difference Δc3.

[0044] For example, it is believed that at the bottom of the recess, the difference Δc3 in the (0001) interplanar spacing is large, which effectively relaxes the strain and reduces the third difference Δa3 in the (10-10) interplanar spacing.

[0045] In the first sample SPL1, the difference Δc3 is larger than the difference Δc1. It is considered that the larger difference Δc3 allows the distortion to be more effectively alleviated.

[0046] It is believed that the large first difference Δa1 in the (10-10) interplanar spacing on the side surface of the recess relieves distortion and effectively reduces the third difference Δa3 in the (10-10) interplanar spacing on the bottom of the recess.

[0047] Thus, in the embodiment, the absolute value of the difference Δc1 between the (0001) lattice spacing in the first region 31a and the (0001) lattice spacing in the fourth partial region 14 may be greater than the third absolute value of the third difference Δa3.

[0048] The absolute value of the difference Δc3 between the (0001) lattice spacing in the third region 31c and the (0001) lattice spacing in the third partial region 13 may be greater than a third absolute value of the third difference Δa3.

[0049] The relationship between the inter-plane distances in the second region 31b and the fifth partial region 15 may be substantially the same as the relationship between the inter-plane distances in the first region 31a and the fourth partial region .

[0050] For example, the difference between the (10-10) interplanar spacing in the second region 31b and the (10-10) interplanar spacing in the fifth partial region 15 is defined as the second difference. The second absolute value of the second difference is greater than the third absolute value of the third difference Δa3. The second difference may be substantially the same as the first difference Δa1.

[0051] For example, the absolute value of the difference between the (0001) lattice spacing in the second region 31b and the (0001) lattice spacing in the fifth partial region 15 may be greater than the third absolute value of the third difference Δa3.

[0052] In the first sample SPL1, the first absolute value of the first difference Δa1 is about 0.005 nm. In an embodiment, the first absolute value of the first difference Δa1 may be 0.003 nm or more. In the first sample SPL1, the third absolute value of the third difference Δa3 is 0.0001 nm or less. In an embodiment, the third absolute value of the third difference Δa3 may be less than 0.001 nm. In an embodiment, the third absolute value of the third difference Δa3 may be 0.0005 nm or less.

[0053] In an embodiment, for example, the first absolute value of the first difference Δa1 may be three times or more than the third absolute value of the third difference Δa3, and in one example, the first absolute value may be 1000 times or less than the third absolute value.

[0054] In the embodiment, for example, the absolute value of the difference Δb1 between the (10-10) spacing at the first position 14p and the (10-10) spacing at the second position 14q is smaller than the first absolute value of the first difference Δa1 (see FIG. 3(a)).

[0055] In the embodiment, for example, the absolute value of the difference Δb3 between the (10-10) spacing at the third position 13p and the (10-10) spacing at the fourth position 13q is smaller than the first absolute value of the first difference Δa1 (see FIG. 3(b)).

[0056] 4(a) to 4(d) are graphs illustrating the characteristics of the semiconductor device. These figures illustrate the evaluation results of the second sample SPL2. The vertical axis of these figures is the lattice spacing LS. FIG. 4(a) shows the measurement results of the (10-10) lattice spacing in the first region 31a, the first position 14p, and the second position 14q. FIG. 4(b) shows the measurement results of the (10-10) lattice spacing in the third region 31c, the third position 13p, and the fourth position 13q. FIG. 4(c) shows the measurement results of the (0001) lattice spacing in the first region 31a, the first position 14p, and the second position 14q. FIG. 4(d) shows the measurement results of the (0001) lattice spacing in the third region 31c, the third position 13p, and the fourth position 13q.

[0057] In the first sample SPL1, after a part of the semiconductor layer is removed by dry etching to form a recess, the alkaline wet treatment is performed, whereas in the second sample SPL2, the alkaline wet treatment is omitted.

[0058] As shown in Fig. 4(a), in the second sample SPL2, the (10-10) interplanar spacing value is significantly different between the first position 14p and the second position 14q, and as shown in Fig. 4(b), in the second sample SPL2, the (10-10) interplanar spacing value is significantly different between the third position 13p and the fourth position 13q.

[0059] In the second sample SPL2, the (10-10) interplanar spacing in the fourth partial region 14 is conveniently defined as the (10-10) interplanar spacing at the first position 14p. In the second sample SPL2, the (10-10) interplanar spacing in the third partial region 13 is conveniently defined as the (10-10) interplanar spacing at the third position 13p.

[0060] In the second sample SPL2, the first difference Δa1 between the (10-10) interplanar spacing in the first region 31a and the (10-10) interplanar spacing in the fourth partial region 14 is about 0.002. In the second sample SPL2, the third difference Δa3 between the (10-10) interplanar spacing in the third region 31c and the (10-10) interplanar spacing in the third partial region 13 is about 0.001 nm. Therefore, in the second sample SPL2 as well, the first absolute value of the first difference Δa1 is larger than the third absolute value of the third difference Δa3. For this reason, it is considered that high mobility and high threshold value can be obtained.

[0061] However, in the second sample SPL2, the difference between the first difference Δa1 and the third difference Δa3 is small.

[0062] As already described, in the first sample SPL1, the first difference Δa1 is about 0.005 nm, and the third difference Δa3 is 0.0001 nm or less, and the difference between these values ​​is large. In the first sample SPL1, a higher mobility is obtained compared to the second sample SPL2. A higher threshold value is stably obtained. In the embodiment, the first absolute value of the first difference Δa1 is preferably 0.002 nm or more. In the embodiment, the third absolute value of the third difference Δa3 is preferably less than 0.001 nm. It is more preferable that the third absolute value of the third difference Δa3 is 0.0005 nm or less.

[0063] 4(a), in the second sample SPL2, for example, the absolute value of the difference Δb1 between the (10-10) interplanar spacing at the first position 14p and the (10-10) interplanar spacing at the second position 14q is greater than the first absolute value of the first difference Δa1. In the second sample SPL2, the absolute value of the difference Δb1 is greater than the third absolute value of the third difference Δa3.

[0064] Thus, in the second sample SPL2, the (10-10) interplanar spacing differs significantly between the first position 14p and the second position 14q. It is considered that the crystal quality in the fourth partial region 14 in the second sample SPL2 is lower than the crystal quality in the fourth partial region 14 in the first sample SPL1.

[0065] 4(b), in the second sample SPL2, for example, the absolute value of the difference Δb3 between the (10-10) interplanar spacing at the third position 13p and the (10-10) interplanar spacing at the fourth position 13q is greater than the first absolute value of the first difference Δa1. In the second sample SPL2, the absolute value of the difference Δb3 is greater than the third absolute value of the third difference Δa3.

[0066] Thus, in the second sample SPL2, the (10-10) interplanar spacing differs significantly between the third position 13p and the fourth position 13q. It is considered that the crystal quality in the third partial region 13 in the second sample SPL2 is lower than the crystal quality in the third partial region 13 in the first sample SPL1.

[0067] The above-mentioned surface spacing (lattice spacing) can be obtained by optimizing the dry etching conditions, wet etching conditions, and compound member 31 formation conditions when forming the recess. For example, by setting the dry etching conditions to low power mild, surface roughness after dry etching is suppressed, and the surface spacing as in the first sample SPL1 can be easily obtained. For example, by optimizing the wet etching conditions, high flatness can be obtained, and the surface spacing as in the first sample SPL1 can be easily obtained. By optimizing the temperature and the flow rate of the raw material gas in forming the compound member 31, the surface spacing as in the first sample SPL1 can be easily obtained. These conditions may be optimized in consideration of the characteristics unique to each of the dry etching apparatus, the wet etching apparatus, and the film forming apparatus. For example, the appropriate conditions for each apparatus can be determined by measuring the lattice spacing of a sample prepared by changing the conditions for each apparatus.

[0068] In the embodiment, the ratio of the third absolute value of the third difference Δa3 to the (10-10) interplanar spacing in the third partial region 13 may be, for example, 0.001 or less. A small third difference Δa3 can provide, for example, high crystallinity in the third partial region 13. High mobility can be provided.

[0069] In the embodiment, the first absolute value of the first difference Δa1 may be more than twice the third absolute value of the third difference Δa3, and the first absolute value may be less than 50 times the third absolute value.

[0070] 1, the third partial region 13 includes a third partial region surface 13F facing the third region 31c. The third partial region surface 13F is along the c-plane of the first semiconductor layer 10, for example.

[0071] The first region 31a includes a first region surface 31aF facing the fourth partial region 14. In the embodiment, the first region surface 31aF may be a non-polar or semi-polar surface. The first region surface 31aF may be, for example, an a-plane or an m-plane.

[0072] 1, the semiconductor device 110 may include a substrate 10S and a nitride layer 10B. The substrate 10S may be, for example, a silicon substrate. The nitride layer 10B is provided between the substrate 10S and the first semiconductor layer 10. The nitride layer 10B includes, for example, Al, Ga, and N. The nitride layer 10B is, for example, a buffer layer.

[0073] The first electrode 51 is electrically connected to, for example, the first semiconductor portion 21. The second electrode 52 is electrically connected to, for example, the second semiconductor portion 22.

[0074] As shown in FIG. 1, the first semiconductor portion 21 includes a first surface 21a and a first other surface 21b. The first surface 21a is between the fourth partial region 14 and the first other surface 21b in the second direction D2. The first surface 21a faces the fourth partial region 14. As already described, the third partial region 13 includes a third partial region surface 13F facing the third region 31c. The distance in the second direction D2 between the position of the third partial region surface 13F in the second direction D2 and the position of the first other surface 21b in the second direction D2 is defined as a distance dz. The distance dz corresponds to the recess depth. In the embodiment, the distance dz may be, for example, 100 nm or more. For example, a high threshold voltage is easily obtained.

[0075] In the embodiment, the thickness of the second semiconductor layer 20 along the second direction D2 may be, for example, 10 nm to 60 nm or less. A stable carrier region 10C is easily obtained.

[0076] 1, the distance between the fourth partial region 14 and the first electrode portion 53a in the first direction D1 is defined as a first distance d1. The distance between the third partial region 13 and the first electrode portion 53a in the second direction D2 is defined as a second distance d2. The first distance d1 may be substantially the same as the second distance d2. For example, the first distance d1 may be 0.8 times or more and 1.2 times or less the second distance d2.

[0077] 1, the third electrode 53 may further include a second electrode portion 53b. The second electrode portion 53b is continuous with the first electrode portion 53a. In the second direction D2, a part of the second semiconductor portion 22 may be provided between a part of the fifth partial region 15 and the second electrode portion 53b. For example, in the second direction D2, a part of the first semiconductor portion 21 may be provided between a part of the fourth partial region 14 and the second electrode portion 53b.

[0078] The first insulating member 41 includes, for example, at least one selected from the group consisting of silicon and aluminum, and at least one selected from the group consisting of oxygen and nitrogen. The first insulating member 41 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0079] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 5, in the semiconductor device 110, the compound member 31 may further include a first intermediate region 31p. The first intermediate region 31p is provided between the first region 31a and the third region 31c. The first intermediate region 31p includes a first intermediate region surface 31pF facing the first semiconductor layer 10. The first intermediate region surface 31pF is inclined with respect to the XY plane.

[0080] On the other hand, the first region 31a includes a first region surface 31aF facing the fourth partial region 14. The angle between the first region surface 31aF and a plane (e.g., the XY plane) perpendicular to the second direction D2 is defined as a first angle θ1. The angle between the plane and the first intermediate region surface 31pF is defined as a second angle θ2. The first angle θ1 is larger than the second angle θ2. When the second angle θ2 is small and the first intermediate region surface 31pF is inclined, for example, a high threshold voltage is easily obtained.

[0081] For example, the first angle θ1 may be equal to or greater than 88 degrees and equal to or less than 90 degrees. For example, the second angle θ2 may be equal to or greater than 30 degrees and equal to or less than 60 degrees.

[0082] As shown in FIG. 5, the thickness of the third region 31c along the second direction D2 is defined as thickness t1. In the embodiment, thickness t1 may be 0.5 nm or more and 5 nm or less. The thickness of the first region 31a along the first direction D1 may be substantially the same as thickness t1. Such thickness t1 makes it easy to obtain the above-mentioned interplanar spacing. For example, in a compound member 31 having a high Al composition ratio, if the thickness is excessively thick, the crystallinity is likely to be low. If thickness t1 is excessively thin, it is difficult to obtain a stable and continuous film shape in the compound member 31.

[0083] In an embodiment, information about length and thickness is obtained by electron microscope images, etc. Information about material composition is obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy dispersive X-ray spectroscopy), etc. Information about lattice length such as interplanar spacing is obtained by electron diffraction, X-ray diffraction, or electron microscope images, etc.

[0084] The embodiments may include the following technical solutions. (Technical proposal 1) A first electrode; A second electrode; A third electrode including a first electrode portion, wherein a position of the third electrode in a first direction from the first electrode to the second electrode is between a position of the first electrode in the first direction and a position of the second electrode in the first direction, the third electrode Al x1 Ga 1-x1 A first semiconductor layer containing N(0≦x1<1), the first semiconductor layer including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, wherein a second direction from the first partial region to the first electrode intersects the first direction, a direction from the second partial region to the second electrode is along the second direction, a direction from the third partial region to the first electrode portion is along the second direction, a position of the fourth partial region in the first direction is between a position of the first partial region in the first direction and a position of the third partial region in the first direction, and a position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and a position of the second partial region in the first direction, the first semiconductor layer Al x2 Ga 1-x2 A second semiconductor layer containing N(0<x2<1, x1<x2), the second semiconductor layer including a first semiconductor portion and a second semiconductor portion, wherein a direction from the fourth partial region to the first semiconductor portion is along the second direction, and a direction from the fifth partial region to the second semiconductor portion is along the second direction, the second semiconductor layer Al z1 Ga 1-z1A compound member including N(0 < z1 ≤ 1, x2 < z1), wherein the compound member includes a first region, a second region, and a third region, the first region is between the fourth partial region and the first electrode portion in the first direction, the second region is between the first electrode portion and the fifth partial region in the first direction, the third region is between the third partial region and the first electrode portion in the second direction, and the first absolute value of the first difference between the (10-10) plane spacing in the first region and the (10-10) plane spacing in the fourth partial region is greater than the third absolute value of the third difference between the (10-10) plane spacing in the third region and the (10-10) plane spacing in the third partial region, the compound member, A semiconductor device provided with .

[0085] (Technical Solution 2) The fourth partial region includes a first position and a second position, The first position is between the second position and the first region in the first direction, The distance in the first direction between the first position and the first region is 1 nm, The distance in the first direction between the second position and the first region is 10 nm, The absolute value of the difference between the (10-10) plane spacing at the first position and the (10-10) plane spacing at the second position is smaller than the first absolute value, the semiconductor device according to Technical Solution 1.

[0086] (Technical Solution 3) The third partial region includes a third position and a fourth position, The third position is between the fourth position and the third region in the second direction, The distance in the first direction between the third position and the third region is 1 nm, The distance in the first direction between the fourth position and the third region is 10 nm, The semiconductor device according to Technical Proposal 1 or 2, wherein an absolute value of a difference between the (10-10) interplanar spacing at the third position and the (10-10) interplanar spacing at the fourth position is smaller than the first absolute value.

[0087] (Technical proposal 4) the third partial region includes a third partial region surface facing the third region, The semiconductor device according to any one of Technical Solutions 1 to 3, wherein the third partial region surface is along a c-plane of the first semiconductor layer.

[0088] (Technical proposal 5) The semiconductor device according to any one of Technical Solutions 1 to 3, wherein the first absolute value is 2 to 50 times the third absolute value.

[0089] (Technical proposal 6) the first absolute value is equal to or greater than 0.002 nm; The semiconductor device according to any one of Technical Solutions 1 to 4, wherein the third absolute value is less than 0.001 nm.

[0090] (Technical proposal 7) The semiconductor device according to any one of Technical Solutions 1 to 5, wherein a ratio of the third absolute value to the (10-10) interplanar spacing in the third partial region is 0.001 or less.

[0091] (Technical proposal 8) The semiconductor device according to any one of technical proposals 1 to 6, wherein an absolute value of a difference between the (0001) interplanar spacing in the first region and the (0001) interplanar spacing in the fourth partial region is greater than the third absolute value.

[0092] (Technical proposal 9) The semiconductor device according to Technical Solution 7, wherein an absolute value of a difference between the (0001) interplanar spacing in the third region and the (0001) interplanar spacing in the third partial region is greater than the third absolute value.

[0093] (Technical proposal 10) The compound member further includes a fourth region and a fifth region, the fourth region is in contact with the first semiconductor portion; The semiconductor device according to any one of Technical Solutions 1 to 9, wherein the fifth region is in contact with the second semiconductor portion.

[0094] (Technical proposal 11) The compound member further includes a sixth region and a seventh region, the first semiconductor portion is provided between the fourth portion region and the sixth region, The semiconductor device described in Technical Proposal 10, wherein the second semiconductor portion is provided between the fifth portion region and the seventh region.

[0095] (Technical proposal 12) Further comprising a first insulating member; the first insulating member includes a first insulating region, a second insulating region, and a third insulating region; the first insulating region is provided between the first region and the first electrode portion in the first direction, the second insulating region is provided between the first electrode portion and the second region in the first direction, The semiconductor device according to any one of Technical Solutions 1 to 11, wherein the third insulating region is provided between the third region and the first electrode portion in the second direction.

[0096] (Technical proposal 13) the first semiconductor portion includes a first surface and a first other surface; the first surface is located between the fourth partial region and the first other surface in the second direction, The first surface faces the fourth partial region, the third partial region includes a third partial region surface facing the third region, A semiconductor device described in any one of Technical Proposals 1 to 3, wherein a distance in the second direction between a position of the third partial region surface in the second direction and a position of the first other surface in the second direction is 100 nm or more.

[0097] (Technical proposal 14) The compound member further comprises a first intermediate region; the first intermediate region is provided between the first region and the third region, the first intermediate region includes a first intermediate region surface facing the first semiconductor layer; the first region includes a first region surface facing the fourth partial region, A semiconductor device described in any one of Technical Proposals 1 to 13, wherein a first angle between a plane perpendicular to the second direction and the first region surface is greater than a second angle between the plane and the first intermediate region surface.

[0098] (Technical proposal 15) the first region includes a first region surface facing the fourth partial region, 14. The semiconductor device according to any one of Technical Solutions 1 to 13, wherein the first region surface is a non-polar surface or a semi-polar surface.

[0099] (Technical proposal 16) The semiconductor device according to any one of Technical Solutions 1 to 15, wherein the third region has a thickness along the second direction of 0.5 nm or more and 5 nm or less.

[0100] (Technical proposal 17) A semiconductor device described in any one of Technical Proposals 1 to 16, wherein a first distance along the first direction between the fourth partial region and the first electrode portion is 0.8 to 1.2 times a second distance along the second direction between the third partial region and the first electrode portion.

[0101] (Technical proposal 18) the first electrode is electrically connected to the first semiconductor portion; The semiconductor device according to any one of Technical Solutions 1 to 17, wherein the second electrode is electrically connected to the second semiconductor portion.

[0102] (Technical proposal 19) The x1 is equal to or greater than 0 and equal to or less than 0.05, The x2 is equal to or greater than 0.15 and equal to or less than 0.35, The semiconductor device according to any one of Technical Schemes 1 to 18, wherein z1 is 0.9 or more and 1 or less.

[0103] (Technical proposal 20) The semiconductor device described in Technical Proposal 19, wherein z1 is 1.

[0104] According to the embodiment, a semiconductor device with improved characteristics can be provided.

[0105] The above describes the embodiments of the present invention with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements included in the semiconductor device, such as the electrodes, semiconductor layers, compound members, and insulating members, are included in the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from the known range.

[0106] Furthermore, any combination of two or more elements of each of the specific examples, within the scope of technical feasibility, is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0107] In addition, all semiconductor devices that can be implemented by those skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also belong to the scope of the present invention as long as they include the gist of the present invention.

[0108] In addition, within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0109] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0110] 10: first semiconductor layer, 10B: nitride layer, 10C: carrier region, 10S: substrate, 11 to 15: first to fifth partial regions, 13F: third partial region surface, 13p, 13q: third and fourth positions, 14p, 14q: first and second positions, 20: second semiconductor layer, 21, 22: first and second semiconductor portions, 21a, 21b: first and second surfaces, 31: compound member, 31a to 31g: first to seventh regions, 31aF: first region surface, 31p: first intermediate region, 31pF: first intermediate region surface, 41: first insulating member, 41a to 41g: first to seventh insulating regions, 51 to 53: first to third electrodes, 53a, 53b: first and second electrode parts, 110: semiconductor device; D1 to D3: first to third directions; LS: surface spacing; SPL1, SPL2: first and second samples; d1, d2: first and second distances; dz: distance; t1: thickness; Δa1: first difference; Δa3: third difference; θ1, θ2: first and second angles

Claims

1. a first electrode, a second electrode, a third electrode including a first electrode portion, wherein a position of the third electrode in a first direction from the first electrode to the second electrode is between a position of the first electrode in the first direction and a position of the second electrode in the first direction, the third electrode; A ｘ１ G １－ｘ１ N (0≦x1<1), the first semiconductor layer including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, a second direction from the first partial region to the first electrode intersects with the first direction, a direction from the second partial region to the second electrode is along the second direction, a direction from the third partial region to the first electrode portion is along the second direction, a position of the fourth partial region in the first direction is between a position of the first partial region in the first direction and a position of the third partial region in the first direction, and a position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and a position of the second partial region in the first direction; A ｘ２ G １－ｘ２ N (0<x2<1, x1<x2), the second semiconductor layer including a first semiconductor portion and a second semiconductor portion, a direction from the fourth partial region to the first semiconductor portion being along the second direction, and a direction from the fifth partial region to the second semiconductor portion being along the second direction; A ｚ１ G １－ｚ１ N (0<z1≦1, x2<z1), the compound member including a first region, a second region, and a third region, the first region being between the fourth partial region and the first electrode portion in the first direction, the second region being between the first electrode portion and the fifth partial region in the first direction, the third region being between the third partial region and the first electrode portion in the second direction, and a first absolute value of a first difference between a (10-10) lattice spacing in the first region and a (10-10) lattice spacing in the fourth partial region being greater than a third absolute value of a third difference between the (10-10) lattice spacing in the third region and the (10-10) lattice spacing in the third partial region; A semiconductor device comprising:

2. The fourth partial region includes a first position and a second position, The first position is between the second position and the first region in the first direction, A distance in the first direction between the first position and the first region is 1 nm, A distance in the first direction between the second position and the first region is 10 nm, The absolute value of the difference between the (10-10) plane spacing at the first position and the (10-10) plane spacing at the second position is smaller than the first absolute value. The semiconductor device according to claim 1.

3. The third partial region includes a third position and a fourth position, The third position is between the fourth position and the third region in the second direction, A distance in the first direction between the third position and the third region is 1 nm, A distance in the first direction between the fourth position and the third region is 10 nm, The absolute value of the difference between the (10-10) plane spacing at the third position and the (10-10) plane spacing at the fourth position is smaller than the first absolute value. The semiconductor device according to claim 1 or 2.

4. The third partial region includes a third partial region surface facing the third region, The third partial region surface is along the c-plane of the first semiconductor layer. The semiconductor device according to claim 1 or 2.

5. The first absolute value is 2 times or more and 50 times or less of the third absolute value. The semiconductor device according to claim 1 or 2.

6. The first absolute value is 0.002 nm or more, The third absolute value is less than 0.001 nm. The semiconductor device according to claim 1 or 2.

7. A ratio of the third absolute value to the (10-10) plane spacing in the third partial region is 0.001 or less. The semiconductor device according to claim 1 or 2.

8. The absolute value of the difference between the (0001) plane spacing in the first region and the (0001) plane spacing in the fourth partial region is larger than the third absolute value. The semiconductor device according to claim 1 or 2.

9. The semiconductor device according to claim 7 , wherein an absolute value of a difference between the (0001) lattice spacing in the third region and the (0001) lattice spacing in the third partial region is greater than the third absolute value.

10. The x1 is 0 or more and 0.05 or less, The x2 is equal to or greater than 0.15 and equal to or less than 0.35, The semiconductor device according to claim 1 , wherein z1 is equal to or greater than 0.9 and equal to or less than 1.

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