Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing a crystal defect in the vicinity of a trench separation structure.SOLUTION: A semiconductor device includes: a chip 2 including a principal surface 3; a trench separation structure 60 including a separation trench 61 formed on the principal surface 3 of the chip 2, a separation insulation film 62 formed in the separation trench 61 and a separation electrode 63, which is embedded in the separation trench 61 via the separation insulation film 62, and defining a definition region 6 on the principal surface 3; and a field insulation layer 95 which is formed integrally with the separation insulation film 62 and pulled out of the separation trench 61 in a horizontal direction along with the principal surface 3. The field insulation layer 95 includes: an edge insulation layer 8 which is integrated with the separation insulation film 62 along an edge of the trench separation structure 60; and a plurality of extension insulation layers 9 selectively extending in the horizontal direction from the edge insulation layer 8 to an opposite side of the trench separation structure 60, arrayed while being spaced in a length direction along with the edge of the trench separation structure 60, and separating mutual tip end portions 303.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor device including a semiconductor layer and a plurality of insulated gate transistors that are electrically independent and formed in the semiconductor layer so that a plurality of electrically independent control signals are individually input, and that are individually on / off controlled so that the on-resistance during active clamp operation differs from the on-resistance during normal operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-97649 A [Summary] One embodiment of the present disclosure includes a chip having a main surface, an isolation trench formed on the main surface of the chip, an isolation insulating film formed in the isolation trench, and an isolation electrode embedded in the isolation trench via the isolation insulating film, and includes a trench isolation structure that divides a partition region on the main surface, and a field insulating layer formed integrally with the isolation insulating film and drawn out from the isolation trench in a horizontal direction along the main surface, the field insulating layer including an edge insulating layer that is integral with the isolation insulating film along an edge of the trench isolation structure, and a plurality of extended insulating layers that selectively extend from the edge insulating layer toward the opposite side of the trench isolation structure along the horizontal direction, are arranged at intervals in the length direction along the edge of the trench isolation structure, and have their tips separated from each other. Provided is a semiconductor device including: [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a schematic plan view showing a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG. [Diagram 3]FIG. 3 is a schematic circuit diagram showing an electrical configuration of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a schematic circuit diagram showing a configuration of an output transistor. [Diagram 5] FIG. 5 is a plan view showing the output area shown in FIG. [Figure 6] FIG. 6 is an enlarged plan view showing a main part of the output region shown in FIG. [Figure 7] FIG. 7 is an enlarged plan view showing a main part of the output region shown in FIG. [Figure 8] FIG. 8 is an enlarged plan view showing a main part of the output region shown in FIG. [Figure 9] FIG. 9 is an enlarged plan view showing further essential parts of the output region shown in FIG. [Figure 10] FIG. 10 is an enlarged perspective view showing a main part of the output region shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG. [Figure 12] FIG. 12 is an enlarged view of the area surrounded by the dashed line XII in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along the line XIII-XIII shown in FIG. [Figure 14] FIG. 14 is an enlarged view of the area surrounded by the dashed line XIV in FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along the line XVI-XVIXIV shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. [Figure 19A] FIG. 19A is a diagram for explaining a part of the manufacturing process of the semiconductor device. [Figure 19B] FIG. 19B is a diagram showing a step subsequent to that of FIG. 19A. [Figure 19C]FIG. 19C is a diagram showing a step subsequent to that of FIG. 19B. [Figure 19D] FIG. 19D is a diagram showing a step subsequent to that of FIG. 19C. [Figure 19E] FIG. 19E is a diagram showing a step subsequent to that of FIG. 19D. [Figure 19F] FIG. 19F shows a step subsequent to that of FIG. 19E. [Figure 19G] FIG. 19G shows a step subsequent to that of FIG. 19F. [Figure 19H] FIG. 19H shows a step subsequent to that of FIG. 19G. [Figure 19I] FIG. 19I shows a step subsequent to that shown in FIG. 19H. [Figure 19J] FIG. 19J shows a step subsequent to that shown in FIG. 19I. [Figure 19K] FIG. 19K shows a step subsequent to that of FIG. 19J. [Figure 19L] FIG. 19L shows a step subsequent to that of FIG. 19K. [Figure 19M] FIG. 19M shows a step subsequent to that of FIG. 19L. [Figure 19N] FIG. 19N shows a step subsequent to that of FIG. 19M. [Figure 20] FIG. 20 is a diagram showing a mask pattern used when patterning the protective insulating layer. [Figure 21] FIG. 21 is a plan view showing the logic circuit region shown in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view of the logic circuit region of FIG. [Figure 23] FIG. 23 is an enlarged view of region XXIII in FIG. [Figure 24] FIG. 24 is a plan view showing the amplifier circuit area shown in FIG. [Diagram 25] FIG. 25 is a cross-sectional view taken along the line XXV-XXV shown in FIG. [Figure 26] FIG. 26 is a cross-sectional view taken along the line XXVI-XXVI shown in FIG. [Figure 27]FIG. 27 is an enlarged view of region XXVII of FIG. [Figure 28] FIG. 28 is a perspective view showing a second example of the field insulating layer. [Figure 29] FIG. 29 is a perspective view showing a third example of the field insulating layer. [Diagram 30] FIG. 30 is a perspective view showing a fourth embodiment of the field insulating layer. [Diagram 31] FIG. 31 is a perspective view showing a fifth embodiment of the field insulating layer.

[0005] [Detailed Description] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. In addition, the same reference numerals are given to corresponding structures among the accompanying drawings, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0006] When the phrase "substantially equal" is used in a description in which a comparison target exists, this phrase includes a numerical value (shape) equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ±10% based on the numerical value (shape) of the comparison target. In the embodiment, the phrases "first", "second", "third", etc. are used, but these are symbols attached to the names of each structure to clarify the order of explanation, and are not attached with the intention of limiting the names of each structure.

[0007] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. With reference to Figs. 1 and 2, the semiconductor device 1 includes a chip 2 formed in a rectangular parallelepiped shape. In this embodiment, the chip 2 is a Si chip including a Si single crystal.

[0008] The chip 2 may be a wide bandgap semiconductor chip including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). For example, the chip 2 may be a SiC chip including a single crystal of SiC.

[0009] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2.

[0010] The first main surface 3 is a circuit surface on which various circuit structures constituting an electronic circuit are formed. The second main surface 4 is a non-circuit surface that does not have any circuit structures. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0011] The semiconductor device 1 includes an output region 6 provided on the first main surface 3. The output region 6 is a region having an electronic circuit (circuit device) configured to generate an output signal to be output to the outside. In this embodiment, the output region 6 is defined in a region on the first side surface 5A side of the first main surface 3. The output region 6 is defined in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0012] The semiconductor device 1 includes a control region 7 provided in a region on the first main surface 3 different from the output region 6. The control region 7 is a region having a plurality of types of electronic circuits (circuit devices) configured to generate control signals for controlling the output region 6. In this embodiment, the control region 7 is defined in a region on the second side surface 5B side with respect to the output region 6, and faces the output region 6 in the second direction Y. In this embodiment, the control region 7 is defined in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0013] The semiconductor device 1 includes an n-type (first conductivity type) drain region 10 formed in a surface layer portion of the second main surface 4. The n-type impurity concentration of the drain region 10 is 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 10 may have a thickness of 50 μm or more and 200 μm or less. The drain region 10 is formed in a layer shape extending along the second main surface 4 over the entire surface layer portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The drain region 10 may have a thickness of 50 μm or more and 200 μm or less. The thickness of the drain region 10 is preferably 150 μm or less. In this embodiment, the drain region 10 is formed by an n-type semiconductor substrate (Si substrate).

[0014] The semiconductor device 1 includes an n-type drift region 11 formed in a surface layer portion of the first main surface 3. The drift region 11 has a lower n-type impurity concentration than the drain region 10. The n-type impurity concentration of the drift region 11 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 11 is formed in a layer extending along the first main surface 3 in the output region 6 and the control region 7. Specifically, the drift region 11 is formed in a layer extending along the first main surface 3 over the entire surface layer portion of the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0015] The drift region 11 is electrically connected to the drain region 10 in the chip 2. The drift region 11 has a thickness less than that of the drain region 10. The drift region 11 may have a thickness of 1 μm or more and 20 μm or less. The drift region 11 preferably has a thickness of 5 μm or more and 15 μm or less. The drift region 11 particularly preferably has a thickness of 10 μm or less. In this embodiment, the drift region 11 is formed by an n-type epitaxial layer (Si epitaxial layer).

[0016] The semiconductor device 1 includes an interlayer insulating layer 12 covering the first main surface 3. The interlayer insulating layer 12 collectively covers the output region 6 and the control region 7. The interlayer insulating layer 12 may cover the entire first main surface 3 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer insulating layer 12 may be formed at a distance inward from the periphery of the first main surface 3 so as to expose the periphery of the first main surface 3.

[0017] In this embodiment, the interlayer insulating layer 12 has a multilayer wiring structure having a laminated structure in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated. Each insulating layer may include at least one of a silicon oxide film and a silicon nitride film. Each wiring layer (for example, a first wiring layer 16 and a second wiring layer 17 described later) may include at least one of a pure Al layer (an Al layer having a purity of 99% or more), a Cu layer (a Cu layer having a purity of 99% or more), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0018] The semiconductor device 1 includes a plurality of terminals 13-15 arranged on either or both (in this embodiment, both) of the first main surface 3 and the second main surface 4. The plurality of terminals 13-15 include a source terminal 13, a plurality of control terminals 14, and a drain terminal 15.

[0019] In this embodiment, the source terminal 13 is provided as an output terminal electrically connected to a load, and is disposed on a portion of the interlayer insulating layer 12 that covers the output region 6. The source terminal 13 may cover the entire output region 6 in a plan view. The source terminal 13 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0020] The multiple control terminals 14 are terminals electrically connected to various electronic circuits in the control region 7, and are arranged on a portion of the interlayer insulating layer 12 that covers the control region 7. The multiple control terminals 14 are arranged at intervals along the periphery of the control region 7 (the periphery of the first main surface 3).

[0021] The plane area of ​​each control terminal 14 is set to a range in which a bonding wire can be connected. The plane area of ​​each control terminal 14 may be 1 / 10 or less of the plane area of ​​the source terminal 13. The multiple control terminals 14 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0022] The multiple control terminals 14 include at least one ground terminal 14a fixed to a ground potential, and at least one input terminal 14b that applies an electric signal to the control region 7. The location of the ground terminal 14a is arbitrary. In a plan view, the ground terminal 14a may be disposed in an inner part of the control region 7, may be disposed along one side of the first main surface 3, or may be disposed at a corner of the first main surface 3. The ground terminal 14a is connected to a bonding wire, and a ground potential is applied from the outside via the bonding wire.

[0023] The input terminal 14b may be disposed at any position. In a plan view, the input terminal 14b may be disposed in an inner portion of the control region 7, may be disposed along one side of the first main surface 3, or may be disposed at a corner of the first main surface 3.

[0024] In this embodiment, an example is shown in which the input terminal 14b is a test terminal to which a test signal for testing the electrical characteristics of the control circuit 23 during the manufacturing process is input. The test terminal is provided as a contact target for a probe of an electrical characteristic test device, and is configured to receive a test signal from the probe.

[0025] The input terminal 14b is a structure that is not to be connected with a bonding wire in the manufactured semiconductor device 1. In other words, the input terminal 14b is formed as an open terminal (dummy terminal). An open terminal is a terminal that does not receive a signal (electric potential) from the outside and is formed in an electrically floating state.

[0026] For example, when the semiconductor device 1 is mounted in a semiconductor package, the entire area of ​​the input terminal 14b is covered with an insulator (e.g., a sealing resin containing a plurality of fillers and a matrix resin) and is electrically insulated from other structures. Of course, the input terminal 14b may be electrically connected to a lead terminal of the semiconductor package via a bonding wire so that a test signal can be input even after the semiconductor device 1 is mounted in the semiconductor package.

[0027] In this embodiment, the drain terminal 15 is provided as a power supply terminal and directly covers the second main surface 4 of the chip 2. That is, in this embodiment, the semiconductor device 1 is a high-side switching device electrically interposed between a power supply and a load. The drain terminal 15 is electrically connected to the drain region 10 on the second main surface 4. The drain terminal 15 covers the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (the first to fourth side surfaces 5A to 5D).

[0028] Fig. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device 1 shown in Fig. 1. Fig. 4 is a schematic circuit diagram showing the configuration of the output transistor 20.

[0029] FIG. 3 shows an example in which an inductive load L as an example of a load is electrically connected to the source terminal 13 to show an operation example of the semiconductor device 1. The inductive load L is not a component of the semiconductor device 1. Therefore, a configuration including the semiconductor device 1 and the inductive load L may be called an "inductive load driving device" or an "inductive load control device." Examples of the inductive load L include a relay, a solenoid, a lamp, a motor, and the like. The inductive load L may be an inductive load for an automobile. That is, the semiconductor device 1 may be an inductive load for an automobile.

[0030] 3 and 4, the semiconductor device 1 includes an output transistor 20 formed in the output region 6. In this embodiment, the output transistor 20 is a gate split transistor including one main drain, one main source, and a plurality of main gates. The main drain is electrically connected to the drain terminal 15. The main source is electrically connected to the source terminal 13.

[0031] The multiple main gates are configured so that multiple electrically independent gate signals (gate potentials) are inputted individually. The output transistor 20 generates a single output current Io (output signal) in response to the multiple gate signals. In other words, the output transistor 20 is a multiple-input single-output switching device. The output current Io is a drain-source current flowing between the main drain and the main source. The output current Io is outputted outside the chip 2 (to an inductive load L) via the source terminal 13.

[0032] The output transistor 20 includes a plurality of (two or more) system transistors 21 that are electrically controlled independently. In this embodiment, the plurality of system transistors 21 includes a first system transistor 21A and a second system transistor 21B. The plurality of system transistors 21 are formed in a concentrated manner in the output region 6. The plurality of system transistors 21 are connected in parallel so that a plurality of gate signals are inputted individually, and are configured so that the system transistors 21 in the on state and the system transistors 21 in the off state coexist.

[0033] Each of the system transistors 21 includes a system drain, a system source, and a system gate. The system drains are electrically connected to a main drain (drain terminal 15). The system sources are electrically connected to a main source (source terminal 13). Each system gate is electrically connected to each main gate. In other words, each system gate constitutes each main gate.

[0034] The multiple system transistors 21 each generate a system current Is in response to a corresponding gate signal. Each system current Is is a drain-source current flowing between the system drain and the system source of each system transistor 21. The multiple system currents Is may have different values ​​or may have approximately equal values. The multiple system currents Is are added between the main drain and the main source. As a result, a single output current Io consisting of the added value of the multiple system currents Is is generated.

[0035] 4, the multiple system transistors 21 each include a single or multiple unit transistors 22 organized (grouped) as individual control targets. Specifically, the multiple system transistors 21 are formed of a single unit transistor 22 or a parallel circuit including multiple unit transistors 22. In this embodiment, each of the multiple unit transistors 22 is of a trench gate vertical type. The multiple system transistors 21 may be formed of the same number of unit transistors 22, or may be formed of different numbers of unit transistors 22.

[0036] Each unit transistor 22 includes a unit drain, a unit source, and a unit gate. The unit drain of each unit transistor 22 is electrically connected to the system drain of the corresponding system transistor 21. The unit source of each unit transistor 22 is electrically connected to the system source of the corresponding system transistor 21. The unit gate of each unit transistor 22 is electrically connected to the system gate of the corresponding system transistor 21.

[0037] The multiple unit transistors 22 each generate a unit current Iu in response to a corresponding gate signal. Each unit current Iu is a drain-source current flowing between the unit drain and unit source of each unit transistor 22. The multiple unit currents Iu may have different values ​​or may have approximately equal values. The multiple unit currents Iu are added between the corresponding system drains and system sources. As a result, a system current Is consisting of the sum of the multiple unit currents Iu is generated.

[0038] In this way, the output transistor 20 is configured so that the first system transistor 21A and the second system transistor 21B are controlled to be on and off in a state where they are electrically independent of each other. That is, the output transistor 20 is configured so that both the first system transistor 21A and the second system transistor 21B are simultaneously in an on state. Also, the output transistor 20 is configured so that either the first system transistor 21A or the second system transistor 21B is in an on state and the other is in an off state.

[0039] When both the first system transistor 21A and the second system transistor 21B are simultaneously turned on, the channel utilization rate of the output transistor 20 increases and the on-resistance decreases. When either the first system transistor 21A or the second system transistor 21B is turned on while the other is turned off, the channel utilization rate of the output transistor 20 decreases and the on-resistance increases. That is, the output transistor 20 is composed of an on-resistance variable switching device.

[0040] The semiconductor device 1 includes a control circuit 23 formed in the control region 7 so as to be electrically connected to the output transistor 20. The control circuit 23 may be referred to as a "control IC." The control circuit 23 includes various functional circuits, and configures an IPD (Intelligent Power Device) together with the output transistor 20. The IPD may be referred to as an "IPM (Intelligent Power Module)," an "IPS (Intelligent Power Switch)," a "smart power driver," a "smart MISFET (smart MOSFET)," or a "protected MISFET (protected MOSFET)."

[0041] In this embodiment, the control circuit 23 includes a gate control circuit 24, a current monitor circuit 25, an overcurrent protection circuit 26, an overheat protection circuit 27, a low voltage malfunction avoidance circuit 28, an open load detection circuit 29, an active clamp circuit 30, a power supply reverse connection protection circuit 31, a logic circuit 32, a test circuit 33, and an amplifier circuit 34. The control circuit 23 does not necessarily need to include all of these functional circuits at the same time, and it is sufficient if it includes at least one of these functional circuits.

[0042] The current monitor circuit 25 may be referred to as a CS circuit (Current Sense circuit). The overcurrent protection circuit 26 may be referred to as an OCP circuit (Over Current Protection circuit). The overheat protection circuit 27 may be referred to as a TSD circuit (Thermal shut down circuit). The low voltage malfunction avoidance circuit 28 may be referred to as a UVLO circuit (Under Voltage Lock Out circuit). The open load detection circuit 29 may be referred to as an OLD circuit (Open Load Detection circuit). The power supply reverse connection protection circuit 31 may be referred to as an RBP circuit (Reverse Battery Protection circuit). The amplifier circuit 34 may be referred to as an AMP circuit (Amplifier circuit).

[0043] The gate control circuit 24 is configured to generate gate signals that control the on / off of the output transistors 20. Specifically, the gate control circuit 24 generates a plurality of gate signals that individually control the on / off of the plurality of system transistors 21. That is, in this embodiment, the gate control circuit 24 generates a first gate signal that individually controls the on / off of the first system transistors 21A, and a second gate signal that individually controls the on / off of the second system transistors 21B electrically independent of the first system transistors 21A.

[0044] The current monitor circuit 25 generates a monitor current that monitors the output current Io of the output transistor 20 and outputs it to another circuit. For example, the monitor circuit may be configured to include a transistor having a similar configuration to the output transistor 20, and to generate a monitor current linked to the output current Io by being on / off controlled simultaneously with the output transistor 20. Of course, the current monitor circuit 25 may also be configured to generate a monitor current linked to one or more system currents Is.

[0045] The overcurrent protection circuit 26 generates an electric signal for controlling the gate control circuit 24 based on the monitor current from the current monitor circuit 25, and cooperates with the gate control circuit 24 to control the on / off of the output transistor 20. For example, the overcurrent protection circuit 26 may be configured to determine that the output transistor 20 is in an overcurrent state when the monitor current is equal to or greater than a predetermined threshold, and to control some or all of the output transistor 20 (the multiple system transistors 21) to an off state in cooperation with the gate control circuit 24. The overcurrent protection circuit 26 may also be configured to cooperate with the gate control circuit 24 to shift the output transistor 20 to a normal operation when the monitor current is less than a predetermined threshold.

[0046] The overheat protection circuit 27 includes a first temperature sensing device (for example, a temperature sensing diode) that detects the temperature of the output region 6, and a second temperature sensing device (for example, a temperature sensing diode) that detects the temperature of the control region 7. The overheat protection circuit 27 generates an electrical signal that controls the gate control circuit 24 based on a first temperature detection signal from the first temperature sensing device and a second temperature detection signal from the second temperature sensing device, and cooperates with the gate control circuit 24 to control the on / off of the output transistor 20.

[0047] For example, the overheat protection circuit 27 may be configured to determine that the output region 6 is in an overheated state when the difference value between the first temperature detection signal and the second temperature detection signal is equal to or greater than a predetermined threshold, and to control some or all of the output transistors 20 (the multiple system transistors 21) to an off state in cooperation with the gate control circuit 24. The overheat protection circuit 27 may also be configured to transition the output transistors 20 to normal operation in cooperation with the gate control circuit 24 when the difference value becomes less than a predetermined threshold.

[0048] Low voltage malfunction avoidance circuit 28 is configured to avoid malfunction of various functional circuits in control circuit 23 when the startup voltage for starting control circuit 23 is less than a predetermined value. For example, low voltage malfunction avoidance circuit 28 may be configured to start control circuit 23 when the startup voltage becomes equal to or greater than a predetermined threshold voltage, and to stop control circuit 23 when the startup voltage becomes less than the threshold voltage. The threshold voltage may have a hysteresis characteristic.

[0049] The open load detection circuit 29 determines the electrical connection state of the inductive load L. For example, the open load detection circuit 29 may be configured to monitor the voltage between the terminals of the output transistor 20 and determine that the inductive load L is in an open state when the voltage between the terminals becomes equal to or higher than a predetermined threshold. For example, the open load detection circuit 29 may be configured to determine that the inductive load L is in an open state when the monitor current becomes equal to or lower than a predetermined threshold.

[0050] The active clamp circuit 30 is electrically connected to the main drain and at least one main gate (for example, the system gate of the first system transistor 21A) of the output transistor 20. The active clamp circuit 30 includes a Zener diode and a pn junction diode connected in series with the Zener diode in a reverse bias state. The pn junction diode is a backflow prevention diode that prevents backflow from the output transistor 20.

[0051] The active clamp circuit 30 is configured to cooperate with the gate control circuit 24 to control a part or the whole of the output transistor 20 to an ON state when a back electromotive voltage caused by the inductive load L is applied to the output transistor 20. Specifically, the output transistor 20 is controlled in a plurality of operation modes including a normal operation, a first OFF operation, an active clamp operation, and a second OFF operation.

[0052] In normal operation, both the first system transistor 21A and the second system transistor 21B are controlled to be in the on state at the same time. This increases the channel utilization rate of the output transistor 20 and reduces the on-resistance. In the first off operation, both the first system transistor 21A and the second system transistor 21B are controlled to be changed from the on state to the off state at the same time. This causes the back electromotive voltage caused by the inductive load L to be applied to both the first system transistor 21A and the second system transistor 21B.

[0053] The active clamp operation is an operation in which the energy stored in the inductive load L is absorbed (consumed) by the output transistor 20, and is executed when the back electromotive voltage caused by the inductive load L becomes equal to or higher than a predetermined threshold voltage. In the active clamp operation, the first system transistor 21A is controlled to change from an OFF state to an ON state, and at the same time, the second system transistor 21B is controlled (maintained) in the OFF state.

[0054] The channel utilization rate of the output transistor 20 during active clamp operation is less than the channel utilization rate of the output transistor 20 during normal operation. The on-resistance of the output transistor 20 during active clamp operation is greater than the on-resistance of the output transistor 20 during normal operation. This suppresses a sudden temperature rise of the output transistor 20 during active clamp operation, improving the active clamp withstand capability.

[0055] The second off operation is executed when the back electromotive voltage becomes less than a predetermined threshold voltage. In the second off operation, the first system transistor 21A is controlled from the on state to the off state, and at the same time, the second system transistor 21B is controlled (maintained) in the off state. In this way, the back electromotive voltage (energy) of the inductive load L is absorbed by a part of the output transistor 20 (here, the first system transistor 21A). Of course, during the active clamp operation, the first system transistor 21A may be controlled (maintained) in the off state, and at the same time, the second system transistor 21B may be controlled to the on state.

[0056] The power supply reverse connection protection circuit 31 is configured to detect a reverse voltage when the power supply is reverse connected, and protect the control circuit 23 and the output transistor 20 from the reverse voltage (reverse current). The logic circuit 32 is configured to generate an electric signal to be supplied to various circuits in the control circuit 23.

[0057] The test circuit 33 is formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15, and is electrically connected to the input terminal 14b and the drain terminal 15. The test circuit 33 is formed to indirectly evaluate the electrical characteristics of the control circuit 23 during the manufacturing process. The test circuit 33 is preferably disposed in a region adjacent to the input terminal 14b in a plan view.

[0058] For example, when the semiconductor device 1 is mounted on a vehicle, the amplifier circuit 34 is configured to amplify detection signals input to the semiconductor device 1 from various sensors (e.g., pressure sensors, inertial sensors, MR sensors, etc.) mounted on the vehicle.

[0059] [Output area 6 structure] Hereinafter, the structure of the output region 6 side will be described with reference to Figs. 5 to 18. Fig. 5 is a plan view showing the output region 6 shown in Fig. 1. Fig. 6 is an enlarged plan view showing a main part of the output region 6 shown in Fig. 5. Fig. 7 is an enlarged plan view showing a main part of the output region 6 shown in Fig. 5. Fig. 8 is an enlarged plan view showing a main part of the output region 6 shown in Fig. 5. The difference between Figs. 6 to 8 is that Fig. 6 shows a planar layout below a first wiring layer 16 described later, Fig. 7 shows the layout of the first wiring layer 16, and Fig. 8 shows the layout of a second wiring layer 17 described later. In Figs. 6 to 8, the field insulating layer 95 is omitted.

[0060] FIG. 9 is an enlarged plan view showing further main parts of the output region 6 shown in FIG. 5. FIG. 10 is an enlarged perspective view showing main parts of the output region 6 shown in FIG. 6. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 6. FIG. 12 is an enlarged view of an area surrounded by dashed line XII in FIG. 11. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 6. FIG. 14 is an enlarged view of an area surrounded by dashed line XIV in FIG. 13. FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. 6. FIG. 16 is a cross-sectional view taken along line XVI-XVIXIV shown in FIG. 6. FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 6. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 6. For clarity, FIG. 10 omits a part of the impurity region shown in FIG. 11 to FIG. 18.

[0061] The semiconductor device 1 includes a first trench isolation structure 60 formed in the first main surface 3 so as to define the output region 6. The first trench isolation structure 60 electrically isolates the output region 6 from the control region 7 within the chip 2. In this embodiment, a source potential is applied to the first trench isolation structure 60. The first trench isolation structure 60 is a part of the output region 6 and forms the outermost periphery of the output region 6.

[0062] The first trench isolation structure 60 is formed in a ring shape surrounding the output region 6 in a plan view. In this embodiment, the first trench isolation structure 60 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The first trench isolation structure 60 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 with a part of the drift region 11 in between.

[0063] In this embodiment, the first trench isolation structure 60 has an isolation corner 68 that connects a portion extending in the first direction X and a portion extending in the second direction Y. The isolation corner 68 is a strip extending in a direction inclined with respect to the first direction X and the second direction Y. More specifically, the isolation corner 68 is inclined at 45° with respect to each of the first direction X and the second direction Y. The isolation corner 68 preferably has a constant first width W1. Although not shown, the isolation corner 68 (the four corners of the first trench isolation structure 60) may be formed in an arc shape. In other words, the output region 6 may be defined by a quadrangle having four corners formed in an arc shape.

[0064] The first trench isolation structure 60 has a first width W1. The first width W1 is a width in a direction perpendicular to the extending direction of the first trench isolation structure 60. The first width W1 may be 0.4 μm or more and 2.5 μm or less. The first width W1 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The first width W1 is preferably 1.25 μm or more and 1.75 μm or less.

[0065] The first trench isolation structure 60 has a first depth D1. The first depth D1 may be 1 μm or more and 6 μm or less. The first depth D1 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The first depth D1 is preferably 3 μm or more and 5 μm or less.

[0066] The aspect ratio D1 / W1 of the first trench isolation structure 60 may be greater than 1 and less than or equal to 5. The aspect ratio D1 / W1 is the ratio of the first depth D1 to the first width W1. The aspect ratio D1 / W1 is preferably greater than or equal to 2.

[0067] The first trench isolation structure 60 includes an isolation trench 61, an isolation insulating film 62, and an isolation electrode 63. In other words, the first trench isolation structure 60 has a single electrode structure including a single electrode (isolation electrode 63) embedded in the isolation trench 61 with an insulator (isolation insulating film 62) sandwiched therebetween. The first trench isolation structure 60 may be referred to as a deep trench isolation (DTI) structure.

[0068] The isolation trench 61 is formed in the first main surface 3 and defines a wall surface of the first trench isolation structure 60. The isolation insulating film 62 covers the wall surface of the isolation trench 61. The isolation insulating film 62 may include a silicon oxide film. The isolation insulating film 62 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The isolation electrode 63 is embedded in the isolation trench 61 with the isolation insulating film 62 sandwiched therebetween. The isolation electrode 63 may include conductive polysilicon.

[0069] The semiconductor device 1 includes an output transistor 20 formed on the first main surface 3 in the output region 6. The following configurations will be described as components of the semiconductor device 1, but are also components of the output transistor 20.

[0070] The semiconductor device 1 may include an n-type high-concentration drift region 64 formed in the surface layer of the drift region 11 in the output region 6. In other words, the formation of the high-concentration drift region 64 is optional. The high-concentration drift region 64 has a higher n-type impurity concentration than the drift region 11. The n-type impurity concentration of the high-concentration drift region 64 may be lower than the n-type impurity concentration of the drain region 10. The n-type impurity concentration of the high-concentration drift region 64 is 1×10 16 cm -3 More than 1×10 19 cm -3 The high concentration drift region 64 may be considered as a high concentration portion of the drift region 11.

[0071] The high-concentration drift region 64 forms a concentration gradient in the drift region 11 in which the n-type impurity concentration increases from the bottom side of the drift region 11 toward the first main surface 3. In other words, the drift region 11 in the output region 6 has a concentration gradient formed by the high-concentration drift region 64 such that the n-type impurity concentration increases from the bottom side toward the first main surface 3.

[0072] The high-concentration drift region 64 is formed in the inner part of the output region 6 at a distance from the first trench isolation structure 60. Therefore, the high-concentration drift region 64 is surrounded by the drift region 11 in the output region 6 and is not in contact with the first trench isolation structure 60. The high-concentration drift region 64 locally increases the n-type impurity concentration of the drift region 11 in the output region 6.

[0073] The high-concentration drift region 64 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a part of the drift region 11. The high-concentration drift region 64 has a bottom that is located closer to the bottom of the drift region 11 than the bottom wall of the first trench isolation structure 60.

[0074] 11 and 13, the bottom of the high-concentration drift region 64 meanders to one side and the other side in the thickness direction in a cross-sectional view. Specifically, the bottom of the high-concentration drift region 64 has a plurality of bulging portions 65 and a plurality of recessed portions 66 in a cross-sectional view. The plurality of bulging portions 65 are portions that bulge in an arc shape toward the bottom side of the drift region 11. The plurality of bulging portions 65 are formed continuously in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. Each of the bulging portions 65 is formed to be wider than the first trench isolation structure 60 in the first direction X.

[0075] The multiple recesses 66 are each formed in a band shape extending in the second direction Y in a region between the multiple bulging portions 65. The multiple recesses 66 are portions where shallow portions of the multiple bulging portions 65 are connected to each other, and are located on the first main surface 3 side with respect to the deepest portions of the multiple bulging portions 65. Of course, the high-concentration drift region 64 may have a flat bottom that does not meander up and down in the thickness direction.

[0076] The high-concentration drift region 64 may be formed by increasing the concentration of the drift region 11 in the output region 6. With this configuration, the on-resistance of the drift region 11 can be reduced by increasing the concentration of the drift region 11. However, in this case, attention should be paid to the possibility that the breakdown voltage may decrease as a result of electric field concentration being easily caused by an increase in carrier density in the drift region 11. Therefore, in order to reduce the on-resistance while suppressing a decrease in the breakdown voltage, it is preferable to introduce the high-concentration drift region 64 into a part of the output region 6.

[0077] The semiconductor device 1 includes a p-type (second conductivity type) body region 67 formed in a surface layer portion of the drift region 11 in the output region 6. The body region 67 extends in a layered manner along the first main surface 3 throughout the output region 6, and is connected to a wall surface of the first trench isolation structure 60. That is, in this embodiment, the body region 67 is not formed in a region outside the first trench isolation structure 60.

[0078] The body region 67 is formed shallower than the high-concentration drift region 64. Specifically, the body region 67 is formed shallower than the first trench isolation structure 60, and has a bottom located closer to the first main surface 3 than the bottom wall of the first trench isolation structure 60. The bottom of the body region 67 is preferably located closer to the first main surface 3 than the intermediate part of the depth range of the first trench isolation structure 60.

[0079] The semiconductor device 1 includes a plurality of trench gate structures 70 formed on the first main surface 3 in the output region 6. The plurality of trench gate structures 70 are formed in the inner part of the output region 6 at intervals from the first trench isolation structure 60. The plurality of trench gate structures 70 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the plurality of trench gate structures 70 are arranged in a stripe shape extending in the second direction Y. With reference to FIG. 6, the plurality of trench gate structures 70 cross one end and the other end of the high concentration drift region 64 in the longitudinal direction (second direction Y).

[0080] 6, the trench gate structures 70 have a first end portion on one side in the longitudinal direction (second direction Y) and a second end portion (not shown in FIG. 6) on the other side in the longitudinal direction (second direction Y). The first end portion is located in a region between the first trench isolation structure 60 and one end portion of the high-concentration drift region 64 in a plan view. The second end portion is located in a region between the first trench isolation structure 60 and the other end portion of the high-concentration drift region 64 in a plan view.

[0081] The multiple trench gate structures 70 penetrate the body region 67 in a cross-sectional view and are located in the high-concentration drift region 64. The multiple trench gate structures 70 are formed at intervals from the bottom of the high-concentration drift region 64 toward the first main surface 3, and face the drift region 11 with a part of the high-concentration drift region 64 in between.

[0082] The trench gate structures 70 are formed offset in the first direction X with respect to the recesses 66, and face the bulges 65 in the thickness direction, respectively. It is preferable that the trench gate structures 70 face the deepest parts of the bulges 65. Such a configuration is obtained by introducing n-type impurities into the chip 2 from the wall surfaces of the gate trenches 71 after the step of forming the gate trenches 71.

[0083] The two trench gate structures 70 located on both sides in the first direction X are preferably formed in regions outside the high-concentration drift region 64. That is, the outermost trench gate structure 70 preferably penetrates the body region 67 at a position spaced from the high-concentration drift region 64 toward the first trench isolation structure 60, and is located within the drift region 11. The outermost trench gate structure 70 is formed spaced from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 with a part of the drift region 11 in between.

[0084] The trench gate structures 70 have a second width W2. The second width W2 is a width in a direction perpendicular to the extension direction of the trench gate structures 70 (i.e., the first direction X). The second width W2 may be approximately equal to the first width W1 of the first trench isolation structure 60. The second width W2 is preferably equal to or smaller than the first width W1. It is particularly preferable that the second width W2 is less than the first width W1.

[0085] The second width W2 may be 0.4 μm or more and 2 μm or less. The second width W2 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The second width W2 is preferably 0.8 μm or more and 1.2 μm or less.

[0086] The multiple trench gate structures 70 are arranged at intervals in the first direction X. An element-side mesa portion 82 consisting of a part of the chip 2 is defined in the region between two adjacent trench gate structures 70. In this embodiment, the multiple element-side mesa portions 82 are formed in stripes extending in the second direction Y, and the multiple trench gate structures 70 and the multiple element-side mesa portions 82 are arranged alternately in the first direction X.

[0087] Furthermore, an isolation-side mesa portion 83 consisting of a part of the chip 2 is defined in a region between the two trench gate structures 70 and the first trench isolation structure 60 located on both sides in the first direction X. The element-side mesa portion 82 and the isolation-side mesa portion 83 are both plate-shaped portions formed by being sandwiched between trench structures (in this embodiment, the trench gate structure 70 and the first trench isolation structure 60), and may be collectively referred to as a "mesa portion sandwiched between adjacent trench structures."

[0088] The first interval I1 (the width of the element-side mesa portion 82) between adjacent trench gate structures 70 is preferably equal to or smaller than the first width W1 of the first trench isolation structure 60. The first interval I1 is preferably equal to or smaller than the second width W2. It is particularly preferable that the first interval I1 be smaller than the second width W2.

[0089] The first interval I1 may be 0.4 μm or more and 1.6 μm or less. The first interval I1 may have a value that belongs to any one of the ranges of 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1.0 μm or less, 1.0 μm or more and 1.2 μm or less, 1.2 μm or more and 1.4 μm or less, and 1.4 μm or more and 1.6 μm or less. The first interval I1 is preferably 0.6 μm or more and 1.4 μm or less.

[0090] A second interval I2 (the width of the isolation-side mesa portion 83) between the outermost trench gate structure 70 and the first trench isolation structure 60 may be greater than the first width W1 of the first trench isolation structure 60. The second interval I2 may be less than or equal to the first width W1.

[0091] The second interval I2 may be 0.4 μm or more and 3.2 μm or less. The second interval I2 may have a value that belongs to any one of the ranges of 0.4 μm or more and 0.8 μm or less, 0.8 μm or more and 1.2 μm or less, 1.2 μm or more and 1.6 μm or less, 1.6 μm or more and 2.0 μm or less, 2.0 μm or more and 2.4 μm or less, 2.4 μm or more and 2.8 μm or less, and 2.8 μm or more and 3.2 μm. Of these, the range of 1.2 μm or more and 1.6 μm or less is preferable.

[0092] 11, 13, 15 and 16, the trench gate structure 70 has a second depth D2. The second depth D2 may be approximately equal to the first depth D1 of the first trench isolation structure 60. The second depth D2 is preferably equal to or less than the first depth D1. It is particularly preferable that the second depth D2 is less than the first depth D1.

[0093] The second depth D2 may be 1 μm or more and 6 μm or less. The second depth D2 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The second depth D2 is preferably 2.5 μm or more and 4.5 μm or less.

[0094] 6, the pitch P1 of the trench gate structures 70 may be 1.0 μm or more and 3.0 μm or less. The pitch P1 may have a value belonging to any one of the ranges of 1.2 μm or more and 2.8 μm or less, 1.2 μm or more and 2.6 μm or less, 1.2 μm or more and 2.4 μm or less, 1.0 μm or more and 2.6 μm or less, and 1.0 μm or more and 2.4 μm or less. The pitch P1 may be the distance between the centers of adjacent trench gate structures 70.

[0095] The internal configuration of one trench gate structure 70 will be described below. The trench gate structure 70 may be referred to as a deep trench isolation (DTI) structure, similar to the first trench isolation structure 60. That is, the aspect ratio D2 / W2 of the trench gate structure 70 may be greater than 1 and less than or equal to 5. The aspect ratio D2 / W2 is the ratio of the second depth D2 to the second width W2. The aspect ratio D2 / W2 is preferably 2 or more.

[0096] More specifically, the trench gate structure 70 includes a gate trench 71, an insulating film 72, an upper electrode 73, a lower electrode 74, and an intermediate insulating film 75. In other words, the trench gate structure 70 has a multi-electrode structure including a plurality of electrodes (upper electrode 73 and lower electrode 74) vertically embedded in the gate trench 71 with an insulator (insulating film 72 and intermediate insulating film 75) sandwiched therebetween.

[0097] The gate trench 71 is formed in the first main surface 3 and defines a wall surface of the trench gate structure 70. The insulating film 72 covers the wall surface of the gate trench 71. The insulating film 72 includes an upper insulating film 76 and a lower insulating film 77.

[0098] The upper insulating film 76 covers the wall surface of the opening side of the gate trench 71 relative to the bottom of the body region 67 .

[0099] The upper insulating film 76 partially covers the wall surface of the gate trench 71 on the bottom wall side relative to the bottom of the body region 67. The upper insulating film 76 is thinner than the isolation insulating film 62. The upper insulating film 76 is formed as a gate insulating film. The upper insulating film 76 may include a silicon oxide film. The upper insulating film 76 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0100] The lower insulating film 77 covers the wall surface on the bottom wall side of the gate trench 71 relative to the bottom of the body region 67. The lower insulating film 77 is thicker than the upper insulating film 76. The thickness of the lower insulating film 77 may be approximately equal to the thickness of the isolation insulating film 62. The lower insulating film 77 may include a silicon oxide film. The lower insulating film 77 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0101] The upper electrode 73 is embedded in the opening side of the gate trench 71 with an insulating film 72 sandwiched therebetween. Specifically, the upper electrode 73 is embedded in the opening side of the gate trench 71 with an upper insulating film 76 sandwiched therebetween, and faces the body region 67 and the high-concentration drift region 64 with the upper insulating film 76 sandwiched therebetween. The upper electrode 73 may include conductive polysilicon.

[0102] 12 and 14, a recess space 35 is formed above the upper electrode 73 in the gate trench 71. The recess space 35 is a space defined by the wall surface of the gate trench 71 and the upper electrode 73.

[0103] The upper insulating film 76 is selectively formed thicker in the recess space 35. For example, the upper insulating film 76 may include a channel insulating film 53 that is sandwiched between the wall surface of the gate trench 71 and the upper electrode 73 and functions as a gate insulating film that contributes to the gate threshold voltage when a channel is formed, and an edge insulating film 54 that is exposed upward from the upper surface 55 of the upper electrode 73 and formed on the opening edge of the gate trench 71. The channel insulating film 53 and the edge insulating film 54 may be referred to as a thin film portion and a thick film portion, respectively, of the upper insulating film 76. The edge insulating film 54 of the upper insulating film 76 has a flat surface that is continuous with the channel insulating film 53 on the wall surface side of the gate trench 71, and is selectively thicker toward the inside in the width direction of the gate trench 71.

[0104] The lower electrode 74 is embedded in the bottom wall side of the gate trench 71 with the insulating film 72 sandwiched therebetween. Specifically, the lower electrode 74 is embedded in the bottom wall side of the gate trench 71 with a lower insulating film 77 sandwiched therebetween, and faces the high-concentration drift region 64 with the lower insulating film 77 sandwiched therebetween. The lower electrode 74 of the outermost trench gate structure 70 faces the drift region 11 with the lower insulating film 77 sandwiched therebetween.

[0105] The lower electrode 74 has an upper end protruding from the lower insulating film 77 toward the upper electrode 73 so as to engage with the bottom of the upper electrode 73. The upper end of the lower electrode 74 faces the upper insulating film 76 across the lower end of the upper electrode 73 in the lateral direction along the first main surface 3. The lower electrode 74 may include conductive polysilicon.

[0106] The intermediate insulating film 75 is interposed between the upper electrode 73 and the lower electrode 74, and electrically insulates the upper electrode 73 and the lower electrode 74 in the gate trench 71. The intermediate insulating film 75 is continuous with the upper insulating film 76 and the lower insulating film 77. The intermediate insulating film 75 is thinner than the lower insulating film 77. The intermediate insulating film 75 may include a silicon oxide film. The intermediate insulating film 75 preferably includes a silicon oxide film made of an oxide of the lower electrode 74.

[0107] 6 and 9, the semiconductor device 1 includes a plurality of channel cells 78 formed on both sides of each trench gate structure 70 as control targets of each trench gate structure 70. In this embodiment, two channel cells 78 arranged on both sides of one trench gate structure 70 are controlled by that one trench gate structure 70 and are not controlled by the other trench gate structure 70.

[0108] The plurality of channel cells 78 are formed in a region along the inner portion of the trench gate structure 70 at intervals from both ends in the longitudinal direction (second direction Y) of the trench gate structure 70. The plurality of channel cells 78 expose the body region 67 from a region of the first main surface 3 sandwiched between both ends of the plurality of trench gate structures 70.

[0109] The multiple channel cells 78 face the high-concentration drift region 64 across a portion of the body region 67 in the thickness direction. The multiple channel cells 78 are preferably formed in the high-concentration drift region 64 further inward than the periphery of the high-concentration drift region 64 in a plan view.

[0110] Each channel cell 78 includes a number of n-type source regions 79 and a number of p-type contact regions 80. In FIG. 6, the source regions 79 are hatched for clarity. The contact regions 80 may be referred to as "backgate regions." Each source region 79 has a higher n-type impurity concentration than the drift region 11. Each source region 79 may have a higher n-type impurity concentration than the high concentration drift region 64. The n-type impurity concentration of each source region 79 is about 1×10 18 cm -3 More than 1×10 21 cm -3 It may be the following.

[0111] The multiple source regions 79 are arranged at intervals along each trench gate structure 70. The multiple source regions 79 are formed at intervals from the bottom of the body region 67 toward the first main surface 3, and face the upper electrode 73 with the insulating film 72 (upper insulating film 76) interposed therebetween.

[0112] Each contact region 80 has a higher p-type impurity concentration than the body region 67. The p-type impurity concentration of each contact region 80 is 1×10 18 cm -3 More than 1×10 21 cm -3 The plurality of contact regions 80 are arranged alternately with the plurality of source regions 79 along each trench gate structure 70. The plurality of contact regions 80 are formed at intervals from the bottom of the body region 67 toward the first main surface 3, and face the upper electrode 73 with the insulating film 72 (upper insulating film 76) interposed therebetween.

[0113] With respect to two channel cells 78 formed on both sides of one trench gate structure 70, a plurality of source regions 79 in one channel cell 78 face a plurality of source regions 79 in the other channel cell 78 across the trench gate structure 70. Also, a plurality of contact regions 80 in one channel cell 78 face a plurality of contact regions 80 in the other channel cell 78 across the trench gate structure 70.

[0114] Of course, the multiple source regions 79 in one channel cell 78 may face the multiple contact regions 80 in the other channel cell 78 across the trench gate structure 70. Also, the multiple contact regions 80 in one channel cell 78 may face the multiple source regions 79 in the other channel cell 78 across the trench gate structure 70.

[0115] With respect to two channel cells 78 interposed between two trench gate structures 70, a plurality of source regions 79 in one channel cell 78 are connected to a plurality of contact regions 80 in the other channel cell 78 in the first direction X. Also, a plurality of contact regions 80 in one channel cell 78 are connected to a plurality of source regions 79 in the other channel cell 78 in the first direction X.

[0116] Of course, a plurality of source regions 79 in one channel cell 78 may be connected in the first direction X to a plurality of source regions 79 in the other channel cell 78. Also, a plurality of contact regions 80 in one channel cell 78 may be connected in the first direction X to a plurality of contact regions 80 in the other channel cell 78.

[0117] Of the two channel cells 78 formed on both sides of the outermost trench gate structure 70, the channel cell 78 located on the inner side faces the drift region 11 across a part of the body region 67 in the thickness direction. On the other hand, the channel cell 78 located on the outer side does not include a source region 79, but only a contact region 80. This suppresses the formation of a current path in the region between the first trench isolation structure 60 and the outermost trench gate structure 70. In other words, both the source region 79 and the contact region 80 are formed in the surface layer portion of the element-side mesa portion 82, while only the contact region 80 is formed in the surface layer portion of the isolation-side mesa portion 83, without the source region 79 being formed.

[0118] 9, the output transistor 20 includes a plurality of unit transistors 22. Each of the plurality of unit transistors 22 includes one trench gate structure 70 and two channel cells 78 formed on both sides of the one trench gate structure 70. For each unit transistor 22, the one trench gate structure 70 constitutes a unit gate, the plurality of source regions 79 (two channel cells 78) constitute a unit source, and the drain region 10 (drift region 11 and high-concentration drift region 64) constitutes a unit drain.

[0119] 3 and 4, the output transistors 20 include first system transistors 21A and second system transistors 21B. The first system transistors 21A include a plurality of unit transistors 22 organized (grouped) as targets of individual control from a plurality of unit transistors 22. The second system transistors 21B include a plurality of unit transistors 22 organized (grouped) as targets of individual control from a plurality of unit transistors 22 other than the first system transistors 21A.

[0120] In this embodiment, the output transistor 20 includes a plurality of block regions 81 provided in the output region 6. The plurality of block regions 81 include a plurality of first block regions 81A and a plurality of second block regions 81B. The plurality of first block regions 81A are regions in which one or more (multiple in this embodiment) unit transistors 22 for the first system transistors 21A are respectively arranged. The plurality of second block regions 81B are regions in which one or more (multiple in this embodiment) unit transistors 22 for the second system transistors 21B are arranged.

[0121] The multiple first block regions 81A are arranged at intervals in the first direction X. The number of unit transistors 22 in each first block region 81A is arbitrary. In this embodiment, two unit transistors 22 are arranged in each first block region 81A. As the number of unit transistors 22 in each first block region 81A increases, the amount of heat generated in each first block region 81A increases. Therefore, it is preferable that the number of unit transistors 22 in each first block region 81A be between two and five.

[0122] The second block regions 81B are arranged alternately with the first block regions 81A in the first direction X so as to sandwich one first block region 81A therebetween. This allows heat generation locations caused by the first block regions 81A to be thinned out by the second block regions 81B, and at the same time, heat generation locations caused by the second block regions 81B to be thinned out by the first block regions 81A.

[0123] The number of unit transistors 22 in each second block region 81B is arbitrary. In this form, two unit transistors 22 are arranged in each second block region 81B. When the number of unit transistors 22 in each second block region 81B increases, the heat generation amount in each second block region 81B increases.

[0124] Therefore, the number of unit transistors 22 in each second block region 81B is preferably 2 or more and 5 or less. Considering the in-plane variation of the temperature in the output region 6, the number of unit transistors 22 in the second block region 81B is preferably the same as the number of unit transistors 22 in the first block region 81A.

[0125] The semiconductor device 1 includes a pair of trench connection structures 90 that connect both ends of a plurality (two in this form) of trench gate structures 70 to be systematized (grouped) in each block region 81. That is, the pair of trench connection structures 90 connect both ends of a plurality of trench gate structures 70 to be systematized as system transistors 21, respectively.

[0126] One side trench connection structure 90 connects the first ends of a plurality (two in this form) of corresponding trench gate structures 70 in an arch shape in a plan view. The other side trench connection structure 90 connects the second ends of a plurality (two in this form) of corresponding trench gate structures 70 in an arch shape in a plan view.

[0127] Specifically, one side trench connection structure 90 has a first portion extending in the first direction X and a plurality (two in this form) of second portions extending in the second direction Y. The first portion faces the first ends of a plurality of trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

[0128] The trench connection structure 90 on the other side has a first portion extending in a first direction X and a plurality of (two in this embodiment) second portions extending in a second direction Y. The first portion faces the second ends of the plurality of trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends. The plurality of trench connection structures 90 and the plurality of trench gate structures 70 in each block region 81 form a ring-shaped or ladder-shaped trench structure.

[0129] The multiple trench connection structures 90 are formed in a region between the first trench isolation structure 60 and the high-concentration drift region 64 at intervals from the first trench isolation structure 60 and the high-concentration drift region 64. The multiple trench connection structures 90 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3, and face the drain region 10 with a part of the drift region 11 in between.

[0130] The trench connection structures 90 may be formed with a width W2 and a depth D2 substantially equal to those of the trench gate structure 70. Of course, the first and second portions of the trench connection structures 90 may have different widths. For example, the second portions of the trench connection structures 90 may be formed narrower than the first portions of the trench connection structures 90.

[0131] In this case, the first portion may have a width approximately equal to the width of the first trench isolation structure 60, and the second portion may have a width approximately equal to the width of the trench gate structure 70. Further, in this case, the first portion may have a depth approximately equal to the depth of the first trench isolation structure 60, and the second portion may have a depth approximately equal to the depth of the trench gate structure 70.

[0132] The trench connection structure 90 on the other side has a structure similar to that of the trench connection structure 90 on one side, except that the trench connection structure 90 on the other side is connected to the second end of the trench gate structure 70. Hereinafter, the configuration of the trench connection structure 90 on one side will be described, and a description of the configuration of the trench connection structure 90 on the other side will be omitted.

[0133] The trench connection structure 90 includes a connection trench 91, a connection insulating film 92, and a connection electrode 93. The connection trench 91 is formed in the first main surface 3 and defines a wall surface of the trench connection structure 90. The connection trench 91 is connected to a plurality of gate trenches 71.

[0134] The connection insulating film 92 covers the wall surface of the connection trench 91. The connection insulating film 92 is connected to the upper insulating film 76, the lower insulating film 77, and the intermediate insulating film 75 at the communicating portion between the connection trench 91 and the gate trench 71. The connection insulating film 92 is thicker than the upper insulating film 76. The thickness of the connection insulating film 92 may be approximately equal to the thickness of the lower insulating film 77. The connection insulating film 92 may include a silicon oxide film. The connection insulating film 92 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0135] The connection electrode 93 is embedded in the connection trench 91 with a connection insulating film 92 interposed therebetween, and faces the drift region 11 and the body region 67 with the connection insulating film 92 interposed therebetween. The connection electrode 93 is connected to the lower electrode 74 at the communicating portion between the connection trench 91 and the gate trench 71, and is electrically insulated from the upper electrode 73 by an intermediate insulating film 75. The connection electrode 93 is formed of an extension portion where the lower electrode 74 is extended from inside the gate trench 71 into the connection trench 91. The connection electrode 93 may include conductive polysilicon.

[0136] The semiconductor device 1 includes a main surface insulating film 94 that selectively covers the first main surface 3 in the output region 6. The main surface insulating film 94 is omitted in Fig. 10. With reference to Fig. 15, the main surface insulating film 94 is connected to the insulating film 72 (upper insulating film 76).

[0137] The main surface insulating film 94 is thinner than the isolation insulating film 62. The main surface insulating film 94 is thinner than the lower insulating film 77. The main surface insulating film 94 is thinner than the connection insulating film 92. The main surface insulating film 94 may have a thickness approximately equal to that of the upper insulating film 76. The main surface insulating film 94 may include a silicon oxide film. The main surface insulating film 94 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0138] The semiconductor device 1 includes a field insulating layer 95 that selectively covers the first main surface 3 inside and outside the output region 6. The field insulating layer 95 is thicker than the main surface insulating film 94. The field insulating layer 95 is thicker than the upper insulating film 76. The field insulating layer 95 may have a thickness approximately equal to that of the isolation insulating film 62. The field insulating layer 95 may include a silicon oxide film. The field insulating layer 95 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0139] The field insulating layer 95 covers the first main surface 3 along the inner wall of the first trench isolation structure 60 in the output region 6, and is connected to the isolation insulating film 62, the connection insulating film 92, and the main surface insulating film 94. The field insulating layer 95 covers the first main surface 3 along the outer wall of the first trench isolation structure 60 outside the output region 6, and is integrally connected to the isolation insulating film 62. The field insulating layer 95 is drawn out from the isolation trench 61 in the horizontal direction along the first main surface 3.

[0140] 10, the field insulating layer 95 includes an edge insulating layer 8 and an extension insulating layer 9. As shown in FIG.

[0141] The edge insulating layer 8 is a portion of the field insulating layer 95 that is integral with the isolation insulating film 62 along the edge of the first trench isolation structure 60. In this embodiment, the edge insulating layer 8 is formed along both the inner and outer periphery edges of the annular first trench isolation structure 60. In other words, the edge insulating layer 8 is drawn out from the isolation trench 61 to both the output region 6 side and the opposite side.

[0142] The edge insulating layer 8 has a stepped structure including a plurality of relatively high step portions 301 and a low step portion 302 that is relatively lower than the high step portions 301 .

[0143] The multiple high step portions 301 are arranged at intervals in the isolation-side mesa portion 83 along the length direction of the first trench isolation structure 60 (in this embodiment, the second direction Y). The low step portions 302 are arranged between adjacent high step portions 301 in the second direction Y. As a result, in the edge insulating layer 8 on the isolation-side mesa portion 83, the multiple high step portions 301 and the multiple low step portions 302 are arranged alternately along the length direction of the first trench isolation structure 60. Each high step portion 301 and each low step portion 302 may be formed in a quadrangular shape in a plan view.

[0144] The extending insulating layer 9 is a plurality of insulating layers that selectively extend from the edge insulating layer 8 toward the opposite side of the first trench isolation structure 60 along the horizontal direction and have their tip portions 303 separated from each other. "The tip portions 303 are separated from each other" means that the extending insulating layers 9 extending from the edge insulating layer 8 as the base portion 304 are not directly connected to each other and are not indirectly connected to each other via other insulating layers. In other words, there is no insulating layer bridged between the adjacent extending insulating layers 9 on the tip portion 303 side of the edge insulating layer 8 (base portion 304). The extending insulating layer 9 covers the upper surface 56 of the isolation side mesa portion 83.

[0145] Each extending insulating layer 9 has a tip portion 303 at a position spaced from the trench gate structure 70 toward the first trench isolation structure 60. As a result, on the upper surface 56 of the isolation-side mesa portion 83, a plurality of main surface contact regions 305 sandwiched between a plurality of extending insulating layers 9 adjacent to each other in the second direction Y, and a main surface connection region 306 extending in a strip shape along the edge of the trench gate structure 70 and connecting the plurality of main surface contact regions 305 are formed.

[0146] In other words, the upper surface 56 of the isolation-side mesa portion 83 may be formed with a strip-shaped main surface connection region 306 formed along the trench gate structure 70, and a plurality of main surface contact regions 305 extending in a comb-like shape from the main surface connection region 306 toward the first trench isolation structure 60. The contact region 80 is exposed from the main surface contact region 305. The main surface contact region 305 may be a part of the contact region 80 selectively exposed from a main surface opening 307 defined on three sides by the edge insulating layer 8 and the extension insulating layer 9.

[0147] The multiple extending insulating layers 9 are arranged at intervals in the length direction along the edge of the first trench isolation structure 60. In this embodiment, each extending insulating layer 9 extends one by one from the position where the high step portion 301 of the edge insulating layer 8 is formed. More specifically, the high step portion 301 of the edge insulating layer 8 and the extending insulating layer 9 are formed in a strip shape extending in a direction intersecting the length direction of the first trench isolation structure 60 in a plan view.

[0148] A cap insulating layer 308 is formed on the upper surface 57 of the separation electrode 63. The cap insulating layer 308 includes a plurality of cap insulating layers 308 that selectively extend from the edge insulating layer 8 toward the first trench isolation structure 60 along the horizontal direction and cover the upper surface 57 of the separation electrode 63. In this embodiment, each cap insulating layer 308 extends one by one from the position where the high step portion 301 of the edge insulating layer 8 is formed. More specifically, the high step portion 301 of the edge insulating layer 8, each extending insulating layer 9, and each cap insulating layer 308 are formed in a strip shape extending in a direction intersecting the length direction of the first trench isolation structure 60 in a plan view.

[0149] In other words, in a direction intersecting the longitudinal direction of the first trench isolation structure 60 (first direction X in this embodiment), strip-shaped insulating layers 309 are formed straddling both the isolation-side mesa portion 83 on one side and the isolation electrode 63 on the other side with respect to the edge insulating layer 8. Each cap insulating layer 308 straddles one and the other sides in the width direction of the first trench isolation structure 60, and the isolation electrode 63 is covered by the cap insulating layer 308 over the entire width direction.

[0150] The multiple cap insulating layers 308 are arranged at intervals from each other along a direction intersecting the longitudinal direction of the first trench isolation structure 60. As a result, multiple isolated contact regions 310 are formed on the upper surface 57 of the isolated electrode 63, sandwiched between the multiple cap insulating layers 308 adjacent to each other in the second direction Y. The isolated contact regions 310 may be parts of the isolated electrode 63 selectively exposed from isolation openings 311 defined by the field insulating layer 95 and the cap insulating layer 308.

[0151] The multiple isolated contact regions 310 face the multiple main surface contact regions 305 across the low step portion 302 of the edge insulating layer 8 in the first direction X. In this embodiment, each isolated contact region 310 faces each main surface contact region 305 in a one-to-one relationship.

[0152] In addition, a connection opening 313 that exposes a part of the connection electrode 93 as an end contact region 312 is formed in the field insulating layer 95 .

[0153] Next, the cross-sectional structures of the edge insulating layer 8 and the extended insulating layer 9 will be described with reference to Fig. 12 and Fig. 14. Fig. 12 shows the cross-sectional structure of the low step portion 302 of the edge insulating layer 8, and Fig. 14 shows the cross-sectional structure of the high step portion 301 of the edge insulating layer 8.

[0154] First, referring to FIG. 14, the extension insulating layer 9 is formed thinner than the edge insulating layer 8. For example, the thickness T1 of the edge insulating layer 8 may be 700 Å or more and 3400 Å or less. The thickness T1 may have a value belonging to any one of the ranges of 700 Å or more and 1000 Å or less, 1000 Å or more and 1300 Å or less, 1300 Å or more and 1600 Å or less, 1600 Å or more and 1900 Å or less, 1900 Å or more and 2200 Å or less, 2200 Å or more and 2500 Å or less, 2500 Å or more and 2800 Å or less, 2800 Å or more and 3100 Å or less, and 3100 Å or more and 3400 Å or less. Among these, the range of 1600 Å or more and 1900 Å or less is preferable.

[0155] The thickness T2 of the extended insulating layer 9 may be smaller than the thickness T1 and may be 100 Å or more and 1000 Å or less. The thickness T2 may have a value belonging to any one of the ranges of 100 Å or more and 300 Å or less, 300 Å or more and 500 Å or less, 500 Å or more and 700 Å or less, 700 Å or more and 900 Å or less, and 800 Å or more and 1000 Å or less. Of these, the range of 500 Å or more and 700 Å or less is preferable.

[0156] 14, the lower surface 314 of the extended insulating layer 9 and the lower surface 315 of the edge insulating layer 8 form an integral flat surface 316 in contact with the first main surface 3. In other words, on the first main surface 3, there is no step between the lower surface 314 of the extended insulating layer 9 and the lower surface 315 of the edge insulating layer 8, and the lower surface 314 of the extended insulating layer 9 and the lower surface 315 of the edge insulating layer 8 are smoothly continuous. On the other hand, since thickness T1>thickness T2, a step S caused by the difference between thickness T1 and thickness T2 is formed between the upper surface 58 of the extended insulating layer 9 and the upper surface 59 of the edge insulating layer 8.

[0157] The length L1 of the edge insulating layer 8 from the isolation trench 61 may be 0.2 μm or more and 1.0 μm or less. The length L1 may have a value belonging to any one of the ranges of 0.2 μm or more and 0.5 μm or less, 0.5 μm or more and 0.8 μm or less, and 0.7 μm or more and 1.0 μm or less. Of these, the range of 0.5 μm or more and 0.8 μm or less is preferable.

[0158] Furthermore, the length L2 of the extended insulating layer 9 from the end of the edge insulating layer 8 may be 0.2 μm or more and 1.0 μm or less. The length L2 may have a value belonging to any one of the ranges of 0.2 μm or more and 0.5 μm or less, 0.5 μm or more and 0.8 μm or less, and 0.7 μm or more and 1.0 μm or less. Of these, the range of 0.5 μm or more and 0.8 μm or less is preferable.

[0159] As a result, in the field insulating layer 95, the ratio (L1 / L1+L2) of the length (L1) at a position where the extended insulating layer 9 is not formed to the length (L1+L2) at a position where the extended insulating layer 9 is formed is, for example, 0.2 / 1.2 or more and 1.0 / 1.2 or less. The ratio (L1 / L1+L2) may have a value belonging to any one of the following ranges: 0.2 / 1.2 or more and 0.2 / 1.0 or less, 0.2 / 1.0 or more and 0.2 / 0.8 or less, 0.2 / 0.8 or more and 0.2 / 0.6 or less, 0.2 / 0.6 or more and 0.2 / 0.4 or less, 0.2 / 0.4 or more and 0.4 / 0.6 or less, 0.4 / 0.6 or more and 0.6 / 0.8 or less, 0.6 / 0.8 or more and 0.8 / 1.0 or less, and 0.8 / 1.0 or more and 1.0 / 1.2 or less.

[0160] 14, the edge insulating layer 8 includes a base insulating layer 317 that is integrally extended from the isolation insulating film 62 to the first main surface 3, and a covering insulating layer 318 that covers the base insulating layer 317. The edge insulating layer 8 is formed of a laminated structure of the base insulating layer 317 and the covering insulating layer 318.

[0161] The thickness T1 of the edge insulating layer 8 may be the total thickness of the base insulating layer 317 and the covering insulating layer 318. In this embodiment, the base insulating layer 317 and the covering insulating layer 318 are formed as different insulating layers, but if these insulating layers are formed of the same material, the boundary between the base insulating layer 317 and the covering insulating layer 318 may not be visible. In that case, for example, the depth position at which the etching rate changes when the edge insulating layer 8 is etched may be recognized as the boundary between the base insulating layer 317 and the covering insulating layer 318.

[0162] In this embodiment, the insulating base layer 317 is selectively formed in the region of the edge insulating layer 8 and the extended insulating layer 9 where the edge insulating layer 8 is formed. The insulating base layer 317 has a different thickness at a position of a high step portion 301 adjacent to the position of the extended insulating layer 9 and at a position of a low step portion 302 not adjacent to the position of the extended insulating layer 9.

[0163] The first base thickness TB1 at the position of the high step portion 301 shown in FIG. 14 may be the same as the isolation thickness TI of the isolation insulating film 62, for example. For example, the first base thickness TB1 and the isolation thickness TI may be 600 Å or more and 2400 Å or less. The first base thickness TB1 and the isolation thickness TI may have a value belonging to any one of the ranges of 600 Å or more and 900 Å or less, 900 Å or more and 1200 Å or less, 1200 Å or more and 1500 Å or less, 1500 Å or more and 1800 Å or less, 1800 Å or more and 2100 Å or less and 2400 Å or less. Among these, the ranges of 900 Å or more and 1200 Å or less, 1200 Å or more and 1500 Å or less, or 900 Å or more and 1500 Å or less are preferable.

[0164] On the other hand, the second base thickness TB2 at the position of the low step portion 302 shown in FIG. 12 may be smaller than the isolation thickness TI, for example. For example, the second base thickness TB2 may be 500 Å or more and 1700 Å or less. The second base thickness TB2 may have a value belonging to any one of the ranges of 500 Å or more and 800 Å or less, 800 Å or more and 1100 Å or less, 1100 Å or more and 1400 Å or less, and 1400 Å or more and 1700 Å or less. Of these, the range of 800 Å or more and 1100 Å or less is preferable.

[0165] 14, the covering insulating layer 318 is formed across both sides of the isolation-side mesa portion 83 on one side and the isolation electrode 63 on the other side with respect to the base insulating layer 317 in a direction (first direction X in this embodiment) intersecting the longitudinal direction of the first trench isolation structure 60. As a result, the edge insulating layer 8 is formed of a laminated structure of the base insulating layer 317 and the covering insulating layer 318.

[0166] On the other hand, the extending insulating layer 9 and the cap insulating layer 308 are each formed by an extension of the covering insulating layer 318 that selectively extends in opposite directions from the end of the base insulating layer 317. The thickness TC of the covering insulating layer 318 may be, for example, 100 Å or more and 1000 Å or less. The thickness TC may have a value belonging to any one of the ranges of 100 Å or more and 300 Å or less, 300 Å or more and 500 Å or less, 500 Å or more and 700 Å or less, 700 Å or more and 900 Å or less, and 800 Å or more and 1000 Å or less. Of these, the range of 500 Å or more and 700 Å or less is preferable.

[0167] In this embodiment, the thickness TC of the covering insulating layer 318 is equal to the thickness T2 of the extending insulating layer 9 and the thickness T3 of the cap insulating layer 308. That is, the thickness T2 of the extending insulating layer 9 and the thickness T3 of the cap insulating layer 308 are the same.

[0168] The semiconductor device 1 includes a plurality of silicide layers 319 formed in regions of the first main surface 3 that are exposed from the field insulating layer 95. In Fig. 10, the regions in which the plurality of silicide layers 319 are formed are indicated by hatching.

[0169] The plurality of silicide layers 319 are formed by silicidizing the surface layer of the chip 2 (SiC in this embodiment), the separation electrode 63 (polysilicon in this embodiment), the upper electrode 73 (polysilicon in this embodiment), or the connection electrode 93 (polysilicon in this embodiment) with a metal material. The plurality of silicide layers 319 are formed by silicidizing the surface layer of the chip 2 (SiC in this embodiment), the separation electrode 63 (polysilicon in this embodiment), the upper electrode 73 (polysilicon in this embodiment), or the connection electrode 93 (polysilicon in this embodiment) with a metal material. 2 layer, NiSi layer, CoSi layer, CoSi 2 layer, MoSi 2 Layer and WSi 2 The at least one layer may include

[0170] 12 and 14, the formation region of the silicide layer 319 may be the upper surface 69 of the element-side mesa portion 82, the upper surface 56 of the isolation-side mesa portion 83, the upper surface 55 of the upper electrode 73, the upper surface 57 of the isolation electrode 63, and the upper surface 89 of the connection electrode 93 (see FIG. 10). More specifically, the formation region may be a surface portion of the source region 79, a surface portion of the contact region 80, a surface portion of the main surface contact region 305 (contact region 80), a surface portion of the isolation contact region 310, and a surface portion of the end contact region 312.

[0171] The semiconductor device 1 further includes a contact insulating layer 97 covering the output region 6. The contact insulating layer 97 may include one or more types of insulators. The contact insulating layer 97 may include at least one insulator selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. The contact insulating layer 97 preferably includes an insulator different from the insulator that constitutes the field insulating layer 95. The contact insulating layer 97 preferably includes an insulator different from the insulator that constitutes the upper insulating film 76 (edge ​​insulating film 54). In this embodiment, the contact insulating layer 97 includes either one or both of silicon nitride and silicon oxynitride. That is, the contact insulating layer 97 includes a nitride film.

[0172] The contact insulating layer 97 has a portion covering the field insulating layer 95 in the output region 6, a portion covering the main surface insulating film 94, a portion covering the first main surface 3, a portion covering the first trench isolation structure 60, a portion covering the multiple trench gate structures 70, and a portion covering the multiple trench connection structures 90. For example, with reference to Figures 12 and 14, the contact insulating layer 97 extends into the recess space 35 from above the field insulating layer 95 and covers the upper electrodes 73 of each trench gate structure 70 in the recess space 35.

[0173] It is preferable that the contact insulating layer 97 directly covers the multiple silicide layers 319 on the first main surface 3. Of course, the contact insulating layer 97 may indirectly cover the multiple silicide layers 319. In this case, the contact insulating layer 97 may cover the multiple silicide layers 319 with an oxide film sandwiched therebetween.

[0174] The above-mentioned interlayer insulating layer 12 covers the first trench isolation structure 60 , the trench gate structure 70 , the trench connection structure 90 , the main surface insulating film 94 and the field insulating layer 95 in the output region 6 .

[0175] The interlayer insulating layer 12 is formed of an insulator such as silicon oxide or silicon nitride. The interlayer insulating layer 12 may include a plurality of insulating layers. The plurality of insulating layers may be divided based on the hierarchical levels of the wiring layers formed on the respective main surfaces. For example, the insulating layer on which the first wiring layer of the multilayer wiring structure formed inside the interlayer insulating layer 12 is formed may be the first insulating layer, and the insulating layer on which the second wiring layer is formed may be the second insulating layer. The number of layers of the interlayer insulating layer 12 may increase as the number of hierarchical levels of the multilayer wiring structure increases.

[0176] In this embodiment, the interlayer insulating layer 12 includes a first insulating layer 84, a second insulating layer 85 laminated on the first insulating layer 84, and a third insulating layer 86 laminated on the second insulating layer 85.

[0177] The first insulating layer 84 includes a lower layer 87 in contact with the contact insulating layer 97, and an upper layer 88 sandwiched between the lower layer 87 and the second insulating layer 85. The lower layer 87 may be formed of silicon oxide having a higher density than the upper layer 88.

[0178] The lower layer 87 may be, for example, a USG (HDP-USG: High Density Plasma CVD-Undoped Silica Glass) film formed by a high density plasma CVD method. If the lower layer 87 in contact with the contact insulating layer 97 and close to the first main surface 3 has a high density, it is possible to accurately fill in the irregularities of the miniaturized transistor structure and improve the insulation between the various parts of the transistor structure. As a result, it is possible to prevent short circuits in the transistor structure. The upper layer 88 may be, for example, a USG film formed by a plasma CVD method under conditions different from those of the lower layer 87. The film qualities (e.g., density, etc.) of the lower layer 87 and the upper layer 88 can be made different by, for example, changing the electron temperature, electron density, etc. in the plasma.

[0179] The second insulating layer 85 and the third insulating layer 86 may be, for example, a USG film formed by a plasma CVD method under the same conditions as the upper layer 88 of the first insulating layer 84.

[0180] The semiconductor device 1 includes a first wiring layer 16 and a second wiring layer 17 disposed in an interlayer insulating layer 12. The first wiring layer 16 is formed on a first insulating layer 84, and the second wiring layer 17 is formed on a second insulating layer 85.

[0181] 7, 11, 13, and 15 to 18, the first wiring layer 16 includes a first gate wiring 18 and a first source wiring 19. The first gate wiring 18 is further separated into a plurality of 1-1 system gate wirings 18A and a plurality of 2-1 system gate wirings 18B.

[0182] The plurality of 1-1 system gate wirings 18A are part of wirings that individually transmit gate signals to the plurality of first system transistors 21 A. Each of the 1-1 system gate wirings 18A is selectively formed in an upper region of the trench connection structure 90 so as to cover the trench connection structure 90 of each first block region 81A.

[0183] In other words, each of the 1-1 system gate wirings 18A is formed avoiding the upper region of the trench connection structure 90 in each of the second block regions 81B. Also, each of the 1-1 system gate wirings 18A is formed straddling between the trench gate structure 70 and the trench connection structure 90. As a result, each of the 1-1 system gate wirings 18A faces the upper electrode 73 and the connection electrode 93 in the thickness direction of the chip 2. In this embodiment, each of the 1-1 system gate wirings 18A is formed in a rectangular shape in a plan view having approximately the same width as the width of the pair of trench gate structures 70 in the first direction X.

[0184] The plurality of 2-1 system gate wirings 18B are part of wirings that individually transmit gate signals to the plurality of second system transistors 21B. Each of the 2-1 system gate wirings 18B is selectively formed in an upper region of the trench connection structure 90 so as to cover the trench connection structure 90 of each of the second block regions 81B. In other words, each of the 2-1 system gate wirings 18B is formed avoiding an upper region of the trench connection structure 90 of each of the first block regions 81A. The 1-1 system gate wirings 18A are disposed between the adjacent 2-1 system gate wirings 18B. As a result, the plurality of 1-1 system gate wirings 18A and the plurality of 2-1 system gate wirings 18B are alternately arranged in the first direction X with a gap between them.

[0185] Moreover, each of the 2-1 system gate wirings 18B is formed across between the trench gate structure 70 and the trench connection structure 90. As a result, each of the 2-1 system gate wirings 18B faces the upper electrode 73 and the connection electrode 93 in the thickness direction of the chip 2. In this embodiment, each of the 2-1 system gate wirings 18B is formed in a rectangular shape in a plan view having approximately the same width as the width of the pair of trench gate structures 70 in the first direction X.

[0186] The first gate wiring 18 further includes a first gate lead-out wiring 18C. The first gate lead-out wiring 18C is collectively connected to the plurality of 1-1 system gate wirings 18A and transmits a gate signal to the plurality of 1-1 system gate wirings 18A. The first gate lead-out wiring 18C extends in the first direction X on the side of the plurality of 1-1 system gate wirings 18A and the plurality of 2-1 system gate wirings 18B and is drawn out to the outside of the first trench isolation structure 60. The 1-1 system gate wiring 18A and the first gate lead-out wiring 18C as a whole have a comb-tooth shape in which the 1-1 system gate wiring 18A is selectively drawn out from the first gate lead-out wiring 18C to the first block region 81A.

[0187] The first source wiring 19 is electrically connected to the system sources (unit sources of the unit transistors 22) of all the system transistors 21. The first source wiring 19 is formed in an island shape crossing the striped first trench isolation structure 60, the isolation-side mesa portion 83, the multiple trench gate structures 70, and the multiple element-side mesa portions 82 in the first direction X. As a result, the first source wiring 19 faces the isolation electrode 63, the contact region 80 of the isolation-side mesa portion 83, and the source region 79 and contact region 80 of the element-side mesa portion 82 in the thickness direction of the chip 2.

[0188] 8, 11, 13, and 15 to 18, the second wiring layer 17 includes a second gate wiring 96 and a second source wiring 98. The second gate wiring 96 is further separated into a plurality of 1-2 system gate wirings 96A and a plurality of 2-2 system gate wirings 96B.

[0189] The plurality of 1-2 system gate wirings 96A are part of wirings that individually transmit gate signals to the plurality of first system transistors 21A. Each of the 1-2 system gate wirings 96A is formed so as to cover each of the 1-1 system gate wirings 18A. Each of the 1-2 system gate wirings 96A is provided in a one-to-one correspondence with each of the 1-1 system gate wirings 18A. Therefore, each of the 1-2 system gate wirings 96A faces one of the 1-1 system gate wirings 18A in the thickness direction of the chip 2. In this embodiment, each of the 1-2 system gate wirings 96A is formed in a rectangular shape in a plan view having approximately the same width as each of the 1-1 system gate wirings 18A.

[0190] The plurality of 2-2 system gate wirings 96B are part of wirings that individually transmit gate signals to the plurality of second system transistors 21B. Each of the 2-2 system gate wirings 96B is formed so as to cover each of the 2-1 system gate wirings 18B. Each of the 2-2 system gate wirings 96B is provided in a one-to-one correspondence with each of the 2-1 system gate wirings 18B. Therefore, each of the 2-2 system gate wirings 96B faces one of the 2-1 system gate wirings 18B in the thickness direction of the chip 2. In this embodiment, each of the 2-2 system gate wirings 96B is formed in a rectangular shape in a plan view having substantially the same width as each of the 2-1 system gate wirings 18B.

[0191] The second gate wiring 96 further includes a second gate lead-out wiring 96C and a first gate connection wiring 96D. The second gate lead-out wiring 96C is collectively connected to the plurality of 2-2 system gate wirings 96B and transmits gate signals to the plurality of 2-2 system gate wirings 96B. The second gate lead-out wiring 96C extends in the first direction X on the side of the plurality of 2-2 system gate wirings 96B and the plurality of 1-2 system gate wirings 96A and is drawn out to the outside of the first trench isolation structure 60. The 2-2 system gate wiring 96B and the second gate lead-out wiring 96C as a whole have a comb-tooth shape in which the 2-2 system gate wiring 96B is selectively drawn out from the second gate lead-out wiring 96C to the 2-1 system gate wiring 18B.

[0192] The first gate connection wiring 96D is connected to the plurality of 1-2 system gate wirings 96A collectively, and transmits gate signals to the plurality of 1-2 system gate wirings 96A. Since the plurality of 1-1 system gate wirings 18A are connected collectively by the first gate lead-out wiring 18C, the first gate connection wiring 96D may be provided independently in a one-to-one correspondence with each of the 1-2 system gate wirings 96A. However, by connecting the plurality of 1-2 system gate wirings 96A collectively to the first gate connection wiring 96D, the gate potential can be stabilized.

[0193] The first gate connection wiring 96D extends laterally of the plurality of 2-2 system gate wirings 96B and the plurality of 1-2 system gate wirings 96A in the first direction X on the opposite side to the second gate lead-out wiring 96C. The 1-2 system gate wirings 96A and the first gate connection wiring 96D as a whole have a comb-tooth shape in which the 1-2 system gate wirings 96A are selectively drawn out from the first gate connection wiring 96D to the 1-1 system gate wiring 18A.

[0194] The second source wiring 98 is electrically connected to the system sources (unit sources of the unit transistors 22) of all the system transistors 21. The second source wiring 98 is formed in an island shape covering almost the entire first source wiring 19. As a result, the second source wiring 98 faces the first source wiring 19 in the thickness direction of the chip 2.

[0195] The semiconductor device 1 further includes a first via electrode 36 and a second via electrode 37 embedded in the interlayer insulating layer 12. The first via electrode 36 and the second via electrode 37 may be plug electrodes including at least one of tungsten, aluminum, and copper, for example. The first via electrode 36 and the second via electrode 37 may be embedded in the interlayer insulating layer 12 via a barrier film (base film) including at least one of Ti and TiN, for example.

[0196] The first via electrode 36 is an electrode embedded in the first insulating layer 84, and may be referred to as a first contact electrode. The first via electrode 36 connects the first wiring layer 16 and a contact object on the first main surface 3 of the chip 2. The "contact object" may include an impurity region formed on the first main surface 3, an impurity region formed at a position recessed through a step on the second main surface 4 side from the first main surface 3, a buried electrode formed in a trench formed on the first main surface 3, a buried conductor buried in the first main surface 3, and the like. The "contact object" is formed on the surface layer of the first main surface 3, and may be referred to as a "first main surface 3 side contact object."

[0197] In this embodiment, referring to Figure 6, the "contact object" includes the isolation electrode 63 (isolation contact region 310) of the first trench isolation structure 60, the contact region 80 (main surface contact region 305) of the isolation side mesa portion 83, the source region 79 and contact region 80 of the element side mesa portion 82, the upper electrode 73 of the trench gate structure 70, and the connection electrode 93 (end contact region 312) of the trench connection structure 90.

[0198] The first via electrode 36 may be referred to by different names for each “contact object.” For example, the first via electrode 36 may include a first isolation contact 38, a first active contact 39, a first element contact 40, a first upper gate contact 41, and a first lower gate contact 42.

[0199] The first isolation contact 38 connects the first source wiring 19 and the isolation electrode 63. In this embodiment, the first isolation contact 38 is physically and electrically connected to the first source wiring 19 and the isolation electrode 63. The first isolation contact 38 is connected to the isolation electrode 63 of the first trench isolation structure 60 to form a trench contact structure.

[0200] 6, the first isolation contact 38 is formed in a band shape extending in the longitudinal direction of the first trench isolation structure 60 in a plan view. In this embodiment, a plurality of band-shaped first isolation contacts 38 are arranged at intervals in the longitudinal direction of the first trench isolation structure 60. Of course, the first isolation contact 38 may be formed in only one place as long as it can connect the first source wiring 19 and the isolation electrode 63.

[0201] The length of the first isolated contact 38 can be freely set as long as it faces the first source wiring 19 in the thickness direction of the chip 2. In other words, the first isolated contact 38 may be longer than the length shown in the figure as long as it is shorter than the width of the first source wiring 19 in the second direction Y.

[0202] The first active contact 39 connects the first source wiring 19 and the contact region 80 of the isolation-side mesa portion 83. In this embodiment, the first active contact 39 is physically and electrically connected to the first source wiring 19 and the contact region 80. The first active contact 39 is connected to the contact region 80 of the isolation-side mesa portion 83 to form a mesa contact structure.

[0203] 6, the first active contact 39 is formed in a band shape extending in the longitudinal direction of the separation-side mesa 83 (the longitudinal direction of the trench gate structure 70) in a plan view. In this embodiment, a plurality of band-shaped first active contacts 39 are arranged at intervals in the longitudinal direction of the separation-side mesa 83. Of course, the first active contact 39 may be formed in only one place as long as it can be connected to the contact region 80 of the separation-side mesa 83.

[0204] The length of the first active contact 39 can be freely set as long as it faces the first source wiring 19 in the thickness direction of the chip 2. In other words, the first active contact 39 may be longer than the length shown in the figure as long as it is shorter than the width of the first source wiring 19 in the second direction Y.

[0205] At least one first active contact 39 and at least one first isolation contact 38 are aligned in a direction perpendicular to the length direction of the first trench isolation structure 60. In this embodiment, each first isolation contact 38 is aligned opposite each first active contact 39 in a one-to-one relationship in the first direction X.

[0206] The first element contact 40 connects the first source wiring 19 to the source region 79 and contact region 80 of the element-side mesa portion 82. The first element contact 40 is physically and electrically connected to the first source wiring 19, the source region 79, and the contact region 80. The first element contact 40 is connected to the source region 79 and contact region 80 of the element-side mesa portion 82 to form a mesa contact structure.

[0207] 6, the first element contact 40 is formed in a strip shape extending in the length direction of the element-side mesa portion 82 (the length direction of the trench gate structure 70) in a plan view. In this embodiment, one elongated strip-shaped first element contact 40 is formed in the length direction of the element-side mesa portion 82. Of course, the first element contact 40 may be formed in multiple locations spaced apart from each other as long as it can connect to the contact region 80 of the element-side mesa portion 82.

[0208] The length of the first element contact 40 can be freely set as long as it faces the first source wiring 19 in the thickness direction of the chip 2. In other words, the first element contact 40 may be longer than the length shown in the figure as long as it is shorter than the width of the first source wiring 19 in the second direction Y.

[0209] The first upper gate contact 41 connects the first gate wiring 18 and the upper electrode 73. The first upper gate contact 41 is physically and electrically connected to the first gate wiring 18 and the upper electrode 73. The first upper gate contact 41 is connected to the upper electrode 73 of the trench gate structure 70 to form a trench contact structure.

[0210] 6, the first upper gate contact 41 is formed in a strip shape extending in the longitudinal direction of the trench gate structure 70 in a plan view. In this embodiment, the first upper gate contact 41 is formed at a first end portion on one side in the longitudinal direction (second direction Y) of each trench gate structure 70, and at a second end portion (not shown in FIG. 6) on the other side in the longitudinal direction (second direction Y). Of course, the first upper gate contact 41 may be formed in only one place as long as it can connect the first gate wiring 18 and the upper electrode 73.

[0211] The length of the first upper gate contact 41 can be freely set as long as it faces the first gate wiring 18 in the thickness direction of the chip 2. In other words, the first upper gate contact 41 may be longer than the length shown in the figure as long as it is shorter than the width of the first gate wiring 18 in the second direction Y and does not overlap with the first source wiring 19.

[0212] The first lower gate contact 42 connects the first gate wiring 18 and the connection electrode 93. The first lower gate contact 42 is physically and electrically connected to the first gate wiring 18 and the connection electrode 93. The first lower gate contact 42 is connected to the connection electrode 93 of the trench connection structure 90 to form a trench contact structure. The first lower gate contact 42 is electrically connected to the lower electrode 74 of the trench gate structure 70 via the connection electrode 93.

[0213] 6, the first lower gate contact 42 is formed in a strip shape extending in the length direction of the trench connection structure 90 in a plan view. In this embodiment, the first lower gate contact 42 is selectively formed in a first portion extending in the first direction of each trench connection structure 90. The first portion of each trench connection structure 90 is longer than a pair of second portions extending in the second direction Y from both ends of the first portion toward the trench gate structure 70. By connecting the first lower gate contact 42 to the first portion of each trench connection structure 90, it is possible to form a first lower gate contact 42 that is longer than when it is connected to the second portion. Of course, the first lower gate contact 42 may be selectively formed in the second portion of each trench connection structure 90 as long as it can connect the first gate wiring 18 and the connection electrode 93, or may be formed in an arch shape in a plan view corresponding to the planar shape of each trench connection structure 90.

[0214] The length of the first lower gate contact 42 can be freely set as long as it faces the first gate wiring 18 in the thickness direction of the chip 2. In other words, the first lower gate contact 42 may be longer than the length shown in the figure as long as it is shorter than the width of the first gate wiring 18 in the first direction X.

[0215] The second via electrode 37 is an electrode embedded in the second insulating layer 85, and may be referred to as a second contact electrode. The second via electrode 37 connects the second wiring layer 17 and the first wiring layer 16 to each other.

[0216] In this embodiment, the second via electrode 37 may include a second source contact 43 and a second gate contact 44 .

[0217] The second source contact 43 connects the second source wiring 98 and the first source wiring 19. With reference to Fig. 8, in this embodiment, the second source contact 43 is formed in a band shape extending in the length direction of the element-side mesa 82 in a plan view. In this embodiment, one band-shaped second source contact 43 extending in the second direction Y is formed in the upper region of each element-side mesa 82. As a result, a plurality of stripe-shaped second source contacts 43 are arranged at intervals in the first direction X in a plan view.

[0218] The second gate contact 44 connects the second gate wiring 96 and the first gate wiring 18. Referring to FIG. 8, in this embodiment, the second gate contact 44 is formed in an opposing region between the 1-1 system gate wiring 18A and the 1-2 system gate wiring 96A and an opposing region between the 2-1 system gate wiring 18B and the 2-2 system gate wiring 96B in a plan view. In this embodiment, a plurality of second gate contacts 44 are arranged in a matrix in an upper region of each of the 1-1 system gate wirings 18A and each of the 2-1 system gate wirings 18B. Each of the second gate contacts 44 is formed in a square shape in a plan view having one side shorter than the first upper gate contact 41 and the first lower gate contact 42.

[0219] Figures 19A to 19N are diagrams for explaining a part of the manufacturing process of the semiconductor device 1. Figure 20 is a diagram showing a mask pattern used when patterning the protective insulating layer 99. The manufacturing flow of the element structure of the output region 6 will be described in order with reference to Figures 19A to 19I, and the description of the manufacturing flow of the element structure of the control region 7 will be omitted.

[0220] 19A, a silicon wafer 45 is prepared as a base for the chip 2. Next, an isolation trench 61, a gate trench 71, and a connection trench 91 are formed on the first main surface 3 of the wafer 45. As a result, an element-side mesa portion 82 and an isolation-side mesa portion 83 are defined.

[0221] 19B, a base insulating layer 46 is formed as a base for the isolation insulating film 62, the lower insulating film 77, and the field insulating layer 95. The base insulating layer 46 is formed in a film shape along the first main surface 3 of the wafer 45, the inner wall of the isolation trench 61, the inner wall of the gate trench 71, and the inner wall of the connection trench 91. The base insulating layer 46 may be formed by an oxidation process (for example, a thermal oxidation process) or a CVD process. In this embodiment, the base insulating layer 46 is formed by a thermal oxidation process.

[0222] Next, referring to FIG. 19C, a base electrode layer 47 serving as a base for the separation electrode 63, the lower electrode 74, and the connection electrode 93 is formed on the first main surface 3 of the wafer 45. The base electrode layer 47 fills the separation trench 61, the gate trench 71, and the connection trench 91 to cover the first main surface 3 of the wafer 45. The base electrode layer 47 includes conductive polysilicon. The base electrode layer 47 may be formed by a CVD method. Thereafter, unnecessary portions of the base electrode layer 47 are removed to form the separation electrode 63, the lower electrode 74, and the connection electrode 93.

[0223] Next, referring to FIG. 19D, a mask 48 having a predetermined pattern is formed on the first main surface 3 of the wafer 45. The mask 48 may be a photoresist. The mask 48 covers the separation electrode 63 and the connection electrode 93, and has an opening 49 that selectively exposes the lower electrode 74 (base electrode layer 47). Next, the base electrode layer 47 in the gate trench 71 is removed by an etching method via the mask 48. The base electrode layer 47 is removed up to the middle of the gate trench 71 in the depth direction. As a result, the lower electrode 74 is formed in its final shape. Furthermore, an unnecessary portion of the base insulating layer 46 is removed by an etching method via the mask 48. The base insulating layer 46 is removed until the end of the lower electrode 74 is exposed in the gate trench 71. As a result, the lower insulating film 77 is formed in the gate trench 71. Next, referring to FIG. 19E, the mask 48 is removed. Of the base insulating layer 46, the portion that is drawn out integrally with the isolation insulating film 62 from the isolation trench 61 is the field insulating layer 95 (edge ​​insulating layer 8). At this stage, of the base insulating layer 317 and the covering insulating layer 318 shown in FIG. 14, the field insulating layer 95 is formed by the single-layer structure of the base insulating layer 317.

[0224] Next, referring to FIG. 19F, an intermediate insulating film 75, an upper insulating film 76, and a main surface insulating film 94 are formed. The intermediate insulating film 75, the upper insulating film 76, and the main surface insulating film 94 may be formed by an oxidation treatment method (for example, a thermal oxidation treatment method) or a CVD method. In this embodiment, the intermediate insulating film 75, the upper insulating film 76, and the main surface insulating film 94 are formed by a thermal oxidation treatment method. Next, a base electrode layer 50 that serves as a base for the upper electrode 73 is formed on the first main surface 3 of the wafer 45. The base electrode layer 50 fills the gate trench 71 and covers the first main surface 3 of the wafer 45. The base electrode layer 50 includes conductive polysilicon. The base electrode layer 50 may be formed by a CVD method. Next, an unnecessary portion of the base electrode layer 50 is removed to form the upper electrode 73. The base electrode layer 50 may be removed by an etching method (etch-back method). The etching method may be a wet etching method.

[0225] The base electrode layer 50 is removed until the main surface insulating film 94 is exposed. At this time, in order to reliably separate the upper electrodes 73 of the first system transistors 21A and the upper electrodes 73 of the second system transistors 21B from each other and to avoid short circuits between them, the etching time is controlled so that the upper surface of the base electrode layer 50 is deeper than the first main surface 3. As a result, a recess space 35 is formed in an upper region of each upper electrode 73. Thereafter, although not shown, impurity regions such as a body region 67, a source region 79, and a contact region 80 are formed in the surface layer portion of the first main surface 3 of the wafer 45.

[0226] The next step is a step of forming a silicide layer 319 shown in FIG. 19G to FIG. 19K. First, referring to FIG. 19G, a protective insulating layer 99 for blocking silicidation is formed on the entire surface of the first main surface 3. The protective insulating layer 99 is a film that serves as a base for the covering insulating layer 318 shown in FIG. 14 and the main surface insulating film 94 shown in FIG. 15 and FIG. 16. The protective insulating layer 99 may be, for example, a USG (HDP-USG: High Density Plasma CVD-Undoped Silica Glass) film formed by a high density plasma CVD method. As a result, the field insulating layer 95 is formed in a laminated structure of the base insulating layer 317 and the covering insulating layer 318 (protective insulating layer 99) (see FIG. 14). In addition, a cap insulating layer 308 is formed on the separation electrode 63. FIG. 19G shows a film in which the main surface insulating film 94 and the protective insulating layer 99 are integrated together.

[0227] Next, referring to Fig. 19H, a mask 100 having a predetermined pattern is formed on the first main surface 3 of the wafer 45. The mask 100 may be a photoresist. Referring to Fig. 20, the mask 100 has an opening 320 that selectively exposes a region where the silicide layer 319 is to be formed, and covers the entire other region of the protective insulating layer 99. In particular, in the first trench isolation structure 60 and the isolation-side mesa portion 83, the region where the strip-shaped insulating layer 309 is to be formed is covered by the strip-shaped portion 321 of the mask 100.

[0228] Next, an unnecessary portion of the protective insulating layer 99 is removed by an etching method through the mask 100. As a result, in the field insulating layer 95, the edge insulating layer 8 and the extension insulating layer 9 are formed, and the main surface contact region 305, the isolation contact region 310, and the end contact region 312 are formed. In addition, the upper surface of the upper electrode 73 is exposed over almost the entire length of the gate trench 71. Next, referring to FIG. 19I, the mask 100 is removed. In the previous etching process, the portion of the field insulating layer 95 covered with the mask 100 remains as the high step portion 301, and the protective insulating layer 99 is removed from the portion exposed from the opening 320, and further, the base insulating layer 317 is thinned by the progress of etching. As a result, as shown in FIG. 12, the second base thickness TB2 at the position of the low step portion 302 becomes smaller than the isolation thickness TI of the isolation insulating film 62.

[0229] Next, referring to FIG. 19J, a metal layer 322 for forming a silicide is formed on the entire surface of the first main surface 3 by, for example, a sputtering method. The metal layer 322 may be, for example, at least one of a titanium (Ti) layer, a nickel (Ni) layer, a cobalt (Co) layer, a molybdenum (Mo) layer, and a tungsten (W) layer. In FIG. 19J, the metal layer 322 is hatched for clarity. Next, the wafer 45 is heat-treated, so that the contact portion between the silicon (including polysilicon) and the metal layer 322 changes to a metal silicide. Meanwhile, the metal layer 322 on the insulating film does not change and remains the original metal material. As a result, a silicide layer 319 is formed on the element-side mesa portion 82 and the isolation-side mesa portion 83 made of SiC, and on the isolation electrode 63 and the upper electrode 73 made of polysilicon.

[0230] 19K, only the material of the metal layer 322 on the insulating film is selectively removed by chemical treatment. At this time, the silicide layer 319 is left without being treated with the chemical solution. As a result, the silicide layer 319 is formed in a self-aligned manner in the region exposed from the field insulating layer 95.

[0231] Next, referring to FIG. 19L, a contact insulating layer 97 is formed on the first main surface 3 of the wafer 45. The contact insulating layer 97 may be formed by a CVD method. Next, a first insulating layer 84 is formed on the contact insulating layer 97. In this embodiment, the first insulating layer 84 has a two-layer structure including a lower layer 87 and an upper layer 88. The first insulating layer 84 may be formed by a CVD method. A planarization process may be performed on the main surface of the first insulating layer 84. The planarization process of the first insulating layer 84 may be performed by a CMP (Chemical Mechanical Polishing) method.

[0232] Next, referring to FIG. 19M, a mask (not shown) having a predetermined pattern is formed on the main surface of the first insulating layer 84. The mask has a plurality of openings exposing regions in which the first isolation contact 38, the first active contact 39, the first element contact 40, the first upper gate contact 41, and the first lower gate contact 42 are to be embedded. Next, unnecessary portions of the first insulating layer 84 are removed by an etching method through the mask. As a result, a plurality of contact holes 51 are formed in the first insulating layer 84. The mask is then removed.

[0233] Next, referring to FIG. 19N, a base plug electrode layer 52 serving as a base for the first isolation contact 38, the first active contact 39, the first element contact 40, the first upper gate contact 41, and the first lower gate contact 42 is formed on the main surface of the first insulating layer 84. The base plug electrode layer 52 fills the contact holes 51 and covers the main surface of the first insulating layer 84. Next, unnecessary portions of the base plug electrode layer 52 are removed. The unnecessary portions of the base plug electrode layer 52 are removed until the main surface of the first insulating layer 84 is exposed. The unnecessary portions of the base plug electrode layer 52 may be removed by an etching method or a CMP method. As a result, the first isolation contact 38, the first active contact 39, the first element contact 40, the first upper gate contact 41, and the first lower gate contact 42 are formed.

[0234] Thereafter, a first wiring layer 16 is formed on the first insulating layer 84, and a second insulating layer 85 is formed on the first insulating layer 84 so as to cover the first wiring layer 16. Next, a second source contact 43 and a second gate contact 44 are embedded in the second insulating layer 85, and a second wiring layer 17 is formed on the second insulating layer 85. Next, a third insulating layer 86 is formed on the second insulating layer 85 so as to cover the second wiring layer 17, thereby forming an interlayer insulating layer 12.

[0235] Next, a plurality of terminals 13, 14 are formed on the interlayer insulating layer 12. The plurality of terminals 13, 14 may be formed by a sputtering method and / or a plating method. Furthermore, a drain terminal 15 is formed on the second main surface 4 (not shown) of the wafer 45. The drain terminal 15 may be formed by a sputtering method and / or a plating method.

[0236] Thereafter, the wafer 45 is selectively cut to cut out the semiconductor device 1. The semiconductor device 1 is manufactured through the steps including those described above.

[0237] [Structure of control area 7] Hereinafter, the configuration of the first circuit region 101 in which the logic circuit 32 on the control region 7 side is formed will be described with reference to FIGS. 21 to 23. FIG. 21 is a plan view showing the first circuit region 101 in which the logic circuit 32 shown in FIG. 1 is formed. FIG. 22 is a schematic cross-sectional view of the first circuit region 101 in FIG. 13. FIG. 22 does not show a cross section along a specific cutting line in the plan view of FIG. 21, but is a diagram showing a schematic cross-sectional structure of each component in the first circuit region 101. FIG. 23 is an enlarged view of region XXIII in FIG. 22. The first circuit region 101 may be referred to as a logic circuit region.

[0238] 21 to 23, the semiconductor device 1 includes a first circuit region 101 defined on the first main surface 3 in the control region 7. The first circuit region 101 is a region to which a voltage (potential) different from that of the output region 6 is applied, and is a region in which a CMIS 101a constituting one circuit out of a plurality of types of electronic circuits (circuit devices) is formed.

[0239] Specifically, the CMIS 101a includes a first n-type MISFET 102 (first n-type channel MIS transistor) and a second p-type MISFET 103 (first p-type channel MIS transistor) that are complementarily connected. The first MISFET 102 is driven and controlled under a voltage application condition different from that of the output transistor 20. The second MISFET 103 is driven and controlled under a voltage application condition different from that of the output transistor 20 and the first MISFET 102. Note that the first n-type MISFET 102 and the second p-type MISFET 103 may be combined complementarily as in this embodiment, or may be formed as independent elements.

[0240] The rated voltage (first rated voltage) of the first MISFET 102 and the second MISFET 103 may be, for example, not less than 1.0 V and not more than 8.0 V.

[0241] The rated voltages of the first MISFET 102 and the second MISFET 103 may be defined as a range of maximum allowable values ​​of voltages applied between the source and drain of the first MISFET 102 and the second MISFET 103. The rated voltages of the first MISFET 102 and the second MISFET 103 may also be referred to as the breakdown voltages of the first MISFET 102 and the second MISFET 103.

[0242] The specific structure within the first circuit region 101 will now be described.

[0243] The semiconductor device 1 includes a second trench separation structure 104 that partitions a first circuit region 101 on the first main surface 3. The first circuit region 101 is a device region that is controlled under a voltage application condition different from that of the output region 6. The second trench separation structure 104 may be referred to as a deep trench isolation (DTI) structure.

[0244] The second trench isolation structure 104 is formed in a ring shape surrounding a partial region of the first main surface 3 in a plan view, and defines a first circuit region 101 having a predetermined shape. In this embodiment, the second trench isolation structure 104 is formed in a quadrangular ring shape having four sides parallel to the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 in a plan view, and defines the quadrangular first circuit region 101. The second trench isolation structure 104 may have any planar shape, and may be formed in a polygonal ring shape. The first circuit region 101 may be defined in a polygonal shape according to the planar shape of the second trench isolation structure 104.

[0245] Similar to the first trench isolation structure 60, the second trench isolation structure 104 has a first width W1 and a first depth D1 (i.e., an aspect ratio D1 / W1). It is particularly preferable that the bottom wall of the second trench isolation structure 104 is formed with a distance of 1 μm or more and 5 μm or less from the bottom of the substrate region 158. The substrate region 158 is integrally connected to the drift region 11 described above, and is formed of an n-type epitaxial layer (Si epitaxial layer).

[0246] The second trench isolation structure 104 has an isolation corner 127 that connects a portion extending in the first direction X and a portion extending in the second direction Y. The isolation corner 127 is strip-shaped extending in a direction inclined with respect to the first direction X and the second direction Y. More specifically, the isolation corner 127 is inclined at 45° with respect to each of the first direction X and the second direction Y. The isolation corner 127 preferably has a constant first width W1. Although not shown, the isolation corner 127 (the four corners of the second trench isolation structure 104) may be formed in an arc shape. In other words, the first circuit region 101 may be partitioned by a quadrangle having four corners formed in an arc shape.

[0247] The second trench isolation structure 104 has a single electrode structure including an isolation trench 61, an isolation insulating film 62, and an isolation electrode 63, similar to the first trench isolation structure 60. The "isolation trench 61", "isolation insulating film 62", and "isolation electrode 63" of the second trench isolation structure 104 may be referred to as a "second isolation trench", a "second isolation insulating film", and a "second isolation electrode", respectively. The explanation of the isolation trench 61, isolation insulating film 62, and isolation electrode 63 of the second trench isolation structure 104 is omitted because the explanation of the isolation trench 61, isolation insulating film 62, and isolation electrode 63 of the first trench isolation structure 60 is applicable.

[0248] A first well region 114 is formed in a surface layer portion of the first main surface 3 in the first circuit region 101. The first well region 114 is formed in a surface layer portion of the first main surface 3 in the first circuit region 101, and is in contact with the second trench isolation structure 104.

[0249] A first contact region 122 is formed in a surface layer portion of the first well region 114. The first contact region 122 may also be referred to as a "first back gate region" or a "guard ring region." The first contact region 122 has a p-type impurity concentration that exceeds the p-type impurity concentration of the first well region 114. The first contact region 122 is formed at a distance from the second trench isolation structure 104.

[0250] 21, first contact region 122 is preferably formed in a ring shape when viewed from above. Note that first contact region 122 does not have to be formed in a ring shape.

[0251] 22, a second well region 115 is formed in a surface layer portion of the first main surface 3 in the first circuit region 101. The second well region 115 is an impurity region selectively protruding from a bottom portion of the first well region 114 toward the second main surface 4. The second well region 115 is formed in almost the entire surface layer portion of the first main surface 3 in the first circuit region 101 across the first MISFET 102 and the second MISFET 103. An end 116 of the second well region 115 is spaced inward from the second trench isolation structure 104. A part of the substrate region 158 may be interposed between the end 116 of the second well region 115 and the second trench isolation structure 104.

[0252] The semiconductor device 1 further includes a first element isolation structure 106 that partitions the first MIS region 105 on the first main surface 3 of the first circuit region 101. The first element isolation structure 106 may be referred to as an STI (shallow trench isolation) structure. The first MIS region 105 may be referred to as a "first active region" or an "n-side active region."

[0253] The first element isolation structure 106 is formed in a ring shape surrounding a portion of the first main surface 3 in a plan view, and defines a first MIS region 105 having a predetermined shape. In this embodiment, the first element isolation structure 106 is formed in a quadrangular ring shape having four sides parallel to the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 in a plan view, and defines the quadrangular first MIS region 105. The first element isolation structure 106 may have any planar shape, and may be formed in a polygonal ring shape. The first MIS region 105 may be defined in a polygonal shape according to the planar shape of the first element isolation structure 106.

[0254] The first element isolation structure 106 includes an isolation trench 107 and a buried insulator 108. The isolation trench 107 is formed on the first main surface 3 and partitions the wall surface of the first element isolation structure 106. The buried insulator 108 is buried over the entire width direction from the bottom to the open end of the isolation trench 107. The isolation trench 107 is filled back with the buried insulator 108. The buried insulator 108 may include a silicon oxide film made of the oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0255] Referring to FIG. 23, the width WE1 of the element structure of the first MISFET 102 including the width WM1 of the first MIS region 105 and the width WM2 of the first element isolation structure 106 may be less than 1 μm. The width WE1 may be the width obtained by adding the width WM2 of the open ends of the isolation trenches 107 of a pair of first element isolation structures 106 and the width WM1 of the first MIS region 105 sandwiched between the pair of first element isolation structures 106 in the cross-sectional view shown in FIG. 23. For example, the width WM1 of the first MIS region 105 may be 0.15 μm or more and 0.3 μm or less, and the width WM2 of each isolation trench 107 may be 0.2 μm or more and 0.4 μm or less.

[0256] A first outer region 109 is formed outside the first element isolation structure 106. The first outer region 109 is a region sandwiched between the first element isolation structure 106 and a first outer isolation structure 110 surrounding the first element isolation structure 106. In FIG. 22, only the portion forming the boundary between the first MISFET 102 and the second MISFET 103 is shown as the first outer isolation structure 110. Similar to the first element isolation structure 106, the first outer isolation structure 110 includes an isolation trench 107 and a buried insulator 108.

[0257] In the first MIS region 105, a first gate electrode 111 is formed on the first main surface 3. The first gate electrode 111 may include conductive polysilicon.

[0258] A first gate insulating film 112 is formed between the first gate electrode 111 and the chip 2. The first gate insulating film 112 may include a silicon oxide film. The first gate insulating film 112 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0259] A first sidewall structure 113 is formed around the first gate electrode 111. The first sidewall structure 113 is continuously formed around the entire periphery of the first gate electrode 111 so as to cover the side surface of the first gate electrode 111. The first sidewall structure 113 includes at least one of silicon oxide and silicon nitride. In this embodiment, the first sidewall structure 113 includes silicon oxide. The first sidewall structure 113 may include silicon nitride. That is, the first sidewall structure 113 may include an insulator different from the first gate insulating film 112.

[0260] A pair of n-type first source region 117 and n-type first drain region 118 are formed at an interval in a surface layer portion of first well region 114. First source region 117 and first drain region 118 have an n-type impurity concentration exceeding a p-type impurity concentration of first well region 114. With reference to FIG. 21, first source region 117 and first drain region 118 extend parallel to each other along second direction Y. First source region 117 and first drain region 118 may be formed in a rectangular shape of the same size that is long along second direction Y in a plan view. With reference to FIG. 22, first source region 117 and first drain region 118 are formed in a self-aligned manner with respect to first gate electrode 111.

[0261] In the first MIS region 105, a p-type region between a pair of the first source region 117 and the first drain region 118 is a first channel region 121. A first gate electrode 111 faces this first channel region 121 with a first gate insulating film 112 interposed therebetween. The first channel region 121 is formed in a part of the first well region 114.

[0262] The semiconductor device 1 includes the above-mentioned silicide layer 319 formed on the first main surface 3 in the first MIS region 105 and the first outer region 109. In this embodiment, the silicide layer 319 is formed in surface layers of the isolation electrode 63, the first gate electrode 111, the first source region 117, the first drain region 118, and the first contact region 122. This silicide layer 319 may be formed in the same process as the silicide layer 319 in the output region 6.

[0263] The semiconductor device 1 further includes the aforementioned contact insulating layer 97 covering the first MIS region 105. This contact insulating layer 97 is formed integrally with the contact insulating layer 97 of the output region 6.

[0264] The semiconductor device 1 includes the aforementioned interlayer insulating layer 12 covering the first main surface 3 in the first MIS region 105 and the first outer region 109. The semiconductor device 1 includes one or more first drain wirings 123 formed in the interlayer insulating layer 12. The one or more first drain wirings 123 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more first drain wirings 123 are selectively routed in the interlayer insulating layer 12 and electrically connected to the first drain region 118 through a first via electrode 126.

[0265] The semiconductor device 1 includes one or more first source wirings 124 formed in the interlayer insulating layer 12. The one or more first source wirings 124 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more first source wirings 124 are selectively routed in the interlayer insulating layer 12, and are electrically connected to the separation electrode 63, the first source region 117, and the first contact region 122 through a first via electrode 126.

[0266] The semiconductor device 1 includes one or more first gate wirings 125 formed in the interlayer insulating layer 12. The one or more first gate wirings 125 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more first gate wirings 125 are selectively routed in the interlayer insulating layer 12 and electrically connected to the first gate electrode 111 through a first via electrode 126.

[0267] The first via electrodes 126 connected to the first drain wiring 123, the first source wiring 124, and the first gate wiring 125 are each formed in a square shape in a plan view.

[0268] 22, a blank region 157 where no first well region 114 exists is formed in a part of the first well region 114 in the first circuit region 101. The second well region 115 fills this blank region 157 and is exposed from the first main surface 3.

[0269] A third well region 144 is formed in a surface layer portion of the second well region 115 in the blank region 157. The third well region 144 is formed inwardly and away from the first well region 114. The bottom of the third well region 144 is formed in a region on the first main surface 3 side with respect to the central portion of the second trench isolation structure 104.

[0270] A fourth well region 145 is further formed in the surface layer of the second well region 115 in the blank region 157. The fourth well region 145 is an impurity region selectively protruding from the bottom of the third well region 144 toward the second main surface 4. The fourth well region 145 is formed away from the first well region 114 on the inside. The fourth well region 145 has an end 146 covering the side of the third well region 144. A part of the second well region 115 may be interposed between the end 146 of the fourth well region 145 and the first well region 114. The fourth well region 145 is formed in a region on the first main surface 3 side with respect to the bottom wall of the second trench isolation structure 104.

[0271] The semiconductor device 1 further includes a second element isolation structure 136 that partitions a second MIS region 135 on the first main surface 3 of the first circuit region 101. The second element isolation structure 136 may be referred to as an STI (shallow trench isolation) structure. The second MIS region 135 may be referred to as a "second active region" or a "p-side active region."

[0272] The second element isolation structure 136 is formed in a ring shape surrounding a portion of the first main surface 3 in a plan view, and defines a second MIS region 135 having a predetermined shape. In this embodiment, the second element isolation structure 136 is formed in a quadrangular ring shape having four sides parallel to the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 in a plan view, and defines the quadrangular second MIS region 135. The second element isolation structure 136 may have any planar shape, and may be formed in a polygonal ring shape. The second MIS region 135 may be defined in a polygonal shape according to the planar shape of the second element isolation structure 136.

[0273] The second element isolation structure 136 includes an isolation trench 137 and a buried insulator 138. The isolation trench 137 is formed in the first main surface 3 and defines the wall surface of the second element isolation structure 136. The buried insulator 138 is buried over the entire width direction from the bottom of the isolation trench 137 to the opening end. The isolation trench 137 is backfilled with the buried insulator 138. The buried insulator 138 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0274] Although not shown, the width of the second MIS region 135 and the width of the second element isolation structure 136 may correspond to the width WM1 and the width WM2, respectively, of Fig. 23. Therefore, the width of the element structure of the second MISFET 103 may be the same as the width WE1 of the element structure of the first MISFET 102 shown in Fig. 23 (for example, less than 1 µm).

[0275] A second outer region 139 is formed outside the second element isolation structure 136. The second outer region 139 is a region sandwiched between the second element isolation structure 136 and a second outer isolation structure 140 surrounding the second element isolation structure 136. In FIG. 22, only a portion of the second outer isolation structure 140 that forms the boundary between the first MISFET 102 and the second MISFET 103 is shown. The second outer isolation structure 140 is formed integrally with the first outer isolation structure 110 between the first outer region 109 and the second outer region 139.

[0276] In the second MIS region 135, a second gate electrode 141 is formed on the first main surface 3. The second gate electrode 141 may contain conductive polysilicon.

[0277] A second gate insulating film 142 is formed between the second gate electrode 141 and the chip 2. The second gate insulating film 142 may contain a silicon oxide film. The second gate insulating film 142 preferably contains a silicon oxide film made of the oxide of the chip 2.

[0278] A second sidewall structure 143 is formed around the second gate electrode 141. The second sidewall structure 143 is continuously formed over the entire periphery of the second gate electrode 141 so as to cover the side surface of the second gate electrode 141. The second sidewall structure 143 contains at least one of silicon oxide and silicon nitride. In this form, the second sidewall structure 143 contains silicon oxide. The second sidewall structure 143 may contain silicon nitride. That is, the second sidewall structure 143 may contain an insulator different from the second gate insulating film 142.

[0279] A pair of p-type second source regions 147 and p-type second drain regions 148 are formed in the surface layer portion of the third well region 144 with a gap therebetween. The second source region 147 and the second drain region 148 have a p-type impurity concentration exceeding the n-type impurity concentration of the third well region 144. Referring to FIG. 21, the second source region 147 and the second drain region 148 extend parallel to each other along the second direction Y. The second source region 147 and the second drain region 148 may be formed in a rectangular shape of the same size and long along the second direction Y in a plan view. Referring to FIG. 22, the second source region 147 and the second drain region 148 are formed self-aligned with respect to the second gate electrode 141.

[0280] In the second MIS region 135, an n-type region between a pair of the second source region 147 and the second drain region 148 is a second channel region 151. The second channel region 151 faces the second gate electrode 141 with a second gate insulating film 142 interposed therebetween. The second channel region 151 is formed in a part of the third well region 144.

[0281] A second contact region 152 is formed in a surface layer portion of the third well region 144 in the second outer region 139. The second contact region 152 may be referred to as a "second back gate region." The second contact region 152 has an n-type impurity concentration that exceeds an n-type impurity concentration of the third well region 144. The second contact region 152 is formed at a distance from the second trench isolation structure 104. The second contact region 152 may be in contact with the second trench isolation structure 104.

[0282] The semiconductor device 1 includes the above-mentioned silicide layer 319 formed on the first main surface 3 in the second MIS region 135 and the second outer region 139. In this embodiment, the silicide layer 319 is formed in surface layers of the isolation electrode 63, the second gate electrode 141, the second source region 147, the second drain region 148, the first contact region 122, and the second contact region 152. This silicide layer 319 may be formed in the same process as the silicide layer 319 in the output region 6.

[0283] Although not shown in the drawings, the semiconductor device 1 further includes the aforementioned contact insulating layer 97 that covers the second MIS region 135. This contact insulating layer 97 is formed integrally with the contact insulating layer 97 of the output region 6.

[0284] The semiconductor device 1 includes the aforementioned interlayer insulating layer 12 covering the first main surface 3 in the second MIS region 135 and the second outer region 139. The semiconductor device 1 includes one or more second drain wirings 153 formed in the interlayer insulating layer 12. The one or more second drain wirings 153 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more second drain wirings 153 are selectively routed in the interlayer insulating layer 12 and electrically connected to the second drain region 148 through a second via electrode 156. Referring to FIG. 21, the second drain wirings 153 and the first drain wiring 123 are common wirings, and thus the first drain region 118 and the second drain region 148 are electrically connected to each other.

[0285] The semiconductor device 1 includes one or more second source wirings 154 formed in the interlayer insulating layer 12. The one or more second source wirings 154 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more second source wirings 154 are selectively routed in the interlayer insulating layer 12 and are electrically connected to the second source region 147 and the second contact region 152 through a second via electrode 156.

[0286] Although a detailed description is omitted here, the planar size and depth of the second via electrode 156 are equivalent to those of the first via electrode 126 described above.

[0287] The semiconductor device 1 includes one or more second gate wirings 155 formed in the interlayer insulating layer 12. The one or more second gate wirings 155 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more second gate wirings 155 are selectively routed in the interlayer insulating layer 12 and electrically connected to the second gate electrode 141 through a second via electrode 156. With reference to FIG. 21, the second gate wiring 155 and the first gate wiring 125 are a common wiring, and thus the first gate electrode 111 and the second gate electrode 141 are electrically connected to each other.

[0288] Hereinafter, the configuration of the second circuit region 201 in which the amplifier circuit 34 on the control region 7 side is formed will be described with reference to Figs. 24 to 27. Fig. 24 is a plan view showing the second circuit region 201 in which the amplifier circuit 34 shown in Fig. 1 is formed. Fig. 25 is a cross-sectional view taken along line XXV-XXV shown in Fig. 24. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 24. Fig. 27 is an enlarged view of region XXVII in Fig. 25. The second circuit region 201 may be referred to as an amplifier circuit region.

[0289] 24 to 27, the semiconductor device 1 includes a second circuit region 201 defined on the first main surface 3 in the control region 7. The second circuit region 201 is a region to which a voltage (potential) different from that of the output region 6 is applied, and is a region in which a CMIS 201a constituting one circuit among a plurality of types of electronic circuits (circuit devices) is formed.

[0290] Specifically, the CMIS 201a includes a first n-type MISFET 202 (second n-type channel MIS transistor) and a second p-type MISFET 203 (second p-type channel MIS transistor) that are complementarily connected. The first MISFET 202 is driven and controlled under a voltage application condition different from that of the output transistor 20. The second MISFET 203 is driven and controlled under a voltage application condition different from that of the output transistor 20 and the first MISFET 202. Note that the first n-type MISFET 202 and the second p-type MISFET 203 may be combined complementarily as in this embodiment, or may be formed as independent elements.

[0291] The rated voltage (second rated voltage) of the first MISFET 202 and the second MISFET 203 may be, for example, higher than the rated voltage of the above-mentioned first MISFET 102 and second MISFET 103. The rated voltage of the first MISFET 202 and the second MISFET 203 may be, for example, 30 V or more and 50 V or less.

[0292] The rated voltages of the first MISFET 202 and the second MISFET 203 may be defined as a range of maximum allowable values ​​of voltages applied between the source and drain of the first MISFET 202 and the second MISFET 203. The rated voltages of the first MISFET 202 and the second MISFET 203 may also be referred to as the breakdown voltages of the first MISFET 202 and the second MISFET 203.

[0293] The specific structure within the second circuit region 201 will now be described.

[0294] 24 and 25, the semiconductor device 1 includes a third trench separation structure 205 that partitions the first MIS region 204 on the first main surface 3 of the second circuit region 201. The first MIS region 204 is a device region that is controlled under a voltage application condition different from that of the output region 6. The third trench separation structure 205 may be referred to as a deep trench isolation (DTI) structure.

[0295] The third trench isolation structure 205 is formed in a ring shape surrounding a partial region of the first main surface 3 in a plan view, and defines a first MIS region 204 having a predetermined shape. In this embodiment, the third trench isolation structure 205 is formed in a quadrangular ring shape having four sides parallel to the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 in a plan view, and defines the quadrangular first MIS region 204. The third trench isolation structure 205 may have any planar shape, and may be formed in a polygonal ring shape. The first MIS region 204 may be defined in a polygonal shape according to the planar shape of the third trench isolation structure 205.

[0296] Similar to the first trench isolation structure 60, the third trench isolation structure 205 has a first width W1 and a first depth D1 (i.e., an aspect ratio D1 / W1). It is particularly preferable that the bottom wall of the third trench isolation structure 205 is formed with a distance of 1 μm or more and 5 μm or less from the bottom of the substrate region 226. The substrate region 226 is integrally connected to the drift region 11 described above, and is formed of an n-type epitaxial layer (Si epitaxial layer).

[0297] The third trench isolation structure 205 has a separation corner 251 connecting a portion extending in the first direction X and a portion extending in the second direction Y. The separation corner 251 is a strip extending in a direction inclined with respect to the first direction X and the second direction Y. More specifically, the separation corner 251 is inclined at 45° with respect to each of the first direction X and the second direction Y. It is preferable that the separation corner 251 has a constant first width W1. Although not shown, the separation corner 251 (the four corners of the third trench isolation structure 205) may be formed in an arc shape. In other words, the first MIS region 204 may be defined by a quadrangle having four corners formed in an arc shape.

[0298] The third trench isolation structure 205 has a single electrode structure including an isolation trench 61, an isolation insulating film 62, and an isolation electrode 63, similar to the first trench isolation structure 60. The "isolation trench 61", "isolation insulating film 62", and "isolation electrode 63" of the third trench isolation structure 205 may be referred to as a "third isolation trench", a "third isolation insulating film", and a "third isolation electrode", respectively. The explanation of the isolation trench 61, isolation insulating film 62, and isolation electrode 63 of the third trench isolation structure 205 is omitted because the explanation of the isolation trench 61, isolation insulating film 62, and isolation electrode 63 of the first trench isolation structure 60 is applicable.

[0299] The semiconductor device 1 includes a p-type first well region 206 formed in a surface layer portion of the first main surface 3 in the first MIS region 204. The first well region 206 is formed in a surface layer portion of the first main surface 3 in the first MIS region 204, and is in contact with a third trench isolation structure 205. The first well region 206 is formed in a region on the first main surface 3 side with respect to the bottom wall of the third trench isolation structure 205. The bottom of the first well region 206 is formed in a region on the bottom wall side of the third trench isolation structure 205 with respect to the middle part of the third trench isolation structure 205. That is, the bottom of the first well region 206 is formed in a region on the bottom wall side of the third trench isolation structure 205 with respect to the depth position of the bottom of the body region 67.

[0300] In the first MIS region 204, a second well region 225 is formed in a surface portion of the first main surface 3. The second well region 225 is an impurity region selectively protruding from the bottom of the first well region 206 toward the second main surface 4.

[0301] The semiconductor device 1 includes an n-type third well region 207 formed in a surface layer portion of the second well region 225. The third well region 207 is formed in a surface layer portion of the second well region 225 at a distance from the third trench isolation structure 205. The third well region 207 may be formed in a strip shape extending in one direction (second direction Y) in a plan view. The third well region 207 is formed at a distance from the bottom of the second well region 225 toward the first main surface 3. The third well region 207 faces the substrate region 226 with a part of the first well region 206 sandwiched therebetween.

[0302] The semiconductor device 1 includes an n-type first drain region 208 formed in a surface layer portion of the third well region 207. The first drain region 208 has an n-type impurity concentration that exceeds the n-type impurity concentration of the third well region 207. The first drain region 208 is formed in a surface layer portion of the third well region 207 with a gap from the periphery of the third well region 207. The first drain region 208 may be formed in a strip shape extending in one direction (second direction Y) in a plan view. The first drain region 208 is formed with a gap from the bottom of the third well region 207 toward the first main surface 3. The first drain region 208 faces the second well region 225 with a part of the third well region 207 in between.

[0303] The semiconductor device 1 includes an n-type first source region 209 formed in a surface layer portion of the first well region 206 at a distance from the third well region 207. The first source region 209 has an n-type impurity concentration substantially equal to the n-type impurity concentration of the first drain region 208. The first source region 209 is formed at a distance from the third trench isolation structure 205. The first source region 209 may be formed in a strip shape extending in one direction (second direction Y) in a plan view. The first source region 209 is formed at a distance from the depth position of the bottom of the first well region 206 toward the first main surface 3.

[0304] The semiconductor device 1 includes a first channel region 210 formed in a region between the third well region 207 and the first source region 209 in surface layers of the first well region 206 and the second well region 225. The first channel region 210 forms the channel of the first MISFET 202.

[0305] The semiconductor device 1 includes a p-type first contact region 211 formed in a surface layer portion of the first well region 206. The first contact region 211 has a p-type impurity concentration that exceeds the p-type impurity concentration of the first well region 206. The first contact region 211 is formed at a distance from the third trench isolation structure 205. The first contact region 211 is formed in a band shape extending along the third trench isolation structure 205 in a plan view. The first contact region 211 is preferably formed in a ring shape surrounding the third well region 207 and the first source region 209. The first contact region 211 may be in contact with the third trench isolation structure 205.

[0306] The semiconductor device 1 includes a first field insulating film 212 that partially covers the first main surface 3 in the first MIS region 204. In this embodiment, the first field insulating film 212 includes a silicon oxide film. Specifically, the first field insulating film 212 is formed by a LOCOS (LOCal Oxidation of Silicon) method, and includes a silicon oxide film made of an oxide of the chip 2 (semiconductor chip).

[0307] The first field insulating film 212 covers the third well region 207. The first field insulating film 212 covers the region between the first drain region 208 and the first contact region 211. The first field insulating film 212 covers the region between the first source region 209 and the first contact region 211. The first field insulating film 212 covers the region between the third trench isolation structure 205 and the first contact region 211. The first field insulating film 212 is continuous with the isolation insulating film 62 exposed from the inner wall of the third trench isolation structure 205 at the periphery of the first MIS region 204.

[0308] The first field insulating film 212 includes a plurality of first openings 213 each exposing the first main surface 3. The plurality of first openings 213 include at least one first drain opening 213A, at least one first channel opening 213B, and at least one first contact opening 213C.

[0309] The first drain opening 213A exposes the first drain region 208. The number of the first drain openings 213A is arbitrary. One first drain opening 213A may be formed, or a plurality of first drain openings 213A may be formed. The first channel opening 213B exposes the first source region 209 and the first channel region 210. The first channel opening 213B may expose the third well region 207. The number of the first channel openings 213B is arbitrary. One first channel opening 213B may be formed, or a plurality of first channel openings 213B may be formed.

[0310] The first contact opening 213C exposes the first contact region 211. The number of first contact openings 213C is arbitrary. One first contact opening 213C may be formed, or multiple first contact openings 213C may be formed. In this case, it is preferable that the multiple first contact openings 213C are formed at intervals along the first contact region 211.

[0311] Each of the first openings 213 may be formed in a quadrangular shape in a plan view. That is, each of the first openings 213 may have a side extending in one direction (first direction X) in a plan view and a side extending in an intersecting direction (second direction Y) that intersects with the one direction.

[0312] The semiconductor device 1 includes a first hidden surface 214 and a first exposed surface 215 formed on the first main surface 3 in the first MIS region 204. The first hidden surface 214 is formed in a portion covered by the first field insulating film 212 on the first main surface 3. The first exposed surface 215 is formed in a portion exposed from the first field insulating film 212 on the first main surface 3. In other words, the first main surface 3 includes the first hidden surface 214 and the first exposed surface 215 partitioned by the first field insulating film 212 in the first MIS region 204. The first exposed surface 215 may be an active region 250 in the first MIS region 204.

[0313] In this form, the first hidden surface 214 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the first exposed surface 215. Specifically, the first hidden surface 214 is recessed in one step in the thickness direction of the chip 2 with respect to the first exposed surface 215 starting from the periphery of each first opening 213 of the first field insulating film 212.

[0314] Referring to FIG. 27, the width WE2 of the element structure of the first MISFET 202 including the width WM3 of the first exposed surface 215 (active region 250) and the width WM4 of the first hidden surface 214 (first field insulating film 212) may be less than 2 μm. For example, the width WM3 of the first exposed surface 215 may be 3 μm or more and 7 μm or less, and the width WM4 of the first hidden surface 214 may be 2 μm or more and 6 μm or less.

[0315] Referring to FIG. 27, the first field insulating film 212 integrally includes an embedded portion 245 embedded in the chip 2 with respect to the first main surface 3 and a protruding portion 246 protruding on the opposite side of the embedded portion 245 with respect to the first main surface 3. The embedded portion 245 and the protruding portion 246 have inclined surfaces 247 and 248 that slope upward and downward, respectively, in the vicinity of the periphery of each first opening 213. When the inclined surface 247 and the inclined surface 248 intersect at the first main surface 3, a bird's beak portion 249 is formed at the periphery of each first opening 213.

[0316] The thickness T1 of the first field insulating film 212 may be, for example, 500 Å or more and 3000 Å or less. In this embodiment, the buried portion 245 and the protruding portion 246 of the first field insulating film 212 have different thicknesses. The thickness T2 of the protruding portion 246 may be equal to or less than the thickness T3 of the buried portion 245. The thickness T2≦thickness T3 is caused, for example, by the fact that, in the manufacturing process of the semiconductor device 1, after the first field insulating film 212 is formed by the LOCOS method, the first field insulating film 212 is exposed to etching and removed. Note that, depending on the process conditions, the protruding portion 246 may not be formed.

[0317] The semiconductor device 1 includes a first main surface insulating film 216 that selectively covers the first main surface 3 in the first MIS region 204. In this embodiment, the first main surface insulating film 216 includes a silicon oxide film. The first main surface insulating film 216 covers the portions of the first main surface 3 that are exposed through the first openings 213. That is, the first main surface insulating film 216 covers at least the first drain region 208, the first source region 209, the first channel region 210, and the first contact region 211. The first main surface insulating film 216 covers the first exposed surface 215 and is continuous with the first field insulating film 212. The first main surface insulating film 216 is thinner than the first field insulating film 212.

[0318] The semiconductor device 1 includes a first gate electrode 217 facing the first channel region 210 in the first channel opening 213B with the first main surface insulating film 216 interposed therebetween. In this embodiment, the first gate electrode 217 includes conductive polysilicon. A gate potential is applied to the first gate electrode 217. The first gate electrode 217 controls the on / off of the first channel region 210. Specifically, the first gate electrode 217 faces the third well region 207, the first source region 209, and the first channel region 210 in a plan view.

[0319] The first gate electrode 217 is formed in a strip shape extending along the first channel region 210 in a plan view. The first gate electrode 217 has a first drawn-out portion 218 drawn out from above the first main surface insulating film 216 onto the first field insulating film 212 located on the first drain region 208 side. The first drawn-out portion 218 is formed at an interval from the first drain region 208 to the first source region 209 side, and faces the third well region 207 across the first field insulating film 212. The first drawn-out portion 218 may be referred to as a field plate that relieves the electric field between the source and drain.

[0320] The first field insulating film 212 (LOCOS structure) may include a breakdown voltage insulating film that supports a field plate. The field plate is not limited to the first drawn-out portion 218 of the first gate electrode 217, but may be a field plate that is electrically and physically independent from the first gate electrode 217. The field plate may be electrically floating or fixed to the source potential.

[0321] The semiconductor device 1 includes a first sidewall structure 219 covering a sidewall of the first gate electrode 217. The first sidewall structure 219 is located on the first field insulating film 212 and the first main surface insulating film 216. The first sidewall structure 219 includes at least one of silicon oxide and silicon nitride. In this embodiment, the first sidewall structure 219 includes silicon oxide. The first sidewall structure 219 may include silicon nitride. That is, the first sidewall structure 219 may include an insulator different from the first field insulating film 212 and the first main surface insulating film 216.

[0322] The semiconductor device 1 includes the above-mentioned silicide layer 319 formed on the first main surface 3 in the first MIS region 204. In this embodiment, the silicide layer 319 is formed in the surface layer portions of the isolation electrode 63, the first gate electrode 217, the first source region 209, the first drain region 208, and the first contact region 211. This silicide layer 319 may be formed in the same process as the silicide layer 319 in the output region 6.

[0323] 27, the semiconductor device 1 further includes the aforementioned contact insulating layer 97 covering the first MIS region 204. This contact insulating layer 97 is formed integrally with the contact insulating layer 97 of the output region 6.

[0324] The semiconductor device 1 includes the aforementioned interlayer insulating layer 12 covering the first main surface 3 in the first MIS region 204. The semiconductor device 1 includes one or more first drain wirings 220 formed in the interlayer insulating layer 12. The one or more first drain wirings 220 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more first drain wirings 220 are selectively routed in the interlayer insulating layer 12 and electrically connected to the first drain region 208 through a first via electrode 223.

[0325] The semiconductor device 1 includes one or more first source wirings 221 formed in the interlayer insulating layer 12. The one or more first source wirings 221 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more first source wirings 221 are selectively routed in the interlayer insulating layer 12, and are electrically connected to the separation electrode 63, the first source region 209, and the first contact region 211 through a first via electrode 223.

[0326] The semiconductor device 1 includes one or more first gate wirings 222 formed in the interlayer insulating layer 12. The one or more first gate wirings 222 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more first gate wirings 222 are selectively routed in the interlayer insulating layer 12 and electrically connected to the first gate electrode 217 through a first via electrode 223.

[0327] Each of the first via electrodes 223 is formed in a square shape in a plan view.

[0328] 24 and 26, the semiconductor device 1 has a second MIS region 224 on the first main surface 3 of the second circuit region 201.

[0329] The semiconductor device 1 includes an n-type fourth well region 227 formed in a surface layer portion of the substrate region 226 in the second MIS region 224. The fourth well region 227 may be formed in a strip shape extending in one direction (second direction Y) in a plan view.

[0330] The semiconductor device 1 includes a p-type fifth well region 228 formed in a surface layer portion of the substrate region 226 in the second MIS region 224. The fifth well region 228 is formed in the surface layer portion of the substrate region 226 with a gap therebetween from the periphery of the fourth well region 227. The fifth well region 228 may be formed in a strip shape extending in one direction (second direction Y) in a plan view.

[0331] The semiconductor device 1 includes a p-type second drain region 229 formed in a surface layer portion of the fifth well region 228. The second drain region 229 has a p-type impurity concentration that exceeds the p-type impurity concentration of the fifth well region 228. The second drain region 229 is formed in a surface layer portion of the fifth well region 228 at a distance from the periphery of the fifth well region 228. The second drain region 229 may be formed in a strip shape extending in one direction (second direction Y) in a plan view. The second drain region 229 is formed at a distance from the bottom of the fifth well region 228 toward the first main surface 3.

[0332] The semiconductor device 1 includes a p-type second source region 230 formed in a surface layer portion of the fourth well region 227 spaced apart from the fifth well region 228. The second source region 230 has a p-type impurity concentration substantially the same as the p-type impurity concentration of the second drain region 229. The second source region 230 may be formed in a strip shape extending in one direction (second direction Y) in a plan view.

[0333] The semiconductor device 1 includes a second channel region 231 formed in the substrate region 226 and the fourth well region 227 in the second MIS region 224. The second channel region 231 forms the channel of the second MISFET 203.

[0334] The semiconductor device 1 includes an n-type second contact region 232 formed in a surface layer portion of the substrate region 226 in the second MIS region 224. The second contact region 232 has an n-type impurity concentration that exceeds the n-type impurity concentration of the substrate region 226. The second contact region 232 is preferably formed in a ring shape surrounding the fourth well region 227 and the fifth well region 228.

[0335] The semiconductor device 1 includes a second field insulating film 233 that partially covers the first main surface 3 in the second MIS region 224. In this embodiment, the second field insulating film 233 includes a silicon oxide film. Specifically, the second field insulating film 233 includes a silicon oxide film made of an oxide of the chip 2 (semiconductor chip).

[0336] The second field insulating film 233 covers the fourth well region 227 and the fifth well region 228. The second field insulating film 233 covers the region between the second drain region 229 and the second contact region 232. The second field insulating film 233 covers the region between the second source region 230 and the second contact region 232.

[0337] The second field insulating film 233 includes a plurality of second openings 234 each exposing the first main surface 3. The plurality of second openings 234 include at least one second drain opening 234A, at least one second channel opening 234B, and at least one second contact opening 234C.

[0338] The second drain opening 234A exposes the second drain region 229. The number of the second drain openings 234A is arbitrary. One second drain opening 234A may be formed, or a plurality of second drain openings 234A may be formed. The second channel opening 234B exposes the second source region 230 and the second channel region 231. The number of the second channel openings 234B is arbitrary. One second channel opening 234B may be formed, or a plurality of second channel openings 234B may be formed.

[0339] The second contact opening 234C exposes the second contact region 232. The number of second contact openings 234C is arbitrary. One second contact opening 234C may be formed, or multiple second contact openings 234C may be formed. In this case, it is preferable that the multiple second contact openings 234C are formed at intervals along the second contact region 232.

[0340] The second openings 234 may each be formed in a quadrangular shape in plan view. That is, the second openings 234 may each have a side extending in one direction (first direction X) in plan view and a side extending in an intersecting direction (second direction Y) that intersects with the first direction.

[0341] The semiconductor device 1 includes a second hidden surface 235 and a second exposed surface 236 formed on the first main surface 3 in the second MIS region 224. The second hidden surface 235 is formed in a portion of the first main surface 3 covered by the second field insulating film 233. The second exposed surface 236 is formed in a portion of the first main surface 3 exposed from the second field insulating film 233. In other words, the first main surface 3 includes the second hidden surface 235 and the second exposed surface 236 partitioned by the second field insulating film 233 in the second MIS region 224.

[0342] In this embodiment, the second hidden surface 235 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the second exposed surface 236. Specifically, the second hidden surface 235 is recessed by one step with respect to the second exposed surface 236 in the thickness direction of the chip 2, starting from the periphery of each second opening 234 of the second field insulating film 233.

[0343] Although not shown, the width of second exposed surface 236 and the width of second hidden surface 235 may be the same as width WM3 and width WM4 shown in Fig. 27, respectively. Therefore, the width of the element structure of second MISFET 203 may be the same as width WE2 of the element structure of first MISFET 202 shown in Fig. 27 (for example, less than 2 µm). Similarly to first field insulating film 212 in Fig. 27, second field insulating film 233 has buried portion 245 and protruding portion 246, and their thicknesses T2 and T3 may also be the same.

[0344] The semiconductor device 1 includes a second main surface insulating film 237 that selectively covers the first main surface 3 in the second MIS region 224. In this embodiment, the second main surface insulating film 237 includes a silicon oxide film. The second main surface insulating film 237 covers the region of the first main surface 3 other than the second field insulating film 233. The second main surface insulating film 237 covers the second exposed surface 236 and is continuous with the second field insulating film 233. The second main surface insulating film 237 is thinner than the second field insulating film 233.

[0345] The semiconductor device 1 includes a second gate electrode 238 (main surface electrode) facing the second channel region 231 in the second channel opening 234B with the second main surface insulating film 237 interposed therebetween. In this embodiment, the second gate electrode 238 includes conductive polysilicon. A gate potential is applied to the second gate electrode 238. The second gate electrode 238 controls the on / off of the second channel region 231. Specifically, the second gate electrode 238 faces the fourth well region 227, the fifth well region 228, the second source region 230, and the second channel region 231 in a plan view.

[0346] The second gate electrode 238 is formed in a strip shape extending along the second channel region 231 in a plan view. The second gate electrode 238 has a second lead-out portion 239 led out from above the second main surface insulating film 237 onto the second field insulating film 233 located on the second drain region 229 side. The second lead-out portion 239 is formed at an interval from the second drain region 229 to the second source region 230 side, and faces the fifth well region 228 across the second field insulating film 233. The second lead-out portion 239 may be referred to as a field plate that relieves the electric field between the source and drain.

[0347] The second field insulating film 233 (LOCOS structure) may include a breakdown voltage insulating film that supports a field plate. The field plate is not limited to the second drawn-out portion 239 of the second gate electrode 238, and may be a field plate that is electrically and physically independent from the second gate electrode 238. The field plate may be electrically floating or fixed to the source potential.

[0348] The semiconductor device 1 includes a second sidewall structure 240 covering the sidewall of the second gate electrode 238. The second sidewall structure 240 is located on the second field insulating film 233 and the second main surface insulating film 237. The second sidewall structure 240 includes at least one of silicon oxide and silicon nitride. In this embodiment, the second sidewall structure 240 includes silicon oxide. The second sidewall structure 240 may include silicon nitride. That is, the second sidewall structure 240 may include an insulator different from the second field insulating film 233 and the second main surface insulating film 237.

[0349] The semiconductor device 1 includes the above-mentioned silicide layer 319 formed on the first main surface 3 in the second MIS region 224. In this embodiment, the silicide layer 319 is formed in surface layers of the second gate electrode 238, the second source region 230, the second drain region 229, and the second contact region 232. This silicide layer 319 may be formed in the same process as the silicide layer 319 in the output region 6.

[0350] Although not shown in the drawings, the semiconductor device 1 further includes the above-mentioned contact insulating layer 97 that covers the second MIS region 224. This contact insulating layer 97 is formed integrally with the contact insulating layer 97 of the output region 6.

[0351] The semiconductor device 1 includes the aforementioned interlayer insulating layer 12 covering the first main surface 3 in the second MIS region 224. The semiconductor device 1 includes one or more second drain wirings 241 formed in the interlayer insulating layer 12. The one or more second drain wirings 241 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more second drain wirings 241 are selectively routed in the interlayer insulating layer 12 and electrically connected to the second drain region 229 through a second via electrode 244.

[0352] The semiconductor device 1 includes one or more second source wirings 242 formed in the interlayer insulating layer 12. The one or more second source wirings 242 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more second source wirings 242 are selectively routed in the interlayer insulating layer 12, and are electrically connected to the separation electrode 63, the second source region 230, and the second contact region 232 through the second via electrode 244.

[0353] The semiconductor device 1 includes one or more second gate wirings 243 formed in the interlayer insulating layer 12. The one or more second gate wirings 243 are made of a wiring layer formed in the interlayer insulating layer 12. The one or more second gate wirings 243 are selectively routed in the interlayer insulating layer 12 and electrically connected to the second gate electrode 238 through a second via electrode 244.

[0354] Although the description is omitted here, the planar size and depth of the second via electrode 244 are equivalent to those of the first via electrode 223 described above.

[0355] [Effects of Semiconductor Device 1] In the semiconductor device 1, the output region 6 is surrounded by the first trench isolation structure 60. The isolation insulating film 62 of the first trench isolation structure 60 is separated from the insulating layer in the surface of the output region 6 and is formed as a physically independent insulating film. In such a case, if the isolation insulating film 62 expands or contracts due to thermal expansion or the like and the stress balance around the first trench isolation structure 60 is lost, crystal defects may occur in the chip 2. In particular, crystal defects are likely to occur near the first trench isolation structure 60 (in this embodiment, the isolation-side mesa portion 83).

[0356] This type of crystal defect can be suppressed by the field insulating layer 95 that is integrally extended from the isolation insulating film 62 to the peripheral portion of the first trench isolation structure 60. On the other hand, in order to enhance the suppression effect, it is preferable to maintain the length of the field insulating layer 95 extending from the first trench isolation structure 60 long and to maintain the thickness large.

[0357] 10, the field insulating layer 95 includes an edge insulating layer 8 and an extending insulating layer 9. The extending insulating layer 9 selectively extends from the edge insulating layer 8 toward the opposite side of the first trench isolation structure 60 along the horizontal direction. As a result, even if a space capable of forming a field insulating layer 95 of sufficient length cannot be secured around the entire periphery of the first trench isolation structure 60, the extending insulating layer 9 is selectively formed, thereby making it possible to suppress the stress balance around the first trench isolation structure 60 from being disrupted.

[0358] For example, in this embodiment, the extending insulating layer 9 is formed in the region of the separation-side mesa portion 83 excluding the main surface contact region 305. As a result, in the separation-side mesa portion 83, a plurality of extending insulating layers 9 and a plurality of main surface contact regions 305 are alternately arranged in the longitudinal direction of the first trench isolation structure 60. This makes it possible to effectively utilize the space on the upper surface 56 of the separation-side mesa portion 83. As a result, even with the separation-side mesa portion 83 having a relatively narrow width, it is possible to both suppress the occurrence of crystal defects and ensure a contact space for the separation-side mesa portion 83.

[0359] In this embodiment, when forming the silicide layer 319, it is necessary to selectively etch away the protective insulating layer 99 (silicide block film), and at that time, a part of the field insulating layer 95 (edge ​​insulating layer 8) is covered and protected by the mask 100. This allows a part of the edge insulating layer 8 to remain as the high step portion 301 without being thinned. This makes it possible to suppress the stress balance around the first trench isolation structure 60 from being destroyed by the presence of the extended insulating layer 9 and the maintenance of the thickness of the edge insulating layer 8 by the high step portion 301. As a result, it is possible to suppress the occurrence of crystal defects in the chip 2.

[0360] As described above, it is possible to suppress the overall thinning of the edge insulating layer 8 caused by removing the protective insulating layer 99, and to suppress the occurrence of crystal defects, so that the silicide layer 319 can be formed without impairing reliability even if the width of the separation-side mesa portion 83 is relatively narrow. This makes it possible to realize low resistance by the silicide layer 319 while maintaining high reliability.

[0361] [Other examples of the field insulating layer 95] Hereinafter, with reference to Figures 28 to 31, several other examples of the field insulating layer 95 will be shown. The several examples shown in Figures 28 to 31 may be applied independently to the above-mentioned embodiment. Of course, an example in which at least two of the several examples shown in Figures 28 to 31 are combined may be applied to the above-mentioned embodiment. The structures shown in Figures 28 to 31 can be obtained by appropriately adjusting the process conditions (for example, the pattern of the mask 100) in the above-mentioned manufacturing process. (1) Second form example 28 is a perspective view showing a second embodiment of the field insulating layer 95. In the second embodiment, the edge insulating layer 8 does not include the high step portion 301 and the low step portion 302, and has a constant thickness in the longitudinal direction of the first trench isolation structure 60. The extension insulating layer 9 integrally includes a base portion 323 continuously connected to the edge insulating layer 8 along the longitudinal direction of the first trench isolation structure 60, and an extension portion 324 intermittently extending from the base portion 323 along the horizontal direction.

[0362] In other words, the extended insulation layer 9 of the field insulation layer 95 may include a strip-shaped base portion 323 formed along the first trench isolation structure 60, and a plurality of extension portions 324 extending in a comb-tooth shape from the base portion 323 toward the trench gate structure 70.

[0363] Although the cross-sectional structure is not shown, in the second embodiment, the edge insulating layer 8 is also formed by a laminated structure of a base insulating layer 317 and a covering insulating layer 318, and the extending insulating layer 9 and the cap insulating layer 308 are each formed by an extension of the covering insulating layer 318 that selectively extends in opposite directions from the end of the base insulating layer 317 (see Figure 14).

[0364] In the field insulating layer 95 of the second embodiment, the base portion 323 is formed in the extended insulating layer 9, so that the coverage area of ​​the field insulating layer 95 on the upper surface 56 of the separation-side mesa portion 83 can be increased. This improves the adhesion of the field insulating layer 95 to the chip 2, so that the stress concentration on the separation-side mesa portion 83 can be further alleviated and the occurrence of crystal defects can be effectively suppressed. (2) Third form example 29 is a perspective view showing a third embodiment of the field insulating layer 95. In the third embodiment, the field insulating layer 95 further includes a bridge insulating layer 325. The bridge insulating layer 325 is formed across the tip portions 303 of the extending insulating layers 9 adjacent to each other in the length direction of the first trench isolation structure 60, and connects the adjacent tip portions 303 to each other. The bridge insulating layer 325 is formed in a strip shape along the length direction of the first trench isolation structure 60, and covers the aforementioned main surface connection region 306. As a result, the main surface opening 307 is defined by being entirely surrounded by the field insulating layer 95.

[0365] Although the cross-sectional structure is not shown, in the third embodiment as well, the edge insulating layer 8 is formed of a laminated structure of the base insulating layer 317 and the covering insulating layer 318, and the extending insulating layer 9 and the cap insulating layer 308 are each formed of an extension of the covering insulating layer 318 that selectively extends in opposite directions from the end of the base insulating layer 317 (see FIG. 14). Also, the extending insulating layer 9 may be the extending insulating layer 9 having the base portion 323 and the extending portion 324 of the second embodiment.

[0366] In the field insulating layer 95 of the third embodiment, the bridge insulating layer 325 that connects the extending insulating layers 9 is formed, so that the coverage area of ​​the field insulating layer 95 on the upper surface 56 of the separation-side mesa portion 83 can be increased. This improves the adhesion of the field insulating layer 95 to the chip 2, so that the stress concentration on the separation-side mesa portion 83 can be further alleviated and the occurrence of crystal defects can be effectively suppressed. (3) Fourth form example 30 is a perspective view showing a fourth embodiment of the field insulating layer 95. In the fourth embodiment, in the layout of the second embodiment, the isolation contact regions 310 do not face the main surface contact regions 305, but are arranged at positions shifted in the length direction of the first trench isolation structure 60. As a result, the first active contacts 39 and the first isolation contacts 38 are arranged at positions shifted from each other in the length direction of the first trench isolation structure 60. In this embodiment, the first active contacts 39 and the first isolation contacts 38 are arranged alternately along the length direction of the first trench isolation structure 60. (4) Fifth form example 31 is a perspective view showing a fifth embodiment of the field insulating layer 95. In the fifth embodiment, in the layout of the third embodiment, the isolation contact regions 310 do not face the main surface contact regions 305, but are arranged at positions shifted from each other in the length direction of the first trench isolation structure 60. As a result, the first active contacts 39 and the first isolation contacts 38 are arranged at positions shifted from each other in the length direction of the first trench isolation structure 60. In this embodiment, the first active contacts 39 and the first isolation contacts 38 are alternately arranged along the length direction of the first trench isolation structure 60.

[0367] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0368] For example, in the above embodiment, two systems of output transistors 20 are shown. However, three or more systems of output transistors 20 may be adopted. In this case, a plurality of block regions 81 for system transistors constituting the three or more systems are provided, and at the same time, three or more systems of first gate wirings 18 and second gate wirings 96 corresponding to the block regions 81 are provided.

[0369] In the above embodiment, a configuration has been shown that includes the current monitor circuit 25. The current monitor circuit 25 may be formed using at least one unit transistor 22 out of the plurality of unit transistors 22.

[0370] In the above embodiment, an example has been shown in which the upper electrode 73 and the lower electrode 74 have the same potential. However, a source potential may be applied to the lower electrode 74. In this case, the first source wiring 19 is electrically connected to the connection electrode 93.

[0371] In the above-described embodiment, a multi-electrode structure is adopted as the trench gate structure 70, but for example, a single electrode structure similar to the first trench isolation structure 60 may be adopted.

[0372] In the above embodiment, an example has been shown in which the source terminal 13 is an output terminal and the drain terminal 15 is a power supply terminal. However, a configuration in which the source terminal 13 is a ground terminal and the drain terminal 15 is an output terminal may be adopted. In this case, the semiconductor device 1 becomes a low-side switching device electrically connected between a load (inductive load L) and ground.

[0373] In the above embodiment, an example is shown in which the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region in the above description and the attached drawings.

[0374] The embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include modifications in all respects.

[0375] The following characteristics can be extracted from the description of this specification and the drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "semiconductor switching device," "semiconductor control device," "semiconductor module," "electronic circuit," "semiconductor circuit," "intelligent power device," "intelligent power module," "intelligent power switch," etc., as necessary.

[0376] [Appendix 1-1] A chip (2) having a main surface (3); a trench isolation structure (60) including an isolation trench (61) formed in the main surface (3) of the chip (2), an isolation insulating film (62) formed in the isolation trench (61), and an isolation electrode (63) embedded in the isolation trench (61) via the isolation insulating film (62), and defining a partition region (6) in the main surface (3); a field insulating layer (95) formed integrally with the isolation insulating film (62) and extending horizontally from the isolation trench (61) along the main surface (3); the field insulation layer (95) includes an edge insulation layer (8) that is integral with the isolation insulation film (62) along an edge of the trench isolation structure (60), and a plurality of extending insulation layers (9) that selectively extend from the edge insulation layer (8) toward an opposite side of the trench isolation structure (60) along the horizontal direction, are arranged at intervals in the length direction along the edge of the trench isolation structure (60), and have tip portions (303) separated from each other, in the semiconductor device (1).

[0377] [Appendix 1-2] The extension insulating layer (9) is formed thinner than the edge insulating layer (8), The semiconductor device (1) according to appendix 1-1, wherein a step (S) is formed between an upper surface (58) of the extended insulating layer (9) and an upper surface (59) of the edge insulating layer (8).

[0378] [Appendix 1-3] The semiconductor device (1) described in Appendix 1-2, wherein a lower surface (314) of the extended insulating layer (9) and a lower surface (315) of the edge insulating layer (8) form an integral flat surface (316) in contact with the main surface (3) of the chip (2).

[0379] [Appendix 1-4] The semiconductor device (1) according to any one of Appendices 1-1 to 1-3, wherein the edge insulating layer (8) has a step structure including a plurality of high step portions (301) that are continuous with the plurality of extending insulating layers (9) in the horizontal direction and have a relatively high height, and a low step portion (302) that is formed between the plurality of high step portions (301) adjacent to each other in the length direction of the trench isolation structure (60) and has a height relatively lower than the high step portions (301).

[0380] [Appendix 1-5] The semiconductor device (1) described in Appendix 1-4, wherein the high step portion (301) of the edge insulating layer (8) and the extended insulating layer (9) are formed in a band shape extending in a direction intersecting the longitudinal direction of the trench isolation structure (60) in a plan view.

[0381] [Appendix 1-6] the edge insulating layer (8) has a constant thickness along the length of the trench isolation structure (60); The semiconductor device (1) according to any one of Appendices 1-1 to 1-3, wherein the extending insulating layer (9) integrally includes a base portion (323) continuously connected to the edge insulating layer (8) along the length direction of the trench isolation structure (60), and an extending portion (324) intermittently extending from the base portion (323) along the horizontal direction.

[0382] [Appendix 1-7] the edge insulating layer (8) includes a base insulating layer (317) integrally drawn out from the isolation insulating film (62) to the main surface (3) of the chip (2), and a covering insulating layer (318) covering the base insulating layer (317); The semiconductor device (1) according to any one of Appendices 1-1 to 1-6, wherein the extending insulating layer (9) is formed by an extension of the covering insulating layer (318) that selectively extends from an end of the base insulating layer (317).

[0383] [Appendix 1-8] The semiconductor device (1) according to any one of Appendices 1-1 to 1-7, comprising a silicide layer (319) formed in an area of ​​the main surface (3) of the chip (2) exposed from the field insulating layer (95).

[0384] [Appendix 1-9] The semiconductor device (1) according to any one of Appendices 1-1 to 1-8, further comprising a cap insulating layer (308) selectively extending from the edge insulating layer (8) toward the trench isolation structure (60) along the horizontal direction and covering an upper surface (57) of the isolation electrode (63).

[0385] [Appendix 1-10] The semiconductor device (1) according to any one of claims 1 to 9, wherein the extending insulating layer (9) and the cap insulating layer (308) are formed to the same thickness.

[0386] [Appendix 1-11] a main surface contact region (305) formed in a region sandwiched between the plurality of extending insulating layers (9) adjacent in the length direction of the trench isolation structure (60) on the main surface (3) of the chip (2); The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-8, further comprising a main surface contact (39) connected to the main surface contact region (305).

[0387] [Appendix 1-12] an interlayer insulating layer (12) laminated on the main surface (3) of the chip (2) and having the main surface contacts (39) embedded therein; A semiconductor device (1) as described in Appendix 1-11, comprising a contact insulating layer (97) formed between the interlayer insulating layer (12) and the main surface (3) of the chip (2) so as to cover the field insulating layer (95) and the main surface contact region (305), the contact insulating layer (97) being made of an insulating material different from that of the interlayer insulating layer (12).

[0388] [Appendix 1-13] a plurality of cap insulating layers (308) selectively extending from the edge insulating layer (8) toward the trench isolation structure (60) along the horizontal direction and covering the upper surface (57) of the isolation electrode (63); an isolation contact region (310) formed on the top surface (57) of the isolation electrode (63) in a region sandwiched between the plurality of cap insulating layers (308) adjacent in the length direction of the trench isolation structure (60); and an isolation contact (38) connected to the isolation contact region (310).

[0389] [Appendix 1-14] The semiconductor device (1) described in Appendix 1-13, wherein at least one of the main surface contacts (39) and at least one of the isolation contacts (38) are aligned in a direction perpendicular to the length direction of the trench isolation structure (60).

[0390] [Appendix 1-15] The semiconductor device (1) described in appendix 1-13, wherein the plurality of main surface contacts (39) and the plurality of isolation contacts (38) are arranged alternately along the length direction of the trench isolation structure (60).

[0391] [Appendix 1-16] a trench isolation structure (70) formed in the partition region (6) and extending alongside the trench isolation structure (60); an isolation mesa portion (83) formed between the trench insulation structure (70) and the trench isolation structure (60); The semiconductor device (1) according to any one of Appendices 1-1 to 1-15, wherein the extending insulating layer (9) extends from the edge insulating layer (8) toward the trench insulating structure (70) and covers an upper surface (56) of the isolation-side mesa portion (83).

[0392] [Appendix 1-17] The semiconductor device (1) described in Appendix 1-16, wherein the extending insulating layer (9) has the tip portion (303) at a position spaced from the trench insulating structure (70) toward the trench isolation structure (60).

[0393] [Appendix 1-18] The semiconductor device (1) according to claim 1-16 or 1-17, wherein the width (I2) of the separation-side mesa portion (83) is not less than 0.4 μm and not more than 3.2 μm.

[0394] [Appendix 1-19] the partition region (6) is an active region (6) including an insulated gate transistor, The semiconductor device (1) according to any one of Supplementary Notes 1-16 to 1-18, wherein the trench insulating structure (70) is formed by a trench gate structure (70) constituting the insulated gate transistor.

[0395] [Appendix 1-20] The semiconductor device (1) according to any one of Appendices 1-1 to 1-19, wherein the edge insulating layer (8) is formed thinner than the isolation insulating film (62) at least in a position not adjacent to the extended insulating layer (9) in the length direction of the trench isolation structure (60).

[0396] [Appendix 2-1] A chip (2) having a main surface (3); a trench isolation structure (60) including an isolation trench (61) formed in the main surface (3) of the chip (2), an isolation insulating film (62) formed in the isolation trench (61), and an isolation electrode (63) embedded in the isolation trench (61) via the isolation insulating film (62), and defining a partition region (6) in the main surface (3); a field insulating layer (95) formed integrally with the isolation insulating film (62) and extending horizontally from the isolation trench (61) along the main surface (3); the field insulating layer (95) includes an edge insulating layer (8) that is integral with the isolation insulating film (62) along an edge of the trench isolation structure (60), and a plurality of extending insulating layers (9) that selectively extend from the edge insulating layer (8) toward an opposite side of the trench isolation structure (60) along the horizontal direction and are arranged at intervals in the length direction along the edge of the trench isolation structure (60); the edge insulating layer (8) includes a base insulating layer (317) integrally drawn out from the isolation insulating film (62) to the main surface (3) of the chip (2), and a covering insulating layer (318) covering the base insulating layer (317); The semiconductor device (1), wherein the extending insulating layer (9) is formed by an extension of the covering insulating layer (318) selectively extending from an end of the base insulating layer (317).

[0397] [Appendix 2-2] The plurality of extending insulating layers (9) are separated from each other at their tip portions (303), The semiconductor device (1) described in Appendix 2-1, wherein the edge insulating layer (8) has a step structure including a plurality of high step portions (301) that are continuous with the plurality of extending insulating layers (9) in the horizontal direction and have a relatively high height, and a low step portion (302) that is formed between the plurality of high step portions (301) adjacent to each other in the length direction of the trench isolation structure (60) and has a height relatively lower than the high step portions (301).

[0398] [Appendix 2-3] the edge insulating layer (8) has a constant thickness along the length of the trench isolation structure (60); The semiconductor device (1) described in Appendix 2-1, wherein the extending insulating layer (9) is an insulating layer whose tip portions (303) are separated from each other, and integrally includes a base portion (323) continuously connected to the edge insulating layer (8) along the length direction of the trench isolation structure (60), and an extending portion (324) intermittently extending from the base portion (323) along the horizontal direction.

[0399] [Appendix 2-4] The semiconductor device (1) described in Appendix 2-1, wherein the field insulation layer (95) is formed across the tip portions (303) of the multiple extended insulation layers (9) adjacent to each other in the longitudinal direction of the trench isolation structure (60), and further includes a bridge insulation layer (325) connecting the adjacent tip portions (303).

[0400] [Appendix 2-5] The semiconductor device (1) according to any one of Appendices 2-1 to 2-4, comprising a silicide layer (319) formed in an area of ​​the main surface (3) of the chip (2) exposed from the field insulating layer (95).

[0401] [Appendix 2-6] The semiconductor device (1) according to any one of Appendices 2-1 to 2-5, further comprising a cap insulating layer (308) selectively extending along the horizontal direction from the edge insulating layer (8) toward the trench isolation structure (60) and covering an upper surface (57) of the isolation electrode (63).

[0402] [Appendix 2-7] The semiconductor device (1) according to claim 2-6, wherein the extending insulating layer (9) and the cap insulating layer (308) are formed to the same thickness.

[0403] [Appendix 2-8] a main surface contact region (305) formed in a region sandwiched between the plurality of extending insulating layers (9) adjacent in the length direction of the trench isolation structure (60) on the main surface (3) of the chip (2); The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-5, further comprising a main surface contact (39) connected to the main surface contact region (305).

[0404] [Appendix 2-9] an interlayer insulating layer (12) laminated on the main surface (3) of the chip (2) and having the main surface contacts (39) embedded therein; A semiconductor device (1) as described in Appendix 2-8, comprising a contact insulating layer (97) formed between the interlayer insulating layer (12) and the main surface (3) of the chip (2) so as to cover the field insulating layer (95) and the main surface contact region (305), the contact insulating layer (97) being made of an insulating material different from that of the interlayer insulating layer (12).

[0405] [Appendix 2-10] a plurality of cap insulating layers (308) selectively extending from the edge insulating layer (8) toward the trench isolation structure (60) along the horizontal direction and covering the upper surface (57) of the isolation electrode (63); an isolation contact region (310) formed on the top surface of the isolation electrode (63) in a region sandwiched between the plurality of cap insulating layers (308) adjacent in the length direction of the trench isolation structure (60); and an isolation contact (38) connected to the isolation contact region (310).

[0406] [Appendix 2-11] A semiconductor device (1) as described in appendix 2-10, wherein at least one of the main surface contacts (39) and at least one of the isolation contacts (38) are aligned in a direction perpendicular to the length direction of the trench isolation structure (60).

[0407] [Appendix 2-12] The semiconductor device (1) described in appendix 2-10, wherein the plurality of main surface contacts (39) and the plurality of isolation contacts (38) are arranged alternately along the length direction of the trench isolation structure (60).

[0408] [Appendix 2-13] a trench isolation structure (70) formed in the partition region (6) and extending alongside the trench isolation structure (60); an isolation mesa portion (83) formed between the trench insulation structure (70) and the trench isolation structure (60); The semiconductor device (1) according to any one of Appendices 2-1 to 2-12, wherein the extending insulating layer (9) extends from the edge insulating layer (8) toward the trench insulating structure (70) and covers an upper surface (56) of the isolation-side mesa portion (83).

[0409] [Appendix 2-14] The semiconductor device (1) described in Appendix 2-13, wherein the extending insulating layer (9) has the tip portion (303) at a position spaced from the trench insulating structure (70) toward the trench isolation structure (60).

[0410] [Appendix 2-15] The semiconductor device (1) according to Appendix 2-13 or Appendix 2-14, wherein the separation-side mesa portion (83) has a width of 0.4 μm or more and 3.2 μm or less.

[0411] [Appendix 2-16] the partition region (6) is an active region (6) including an insulated gate transistor, The semiconductor device (1) according to any one of Supplementary Note 2-13 to Supplementary Note 2-15, wherein the trench insulating structure (70) is formed by a trench gate structure (70) constituting the insulated gate transistor.

[0412] [Appendix 2-17] The semiconductor device (1) according to any one of Appendices 2-1 to 2-16, wherein the edge insulating layer (8) is formed thinner than the isolation insulating film (62) at least in a position not adjacent to the extended insulating layer (9) in the length direction of the trench isolation structure (60). [Explanation of symbols]

[0413] 1: Semiconductor device 2: Tip 3: First main surface 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: Output area 7: Control area 8: Edge insulation layer 9: Extension insulation layer 10: Drain region 11: Drift region 12: Interlayer insulation layer 13: Source terminal 14: Control terminal 14a: Ground terminal 14b: Input terminal 15: Drain terminal 16: 1st wiring layer 17: 2nd wiring layer 18: First gate wiring 18A: 1 gate wiring 18B: 1 gate wiring 18C: Wiring 19: First source wiring 20: Output transistor 21: System transistor 21A: First system transistor 21B: Second system transistor 22: Unit transistor 23: Control circuit 24: Gate control circuit 25: Current monitor circuit 26: Overcurrent protection circuit 27: Overheat protection circuit 28: Low voltage malfunction prevention circuit 29: Load open detection circuit 30: Active clamp circuit 31: Power supply reverse connection protection circuit 32: Logic circuit 33: Test circuit 34: Amplification circuit 35: Recessed space 36: First via electrode 37: Second via electrode 38: First separation contact 39: First active contact 40: First element contact 41: First upper gate contact 42: First lower gate contact 43: Second Source Contact 44: Second gate contact 45: Wafer 46: Base insulation layer 47: Base electrode layer 48: Mask 49:Aperture 50: Base electrode layer 51: Contact hole 52: Base plug electrode layer 53: Channel insulating film 54: Edge insulating film 55:Top surface 56:Top surface 57:Top surface 58:Top surface 59:Top surface 60: First trench isolation structure 61: Isolation trench 62: Isolation insulating film 63: Separation electrode 64: High concentration drift region 65 :bulge 66: Recess 67: Body region 68: Separation corner 69:Top surface 70: Trench gate structure 71: Gate trench 72: Insulating film 73: Upper electrode 74: Lower electrode 75: Intermediate insulating film 76: Upper insulating film 77: Lower insulating film 78: Channel cell 79: Source area 80: Contact area 81: Block area 81A: First block area 81B: Second block area 82: Mesa part on element side 83: Separation side mesa 84: First insulating layer 85: Second insulating layer 86: Third insulating layer 87: Lower layer 88: Upper layer 89:Top surface 90: Trench connection structure 91: Connection trench 92: Connection insulating film 93: Connection electrode 94: Main surface insulating film 95: Field insulation layer 96: Second gate wiring 96A: 2-way gate wiring 96B: 2-way gate wiring 96C: Wiring 96D: First gate connection wiring 97: Contact insulating layer 98: Second source wiring 99: Protective insulation layer 100: Mask 101: 1st circuit area 104: Second trench isolation structure 105: 1st MIS area 106:First element isolation structure 107: Isolation trench 108: Buried insulation 109: 1st outer area 110: 1st outer separation structure 111: First gate electrode 112: First gate insulating film 113: First sidewall structure 114: First well region 115: Second well region 116: End 117: First source area 118: First drain region 121: First channel region 122: First contact region 123: First drain wiring 124: First source wiring 125: First gate wiring 126: First via electrode 127: Separation corner 135: 2nd MIS area 136:Second element isolation structure 137: Isolation trench 138: Buried insulation 139:Second outer area 140:Second outer separation structure 141: Second gate electrode 142: Second gate insulating film 143: Second sidewall structure 144: Third well region 145: 4th well region 146: End 147: Second source area 148: Second drain region 151: Second channel region 152: Second contact area 153: Second drain wiring 154: Second source wiring 155: Second gate wiring 156: Second via electrode 157 :Blank area 158: Board area 201: 2nd circuit area 204: 1st MIS area 205: Third trench isolation structure 206: First well region 207: Third well region 208: First drain region 209: First source area 210: First channel region 211: First contact region 212: First field insulating film 213: First opening 213A: First drain opening 213B: First channel opening 213C: First contact opening 214: First concealed surface 215: 1st exposed surface 216: First main surface insulating film 217: First gate electrode 218: First drawer 219: First sidewall structure 220: First drain wiring 221: First source wiring 222: First gate wiring 223: First via electrode 224: 2nd MIS area 225: Second well region 226: Board area 227: 4th well region 228: 5th well region 229: Second drain region 230: Second source area 231: Second channel region 232: Second contact region 233: Second field insulating film 234: Second opening 234A: Second drain opening 234B: Second channel opening 234C: Second contact opening 235: Second concealed surface 236: 2nd exposed surface 237: Second main surface insulating film 238: Second gate electrode 239: Second drawer 240: Second sidewall structure 241: Second drain wiring 242: Second source wiring 243: Second gate wiring 244: Second via electrode 245: Buried section 246:Protrusion 247: Inclined surface 248: Inclined surface 249: Birdsbeak Club 250 : Active area 251: Separation corner 301: High level 302: Low section 303:Tip 304: Proximal end 305: Main surface contact area 306: Main surface connection area 307: Main surface opening 308: Cap insulating layer 309: Strip-shaped insulating layer 310: Isolation contact area 311: Separation opening 312: Edge contact area 313: Connection opening 314: Bottom surface 315: Bottom surface 316 :Flat surface 317: Base insulation layer 318: Insulating coating 319: Silicide layer 320 :Aperture 321: Belt 322: Metal layer 323: Base part 324: Extension part 325: Bridge insulation layer

Claims

1. a chip having a major surface; a trench isolation structure including an isolation trench formed on the main surface of the chip, an isolation insulating film formed in the isolation trench, and an isolation electrode embedded in the isolation trench via the isolation insulating film, the trench isolation structure defining a partition region on the main surface; a field insulating layer formed integrally with the isolation insulating film and extended from the isolation trench in a horizontal direction along the main surface, the field insulation layer includes an edge insulation layer that is integral with the isolation insulation film along an edge of the trench isolation structure, and a plurality of extending insulation layers that selectively extend from the edge insulation layer toward an opposite side of the trench isolation structure along the horizontal direction, are arranged at intervals in the length direction along the edge of the trench isolation structure, and have mutually separated tip portions.

2. The extension insulating layer is formed thinner than the edge insulating layer, The semiconductor device according to claim 1 , wherein a step is formed between an upper surface of said extending insulating layer and an upper surface of said edge insulating layer.

3. 3. The semiconductor device according to claim 2, wherein a lower surface of said extending insulating layer and a lower surface of said edge insulating layer form an integral flat surface in contact with said main surface of said chip.

4. 2. The semiconductor device according to claim 1, wherein the edge insulating layer has a step structure including a plurality of relatively high step portions that are continuous with the plurality of extending insulating layers in the horizontal direction, and a low step portion that is formed between the plurality of adjacent high step portions in the longitudinal direction of the trench isolation structure and is relatively lower in height than the high step portions.

5. 5. The semiconductor device according to claim 4, wherein the higher step portion of the edge insulating layer and the extended insulating layer are formed in a band shape extending in a direction intersecting the length direction of the trench isolation structure in a plan view.

6. the edge insulating layer has a constant thickness along the length of the trench isolation structure; 2. The semiconductor device according to claim 1, wherein the extending insulating layer integrally includes a base portion continuously connected to the edge insulating layer along the length direction of the trench isolation structure, and an extending portion intermittently extending from the base portion along the horizontal direction.

7. the edge insulating layer includes a base insulating layer integrally drawn out from the isolation insulating film to the main surface of the chip, and a covering insulating layer covering the base insulating layer; 7. The semiconductor device according to claim 1, wherein the extending insulating layer is formed by an extension of the covering insulating layer selectively extending from an end of the base insulating layer.

8. 7. The semiconductor device according to claim 1, further comprising a silicide layer formed in an area of ​​said main surface of said chip that is exposed from said field insulating layer.

9. 7. The semiconductor device according to claim 1, further comprising a cap insulating layer selectively extending from said edge insulating layer toward said trench isolation structure side along said horizontal direction and covering an upper surface of said isolation electrode.

10. The semiconductor device according to claim 9 , wherein the extending insulating layer and the cap insulating layer are formed to the same thickness.

11. a main surface contact region formed in a region sandwiched between the plurality of extending insulating layers adjacent to each other in the longitudinal direction of the trench isolation structure on the main surface of the chip; 7. The semiconductor device according to claim 1, further comprising a main surface contact connected to said main surface contact region.

12. an interlayer insulating layer laminated on the main surface of the chip and having the main surface contacts embedded therein; 12. The semiconductor device according to claim 11, further comprising: a contact insulating layer formed between the interlayer insulating layer and the main surface of the chip so as to cover the field insulating layer and the main surface contact region, the contact insulating layer being made of an insulating material different from that of the interlayer insulating layer.

13. a plurality of cap insulating layers selectively extending from the edge insulating layer toward the trench isolation structure along the horizontal direction and covering an upper surface of the isolation electrode; an isolation contact region formed in the upper surface of the isolation electrode in a region sandwiched between the plurality of cap insulating layers adjacent in the longitudinal direction of the trench isolation structure; 12. The semiconductor device of claim 11, further comprising an isolation contact connected to the isolation contact region.

14. 14. The semiconductor device of claim 13, wherein at least one of the main surface contacts and at least one of the isolation contacts are aligned in a direction perpendicular to the length of the trench isolation structure.

15. 14. The semiconductor device of claim 13, wherein the plurality of main surface contacts and the plurality of isolation contacts are arranged alternately along the length direction of the trench isolation structure.

16. a trench isolation structure formed in the partition region and extending alongside the trench isolation structure; an isolation-side mesa portion formed between the trench insulation structure and the trench isolation structure, 7. The semiconductor device according to claim 1, wherein the extending insulating layer extends from the edge insulating layer toward the trench insulating structure and covers an upper surface of the isolation-side mesa portion.

17. 17. The semiconductor device according to claim 16, wherein the extending insulating layer has the tip portion at a position spaced from the trench insulating structure toward the trench isolation structure.

18. 17. The semiconductor device according to claim 16, wherein the width of the isolation-side mesa portion is not less than 0.4 [mu]m and not more than 3.2 [mu]m.

19. the partitioned region is an active region including an insulated gate transistor, 17. The semiconductor device according to claim 16, wherein said trench insulating structure is formed by a trench gate structure constituting said insulated gate type transistor.

20. The semiconductor device according to any one of claims 1 to 3, wherein the edge insulating layer is formed thinner than the isolation insulating film at least at a position not adjacent to the extended insulating layer in the longitudinal direction of the trench isolation structure.

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