Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing current concentration in a source ring part and inhibiting the growth of stacking defects.SOLUTION: A semiconductor device comprises an active region 40 through which a main current flows, a termination region 42 surrounding the active region 40, and an intermediate region 41 located between the active region 40 and the termination region 42, on a semiconductor substrate 1 of a first conductivity type. On the front surface side of the semiconductor substrate 1 in the active region 40, a front surface electrode 12 that is connected to a first semiconductor region 8 of a second conductivity type is provided. In the intermediate region 41, a source ring 25 that is electrically connected to the front surface electrode 12 and connected to a second semiconductor region 6 of the second conductivity type for extracting hole current is provided. The contact between the front surface electrode 12 in the active region 40 and the first semiconductor region 8 is the ohmic contact, and the contact between the source ring 25 in the intermediate region 41 and the second semiconductor region 6 is the Schottky junction.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, in order to extract the hole current around the active region, a semiconductor device is known in which a source ring portion connected to the source potential is provided in a p-type region between the active region and an inactive region such as a breakdown voltage structure (see, for example, Patent Document 1 below).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device, when the parasitic diode of a MOSFET is used as a reflux diode, current concentrates in the source ring portion and the hole density increases, so there is a problem that the on-voltage is likely to increase due to the growth of a stacking defect starting from directly below the source ring portion. An object of this disclosure is to provide a semiconductor device capable of suppressing current concentration in the source ring portion and suppressing the growth of stacking defects.

Means for Solving the Problems

[0005] In order to solve the above-described problems and achieve the object of the present disclosure, a semiconductor device according to this disclosure has the following features. The semiconductor device includes an active region through which a main current flows, a termination region surrounding the periphery of the active region, and an intermediate region between the active region and the termination region, on a semiconductor substrate of a first conductivity type. On the front surface side of the semiconductor substrate of the active region, it has a front surface electrode connected to a first semiconductor region of a second conductivity type, and a source ring that is electrically connected to the front surface electrode in the intermediate region and is connected to a second semiconductor region of the second conductivity type for extracting a hole current. The contact between the front surface electrode of the active region and the first semiconductor region is an ohmic contact, and the contact between the source ring in the intermediate region and the second semiconductor region is a Schottky junction.

[0006] According to the above-described disclosure, by making the contact between the source ring and the p-type base layer (the second semiconductor region of the second conductivity type) a Schottky junction, it is possible to sufficiently extract holes from the p-type base layer in the source ring when a dV / dt is applied, and to prevent holes from being injected from the source ring when the parasitic diode of the MOSFET is forward-biased. For this reason, it is possible to suppress current concentration in the source ring while ensuring the dV / dt tolerance and suppress the growth of stacking defects.

Effects of the Invention

[0007] According to the semiconductor device of the present disclosure, there is an effect that current concentration in the source ring portion can be suppressed and the growth of stacking defects can be suppressed.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] <Summary of Embodiments of the Present Disclosure> In order to solve the above-described problems and achieve the object of the present disclosure, a semiconductor device according to this disclosure has the following features. The semiconductor device includes an active region through which a main current flows, a termination region surrounding the periphery of the active region, and an intermediate region between the active region and the termination region, on a semiconductor substrate of a first conductivity type. On the front surface side of the semiconductor substrate of the active region, it has a front surface electrode connected to a first semiconductor region of a second conductivity type, and has a source ring that is electrically connected to the front surface electrode in the intermediate region and is connected to a second semiconductor region of the second conductivity type for extracting a hole current. The contact between the front surface electrode of the active region and the first semiconductor region is an ohmic contact, and the contact between the source ring in the intermediate region and the second semiconductor region is a Schottky junction.

[0010] According to the above-described disclosure, by making the contact between the source ring and the p-type base layer a Schottky junction, it is possible to sufficiently extract holes from the p-type base layer in the source ring when a dV / dt is applied, and to prevent holes from being injected from the source ring when the parasitic diode of the MOSFET is forward-biased. For this reason, it is possible to suppress current concentration in the source ring while ensuring the dV / dt tolerance and suppress the growth of stacking defects.

[0011] Also, in the semiconductor device according to the present disclosure, in the above-described disclosure, the contact between the source ring in the intermediate region and the second semiconductor region is a heterojunction formed by a semiconductor having a large band offset on the valence band side with respect to the second semiconductor region.

[0012] In addition, in the semiconductor device according to the present disclosure, in the above-described disclosure, the semiconductor having a large band offset on the valence band side with respect to the second semiconductor region is silicon.

[0013] In order to solve the above-described problems and achieve the object of the present disclosure, a semiconductor device according to this disclosure has the following features. The semiconductor device includes an active region through which a main current flows, a terminal region surrounding the active region, and an intermediate region between the active region and the terminal region, on a semiconductor substrate of a first conductivity type. On the front surface side of the semiconductor substrate of the active region, it has a front surface electrode connected to a first semiconductor region of a second conductivity type, and has a source ring that is electrically connected to the front surface electrode in the intermediate region and is connected to a second semiconductor region of the second conductivity type for extracting a hole current. A diode is provided between the front surface electrode and the source ring, which allows the current flowing from the source ring to the front surface electrode and blocks the current flowing in the opposite direction.

[0014] According to the above-described disclosure, at the time of dV / dt application, it is possible to extract holes from the p-type base layer in the source ring, and in a state where the parasitic diode of the MOSFET is forward-biased, it is possible to reduce the injection of holes from the source ring by the diode. For this reason, it is possible to suppress the current concentration in the source ring while ensuring the dV / dt tolerance and suppress the growth of stacking defects.

[0015] In addition, in the semiconductor device according to the present disclosure, in the above-described disclosure, the diode is formed by a polysilicon layer formed on the semiconductor substrate via an insulating layer.

[0016] In addition, in the semiconductor device according to the present disclosure, in the above-described disclosure, instead of the diode, a resistor is provided between the front surface electrode and the source ring.

[0017] Further, in the semiconductor device according to the present disclosure, in the above-described disclosure, the resistor is formed by a polysilicon layer formed on the semiconductor substrate with an insulating layer therebetween.

[0018] In order to solve the above-described problems and achieve the object of the present disclosure, a semiconductor device according to this disclosure has the following features. The semiconductor device includes an active region through which a main current flows, a terminal region surrounding the active region, and an intermediate region between the active region and the terminal region, on a semiconductor substrate of a first conductivity type. On a front surface side of the semiconductor substrate of the active region, it has a front surface electrode connected to a first semiconductor region of a second conductivity type, and has a source ring connected to the front surface electrode electrically and connected to a second semiconductor region of the second conductivity type for extracting a hole current, in the intermediate region. A contact resistance between the source ring and the second semiconductor region is larger than a contact resistance between the front surface electrode of the active region and the first semiconductor region.

[0019] According to the above-described disclosure, at the time of dV / dt application, it is possible to extract holes from the p-type base layer in the source ring, and it is possible to reduce the injection of holes from the source ring in a state where the parasitic diode of the MOSFET is forward-biased. For this reason, it is possible to suppress current concentration in the source ring while ensuring a dV / dt tolerance and suppress the growth of stacking defects.

[0020] Further, in the semiconductor device according to the present disclosure, in the above-described disclosure, an average area of a region where the source ring and the second semiconductor region make an ohmic contact is smaller than an average area of a region where the front surface electrode of the active region and the first semiconductor region make an ohmic contact.

[0021] Further, in the semiconductor device according to the present disclosure, in the above-described disclosure, the first semiconductor region of the active region has a higher impurity concentration than the second semiconductor region of the intermediate region.

[0022] In addition, in the semiconductor device according to the present disclosure, in the above-described disclosure, the first semiconductor region of the active region is characterized in that it is separated from the second semiconductor region connected to the source ring of the intermediate region.

[0023] <Knowledge underlying the present disclosure> First, the problems of conventional semiconductor devices will be described. From the perspective of power semiconductor devices, semiconductor materials to replace silicon have been studied, and silicon carbide (SiC) has attracted attention as a semiconductor material capable of fabricating (manufacturing) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics.

[0024] In SiC, since the energy level of p-type impurities is deep, the resistance of the p-type region is high especially at low temperatures such as -40 °C or -55 °C. For this reason, when dV / dt is applied to the element, the lateral voltage drop due to the hole current flowing in the p-type region is large, a large voltage is applied between the p-type region and the electrode provided thereon via the insulating film, and the insulating film is damaged. This phenomenon is likely to occur around the active region where current concentrates from non-active regions such as the breakdown voltage structure portion. To solve this problem, conventionally, a source ring portion for extracting the hole current in the peripheral portion of the active region and flowing it to the source electrode has been provided.

[0025] FIG. 29 is a cross-sectional view showing the structure of the source ring portion of a conventional silicon carbide semiconductor device. The left side of the paper surface of FIG. 29 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side. In a conventional silicon carbide semiconductor device, an n + -type silicon carbide substrate 101 has an n - -type drift layer 102, a first p + -type region 104a, a second p + -type region 104b, a p-type base layer 106, and a p ++ -type contact region 108 deposited thereon. An initial oxide film 117 and an interlayer insulating film 111 are provided on the front surface of the p ++ -type contact region 108, a source ring 125 is embedded in the openings of the initial oxide film 117 and the interlayer insulating film 111, and the silicide layer 134 of the source ring 125 is p ++It is in ohmic contact with the p-type contact region 108. The source ring 125 is electrically connected to a source electrode (not shown). With this configuration, it becomes possible to extract the hole current in the peripheral portion of the active region to the source ring 125 and flow it through the source electrode.

[0026] Figure 30 is a band diagram of the source ring of a conventional silicon carbide semiconductor device. In Figure 30, the p ++ type contact region 108 shows the band gap. In Figure 30, the dashed line indicates the Fermi level (energy level), and the symbol with a + surrounded by a circle indicates a hole. The same applies to other band diagrams other than Figure 30. The p ++ type contact region 108 has the energy level of the valence band being approximately equal to the energy level of the ohmic electrode (silicide layer 134). Therefore, holes can be extracted from the p ++ type contact region 108 to the ohmic electrode. Conversely, hole injection from the p ++ type contact region 108 to the n - type drift layer 102 also occurs.

[0027] Therefore, when using the parasitic diode as a reflux diode for the silicon carbide semiconductor device provided with the source ring 125, current concentrates in the source ring 125 and the hole density increases. Thus, there is a problem that an increase in the on-voltage is likely to occur due to the growth of a stacking defect starting from directly below the source ring 125.

[0028] Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the semiconductor device according to the present disclosure that solves the problems of the above-described conventional semiconductor device will be described in detail. In this specification and the accompanying drawings, in the layers and regions with n or p prefixed, it means that electrons or holes are the majority carriers, respectively. Also, the + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers and regions to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. And the description of the same or equivalent should include within 5% in consideration of variations in manufacturing.

[0029] (Embodiment 1) The semiconductor device according to the present disclosure is configured using a wide bandgap semiconductor. In Embodiment 1, a silicon carbide semiconductor device manufactured (produced) using, for example, silicon carbide (SiC) as the wide bandgap semiconductor will be described by taking the trench-type MOSFET 50 as an example. FIG. 1 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. FIG. 2 is a cross-sectional view taken along the line X-X' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to Embodiment 1. FIG. 3 is a cross-sectional view taken along the line Y-Y' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to Embodiment 1.

[0030] As shown in FIGS. 1 to 3, the trench-type MOSFET 50 according to Embodiment 1 includes an active region 40 where current flows when the element structure is formed and is in an on state, a termination structure region 42 that surrounds the periphery of the active region 40 and holds the breakdown voltage, and an intermediate region 41 between the active region 40 and the termination structure region 42. Further, the trench-type MOSFET 50 is an n + -type silicon carbide substrate 1 on the first main surface (front surface), for example, the (0001) surface (Si surface), an n - -type drift layer 2 is deposited.

[0031] n + -type silicon carbide substrate 1 is a single-crystal silicon carbide substrate. The n - -type drift layer 2 has an impurity concentration lower than that of the n + -type silicon carbide substrate 1 and is, for example, a low-concentration n-type drift layer. On the surface of the n - -type drift layer 2 opposite to the n + -type silicon carbide substrate 1 side, an n-type high-concentration region (not shown) may be provided. The n-type high-concentration region is a high-concentration n-type layer having an impurity concentration lower than that of the n + -type silicon carbide substrate 1 and higher than that of the n - -type drift layer 2.

[0032] n - -type drift layer 2 (when the n-type high-concentration region is provided, the n-type high-concentration region), the n +On the surface side opposite to one side of the silicon carbide substrate 1, a p-type base layer (a second semiconductor region of the second conductivity type) 6 is provided. Hereinafter, n + type silicon carbide substrate 1 and n - type drift layer 2 and p-type base layer 6 are combined to form a silicon carbide semiconductor substrate. Inside the p-type base layer 6, n ++ type source region 7 and p ++ type contact region (a first semiconductor region of the second conductivity type) 8 are selectively provided respectively.

[0033] n + On the second main surface (the back surface, that is, the back surface of the silicon carbide semiconductor substrate) of the n-type silicon carbide substrate 1, a drain electrode serving as a back surface electrode 13 is provided.

[0034] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the trench 16 penetrates the p-type base layer 6 from the surface on the side opposite to the n + type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate) and reaches the n - type drift layer 2. Also, the trench 16 is provided in a stripe shape. Along the inner wall of the trench 16, a gate insulating film 9 is formed on the bottom and side walls of the trench 16, and a gate electrode 10 is formed on the front surface of the gate insulating film 9 in the trench 16. The gate insulating film 9 insulates the gate electrode 10 from the n - type drift layer 2 and p-type base layer 6. A part of the gate electrode 10 may protrude toward the source electrode 12 from above the trench 16 (the side where the source electrode 12 described later is provided).

[0035] n - On the side of the n-type drift layer 2 opposite to the n + type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate), a second p + type base region 4 is selectively provided. The second p + type base region 4 includes at least the n - type drift layer 2 of the n +It is provided in the surface layer on the side opposite to one side of the silicon carbide substrate. Second p + The second p-type base region 4 is separated from the trench 16 and reaches a position deeper on the drain side than the bottom of the trench 16. Second p + The p-type region 4 has a first p + The first p-type base region 3 with the same thickness as the first p + type region 4a, and a second p + type region 4b provided on the surface of the first p + type region 4a.

[0036] A first p + type base region 3 is provided at a position facing the bottom of the trench 16 in the depth direction. First p + The width of the first p-type base region 3 is the same as or wider than the width of the trench 16. The bottom of the trench 16 may reach the first p + type base region 3, or may be located in the n + type drift layer 2 sandwiched between the p-type base layer 6 and the first p - type base region 3. First p + The first p-type base region 3 and the second p + type base region 4 are, for example, doped with aluminum (Al).

[0037] First p + By extending a part of the first p-type base region 3 toward the trench side, a structure connected to the second p + type base region 4 is formed. Second p + A part of the first p + type region 4a on the drain side of the bottom of the trench 16 in the second p-type base region 4 is extended and connected to the first p + type base region 3. Also, a part of the second p + type region 4b on the source side of the bottom of the trench 16 in the second p-type base region 4 may be extended. FIGS. 2 and 3 illustrate a portion where the first p + type base region 3 and the second p + type base region 4 are arranged separately. The p-type base layer 6 is a second p + in the portions of the active region 40 and the intermediate region 41, the second p + type region 4b and n -It is provided so as to cover the type drift layer 2.

[0038] The interlayer insulating film 11 is provided so as to cover the gate electrode 10 embedded in the trench 16 on the entire front surface side of the silicon carbide substrate. The source electrode (front surface electrode) 12 is n ++ type source region 7 and p ++ type contact region 8 and is in ohmic contact. The source electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad 26 is provided on the source electrode 12.

[0039] In the active regions 40 of FIGS. 2 and 3, three trench MOS structures are illustrated, but more trench MOS (insulated gate composed of metal-oxide-semiconductor) structures may be arranged in parallel.

[0040] Also, in the intermediate region 41, a gate ring 24 for connecting the gate electrode 10 to the gate electrode pad 27 is formed in a substantially rectangular shape surrounding the active region 40. In the intermediate region 41, p ++ type contact region 8 and is insulated, an initial oxide film 17 functioning as a field oxide film is provided on the p ++ type contact region 8. A gate insulating film 9 is provided on the initial oxide film 17, and a polysilicon 18 connected to the gate electrode 10 is provided on the gate insulating film 9. The gate ring 24 is connected to the polysilicon 18 at an opening provided in the interlayer insulating film 11.

[0041] Also, in the intermediate region 41, a source ring 25 for extracting charges is formed in a substantially rectangular shape surrounding the gate ring 24. The source ring 25 is connected to the source electrode pad 26 at the source ring connection portion 28. There may be a plurality of source ring connection portions 28. The source ring 25 is p ++It is connected to the type - contact region 8. Thus, the source ring 25 can draw out the current generated in the intermediate region 41 to the source electrode 10.

[0042] Also, the terminal structure region 42 is not provided with the p - type base layer 6 and the n - type high - concentration region, and the n - type drift layer 2 is exposed, and a breakdown - voltage structure such as a guard - ring structure 21 or a JTE (Junction Termination Extension) structure is provided on the n - type drift layer 2.

[0043] The guard - ring structure 21 is arranged in a substantially rectangular planar shape surrounding the periphery of the active region 40 and the intermediate region 41 with a plurality of dispersed p - type regions whose impurity concentration decreases as it goes from the inner side (the intermediate - region 41 side) to the outer side (the end - side of the n + type silicon carbide substrate 1). Also, instead of changing the impurity concentration, it may be arranged such that the interval between p - type regions is widened from the inner side to the outer side, or the width of the p - type region is narrowed. In the case of the JTE structure, a plurality of connected p - type regions whose impurity concentration decreases as it goes from the inner side (the intermediate - region 41 side) to the outer side (the end - side of the n + type silicon carbide substrate 1) are arranged in a substantially rectangular planar shape surrounding the periphery of the active region 40 and the intermediate region 41. An n ++ type region 23 serving as a channel stopper is arranged outside these breakdown - voltage structures. On the surfaces of the breakdown - voltage structure and the n ++ type region 23, an inter - layer insulating film 11, a gate insulating film 9, and an initial oxide film 17 are provided, and a protective film (not shown) made of polyimide or the like is provided on the outermost surface of the trench - type MOSFET 50.

[0044] Here, the boundary between the active region 40 and the intermediate region 41 is the bottom of the step between the inter - layer insulating film 11 and the gate insulating film 9 provided on the p ++ type contact region 8, and the boundary between the intermediate region 41 and the terminal structure region 42 is the bottom of the step of the initial oxide film 17.

[0045] FIG. 4 is a cross-sectional view showing a first structure of a source ring of a silicon carbide semiconductor device according to Embodiment 1. The configuration of the p-type region may vary depending on the design. In Embodiment 1, the p-type region is the first p + type region 4a, the second p + type region 4b, the p-type base layer 6, and the p ++ type contact region 8. In Embodiments 2 to 4 described below, the p-type region also has this structure. The structure below the n - type drift layer 2 is not described. The left side of the paper surface of FIG. 4 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side. As shown in FIG. 4, in the first structure of the source ring of Embodiment 1, the source ring 25 makes a Schottky contact with the p-type base layer 6 through the Schottky electrode 30. This enables the extraction of holes from the p-type base layer 6 and can prevent the injection of holes from the p-type base layer 6 into the n - type drift layer 2.

[0046] Here, FIG. 5 is a band diagram at the time of forward bias (drain is at a positive voltage) in the first structure of the source ring of the silicon carbide semiconductor device according to Embodiment 1. In FIG. 5, the bandgap of the p-type base layer 6 is shown. The hole state density × Fermi distribution function in the valence band of the p-type base layer 6 is shown. At the time of forward bias (drain is at a positive voltage), the Fermi level of the Schottky electrode 30 is higher than the Fermi level of the p-type base layer 6, the bending of the band becomes smaller, and the potential barrier for holes becomes smaller, so holes can be extracted from the p-type base layer 6 to the Schottky electrode 30.

[0047] Also, FIG. 6 is a band diagram at thermal equilibrium (drain is 0 V) in the first structure of the source ring of the silicon carbide semiconductor device according to Embodiment 1. At thermal equilibrium (drain is 0 V), the Fermi level of the Schottky electrode 30 becomes the same as the Fermi level of the p-type base layer 6.

[0048] FIG. 7 is a band diagram at the time of reverse bias (drain is at a negative voltage) in the first structure of the source ring of the silicon carbide semiconductor device according to Embodiment 1. At the time of reverse bias (drain is at a negative voltage), the Fermi level of the Schottky electrode 30 becomes lower than the Fermi level of the p-type base layer 6. However, the energy difference from the energy level where the Schottky electrode is not clogged with electrons (which can be regarded as having holes) to the charged electron band of the p-type base layer 6 is large, and holes are not injected from the Schottky electrode 30.

[0049] FIG. 8 is a cross-sectional view showing the second structure of the source ring of the silicon carbide semiconductor device according to Embodiment 1. The configuration of the p-type region may vary depending on the design. Here, the same configuration as in FIG. 4 is shown. The left side of the paper surface of FIG. 8 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side. In the second structure of the source ring of Embodiment 1, the source ring 25 is heterojunctioned with the p-type base layer 6 by a silicon layer 31 such as polysilicon. In this way, by forming a heterojunction with a semiconductor (for example, Si) having a large band offset on the valence band side with respect to the SiC of the p-type region, it is possible to extract holes from the p-type base layer 6 and prevent hole injection from the p-type base layer 6.

[0050] FIG. 9 is a band diagram at the time of forward bias (drain is at a positive voltage) in the second structure (n + type) of the source ring of the silicon carbide semiconductor device according to Embodiment 1. As shown in FIG. 9, at the time of forward bias (drain is at a positive voltage), the Fermi level of the silicon layer 31 is higher than the Fermi level of the p-type base layer 6, the bending of the band becomes smaller, and the potential barrier for holes becomes smaller, so holes can be extracted from the p-type base layer 6 to the silicon layer 31. Here, the silicon layer 31 is n + type, but it may also be polysilicon without added impurities.

[0051] FIG. 10 is the second structure (n +It is a band diagram at thermal equilibrium (drain is 0 V) in the (type). As shown in FIG. 10, at thermal equilibrium (drain is 0 V), the Fermi level of the silicon layer 31 becomes the same as the Fermi level of the p-type base layer 6.

[0052] FIG. 11 is a band diagram at reverse bias (drain is negative voltage) in the second structure (n + type) of the source ring of the silicon carbide semiconductor device according to Embodiment 1. As shown in FIG. 11, at reverse bias (drain is negative voltage), the Fermi level of the silicon layer 31 becomes lower than the Fermi level of the p-type base layer 6, but n + The energy difference from the energy level where the silicon conduction band is not filled with electrons (which can be regarded as having holes) to the charged electron band of the p-type base layer 6 is large, and holes are not injected from the silicon layer 31 to the p-type base layer 6.

[0053] FIG. 12 is a band diagram at forward bias (drain is positive voltage) in the second structure (p + type) of the source ring of the silicon carbide semiconductor device according to Embodiment 1. As shown in FIG. 12, at forward bias (drain is positive voltage), the Fermi level of the silicon layer 31 is higher than the Fermi level of the p-type base layer 6, the bend of the band becomes smaller, and the potential barrier for holes becomes smaller, so holes can be extracted from the p-type base layer 6 to the silicon layer 31. Here, the silicon layer 31 may be polysilicon of p + type without impurities added.

[0054] FIG. 13 is a band diagram at thermal equilibrium (drain is 0 V) in the second structure (p + type) of the source ring of the silicon carbide semiconductor device according to Embodiment 1. As shown in FIG. 13, at thermal equilibrium (drain is 0 V), the Fermi level of the silicon layer 31 becomes the same as the Fermi level of the p-type base layer 6.

[0055] FIG. 14 is a band diagram at thermal equilibrium (drain is 0 V) in the second structure (p +It is a band diagram during reverse bias (drain is at negative voltage) in the (type). As shown in FIG. 14, during reverse bias (drain is at negative voltage), the Fermi level of the silicon layer 31 becomes lower than the Fermi level of the p-type base layer 6, but p + The energy difference from the energy level where holes exist at the upper end of the silicon valence band to the electron band of the p-type base layer 6 is large, and p + Holes are not injected from the silicon layer 31 into the p-type base layer 6. Note that n + type, since the energy difference is larger than that of the p + type, the first structure (n + type) is more preferable than the second structure (p + type).

[0056] Thus, by making the contact between the source ring 25 and the p-type base layer 6 a Schottky junction or a heterojunction, it becomes possible to sufficiently extract holes from the p-type base layer 6 in the source ring 25 when dV / dt is applied, and to prevent holes from being injected from the source ring 25 when the parasitic diode of the MOSFET 50 is forward-biased. For this reason, while ensuring the dV / dt tolerance, current concentration in the source ring 25 can be suppressed and the growth of stacking defects can be suppressed.

[0057] (Manufacturing method of the silicon carbide semiconductor device according to Embodiment 1) The manufacturing method of the silicon carbide semiconductor device according to Embodiment 1 can be created by the following method. Here, the case of manufacturing a MOSFET with a breakdown voltage class of 1200V will be described as an example. First, for example, an n 19 / cm 3 -type silicon carbide single crystal doped with an n-type impurity (dopant) such as nitrogen (N) so as to have an impurity concentration of + is prepared. The front surface of the n + -type silicon carbide substrate 1 may be, for example, a (0001) surface having an off-angle of about 4 degrees in the <11-20> direction. Next, on the front surface of the n + -type silicon carbide substrate 1, for example, 1.0×10 16 / cm 3An n-type drift layer 2 doped with an n-type impurity such as nitrogen is doped so as to have an impurity concentration of n - is epitaxially grown, for example, to a thickness of 10 μm.

[0058] Next, an n-type high-concentration region may be selectively formed on the surface layer of the n-type drift layer 2 by photolithography and ion implantation. In this ion implantation, for example, an n-type impurity (dopant) such as nitrogen may be implanted so as to have a concentration of 1×10 - / cm 17 / cm 3 .

[0059] Next, a first p - -type base region 3 and a first p + -type region 4a are selectively formed inside the n-type drift layer 2. Next, a second p + -type region 4b is selectively formed on the surface layer of the n-type drift layer 2. In this ion implantation, for example, a p-type impurity (dopant) such as aluminum (Al) is used for the first p - -type base region 3, the first p + -type region 4a, and the second p + -type base region 3, the first p + -type region 4a and the second p + -type region 4b are implanted so that the impurity concentration becomes 5.0×10 18 / cm 3 .

[0060] Next, a p-type base layer 6 doped with a p-type impurity such as aluminum is epitaxially grown on the surface of the n-type drift layer 2, for example, to a thickness of 1.3 μm so as to have an impurity concentration of 2.0×10 - / cm 17 / cm 3 .

[0061] In the steps up to this point, on the front surface of the n-type silicon carbide substrate 1, an n + -type -A silicon carbide substrate is fabricated by sequentially laminating an n-type drift layer 2 and a p-type base layer 6. Next, a process including forming an ion implantation mask by photolithography and etching, ion implantation using this ion implantation mask, and removing the ion implantation mask is repeated under different ion implantation conditions, so that n ++ -type source regions 7 and p ++ -type contact regions 8 are formed in the surface layer of the p-type base layer 6.

[0062] Next, in the termination structure region 42, a guard ring structure 21 is selectively formed by photolithography and ion implantation. Next, in the termination structure region 42, an n ++ -type region 23 is selectively formed by photolithography and ion implantation.

[0063] Next, a heat treatment (annealing) is performed to activate, for example, the p + -type base region 3, the n ++ -type source region 7, the p ++ -type contact region 8, the guard ring structure 21, and the n ++ -type region 23. The temperature of the heat treatment may be, for example, about 1700 °C. The time of the heat treatment may be, for example, about 2 minutes. Note that, as described above, each ion implantation region may be activated collectively by one heat treatment, or each ion implantation may be followed by a heat treatment for activation.

[0064] Next, an oxide film is formed on the surface of the p-type base layer 6 (that is, the surfaces of the n ++ -type source region 7 and the p ++ -type contact region 8). The oxide film may be, for example, a thermal oxide film or a deposited film. The thickness of the oxide film in the active region 40 is formed thinner than the thick portion of the oxide film formed on the outer peripheral side of the termination structure region 42.

[0065] Next, a resist mask (not shown) having a predetermined opening is formed on the surface of the oxide film by photolithography technology. Next, using the resist mask as a mask, an opening is formed in the oxide film by dry etching. Next, the resist mask is removed, and using the oxide film as a mask, an anisotropic dry etching is performed to form a trench 16 that penetrates the n ++ -type source region 7 and the p-type base layer 6 and reaches the n - -type drift layer 2. The bottom of the trench 16 reaches the first p + -type base region 3.

[0066] Next, isotropic etching and sacrificial oxidation are performed with the oxide film attached. By this process, the damage of the trench 16 is removed and the bottom of the trench 16 is rounded. The order of performing isotropic etching and sacrificial oxidation may be either one first. Also, only one of isotropic etching and sacrificial oxidation may be performed. Then, the oxide film in the thin portion used as a mask for forming the trench 16 is removed. At this time, the oxide film in the thin portion and the sacrificial oxide film may be removed simultaneously. Since the oxide film has a thin portion and a thick portion in the termination structure region 42, a blanket etching for removing the thin portion of the oxide film is performed to leave the oxide film in the thick portion of the termination structure region 42. The sacrificial oxide film (not shown) may be removed together with the thin portion of the oxide film. Also, by removing the oxide film by photolithography technology and etching technology, the oxide film may be left in the termination structure region 42. The oxide film remaining in the termination structure region 42 (the thick portion of the oxide film) becomes the initial oxide film 17.

[0067] Next, a gate insulating film 9 is formed along the surfaces of the initial oxide film 17, the n ++ -type source region 7 and the p ++ -type contact region 8, and the bottom and side walls of the trench 16. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000°C in an oxygen atmosphere. Also, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as High Temperature Oxide (HTO).

[0068] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms (P) is formed on the gate insulating film 9. This polycrystalline silicon layer is formed so as to fill the trench 16. By patterning this polycrystalline silicon layer and leaving it inside the trench 16, the gate electrode 10 is formed. A part of the gate electrode 10 may protrude toward the source electrode 12 above the trench 16.

[0069] Next, an interlayer insulating film 11 is formed by depositing, for example, phosphosilicate glass (PSG) to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10. By patterning and selectively removing the interlayer insulating film 11 and the gate insulating film 9, a contact hole is formed, and the n ++ -type source region 7 and the p ++ -type contact region 8 are exposed. Then, a heat treatment (reflow) is performed to planarize the interlayer insulating film 11.

[0070] Next, a conductive film to be the source electrode 12 is formed in the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed so that, for example, only the source electrode 12 remains in the contact hole. In the intermediate region 41, a conductive film to be the Schottky electrode 30 or the silicon layer 31 is formed in the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed so that, for example, only the Schottky electrode 30 or the silicon layer 31 remains in the contact hole. The source electrode 12 is formed to be in ohmic contact with the p ++ -type contact region 8 and the p-type base layer 6, the Schottky electrode 30 is formed to be in Schottky contact with the p-type base layer 6, and the silicon layer 31 is formed to be in heterojunction with the p-type base layer 6.

[0071] Next, for example, by a sputtering method, an aluminum film is provided so as to cover the source electrode 12 and the interlayer insulating film 11, for example, to a thickness of about 5 μm. Thereafter, the aluminum film is selectively removed and left so as to cover the active region 40 and the intermediate region 41 of the entire element, thereby forming the gate ring 24, the source ring 25, the source electrode pad 26, and the gate electrode pad 27. After this, polyimide is applied as a surface passivation film, for example, by spin coating, patterned using photolithography technology, and heat-treated (cured) to form a protective film (not shown).

[0072] Next, on the back surface of the silicon carbide substrate (the back surface of the n + -type silicon carbide substrate 1), a back surface electrode 13 made of, for example, a nickel (Ni) film is formed. Thereafter, heat treatment is performed, for example, at a temperature of about 970° C. to ohmically bond the n + -type silicon carbide substrate 1 and the back surface electrode 13.

[0073] The back surface electrode 13 may be, for example, a laminated film in which titanium (Ti), nickel (Ni), and gold (Au) are laminated in sequence or a laminated film of nickel (Ni), titanium (Ti), molybdenum (Mo), and gold (Au). As described above, the semiconductor device shown in FIGS. 1 to 3 is completed.

[0074] Thus, according to Embodiment 1, by making the contact between the source ring and the p-type base layer a Schottky junction or a heterojunction, it is possible to sufficiently extract holes from the p-type base layer in the source ring when dV / dt is applied, and to prevent holes from being injected from the source ring when the parasitic diode of the MOSFET is forward biased. For this reason, while ensuring the dV / dt tolerance, it is possible to suppress current concentration in the source ring and suppress the growth of stacking defects.

[0075] (Embodiment 2) Next, Embodiment 2 will be described. FIG. 15 is a top view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. As shown in FIG. 15, in Embodiment 2, a diode or a resistor is provided between the source ring 25 and the source electrode 12.

[0076] FIG. 16 is a cross-sectional view taken along the line Y-Y' of FIG. 15 showing the first structure of the source ring of the silicon carbide semiconductor device according to Embodiment 2. In the terminal structure region 42 of FIG. 16, the JTE structure 22 is used, but a guard ring structure may also be used. FIG. 17 is a top view of the region S showing the first structure of the source ring of the silicon carbide semiconductor device according to Embodiment 2. In FIG. 17, the region where the source ring 25 is in contact with the p ++ type contact region 8 is indicated by the source ring contact 29. As shown in FIGS. 16 and 17, in the first structure of the source ring of Embodiment 2, a diode 35 that allows the current flowing from the source ring 25 to the source electrode 12 and blocks the current flowing in the opposite direction is provided between the source ring 25 and the source electrode 12. For example, in the diode 35, the source electrode 12 side is an n + type polysilicon layer 32, and the source ring 25 side is a p + type polysilicon layer 33. The diode 35 is provided on the p ++ type contact region 8 via the initial oxide film 17 and the gate insulating film 7 on the silicon carbide semiconductor substrate.

[0077] Thereby, when dV / dt is applied, it is possible to extract holes from the p-type base layer 6 in the source ring 25, and to prevent holes from being injected from the source ring 25 when the parasitic diode of the MOSFET 50 is forward-biased. Therefore, while ensuring the dV / dt tolerance, it is possible to suppress the current concentration in the source ring 25 and suppress the growth of stacking defects.

[0078] FIG. 18 is a cross-sectional view taken along line Y-Y' of FIG. 15 showing a second structure of the source ring of the silicon carbide semiconductor device according to Embodiment 2. FIG. 19 is a top view of region S showing the second structure of the source ring of the silicon carbide semiconductor device according to Embodiment 2. In FIG. 19, the region where the source ring 25 contacts the p ++ -type contact region 8 is indicated by a source ring contact 29. As shown in FIGS. 18 and 19, in the second structure of the source ring of Embodiment 2, a resistor 36 composed of an n + -type polysilicon layer is provided between the source ring 25 and the source electrode 12. This resistor 36 can reduce the injection of holes from the source ring 25 when the parasitic diode of the MOSFET 50 is forward-biased. The resistor 36 is preferably, for example, a high-concentration n 19 / cm 3 -type polysilicon layer with an impurity concentration of 1×10 + or higher.

[0079] Thus, according to Embodiment 2, during dV / dt application, it is possible to extract holes from the p-type base layer in the source ring, and to reduce the injection of holes from the source ring when the parasitic diode of the MOSFET is forward-biased. In the second structure, the dV / dt tolerance decreases due to the n + -type polysilicon layer, but the decrease is within a practical range. Therefore, it is possible to suppress current concentration in the source ring and suppress the growth of stacking defects while ensuring the dV / dt tolerance.

[0080] (Embodiment 3) Next, Embodiment 3 will be described. In Embodiment 3, the contact resistance between the p-type region of the source ring 26 is made larger than the contact resistance between the source electrode 12 of the active region 40 and the p-type region. Since the top view of Embodiment 3 is the same as that of Embodiment 1, the description thereof is omitted.

[0081] FIG. 20 is a cross-sectional view showing a first structure of a source ring of a silicon carbide semiconductor device according to Embodiment 3. The left side of the paper surface of FIG. 20 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side. As shown in FIG. 20, in the first structure of the source ring 25 of Embodiment 3, the source ring 25 makes an ohmic contact with the p-type base layer 6 through the silicide layer 34. In this way, the source electrode 12 in the active region 40 is in contact with the p ++ type contact region 8, and a p ++ type contact region 8 is not provided at the location where the source ring 25 is in contact, so that it is in contact with the p-type base layer 6, thereby increasing the contact resistance.

[0082] Further, FIG. 21 is a cross-sectional view showing a second structure of a source ring of a silicon carbide semiconductor device according to Embodiment 3. The left side of the paper surface of FIG. 21 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side. As shown in FIG. 21, in the second structure of the source ring 25 of Embodiment 3, the source ring 25 makes an ohmic contact with the p ++ type contact region 8 through the silicide layer 34. FIG. 22 is a top view showing the second structure of the source ring of the silicon carbide semiconductor device according to Embodiment 3. The left side of the paper surface of FIG. 22 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side. As a means for making the contact resistance of the source ring 25 larger than the contact resistance of the active region 40, the average area of the region where the source ring 25 and the p ++ type contact region 8 make an ohmic contact is made smaller than the average area of the region where the source electrode 12 and the p ++ type contact region 8 make an ohmic contact in the active region 40. For example, as shown in FIG. 22, only a part of the silicide layer 34 of the source ring 25 is made to make an ohmic contact with the p ++ type contact region 8. In this way, by reducing the average area of the region where the silicide layer 34 of the source ring 25 is in contact, the contact resistance is made larger.

[0083] In the second structure of the source ring 25 of Embodiment 3, the source ring 25 and the p-type base layer 6 may be ohmic - contacted in the same manner as in the first structure of the source ring 25 of Embodiment 3.

[0084] Thus, according to Embodiment 3, when a dV / dt is applied, holes can be extracted from the p-type base layer in the source ring, and the injection of holes from the source ring can be reduced in a state where the parasitic diode of the MOSFET is forward - biased. Although the dV / dt tolerance decreases due to a large contact resistance, the decrease is within a practically acceptable range. Therefore, while ensuring the dV / dt tolerance, the current concentration in the source ring can be suppressed, and the growth of stacking defects can be suppressed.

[0085] (Embodiment 4) Next, Embodiment 4 will be described. In Embodiment 4, the p-type region of the active region 40 and the p-type region connected to the source ring 25 are separated. Embodiment 4 is used in combination with Embodiments 1 - 3. In Embodiment 4, by separating the p-type regions, the current around the active region 40 when a dV / dt is applied mainly flows into the source ring 25, and the effects of Embodiments 1 - 3 can be enhanced.

[0086] FIG. 23 is a cross - sectional view showing the first structure of the source ring of the silicon carbide semiconductor device according to Embodiment 4. The left side of the paper surface of FIG. 23 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side. FIG. 23 is a form in which Embodiment 4 is applied to the first structure of the source ring of Embodiment 3. FIG. 24 is a cross - sectional view showing the second structure of the source ring of the silicon carbide semiconductor device according to Embodiment 4. FIG. 25 is a top view showing the second structure of the source ring of the silicon carbide semiconductor device according to Embodiment 4. FIGS. 24 and 25 are forms in which Embodiment 4 is applied to the second structure of the source ring of Embodiment 3. The left side of the paper surface of FIGS. 24 and 25 is the active region 40 side, and the right side of the paper surface is the termination structure region 42 side.

[0087] Thus, according to the fourth embodiment, by separating the p-type region in the active region from the p-type region connected to the source ring, the current in the peripheral portion of the active region when dV / dt is applied mostly flows into the source ring, and the effects of the first to third embodiments can be enhanced.

[0088] (Example) A silicon carbide semiconductor device was prototyped with the first structure of the source ring in the third embodiment, and the light emission during the energization of the parasitic diode was compared with that of an existing silicon carbide semiconductor device. FIG. 26 is a top view showing the structure of the silicon carbide semiconductor device of the example. FIG. 27 is a graph showing the light emission intensity distribution from the surface along the Y-Y' portion during the reverse conduction (energization of the parasitic diode) of the existing silicon carbide semiconductor device. FIG. 28 is a graph showing the light emission intensity distribution from the surface along the Y-Y' portion during the reverse conduction (energization of the parasitic diode) with the first structure of the source ring of the silicon carbide semiconductor device according to the third embodiment. In FIGS. 27 and 28, the vertical axis represents the light emission intensity of light with a wavelength of 400 nm, and the horizontal axis represents the distance from the end on the Y side of the silicon carbide semiconductor device, with the unit being mm.

[0089] As shown in FIG. 27, in the existing silicon carbide semiconductor device, strong light emission is detected in the vicinity of the source ring connection portion (between 0 mm and 2 mm), and as the distance from the source ring connection portion increases, the light emission intensity decreases due to the voltage drop caused by the lateral resistance. On the other hand, in the third embodiment, as shown in FIG. 28, it can be confirmed that the peak intensity in the vicinity of the source ring connection portion (between 0 mm and 2 mm) has decreased to about 1 / 500 of that of the existing device.

[0090] The decrease in light emission in the vicinity of the source ring connection portion is the result of reduced injection of holes from the source ring 25 in a state where the parasitic diode is forward-biased, indicating that the current concentration into the source ring 25 can be suppressed in the present disclosure, and the growth of stacking defects can be suppressed. Also, the dv / dt withstand voltage at low temperatures satisfies the specified value for both the structures of the existing and third embodiment silicon carbide semiconductor devices, ensuring the dv / dt withstand voltage.

[0091] In the above description of the present disclosure, the case where a MOS gate structure is formed on the first main surface of a silicon carbide substrate has been described as an example. However, the present disclosure is not limited thereto, and various changes such as the plane orientation of the substrate main surface are possible. Further, in the embodiments of the present disclosure, a trench-type MOSFET has been described as an example. However, the present disclosure is not limited thereto, and the present disclosure is applicable to semiconductor devices having various configurations such as MOS-type semiconductor devices such as trench-type IGBTs. Further, in the present disclosure, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present disclosure also holds true when the first conductivity type is p-type and the second conductivity type is n-type.

Industrial Applicability

[0092] As described above, the semiconductor device according to the present disclosure is useful for high-voltage-resistant semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Explanation of Reference Numerals

[0093] 1, 101 n + type silicon carbide substrate 2, 102 n - type drift layer 3, 103 First p + type base region 4, 104 Second p + type base region 4a, 104a First p + type region 4b, 104b Second p + type region 6, 106 p-type base layer 7 n ++ type source region 8, 108 p ++ type contact region 9 Gate insulating film 10 Gate electrode 11, 111 Interlayer insulating film 12 Source electrode 13 Back surface electrode 16 Trench 17, 117 Initial oxide film 18 Polysilicon 19 Protective film 21 Guard ring structure 22 JTE structure 23 n ++ type region 24 gate ring 25, 125 source ring 26 source electrode pad 27 gate electrode pad 28 source ring connection part 29 source ring contact 30 Schottky electrode 31 silicon layer 32 n + type polysilicon layer 33 p + type polysilicon layer 34, 134 silicide layer 35 diode 36 resistor 40 active region 41 intermediate region 42 terminal structure region 50 trench type MOSFET

Claims

1. On a semiconductor substrate of a first conductivity type, there are provided an active region through which a main current flows, a termination region surrounding the periphery of the active region, and an intermediate region between the active region and the termination region. On the front surface side of the semiconductor substrate of the active region, there is a front surface electrode connected to a first semiconductor region of a second conductivity type. In the intermediate region, there is a source ring electrically connected to the front surface electrode and connected to a second semiconductor region of the second conductivity type for extracting a hole current. The contact between the front surface electrode of the active region and the first semiconductor region is an ohmic contact. A semiconductor device, wherein the contact between the source ring in the intermediate region and the second semiconductor region is a Schottky junction.

2. The semiconductor device according to claim 1, wherein the contact between the source ring in the intermediate region and the second semiconductor region is a heterojunction formed by a semiconductor having a large band offset on the valence band side with respect to the second semiconductor region.

3. The semiconductor device according to claim 2, wherein the semiconductor having a large band offset on the valence band side with respect to the second semiconductor region is silicon.

4. On a semiconductor substrate of a first conductivity type, there are provided an active region through which a main current flows, a termination region surrounding the periphery of the active region, and an intermediate region between the active region and the termination region. On the front surface side of the semiconductor substrate of the active region, there is a front surface electrode connected to a first semiconductor region of a second conductivity type. In the intermediate region, there is a source ring electrically connected to the front surface electrode and connected to a second semiconductor region of the second conductivity type for extracting a hole current. A semiconductor device, wherein a diode is provided between the front surface electrode and the source ring, which allows the current flowing from the source ring to the front surface electrode and blocks the current flowing in the opposite direction.

5. The semiconductor device according to claim 4, wherein the diode is formed by a polysilicon layer formed on the semiconductor substrate with an insulating layer interposed therebetween.

6. The semiconductor device according to claim 4, wherein a resistor is provided between the front surface electrode and the source ring instead of the diode.

7. The semiconductor device according to claim 6, wherein the resistor is formed by a polysilicon layer formed on the semiconductor substrate with an insulating layer interposed therebetween.

8. On a semiconductor substrate of a first conductivity type, an active region through which a main current flows, a termination region surrounding the periphery of the active region, and an intermediate region between the active region and the termination region are provided. On the front surface side of the semiconductor substrate of the active region, a front surface electrode connected to a first semiconductor region of a second conductivity type is provided. The intermediate region has a source ring that is electrically connected to the front surface electrode and is connected to a second semiconductor region of the second conductivity type for extracting a hole current. A semiconductor device, characterized in that a contact resistance between the source ring and the second semiconductor region is larger than a contact resistance between the front surface electrode of the active region and the first semiconductor region. **Claim 9** The semiconductor device according to claim 8, characterized in that an average area of a region where the source ring and the second semiconductor region are in ohmic contact is smaller than an average area of a region where the front surface electrode of the active region and the first semiconductor region are in ohmic contact. **Claim 10** The semiconductor device according to claim 8, characterized in that the first semiconductor region of the active region has a higher impurity concentration than the second semiconductor region of the intermediate region. **Claim 11** The semiconductor device according to any one of claims 1 to 10, characterized in that the first semiconductor region of the active region is separated from the second semiconductor region connected to the source ring of the intermediate region.

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