Display device

Abstract

To provide an active matrix type liquid crystal display device in which a plurality of types of circuits are formed on the same substrate and a plurality of types of thin film transistors are provided according to the characteristics of a plurality of types of circuits.SOLUTION: An inverted coplanar type having an oxide semiconductor layer overlapping a source electrode layer and a drain electrode layer is used as a pixel thin film transistor, a channel protection type is used as a drive circuit thin film transistor, and the main part of the pixel thin film transistor is configured by a translucent material to increase the aperture ratio.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an active matrix type liquid crystal display device and a method for manufacturing the same. Further, the present invention relates to an electronic device equipped with an active matrix type liquid crystal display device as a component.

Background Art

[0002] In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. The thin film transistor is widely applied to electronic devices such as ICs and electro-optical devices, and in particular, development is being rushed as a switching element of an image display device. Metal oxides exist in various forms and are used in various applications. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

[0003] The thin film transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region, and current can flow through the drain region, the channel region, and the source region. In this specification, without distinguishing between the source and the drain, when one is called the source, the other is called the drain.

[0004] Some metal oxides exhibit semiconductor characteristics. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. A thin film transistor using an oxide semiconductor has a high field effect mobility. Therefore, a drive circuit such as a display device can also be configured using the thin film transistor. Such semiconductor characteristics ​​​​​​​​​​​​​ Thin film transistors having a metal oxide exhibiting properties as a channel formation region are already known (Patent Literature 1 and Patent Literature 2).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] When forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate , the thin film transistor used in the pixel portion is required to have excellent switching characteristics, for example, a large on-off ratio, and the thin film transistor used in the driving circuit is required to have a high operating speed. In particular, the higher the definition of the display device, the shorter the writing time of the display image, so the thin film transistor used in the driving circuit preferably has a high operating speed.

[0007] To provide an active matrix liquid crystal display device that forms a plurality of types of circuits on the same substrate and includes a plurality of types of thin film transistors adapted to the characteristics of the plurality of types of circuits is one of the problems.

[0008] Another problem is to reduce the variation in the electrical characteristics of thin film transistors using an oxide semiconductor film in the above active matrix liquid crystal display device.

Means for Solving the Problems

[0009] One embodiment of the present invention is a display device having a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driving circuit portion has a gate electrode layer, a source electrode layer, and a drain electrode layer formed of a metal conductive film. a thin film transistor for a driver circuit, the thin film transistor being configured such that the semiconductor layer is configured from an oxide semiconductor; and a driving circuit wiring formed of a metal conductive film. The display section includes a source electrode layer The drain electrode layer is made of an oxide conductor and the semiconductor layer is made of an oxide semiconductor. and a pixel thin film transistor configured as above. .

[0010] Thin-film transistors with bottom gate structure are used as thin-film transistors for pixels and thin-film transistors for driving circuits. The pixel thin film transistor is formed on the source electrode layer and the drain electrode layer. Inverted coplanar (also called bottom-contact) thin-film transistors having an oxide semiconductor layer overlapping a It is a ninja.

[0011] In the present invention, a plurality of pixel electrodes are provided on the same substrate, and pixel electrodes are electrically connected to the pixel electrodes. It is possible to manufacture an active matrix type liquid crystal display device in which a thin film transistor for use is formed. Cut.

[0012] In the above-mentioned active matrix type liquid crystal display device, the formation of an active matrix circuit An optical film, specifically a color filter, is formed on a substrate (opposite substrate) facing the above substrate. and a white light source is provided, and liquid crystal is sandwiched between the substrates to form a full-color liquid crystal display device. In this way, when displaying through a color filter, As a material for the gate electrode layer, source electrode layer, and drain electrode layer of a film transistor, Using a conductive film having [it] can improve the aperture ratio. Here, the color filter refers not to the entire film including the black matrix and overcoat, etc., but to a color filter of one color, including a three-color color filter layer (such as a red color filter, a blue color filter, a green color filter, etc.).

[0013] On the other hand, the thin-film transistor for the driving circuit has a different structure from the thin-film transistor for pixels, and is a bottom-gate type thin-film transistor in which an oxide insulating layer in contact with an oxide semiconductor layer exposed between the source electrode layer and the drain electrode layer is provided.

[0014] The thin-film transistor for the driving circuit has a drain electrode layer made of a metal conductive film such as Ti, is oxygen-deficient and high-resistance, in contact with a part of the upper surface of the oxide semiconductor layer and overlapping the drain electrode layer, a drain region (also called an HRD (High Resistance Drain) region) is formed. Specifically, the carrier concentration in the high-resistance drain region is 1×10 / cm 18 or more and 1×10 3 / cm or less (preferably, 1×10 21 / cm 3 or more and 1×10 18 / cm 3 or more and 1×10 20 / c m 3 or less) within the range, and is a region higher than at least the carrier concentration in the channel formation region (1×10 14 / cm 3 or more and 1×10 18 / cm 3 less). Here, the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature.

[0015] ​​​​Further, the source electrode layer is in contact with a part of the upper surface of the oxide semiconductor layer, and a high-resistance source region (also referred to as an HRS (High Resistance Source) region) that is an oxygen-deficient type and overlaps with the source electrode layer is formed.

[0016] One aspect of the invention disclosed in this specification has a pixel portion having a first thin-film transistor on the same substrate and a driving circuit having a second thin-film transistor with a different structure from the first thin-film transistor. The first thin-film transistor has a gate electrode layer on the substrate, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, an oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer on the gate insulating layer, an oxide insulating layer in contact with the oxide semiconductor layer, and a pixel electrode layer electrically connected to the drain electrode layer on the oxide insulating layer. At least one of the gate electrode layer, gate insulating layer, oxide semiconductor layer, source electrode layer, drain electrode layer, and oxide insulating layer of the first thin-film transistor has a light-transmitting active matrix type liquid crystal display device.

[0017] The above configuration solves at least one of the above problems.

[0018] In addition, in the above and in this specification, the ordinal numbers attached as the first and the second are used for convenience and do not indicate the process order or the stacking order. Also, in this specification, they do not indicate specific names for identifying the invention.

[0019] Further, in the above configuration, a connection electrode layer may be provided between the pixel electrode layer and the drain electrode layer. The connection electrode layer mainly contains an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. ​​​​​​​​​​​​​A metallic film as a component, or an alloy film thereof, and a laminated film combining them may be used. Also, for the source electrode layer and the drain electrode layer of the first thin film transistor, indium oxide, indium tin oxide, indium zinc oxide, or zinc oxide may be used.

[0020] Also, for the source electrode layer and the drain electrode layer of the second thin film transistor which is a thin film transistor for a driving circuit, an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above-described element as a component, or a metallic material such as an alloy combining the above-described elements is used. The source electrode layer and the drain electrode layer are not limited to a single layer containing the above-described element, and a laminate of two or more layers can be used.

[0021] Also, the source electrode layer and the drain electrode layer of the second thin film transistor are configured not to overlap with the channel formation region of the oxide semiconductor layer. Also, the distance between the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface is wider than the width of the oxide insulating layer functioning as a channel protection layer. In order to increase the operating speed of the thin film transistor for a driving circuit, if the width (length in the channel length direction) of the oxide insulating layer functioning as a channel protection layer is designed to be small, the distance between the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface also becomes small, and there is a risk that the source electrode layer and the drain electrode layer may be short-circuited. Therefore, it is useful to widen the distance. Also, by using a thin film transistor with a high operating speed, the integration degree of the circuit is improved.

[0022] Also, in the above configuration, the second thin film transistor has an oxide semiconductor layer, and the oxide ​​​​​​​​​​​​​​It has an oxide insulating layer on the semiconductor layer, and the channel formation region of the oxide semiconductor layer and the peripheral portion of the oxide semiconductor layer are in contact with the oxide insulating layer. The oxide insulating layer in contact with the channel formation region of the oxide semiconductor layer functions as a channel protection layer. Also, in the above configuration, the oxide insulating layer that functions as a channel protection layer of the thin film transistor for the drive circuit uses an inorganic insulating film formed by a sputtering method. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, etc.

[0023] is used. Also, the second thin film transistor may be configured to have oxide conductive layers on both sides between the oxide semiconductor layer and the source electrode layer and between the oxide semiconductor layer and the drain electrode layer. By adopting this configuration, the contact resistance can be reduced, and a thin film transistor capable of high-speed operation can be realized. Note that the oxide conductive layer preferably contains zinc oxide as a component and preferably does not contain indium oxide. Examples of such oxide conductive layers include zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, and zinc gallium oxide.

[0024] Also, the oxide semiconductor layer of the thin film transistor for the drive circuit has, on the upper surface of the oxide semiconductor layer, a region that does not overlap with the oxide insulating layer, the drain electrode layer, and the source electrode layer, that is, a third region. The length of this third region in the channel length direction is determined by the patterning position of the oxide semiconductor layer and the patterning positions of the drain electrode layer and the source electrode layer. If the length of this third region in the channel length direction is made wider, the off current of the thin film transistor for the drive circuit will be... Also, the oxide semiconductor layer of the thin film transistor for the drive circuit has, on the upper surface of the oxide semiconductor layer, a region that does not overlap with the oxide insulating layer, the drain electrode layer, and the source electrode layer, that is, a third region.

[0025] Also, the oxide semiconductor layer of the thin film transistor for the drive circuit has, on the upper surface of the oxide semiconductor layer, a region that does not overlap with the oxide insulating layer, the drain electrode layer, and the source electrode layer, that is, a third region. The length of this third region in the channel length direction is determined by the patterning position of the oxide semiconductor layer and the patterning positions of the drain electrode layer and the source electrode layer. If the length of this third region in the channel length direction is widened, the off current of the thin film transistor for the drive circuit Flow reduction can be achieved. Also, if the length of the third region in the channel length direction is made narrower, the operation (switching) of the thin film transistor for the drive circuit can be speeded up. .

[0026] Also, an insulating layer in contact with the third region is formed using an inorganic insulating film formed by a physical film formation method such as sputtering. Typically, a silicon nitride film, a silicon oxynitride film, or an aluminum nitride film is used. In these film formations, it is desirable to reduce the atmosphere and the hydrogen concentration in the film formation material (including not only the hydrogen concentration as a single substance but also the hydrogen contained in the compound) as much as possible, so that the hydrogen concentration in the obtained film is sufficiently low. Specifically, the hydrogen concentration in the obtained film is preferably 1×10 atoms or more and 1×10 atoms or less per 1 cm. 3 12 18

[0027] Note that as the oxide semiconductor layer, a thin film represented by InMO(ZnO)(m>0 and m is not an integer) may be formed, and a thin film transistor using the thin film as the oxide semiconductor layer may be manufactured. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and Fe, are included. Also, in the above oxide semiconductor, in addition to the metal elements included as M, there are those containing impurity elements such as Fe, Ni, and other transition metal elements, or oxides of the transition metals. In this specification, for example, an oxide semiconductor having In, Ga, and Zn is referred to as In-Ga-Zn-O. 3 (ZnO) m It is called an indium-gallium-zinc-oxide-based oxide semiconductor, and its thin film is also referred to as an In-Ga-Zn-O-based film. Other elements may be included in the In-Ga-Z n-O-based oxide semiconductor.

[0028] In addition to the above, as the metal oxide applied to the oxide semiconductor layer, In-Sn-O-based, I n-Ga-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn -O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn- Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. Also, silicon may be included in the oxide semiconductor layer composed of the above metal oxides.

[0029] Also, one aspect of the present invention for realizing the above structure is to form a first gate electrode layer and a second gate electrode layer on a substrate having an insulating surface, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form a first source electrode layer and a first drain electrode layer overlapping the first gate electrode layer on the gate insulating layer, form a first oxide semiconductor layer overlapping the first gate electrode layer, a part of the first source electrode layer, and a part of the first drain electrode layer on the gate insulating layer, and a second oxide semiconductor layer overlapping the second gate electrode layer, form an oxide insulating layer in contact with a part of the first oxide semiconductor layer and in contact with the upper surface and side surfaces of the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the second oxide semiconductor layer, and form a pixel electrode layer electrically connected to the first drain electrode layer on the oxide insulating layer. This is a method for manufacturing an active matrix type display device.

[0030] In the configuration of the above manufacturing method, in contact with the first oxide semiconductor layer and the second oxide semiconductor layer The formation of the oxide insulating layer is carried out after dehydrating or dehydrogenating the oxide semiconductor layer without exposing it to the atmosphere, preventing the re-mixing of water and hydrogen into the oxide semiconductor layer.

[0031] In this specification, only the desorption of H 2 as a result of this heat treatment is not simply called dehydrogenation, but dehydration or dehydrogenation is also conveniently referred to as including the desorption of H, OH, etc. for convenience. Although it depends on the film formation method, the oxide semiconductor layer contains some hydrogen or water, and a part of it serves as a donor that supplies electrons. When heat treatment is carried out in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.), the hydrogen and water contained in the oxide semiconductor layer are removed. At the same time, the oxide semiconductor layer becomes oxygen-deficient type and has low resistance, that is, N-type doping (N

[0032] type doping, etc.) due to this heat treatment. After that, by forming an oxide insulating film in contact with the oxide semiconductor layer, the oxide semiconductor layer can be made into an oxygen-excessive state to increase the resistance, that is, to make it I-type. Thereby, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. The dehydration or dehydrogenation is carried out by heat treatment at 350 °C or higher, preferably 425 °C or higher and 700 °C or lower in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to reduce impurities such as the contained moisture in the oxide semiconductor layer. type doping, etc.). type doping, etc.). - type doping, etc.).

[0033] After that, by forming an oxide insulating film in contact with the oxide semiconductor layer, the oxide semiconductor layer can be made into an oxygen-excessive state to increase the resistance, that is, to make it I-type. Thereby, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. By making the oxide semiconductor layer in an oxygen-excessive state, the resistance can be increased, that is, it can be made I-type. As a result, it is possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. By making the oxide semiconductor layer in an oxygen-excessive state, the resistance can be increased, that is, it can be made I-type. As a result, it is possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. It becomes possible.

[0034] The dehydration or dehydrogenation is carried out by heat treatment at 350 °C or higher, preferably 425 °C or higher and 700 °C or lower in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to reduce impurities such as the contained moisture in the oxide semiconductor layer. The dehydration or dehydrogenation is carried out by heat treatment at 350 °C or higher, preferably 425 °C or higher and 700 °C or lower in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to reduce impurities such as the contained moisture in the oxide semiconductor layer. The dehydration or dehydrogenation is carried out by heat treatment at 350 °C or higher, preferably 425 °C or higher and 700 °C or lower in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) to reduce impurities such as the contained moisture in the oxide semiconductor layer.

[0035] For the oxide semiconductor layer in which the above dehydration or dehydrogenation has been appropriately performed, analysis of the gas desorbed using the temperature-programmed desorption gas analysis (TDS) method (from room temperature to 450 °C) is carried out, and among the two peaks derived from water, the peak appearing at around at least 300 °C is not detected. When performing the analysis of the gas desorbed using the temperature-programmed desorption gas analysis (TDS) method (from room temperature to 450 °C) on the oxide semiconductor layer in which the above dehydration or dehydrogenation has been appropriately performed, among the two peaks derived from water, the peak appearing at around at least 300 °C is not detected. For the oxide semiconductor layer in which the above dehydration or dehydrogenation has been appropriately performed, analysis of the gas desorbed using the temperature-programmed desorption gas analysis (TDS) method (from room temperature to 450 °C) is carried out, and among the two peaks derived from water, the peak appearing at around at least 300 °C is not detected. .

[0036] Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage. Note that from the heating temperature at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, without exposing it to the atmosphere in the same furnace where dehydration or dehydrogenation has been performed, it is preferable to lower the temperature to room temperature without allowing water or hydrogen to be mixed in again. Also, when dehydration or dehydrogenation is performed, oxygen deficiency occurs (becoming oxygen-deficient type), and the oxide semiconductor layer becomes low-resistance (i.e., N-type). Therefore, when an oxide insulating film is formed in contact with the oxide semiconductor layer, the oxide semiconductor layer becomes high-resistance again (i.e., P-type). When a thin-film transistor is fabricated using such an oxide semiconductor layer, the threshold voltage (Vth) of the thin-film transistor can be made positive, and a so-called normally-off switching element can be realized. In a thin-film transistor used in a display device, it is desirable that a channel is formed at a positive voltage as close as possible to 0 V for the gate voltage.

[0037] Note that if the threshold voltage of the thin-film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, and it easily becomes a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin-film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. Note that if the threshold voltage of the thin-film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, and it easily becomes a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin-film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. Note that if the threshold voltage of the thin-film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, and it easily becomes a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin-film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. Note that if the threshold voltage of the thin-film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0 V, and it easily becomes a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin-film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device.

[0038] In particular, among the electrical characteristics of the thin-film transistor, the threshold voltage is important. For an n-channel type Taking a thin-film transistor as an example, even if the field-effect mobility is high, if the threshold voltage is extremely high or the threshold voltage is negative, it is difficult to control as a circuit. When the threshold voltage of a thin-film transistor is high, the thin-film transistor cannot perform its switching function in a state where the drive voltage is low, and there is a risk of becoming a load.

[0039] In the case of an n-channel thin-film transistor, when a voltage of 0 V is applied to the gate, no channel is formed. It is desirable to have a transistor in which a positive voltage of +1 V to +5 V is applied to form a channel and a drain current flows out. A transistor in which a channel is not formed unless the drive voltage is increased to +10 V or higher, or a transistor in which a channel is formed even in a negative voltage state and a drain current flows, is not suitable as a thin-film transistor used in a circuit.

[0040] Note that when lowering the temperature from the heating temperature for performing the above dehydration or dehydrogenation to room temperature, the gas atmosphere may be switched to a gas atmosphere different from the gas atmosphere at the above heating temperature. For example, dehydration or dehydrogenation is performed in a nitrogen atmosphere, and then the atmosphere in the furnace is filled with high-purity oxygen gas or N 2 O gas, ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower), and cooling may be performed.

[0041] After reducing the water content in the film by the heat treatment for performing dehydration or dehydrogenation, using an oxide semiconductor film slowly cooled (or cooled) in a substantially water-free dry atmosphere (dew point of -40°C or lower, preferably -60°C or lower), the electrical characteristics of the thin-film transistor are improved while realizing a thin-film transistor having both mass productivity and high performance. ​

[0042] Active matrix type display devices have a plurality of thin film transistors in their pixel portions, and in the pixel portion, there are some where the gate electrode of a certain thin film transistor is connected to the source wiring of another thin film transistor, or the drain wiring. Also, when a drive circuit is formed by thin film transistors in an active matrix type device, there are some where the gate electrode of the thin film transistor is connected to the source wiring of that thin film transistor, or the drain wiring. portion.

[0043] Further, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the thin film transistors in the pixel portion on the same substrate with respect to the gate line or the source line. At that time, the protection circuit can be configured using a non-linear element using an oxide semiconductor layer.

[0044] A semiconductor device according to one aspect of the present invention has a drive circuit portion having drive circuit thin film transistors and a pixel portion having pixel thin film transistors formed on the same substrate. Therefore, the manufacturing cost of the active matrix type display device can be reduced.

Effect of the Invention

[0045] By using an oxide semiconductor layer that has undergone a heat treatment for dehydration or dehydrogenation, a thin film transistor with good electrical characteristics and high reliability can be used as a switching element, and an active matrix type display device with high reliability can be manufactured. Also, pixel thin film transistors and drive circuit thin film transistors are formed on the same substrate, and these are respectively high reliable ​​​​​As a structure adapted to the circuit, an active matrix type display device can be manufactured. .

Brief Description of the Drawings

[0046]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Best Mode for Carrying Out the Invention

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below. In the drawings in this specification, the same part or parts having the same function are denoted by the same reference numerals, and the description thereof may be omitted.

[0048] (Embodiment 1) In this embodiment, one form of an active matrix display device and a method for manufacturing the active matrix display device will be described with reference to FIG. 1. FIG. 1(E) shows an example of the cross-sectional structure of two thin film transistors having different structures formed on the same substrate.

[0049] The thin film transistor 12 shown in FIG. 1(E) is one of the bottom gate structures. Also, the thin film transistor 13 is one of the bottom gate structures called the bottom contact type (also called the inverse coplanar type).

[0050] The thin film transistor 13 disposed in the pixel includes a gate electrode layer 3a, a gate insulating layer 4, an oxide semiconductor layer 8b including a channel formation region, a source electrode layer 5a , and a drain electrode layer 5b on a substrate 1 having an insulating surface. Also, an oxide insulating layer 7b that covers the thin film transistor 13 and is in contact with the upper surface and side surfaces of the oxide semiconductor layer 8b is provided.

[0051] Also, the thin film transistor 13 disposed in the pixel is a thin film transistor having a single gate structure. Although described using it, a multi-gate structure having a plurality of channel formation regions can also be formed as needed. A thin film transistor.

[0052] Note that the oxide semiconductor layer 8b is formed above the source electrode layer 5a and the drain electrode layer 5b and partially overlaps. Also, the oxide semiconductor layer 8b overlaps with the gate electrode layer 3a via the gate insulating layer 4. The channel formation region of the thin film transistor 13 disposed in the pixel is the region sandwiched between the side surface of the source electrode layer 5a and the side surface of the drain electrode layer 5b facing the side surface in the oxide semiconductor layer 8b, that is, the region in contact with the gate insulating layer 4 and overlapping with the gate electrode layer 3 a. a. a.

[0053] Also, the thin film transistor 13 has a high aperture ratio as a thin film transistor having translucency. To realize a liquid crystal display device, the source electrode layer 5a and the drain electrode layer 5b use a conductive film having translucency. A conductive film having translucency is used.

[0054] Also, a conductive film having translucency is used for the gate electrode layer 3a of the thin film transistor 13. In this specification, a film having translucency with respect to visible light refers to a film having a film thickness with a transmittance of visible light of 75% or more and 100 % or less. When the film has conductivity, it is also called a transparent conductive film. Also, a semi-transparent conductive film with respect to visible light may be used. Semi-transparent with respect to visible light means that the transmittance of visible light is 50% or more and less than 75%. % or less. When the film has conductivity, it is also called a transparent conductive film. Also, a semi-transparent conductive film with respect to visible light may be used. Semi-transparent with respect to visible light means that the transmittance of visible light is 50% or more and less than 75%.

[0055] Also, the thin film transistor 12 disposed in the drive circuit is on the substrate 1 having an insulating surface, and the gate electrode layer 2a, the gate insulating layer 4, the oxide semiconductor layer 6a, the source electrode layer 9a, and the drain electrode layer. ​​​The oxide semiconductor layer 6a includes at least a channel formation region 8a, a high resistance solenoid layer 9b, and a gate electrode layer 9b. The source region 11a and the high-resistance drain region 11b are also included in the channel formation region 8a. The oxide insulating layer 7a is provided in contact with the source electrode layer 9a and the drain electrode layer 9 An insulating layer 10 is provided on b.

[0056] In addition, the first region 11c and the second region 11d of the oxide semiconductor layer 6a overlapping the oxide insulating layer 7b are is in the same oxygen-excess state as the channel formation region 8a, and thus the leakage current is reduced and the parasitic capacitance is reduced. In addition, the third region of the oxide semiconductor layer 6a in contact with the insulating layer 10 also serves to reduce the The region 11e is provided between the channel formation region 8a and the high-resistance source region 11a. The fourth region 11f of the oxide semiconductor layer 6a in contact with the insulating layer 10 is high-density with the channel formation region 8a. The first insulating layer 10 is provided between the first and second drain regions 11b of the oxide semiconductor layer 6a. The third region 11e and the fourth region 11f can reduce the off current.

[0057] In general, a channel protection type thin film transistor has a source electrode that overlaps with the channel protection layer. In this structure, a channel layer and a drain electrode layer are formed in the channel forming region. To shorten the length L, it is necessary to narrow the width of the channel protection layer. When a source electrode layer and a drain electrode layer are provided on the channel protection layer, the source In this embodiment, the channel protection layer is formed of a thin film. The narrow oxide insulating layer 7a, which functions as a gate insulating layer, overlaps the source electrode layer 9a and the drain electrode layer 9b. The above problem can be overcome by adopting a configuration that does not include the above-mentioned.

[0058] In FIG. 1(E), the region of the oxide semiconductor layer 6a where the oxide insulating layer 7a and the gate electrode layer 2a overlap via the gate insulating layer is referred to as the channel formation region. Therefore, the channel length L of the thin film transistor 12 is equal to the length of the oxide insulating layer 7a in the channel length direction. Note that in the cross-sectional view shown in FIG. 1(E), the oxide insulating layer 7a is shown as a trapezoid, and the channel length L of the thin film transistor 12 is the length of the bottom side of the trapezoid.

[0059] Hereinafter, the process of manufacturing the thin film transistor 12 and the thin film transistor 13 on the same substrate will be described with reference to FIGS. 1(A), 1(B), 1(C), 1(D), and 1(E).

[0060] First, after forming a conductive film on the substrate 1 having an insulating surface, the gate electrode layers 2a and 2b are formed by a first photolithography process. Note that this process may be substituted with a method of forming a resist mask by an inkjet method. When forming a resist mask by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0061] Examples of the conductive film for forming the gate electrode layers 2a and 2b include a metal containing any one of elements selected from Al, Cr, Ta, Ti, Mo, and W as a main component, an alloy containing the above-described elements as components, or an alloy film formed by combining the above-described elements.

[0062] When using a glass substrate as the substrate 1, if the temperature of the subsequent heat treatment is high, it is preferable to use a glass substrate having a strain point of 730°C or higher. For the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. In addition, crystallized glass or the like can also be used. ​​​​​​​​​​​​

[0063] In general, by including more barium oxide (BaO) compared with boric acid, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B O 2 O 3 For example, it is preferable to use a glass substrate containing more BaO than B O.

[0064] In addition, as the substrate 1, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. For example, it is preferable to use a glass substrate containing more BaO than B

[0065] Further, an insulating film serving as an underlayer film may be provided between the substrate 1 and the gate electrode layers 2a and 2b. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 1, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 1, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 1, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 1, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0066] Next, after forming a conductive film having translucency so as to cover the gate electrode layers 2a and 2b, the gate electrode layers 3a and 3b are formed by a second photolithography process. In the present embodiment, in order to reduce the wiring resistance, the gate wiring disposed in the pixel portion is formed of the same metal conductive film as the gate electrode layer 2b, and the material of the gate electrode layer 3a that overlaps with the oxide semiconductor layer and the gate insulating layer 4 formed later is formed of a conductive film having translucency. Next, after forming a conductive film having translucency so as to cover the gate electrode layers 2a and 2b, the gate electrode layers 3a and 3b are formed by a second photolithography process. In the present embodiment, in order to reduce the wiring resistance, the gate wiring disposed in the pixel portion is formed of the same metal conductive film as the gate electrode layer 2b, and the material of the gate electrode layer 3a that overlaps with the oxide semiconductor layer and the gate insulating layer 4 formed later is formed of a conductive film having translucency. Next, after forming a conductive film having translucency so as to cover the gate electrode layers 2a and 2b, the gate electrode layers 3a and 3b are formed by a second photolithography process. In the present embodiment, in order to reduce the wiring resistance, the gate wiring disposed in the pixel portion is formed of the same metal conductive film as the gate electrode layer 2b, and the material of the gate electrode layer 3a that overlaps with the oxide semiconductor layer and the gate insulating layer 4 formed later is formed of a conductive film having translucency. Next, after forming a conductive film having translucency so as to cover the gate electrode layers 2a and 2b, the gate electrode layers 3a and 3b are formed by a second photolithography process. In the present embodiment, in order to reduce the wiring resistance, the gate wiring disposed in the pixel portion is formed of the same metal conductive film as the gate electrode layer 2b, and the material of the gate electrode layer 3a that overlaps with the oxide semiconductor layer and the gate insulating layer 4 formed later is formed of a conductive film having translucency. Next, after forming a conductive film having translucency so as to cover the gate electrode layers 2a and 2b, the gate electrode layers 3a and 3b are formed by a second photolithography process. In the present embodiment, in order to reduce the wiring resistance, the gate wiring disposed in the pixel portion is formed of the same metal conductive film as the gate electrode layer 2b, and the material of the gate electrode layer 3a that overlaps with the oxide semiconductor layer and the gate insulating layer 4 formed later is formed of a conductive film having translucency.

[0067] Next, a gate insulating layer 4 is formed on the gate electrode layers 2a, 2b, 3a, and 3b. The gate insulating layer 4 can be formed by a physical vapor deposition (PVD) method such as a plasma CVD method or a sputtering method, and can be formed as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. For example, as the film-forming gas, SiH Next, a gate insulating layer 4 is formed on the gate electrode layers 2a, 2b, 3a, and 3b. The gate insulating layer 4 can be formed by a physical vapor deposition (PVD) method such as a plasma CVD method or a sputtering method, and can be formed as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. For example, as the film-forming gas, SiH Next, a gate insulating layer 4 is formed on the gate electrode layers 2a, 2b, 3a, and 3b. The gate insulating layer 4 can be formed by a physical vapor deposition (PVD) method such as a plasma CVD method or a sputtering method, and can be formed as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. For example, as the film-forming gas, SiH Next, a gate insulating layer 4 is formed on the gate electrode layers 2a, 2b, 3a, and 3b. The gate insulating layer 4 can be formed by a physical vapor deposition (PVD) method such as a plasma CVD method or a sputtering method, and can be formed as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. For example, as the film-forming gas, SiH 4, using oxygen and nitrogen, a silicon oxynitride layer may be formed by plasma CVD method. The film thickness of the gate insulating layer 4 is 10 0 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer may be laminated.

[0068] In this embodiment, the gate insulating layer 4 is formed using silicon oxynitride (SiON( nitrogen concentration is less than oxygen concentration) with a thickness of 100 nm by plasma CVD method.

[0069] Note that, in order to prevent hydrogen from diffusing into the oxide semiconductor layer formed thereon, it is preferable that the hydrogen concentration in the gate insulating layer 4 is sufficiently low. For this purpose, a physical vapor deposition (PVD) method such as sputtering method, laser ablation method (also called laser sputtering method), vacuum evaporation method, etc., which can be performed in a state where hydrogen contained in the film forming material and atmosphere is very small or completely absent, is preferably used.

[0070] Next, after forming a conductive film having translucency on the gate insulating layer 4, a source electrode layer 5a and a drain electrode layer 5b are formed by a third photolithography process (see Fig. 1(A)). The conductive film having translucency is a conductive material having translucency to visible light, for example, In -Sn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn- O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Z n-O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system of metal oxides can be applied and the film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. Also, s​​​​​ When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO 2 is used to form a film, and SiOx (X>0) that inhibits crystallization is included in the conductive film having translucency, and then crystallization during the heat treatment for dehydration or dehydrogenation performed in the subsequent process is preferably suppressed.

[0071] Next, the gate insulating layer 4 is selectively etched by a fourth photolithography process to form a contact hole reaching the gate electrode layer 2b as shown in FIG. 1(B).

[0072] Next, an oxide semiconductor film having a thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 20 nm or less, is formed on the gate insulating layer 4. If the thickness of the oxide semiconductor film is made as thin as 50 nm or less, the oxide semiconductor film can be kept in an amorphous state even after the heat treatment for dehydration or dehydrogenation is performed later.

[0073] The oxide semiconductor film is an In-Ga-Zn-O-based, In-Sn-Zn-O-based, In-Al-Z n-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based oxide semiconductor film, an In-Zn-O-based, In-Ga-O-based, Sn-Zn-O-based, Al-Zn-O-based, In- O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. Further, the oxide semiconductor film can be formed by sputtering in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of an inert gas (typically argon ) and an oxygen atmosphere.

[0074] Also, when using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO 2 is used. ​​​​Film formation is carried out using this, and SiOx (X>0) that inhibits crystallization is included in the oxide semiconductor film. This is preferable because it can suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is preferable because it can be suppressed.

[0075] In this embodiment, an oxide semiconductor target containing In, Ga, and Zn (In:Ga: Zn = 1:1:0.5 [at%]) is used, and the distance between the substrate and the target is 100 m. m, the pressure is 0.6 Pa, the DC (direct current) power supply is 0.5 kW, and film formation is carried out in an oxygen (oxygen flow rate ratio 100%) atmosphere. When using a pulsed DC power supply, the powdery substances (also called particles) generated during film formation can be reduced, and the film thickness distribution becomes uniform, so it is preferable. In this embodiment, an In-Ga-Zn-O-based polycrystalline film with a film thickness of 15 nm is formed under the above conditions. is formed.

[0076] Sputtering methods include the RF sputtering method that uses a high-frequency power supply for the sputtering power supply and the DC sputtering method. There is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal conductive film. is used in the case of forming.

[0077] There is also a multi-target sputtering apparatus that can install a plurality of targets made of different materials. The multi-target sputtering apparatus can laminate and deposit different material films in the same chamber, or can simultaneously discharge and deposit multiple types of materials in the same chamber. There is also a reactive sputtering method that reacts the elements sputtered from the target material with the sputtering atmosphere. is formed.

[0078] There is also a sputtering apparatus that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber. There is also a sputtering apparatus that uses ECR sputtering using plasma generated using microwaves without using glow discharge. There is a sputtering method using a method.

[0079] In addition, as a film formation method using the sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, or during film formation There is also a bias sputtering method in which a voltage is also applied to the substrate. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0080] One of these methods may be adopted for the production of the oxide semiconductor film. Note that before forming the oxide semiconductor film by sputtering, reverse sputtering is performed by introducing argon gas to generate plasma, and moisture, organic matter, dust, etc. adhering to the surface of the gate insulating layer 4 are removed. This is preferable. Reverse sputtering is a method of applying a voltage using an RF power source on the substrate side instead of the target side to form plasma near the substrate and modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. Reverse sputtering is not limited to before forming the oxide semiconductor film, and may be performed before other film formation steps. film, and may be performed before other film formation steps. film, and may be performed before other film formation steps.

[0081] In this embodiment, the gate insulating layer is selectively etched by the fourth photolithography process to form a contact hole reaching the gate electrode layer 2b, but it is not particularly limited and a resist mask may be formed on the oxide semiconductor layer formed by etching the oxide semiconductor film, and a contact hole reaching the gate electrode layer 2b may be formed. In that case, reverse sputtering is performed to remove resist residues and the like adhering to the surfaces of the oxide semiconductor layer and the gate insulating layer 4. is performed to remove resist residues and the like adhering to the surfaces of the oxide semiconductor layer and the gate insulating layer 4. is performed to remove resist residues and the like adhering to the surfaces of the oxide semiconductor layer and the gate insulating layer 4. This is preferable.

[0082] Also, after forming an oxide semiconductor film on the gate insulating layer, a resist mask is formed on the oxide semiconductor film. After forming a contact hole reaching the gate electrode layer 2b, the resist mask is removed. Then, a resist mask is formed again on the oxide semiconductor film, and the oxide semiconductor film is selectively etched to be processed into an island-shaped oxide semiconductor layer. This may be used as a process.

[0083] In this embodiment, since the gate insulating layer 4 is selectively etched by the fourth photolithography process to form a contact hole reaching the gate electrode layer 2b, after contact formation , heating treatment (400 °C or higher) is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) to remove impurities such as hydrogen and water contained in the gate insulating layer 4 . After that, it is preferable to form an oxide semiconductor film.

[0084] Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer by the fifth photolithography process. Also, a resist mask for forming the island-shaped oxide semiconductor layer may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. The etching of the oxide semiconductor film may be wet etching or dry etching.

[0085] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CC l 4 ) etc.) is preferable.

[0086] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), nitrogen trifluoride (NF 3 ), trifluoromethane (CHF 3 ), etc.), hydrogen bromide (HBr ), oxygen (O 2 ), gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases, etc. can be used. As the dry etching method, a parallel plate type RIE (Reactive Ion Etch

[0087] ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that the desired processing shape can be etched.

[0088] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid can be used. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0089] In addition, the etching solution after wet etching is removed by washing together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0090] The etching conditions (etching Appropriately adjust the liquid, etching time, temperature, etc.

[0091] Next, perform dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment for performing dehydration or dehydrogenation is set to be 400°C or higher and less than 700°C, preferably 425°C or higher. Furthermore, if it is 425°C or higher, the heat treatment time may be 1 hour or less, but if it is less than 425°C, the heating treatment time should be longer than 1 hour.

[0092] Here, introduce the substrate into an electric furnace, which is one of the heat treatment apparatuses, and perform heat treatment on the oxide semiconductor layer in a nitrogen atmosphere. Then, without exposing it to the atmosphere, cool it to prevent re - mixing of water and hydrogen into the oxide semiconductor layer. In this embodiment, from the heating temperature for performing dehydration or dehydrogenation of the oxide semiconductor layer, keep using the same furnace until reaching a sufficient temperature where water does not enter again. Specifically, gradually cool it in a nitrogen atmosphere until the temperature drops by 100°C or more from the heating temperature. Also, it is not limited to a nitrogen atmosphere, and dehydration or dehydrogenation may be performed in a noble gas atmosphere (for example, helium, neon, argon, etc.).

[0093] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus can use halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high - pressure sodium lamps, high - pressure An apparatus for heating an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a mercury lamp It is. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, a noble gas such as argon, or an inert gas that does not react with the object to be processed by the heat treatment, such as nitrogen, is used. It is preferably free of water, hydrogen, hydrocarbons, etc. in the noble gas such as argon or in the nitrogen, helium, neon, argon, etc. used in the first heat treatment. Alternatively, the purity of the nitrogen or noble gas such as helium, neon, argon, etc. introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0094] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become a microcrystalline film or a polycrystalline film. Also, in the case of a microcrystalline film, the proportion of the crystalline component in the whole is 80% or more (preferably 90% or more), and it is preferably filled so that adjacent microcrystalline grains are in contact with each other. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, all of the oxide semiconductor layer may be in an amorphous state. After the first heat treatment, the oxide semiconductor layers 6a and 6b become oxygen-deficient type and have a lower resistance (see Fig. 1(B)). That is, after the first heat treatment, the carrier concentration increases compared to the oxide semiconductor film immediately after film formation, and preferably has a carrier concentration of 1×10 / cm or more, and becomes the oxide semiconductor layers 6a and 6b. 1 ppm or less, preferably 0.1 ppm or less).

[0095] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become a microcrystalline film or a polycrystalline film. Also, in the case of a microcrystalline film, the proportion of the crystalline component in the whole is 80% or more (preferably 90% or more), and it is preferably filled so that adjacent microcrystalline grains are in contact with each other. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, all of the oxide semiconductor layer may be in an amorphous state. After the first heat treatment, the oxide semiconductor layers 6a and 6b become oxygen-deficient type and have a lower resistance (see Fig. 1(B)). That is, after the first heat treatment, the carrier concentration increases compared to the oxide semiconductor film immediately after film formation, and preferably has a carrier concentration of 1×10 / cm or more, and becomes the oxide semiconductor layers 6a and 6b. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, all of the oxide semiconductor layer may be in an amorphous state. After the first heat treatment, the oxide semiconductor layers 6a and 6b become oxygen-deficient type and have a lower resistance (see Fig. 1(B)). That is, after the first heat treatment, the carrier concentration increases compared to the oxide semiconductor film immediately after film formation, and preferably has a carrier concentration of 1×10

[0096] After the first heat treatment, the oxide semiconductor layers 6a and 6b become oxygen-deficient type and have a lower resistance (see Fig. 1(B)). That is, after the first heat treatment, the carrier concentration increases compared to the oxide semiconductor film immediately after film formation, and preferably has a carrier concentration of 1×10 / cm or more, and becomes the oxide semiconductor layers 6a and 6b. 18 / cm 3 or more, and becomes the oxide semiconductor layers 6a and 6b. After the first heat treatment, the oxide semiconductor layers 6a and 6b become oxygen-deficient type and have a lower resistance (see Fig. 1(B)). That is, after the first heat treatment, the carrier concentration increases compared to the oxide semiconductor film immediately after film formation, and preferably has a carrier concentration of 1×10

[0097] Also, depending on the conditions of the first heat treatment or the material of the gate electrode layers 3a and 3b, the gate electrode layers 3a and 3b may crystallize and become a microcrystalline film or a polycrystalline film. For example, when using an indium tin oxide film as the gate electrode layers 3a and 3b, crystallization occurs with the first heat treatment at 450°C for 1 hour, and when using an indium tin oxide film containing silicon oxide as the gate electrode layers 3a and 3b, crystallization does not occur.

[0098] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heat treatment apparatus, and the fifth photolithography process is performed. As a result of the first heat treatment, the etching rate of the oxide semiconductor may decrease.

[0099] Next, after forming an oxide insulating film by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6a and 6b, a resist mask is formed by the sixth photolithography process, and selective etching is performed to form the oxide insulating layers 7a and 7b, and then the resist mask is removed (see Fig. 1(C)). At this stage, regions in contact with the oxide insulating layers 7a and 7b are formed in the oxide semiconductor layers 6a and 6b. Among these regions, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region 8a. Also, a first region 11c and a second region 11d overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer are also formed. Also, the formation of contact holes reaching the gate electrode layer 2b and the formation of contact holes reaching the drain electrode layer 5b are performed by the sixth photolithography process.

[0100] The oxide insulating film has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating film. In this embodiment, a silicon oxide film is formed as the oxide insulating film by using the sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and is set to 100 °C in this embodiment . The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen . Also, a silicon oxide target or a silicon target can be used as the target . . For example, silicon oxide can be formed by sputtering using a silicon target in an atmosphere of oxygen and a rare gas . The oxide insulating film formed in contact with the low-resistance oxide semiconductor layers 6a and 6b does not contain impurities such as moisture, hydrogen ions, and OH , and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used

[0101] . In this embodiment, a silicon target with a purity of 6N and columnar polycrystalline boron-doped (resistivity 0.01 Ωcm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, - the pressure is 0.4 Pa, a DC (direct current) power supply of 6 kW, and film formation is performed by pulsed DC sputtering in an oxygen (oxygen flow ratio 100%) atmosphere. The film thickness is 300 nm . .

[0102] . . . .

[0103] Next, a second heat treatment (preferably at 2 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, the end of the oxide semiconductor layer 6a overlapping the oxide insulating layer 7b and a part of the oxide semiconductor layer 6a overlapping the oxide insulating layer 7a are heated in a state of being in contact with the oxide insulating layer. When the second heat treatment is performed, a part of the oxide semiconductor layer that does not overlap the oxide insulating layer is heated in an exposed state. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 6a exposed, the resistance of that part can be further reduced. Also, the parts in contact with the oxide insulating layers 7a and 7b are supplied with oxygen (resulting in oxygen excess) and can be made highly resistive (type I conversion). Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer. The end of the oxide semiconductor layer 6a overlapping the oxide insulating layer 7b and a part of the oxide semiconductor layer 6a overlapping the oxide insulating layer 7a are heated in a state of being in contact with the oxide insulating layer. When the second heat treatment is performed, a part of the oxide semiconductor layer that does not overlap the oxide insulating layer is heated in an exposed state. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 6a exposed, the resistance of that part can be further reduced. Also, the parts in contact with the oxide insulating layers 7a and 7b are supplied with oxygen (resulting in oxygen excess) and can be made highly resistive (type I conversion). Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer.

[0104] When the second heat treatment is performed, a part of the oxide semiconductor layer that does not overlap the oxide insulating layer is heated in an exposed state. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 6a exposed, the resistance of that part can be further reduced. Also, the parts in contact with the oxide insulating layers 7a and 7b are supplied with oxygen (resulting in oxygen excess) and can be made highly resistive (type I conversion). Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 6a exposed, the resistance of that part can be further reduced. Also, the parts in contact with the oxide insulating layers 7a and 7b are supplied with oxygen (resulting in oxygen excess) and can be made highly resistive (type I conversion). Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 6a exposed, the resistance of that part can be further reduced. Also, the parts in contact with the oxide insulating layers 7a and 7b are supplied with oxygen (resulting in oxygen excess) and can be made highly resistive (type I conversion). Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 6a exposed, the resistance of that part can be further reduced. Also, the parts in contact with the oxide insulating layers 7a and 7b are supplied with oxygen (resulting in oxygen excess) and can be made highly resistive (type I conversion). Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 6a exposed, the resistance of that part can be further reduced. Also, the parts in contact with the oxide insulating layers 7a and 7b are supplied with oxygen (resulting in oxygen excess) and can be made highly resistive (type I conversion). Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer. Note that the oxide insulating layer 7a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 6a and functions as a channel protection layer.

[0105] Note that the timing of performing the second heat treatment is not limited to immediately after the end of the sixth photolithography process, and is not particularly limited as long as it is a process after the sixth photolithography process. Note that the timing of performing the second heat treatment is not limited to immediately after the end of the sixth photolithography process, and is not particularly limited as long as it is a process after the sixth photolithography process.

[0106] Next, after forming a conductive film on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer 6a, a resist mask is formed by a seventh photolithography process, and selective etching is performed to form a source electrode layer 9a and a drain electrode layer 9b (see Fig. 1(D)). Next, after forming a conductive film on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer 6a, a resist mask is formed by a seventh photolithography process, and selective etching is performed to form a source electrode layer 9a and a drain electrode layer 9b (see Fig. 1(D)). Next, after forming a conductive film on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer 6a, a resist mask is formed by a seventh photolithography process, and selective etching is performed to form a source electrode layer 9a and a drain electrode layer 9b (see Fig. 1(D)). Next, after forming a conductive film on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer 6a, a resist mask is formed by a seventh photolithography process, and selective etching is performed to form a source electrode layer 9a and a drain electrode layer 9b (see Fig. 1(D)).

[0107] Also, as shown in Fig. 1(D), a connection electrode layer 9c that is electrically connected to the gate electrode layer 2b and , a connection electrode layer 9d that is electrically connected to the drain electrode layer 5b is also formed. Film formation method of the conductive film uses a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method.

[0108] As the conductive film, an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above-described elements as components, or an alloy combining the above-described elements, etc. is used. The conductive film is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used. In this embodiment, a conductive film having a three-layer structure of a titanium film (film thickness: 100 nm), an aluminum film (film thickness: 200 nm), and a titanium film (film thickness: 100 nm) is formed. Also, a titanium nitride film may be used instead of the Ti film.

[0109] Also, in the seventh photolithography process, there is a portion for selectively removing only the conductive film in contact with the oxide semiconductor layer. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, an alkaline etchant such as ammonia peroxide (for example, a mixed solution of hydrogen peroxide : ammonia: water = 5:2:2) can be used to selectively remove the metal conductive film and leave the oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor.

[0110] Note that a resist mask for forming the source electrode layer 9a and the drain electrode layer 9b may be formed by an ink jet method. When the resist mask is formed by the ink jet method, since a photomask is not used, the manufacturing cost can be reduced.

[0111] By going through the above steps, the oxide semiconductor layers 6a and 6b are made to have a lower resistance, and the reduction of this lower resistance Selectively make a part of the formed region in an oxygen-excessive state. As a result, the channel formation region 8a in contact with the oxide insulating layer 7a becomes of type I, and the first region 11c and the second region 11d in contact with the oxide insulating layer 7b in the oxide semiconductor layer 6a become of type I, and a high-resistance source region 11a overlapping the source electrode layer 9a and a high-resistance drain region 11b overlapping the drain electrode layer 9b are self-alignedly formed. The channel formation region 8a in contact with the oxide insulating layer 7a becomes of type I, and the first region 11c and the second region 11d in contact with the oxide insulating layer 7b in the oxide semiconductor layer 6a become of type I, and a high-resistance source region 11a overlapping the source electrode layer 9a and a high-resistance drain region 11b overlapping the drain electrode layer 9b are self-alignedly formed. The channel formation region 8a in contact with the oxide insulating layer 7a becomes of type I, and the first region 11c and the second region 11d in contact with the oxide insulating layer 7b in the oxide semiconductor layer 6a become of type I, and a high-resistance source region 11a overlapping the source electrode layer 9a and a high-resistance drain region 11b overlapping the drain electrode layer 9b are self-alignedly formed. The channel formation region 8a in contact with the oxide insulating layer 7a becomes of type I, and the first region 11c and the second region 11d in contact with the oxide insulating layer 7b in the oxide semiconductor layer 6a become of type I, and a high-resistance source region 11a overlapping the source electrode layer 9a and a high-resistance drain region 11b overlapping the drain electrode layer 9b are self-alignedly formed. The channel formation region 8a in contact with the oxide insulating layer 7a becomes of type I, and the first region 11c and the second region 11d in contact with the oxide insulating layer 7b in the oxide semiconductor layer 6a become of type I, and a high-resistance source region 11a overlapping the source electrode layer 9a and a high-resistance drain region 11b overlapping the drain electrode layer 9b are self-alignedly formed.

[0112] Note that the formation ranges of the high-resistance source region 11a and the high-resistance drain region 11b are different according to the film thickness of the oxide semiconductor layer. When the film thickness of the oxide semiconductor layer is, for example, 15 nm or less, all the portions overlapping the source electrode layer, the drain electrode layer, or the conductive layer become regions of type N (N ), but when the film thickness of the oxide semiconductor layer is, for example, 30 nm to 50 nm, an N-type region is formed in the portion near the source electrode layer, the drain electrode layer, or the conductive layer in the portion overlapping the source electrode layer, the drain electrode layer, or the conductive layer, and an I-type region may be formed under the N-type region. ), but when the film thickness of the oxide semiconductor layer is, for example, 30 nm to 50 nm, an N-type region is formed in the portion near the source electrode layer, the drain electrode layer, or the conductive layer in the portion overlapping the source electrode layer, the drain electrode layer, or the conductive layer, and an I-type region may be formed under the N-type region. - ), but when the film thickness of the oxide semiconductor layer is, for example, 30 nm to 50 nm, an N-type region is formed in the portion near the source electrode layer, the drain electrode layer, or the conductive layer in the portion overlapping the source electrode layer, the drain electrode layer, or the conductive layer, and an I-type region may be formed under the N-type region. In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region. In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region. In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region. In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region.

[0113] In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region. In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region. In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region. In addition, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), the reliability when forming a drive circuit can be improved. Specifically, by forming the high-resistance drain region 11b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region 11b and the channel formation region. Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region (or the high-resistance source region) serves as a buffer and a local high electric field is not applied, and the transistor Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region (or the high-resistance source region) serves as a buffer and a local high electric field is not applied, and the transistor Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region (or the high-resistance source region) serves as a buffer and a local high electric field is not applied, and the transistor It can be configured to improve the pressure resistance.

[0114] Also, by forming the high-resistance drain region 11b (or the high-resistance source region 11a), it is possible to reduce the leakage current in the channel formation region 8a when the drive circuit is formed. It is possible.

[0115] Next, an insulating layer 10 is formed on the oxide insulating layers 7a, 7b, the source electrode layer 9a, the drain electrode layer 9b, the connection electrode layer 9c, and the connection electrode layer 9d (see Fig. 1(E)). As the insulating layer 10, a silicon nitride film, a silicon oxynitride film, aluminum nitride, or the like is used. In this embodiment form, the insulating layer 10 of a silicon nitride film is formed by using the RF sputtering method.

[0116] By the above steps, two types of thin-film transistors, a channel protection type thin-film transistor 12 and a bottom contact type thin-film transistor 13 can be fabricated on the same substrate.

[0117] For the channel protection type thin-film transistor 12, when the width of the oxide insulating layer 7a is narrowed, the channel length L can be shortened to 0.1 μm or more and 2 μm or less, and a thin-film transistor with a high operating speed can be realized. Also, the bottom contact type thin-film transistor 13 has a longer channel length than the channel protection type thin-film transistor 12, and a thin-film transistor with a reduced off-current can be realized. Furthermore, the bottom contact type thin-film transistor 13 is made of a material having translucency except for the connection electrode layer 9d. It is composed of a material having translucency.

[0118] When manufacturing an active matrix type display device, a plurality of thin-film transistors may be arranged in one pixel. For example, electrically connected to the pixel selection thin-film transistor, the pixel electrode Another thin film transistor connected to the pole or holding capacitance may be provided. Such a thin film transistor has a channel length L of 55 μm and a channel width W of 20 μm. On the other hand, for the pixel selection thin film transistor, the channel length L is preferably 25 μm and the channel width W is 60 μm. Note that the overlapping width of the source electrode layer and the gate electrode layer in the channel length direction is 5 μm, and the overlapping width of the drain electrode layer and the gate electrode layer in the channel length direction is 5 μm. It is preferable to use the structure of the bottom contact type thin film transistor 13 for any thin film transistor.

[0119] When a plurality of thin film transistors are provided in one pixel as described above, a power supply line electrically connected to the source electrode layer of the thin film transistor connected to the pixel is provided. The power supply line intersects the gate wiring and may be formed of the same material and in the same process as the connection electrode layer 9c made of a metal conductive film. Alternatively, the power supply line may intersect the source wiring and may be formed of the same material and in the same process as the gate electrode layer 2b.

[0120] When forming a drive circuit on the same substrate, for example, a channel protection type thin film transistor 12 is used, and the channel length L is preferably 2 μm and the channel width W is 50 μm. Note that the widths of the third region 11e and the fourth region 11f in the channel length direction are preferably 2 μm each. Also, the overlapping width of the source electrode layer and the gate electrode layer in the channel length direction is 2 μm, and the overlapping width of the drain electrode layer and the gate electrode layer in the channel length direction is 2 μm.

[0121] When forming a plurality of types of circuits on the same substrate, in this embodiment, a drive circuit and a pixel portion are formed. According to the characteristics of the drive circuit and the pixel portion respectively, a channel protection type thin film transistor 12 or a bottom contact type thin film transistor is used.​​​​​​​​​​ Optimization can be achieved by using a contact type thin film transistor 13.

[0122] This completes the active matrix circuit. The process will be explained with reference to Figs. 2(A) and (B).

[0123] First, a planarizing insulating layer 14 is formed on the insulating layer 10 of the silicon nitride film of the substrate fabricated up to FIG. The planarizing insulating layer 14 is formed to make the thickness of the liquid crystal layer uniform so that the liquid crystal display is uniform. This is provided for the purpose of reducing the noise generated by the driver circuit, and does not need to be provided in the driver circuit. As shown in FIG. 1, the driver circuit is not provided with a filter.

[0124] However, when forming a planarizing insulating layer, a method such as spin coating is used to coat the entire substrate. When the insulating layer is formed on the surface of the driving circuit, the insulating layer is then planarized by photolithography. In such a case, it is necessary to perform patterning and etching using a method such as the above. In order to simplify the process, the planarized insulating layer is intentionally left in the driving circuit area. This is also fine.

[0125] On the other hand, the patterning of the planarizing insulating layer does not require high accuracy, so the process is If it is judged that the use of the transparent conductive film formed thereafter will not result in a decrease in the yield, The dielectric material can also be used as a back gate for the thin film transistor in the driving circuit section.

[0126] In one embodiment of the present invention, a part of a thin film transistor and a wiring in a pixel region also have a light-transmitting property. It is made of materials, but in order to get the most out of it, it is necessary to shape it afterwards. It is preferable to make the area of the pixel electrode layer constituting it as large as possible. That is, the structure is such that the pixel electrode layer is provided on the thin film transistor and the wiring.

[0127] However, in such a structure, the parasitic capacitance between the thin film transistor and the pixel electrode layer or between the wiring and the pixel electrode layer becomes a problem. Therefore, attention must be paid to the selection of the material and thickness of the planarization insulating layer. That is, the planarization insulating layer is preferably as thick as possible and has a relative dielectric constant as small as possible.

[0128] As the material constituting the planarization insulating layer, for example, heat-resistant organic materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins , PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that a planarization insulating layer may be formed by laminating a plurality of insulating films formed of these materials.

[0129] The siloxane resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group.

[0130] The method for forming the planarization insulating layer 14 is not particularly limited, and depending on the material, sputtering method, SOG method, spin coating method, dip method, spray coating method, droplet ejection method (inkjet method, screen printing, offset printing, etc.), etc., and doctor knife, roll coater, Apparatuses such as a curtain coater and a knife coater can be used.

[0131] Also, the thickness is preferably 500 nm or more and 20 μm or less. In this embodiment, photosensitive acrylic is used as the planarization insulating layer 14 and formed with a thickness of 5 μm. The eighth photolithography process is performed to form contact holes that reach the source electrode layer 5a through the etching of the planarization insulating layer 14, the oxide insulating layer 7b, and the insulating layer 10.

[0132] Next, a conductive film having light transmittance is formed, the ninth photolithography process is performed, a resist mask is formed, and unnecessary portions are removed by etching to form the pixel electrode layer 15a, other pixel electrode layers 15b, and the pixel electrode layer 15c of an adjacent pixel on the planarization insulating layer 14, and further form a conductive layer 15d serving as the back gate of the thin film transistor in the drive circuit portion on the insulating layer 10, respectively. As shown in FIG. 2(A), the pixel electrode layers 15b and 15c are separated on the gate electrode layer 2b which is a metal wiring. By doing so, the light incident on the display portion can be used for display without being blocked as much as possible.

[0133] By providing the conductive layer 15d at a position overlapping the channel formation region 8a of the oxide semiconductor layer, the reliability of the thin film transistor can be improved. Generally, to examine the reliability of a thin film transistor, a bias - thermal stress test (hereinafter referred to as a BT test) is performed. Among those, a thin film transistor with a small change in the threshold voltage before and after this test has high reliability. In the thin film transistor having the above structure, the amount of change in the threshold voltage of the thin film transistor before and after the BT test can be reduced compared with others. Note that the conductive Layer 15d may have the same potential as the gate electrode layer 2a or a different potential, and can also function as the second gate electrode layer.

[0134] For example, the potential of the conductive layer 15d may be GND, 0V, or in a floating state. Furthermore, when the threshold values of the thin film transistors are different between substrates or within a substrate, the threshold value can be adjusted by adjusting the potential of this conductive layer 15d. .

[0135] Thereafter, a protective layer 16 that functions as an alignment film is formed of polyimide. Thus, the substrate on the active matrix side of the display device is completed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

[0136] When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. A common electrode that is electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a terminal that is electrically connected to the common electrode is provided. This terminal is a terminal for setting the common electrode to a fixed potential, such as GND, 0V, etc. .

[0137] Hereinafter, a method for manufacturing the counter substrate 30 will be described. A color filter layer 18 is formed on the glass substrate 17. The color filter is painted separately according to the pixel, but here it is shown integrally. As the glass substrate 17, it may be selected from those shown as appropriate for use on the substrate 1 of the active matrix substrate. Furthermore, a transparent conductive material is used to form a counter electrode 19 on the color filter layer 18. , a counter electrode 19, and a protective film 20 that functions as an alignment film are formed from polyimide.

[0138] Thus, a counter substrate 30 is obtained. Thereafter, the surface of the protective layer 1 6 on the surface of the active matrix substrate and the protective film 20 of the counter substrate 30 are subjected to rubbing treatment so that the liquid crystal is aligned. Thereafter, a liquid crystal layer 21 made of a liquid crystal material is sandwiched between the substrates and bonded together.

[0139] When bonding, the substrate 1 and the counter substrate 30 are sandwiched with a spacer (not shown) for adjusting the cell gap of the liquid crystal display device, and bonded with a sealing material (not shown). The above bonding step may be performed under reduced pressure. Thereby, the liquid crystal layer 21 is sandwiched and bonded by a sealing material (not shown) via a spacer (not shown) that adjusts the cell gap of the liquid crystal display device. The above bonding step may be performed under reduced pressure.

[0140] As the sealing material, it is typically preferable to use a visible light curable, ultraviolet curable, or thermosetting resin. Typically, an acrylic resin, an epoxy resin, an amine resin, etc. can be used. It is possible to use, for example, an acrylic resin, an epoxy resin, an amine resin, etc. Further, it may contain a photo (typically ultraviolet) polymerization initiator, a thermosetting agent, a filler, a coupling agent. And it may contain a photo (typically ultraviolet) polymerization initiator, a thermosetting agent, a filler, a coupling agent. The liquid crystal layer 21 is formed by enclosing a liquid crystal material in voids. As a method for forming the liquid crystal layer 21, a dispenser method (dropping method) of dropping before bonding the substrate 1 and the counter substrate 30 may be used,

[0141] or an injection method of injecting the liquid crystal using capillary action after bonding the substrate 1 and the counter substrate 30 can be used. The liquid crystal layer 21 is formed by enclosing a liquid crystal material in voids. As a method for forming the liquid crystal layer 21, a dispenser method (dropping method) of dropping before bonding the substrate 1 and the counter substrate 30 may be used, or an injection method of injecting the liquid crystal using capillary action after bonding the substrate 1 and the counter substrate 30 can be used. The liquid crystal material is not particularly limited, and various materials can be used. Also, when using a material that exhibits a blue phase as the liquid crystal material, the alignment treatment can be made unnecessary.

[0142] The liquid crystal material is not particularly limited, and various materials can be used. Also, when using a material that exhibits a blue phase as the liquid crystal material, the alignment treatment can be made unnecessary. The liquid crystal material is not particularly limited, and various materials can be used. Also, when using a material that exhibits a blue phase as the liquid crystal material, the alignment treatment can be made unnecessary.

[0143] A polarizing plate 22a is provided on the outer side of the substrate 1, and a polarizing plate 22b is provided on the outer side of the counter substrate 30. A transmissive liquid crystal display device in this embodiment can be manufactured (see FIG. 2B).

[0144] Although not shown in the present embodiment, a black matrix (light-shielding layer), a polarizing member, a phase Optical members (optical substrates) such as a polarizing member and an anti-reflection member are provided as appropriate. A circularly polarized light source using a retardation substrate may be used. A thread or the like may also be used.

[0145] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form A display pattern is formed on the screen by driving the selected pixel electrodes. By applying a voltage between the pixel electrode and the counter electrode corresponding to the pixel electrode, The liquid crystal layer arranged between the electrodes is optically modulated, and this optical modulation is observed as a display pattern. be recognized by observers.

[0146] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0147] In addition, by increasing the vertical sync frequency by 1.5 times or more, preferably by 2 times or more, the response speed can be improved. In addition, the gray scale to be written for each divided field in each frame is selected. There is also a driving technology called double speed driving, in which the speed is increased by 100 ps.

[0148] In addition, in order to improve the video characteristics of liquid crystal display devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is configured using a diode light source or a plurality of EL light sources, etc., and the surface light source is configured There is also a driving technique in which each light source that exists is driven to blink intermittently within one frame independently. As the surface light source, Three or more types of LEDs may be used, or white light-emitting LEDs may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of the LEDs can be synchronized according to the switching timing of the optical modulation of the liquid crystal layer. This driving technique can turn off the LEDs partially, so especially in the case of video display where the proportion of the black display area occupying one screen is large, The effect of reducing power consumption can be achieved.

[0149] By combining these driving techniques, display characteristics such as the video characteristics of the liquid crystal display device can be improved compared to the conventional ones.

[0150] In addition, the thin film transistor shown in this embodiment can also be applied to electronic paper. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of the same readability as paper, lower power consumption compared to other display devices, and being able to be made thin and light in shape.

[0151] Although various forms of electrophoretic displays are conceivable, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in a solvent or a solute, and by applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (colorless is also included).​​​​​​​​​​ shall be assumed to include).

[0152] Thus, the electrophoresis display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0153] A dispersion of the above microcapsules in a solvent is called electronic ink, and the electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using a color filter or particles having a pigment. A dispersion of the above microcapsules in a solvent is called electronic ink, and the electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using a color filter or particles having a pigment. A dispersion of the above microcapsules in a solvent is called electronic ink, and the electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using a color filter or particles having a pigment.

[0154] Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. As the active matrix substrate, for example, an active matrix substrate having a thin film transistor circuit described in the present embodiment can be used. Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. As the active matrix substrate, for example, an active matrix substrate having a thin film transistor circuit described in the present embodiment can be used. Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. As the active matrix substrate, for example, an active matrix substrate having a thin film transistor circuit described in the present embodiment can be used. Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. As the active matrix substrate, for example, an active matrix substrate having a thin film transistor circuit described in the present embodiment can be used. substrate can be used.

[0155] Note that the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. Note that the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. Note that the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. can be used.

[0156] FIG. 17 shows an active matrix type electronic paper using the thin film transistor of the present embodiment. The thin film transistor 13 used in the semiconductor device can be manufactured in the same manner as the thin film transistor shown in the present embodiment, and is a highly reliable thin film transistor including an oxide semiconductor layer. FIG. 17 shows an active matrix type electronic paper using the thin film transistor of the present embodiment. The thin film transistor 13 used in the semiconductor device can be manufactured in the same manner as the thin film transistor shown in the present embodiment, and is a highly reliable thin film transistor including an oxide semiconductor layer. FIG. 17 shows an active matrix type electronic paper using the thin film transistor of the present embodiment. The thin film transistor 13 used in the semiconductor device can be manufactured in the same manner as the thin film transistor shown in the present embodiment, and is a highly reliable thin film transistor including an oxide semiconductor layer. Yes. In addition, thin film transistors shown in other embodiments can also be used. Note that in FIG. 17, unless otherwise specified, the same reference numerals are used when referring to the same components as in FIG. 1 or FIG. 2.

[0157] The electronic paper in FIG. 17 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by disposing spherical particles painted white and black between a first electrode layer and a second electrode layer that are electrode layers using the display element, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0158] The thin film transistor 13 is a thin film transistor having a bottom gate structure and is covered with an oxide insulating layer 7b in contact with the semiconductor layer. The source electrode layer or drain electrode layer of the thin film transistor 13 is in contact with and electrically connected to the pixel electrode layer 15g of the active matrix through an opening formed in the planarization insulating layer 14. Between the pixel electrode layer 15g of the active matrix and the electrode layer 202 of the counter substrate 201, there are a black region 205a and a white region 205b, and spherical particles 204 including a cavity 206 filled with a liquid are provided around them, and the periphery of the spherical particles 204 is filled with a filler 203 such as resin. The electrode layer 202 of the counter substrate 201 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 13. Using a common connection portion, the second electrode layer 202 and the common potential line can be electrically connected through conductive particles disposed between the pair of substrates.

[0159] Also, instead of the twist ball, it is also possible to use an electrophoresis element. A transparent liquid and microcapsules with a diameter of about 10 μm to 20 μm encapsulating positively charged white fine particles and negatively charged black fine particles are used. The microcapsules provided between the first electrode layer and the second electrode layer are such that when an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. A display element applying this principle is an electrophoretic display element, which is generally called electronic paper . Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required , and also the power consumption is small, and it is possible to recognize the display portion even in a dim place. Also , even when no power is supplied to the display portion, it is possible to hold an image once displayed .

[0160] By the above steps, highly reliable electronic paper can be manufactured as a semiconductor device .

[0161] In this way, by forming various liquid crystal display devices with thin film transistors using an oxide semiconductor , the manufacturing cost can be reduced. In particular, by forming an oxide insulating film in contact with the oxide semiconductor layer by the above method, a thin film transistor having stable electrical characteristics can be manufactured and provided. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be provided .

[0162] In particular, since the semiconductor layer in the channel formation region of the thin film transistor 13 is a high resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current can be prevented. Thus , a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be obtained . ​​It becomes possible.

[0163] In addition, since the thin film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer.

[0164] For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are disposed so that a surge voltage is applied to the scanning line, the signal line, and the capacitance bus line due to static electricity or the like, and the pixel transistor or the like is not damaged.

[0165] Therefore, the protection circuit is configured to discharge the charge to the common wiring when a surge voltage is applied. In addition, the protection circuit is composed of non-linear elements arranged in parallel with the scanning line. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can be formed in the same process as the thin film transistor 13 of the pixel portion, and by connecting the gate terminal and the drain terminal, it can have characteristics similar to those of a diode.

[0166] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0167] (Embodiment 2) In this embodiment, a case where a transparent holding capacitor is formed using a wiring layer used for the thin film transistor of the present invention in an active matrix type liquid crystal display device will be described.

[0168] ​​​​​​​Figure 3 shows a circuit diagram of one pixel 31 of a general active matrix type liquid crystal display device. Here, wiring 36 is a wiring called a gate line, a column (row) line, or a scanning line, and is used to perform switching of the selection transistor 32 of the pixel. Also, wiring 35 is a wiring called a source line, a row (column) line, or a data line, and is used to send data to the pixel.

[0169] The transistor 32 of the pixel becomes on when a signal is sent to the wiring 36, and becomes off otherwise. While it is on, current flows between the source and drain of the transistor 32, but the current is blocked when it is off. Utilizing this characteristic, when a signal is passed through the wiring 35 while the transistor 32 is on, the signal passes through the transistor 32 and is stored in the liquid crystal element 33. The liquid crystal element 33 is a type of capacitor, and its light transmittance changes depending on the voltage generated by the charge held between it and the counter substrate 38. When the transistor 32 is turned off in this state, the voltage of the liquid crystal element 33 is maintained at a certain level to some extent.

[0170] The charge held in the liquid crystal element is desirably held constantly when the transistor 32 is off, but in reality, due to leakage current caused by the liquid crystal material and the transistor, it decreases over time. This causes problems such as display flickering. Therefore, in an actual active matrix type liquid crystal display device, a holding capacitor 34 is provided to minimize the influence of charge reduction.

[0171] The holding capacitor 34 is a capacitor, and one of its terminals is at a constant potential via the capacitor line 37. is designed to be maintained. In FIG. 3, the capacitance line 37 is shown to be arranged in parallel with the wiring 35, but it may be arranged in parallel with the wiring 36 or utilize the gate lines of pixels in other rows.

[0172] Conventionally, since the storage capacitance 34 was generally made of a metal material, it contributed to a decrease in the aperture ratio. Also, there have been attempts to form the storage capacitance with a transparent conductive material. However, in a conventional active matrix type liquid crystal display device, to form two or more transparent conductive layers, separate processes of deposition, photolithography, and etching are required, leading to a decrease in productivity.

[0173] In contrast, in one aspect of the present invention, since at least two layers of a transparent conductive material other than the pixel electrode layer are used, a transparent storage capacitance can be obtained without particularly requiring additional processes by forming the storage capacitance using this material. Hereinafter, the manufacturing process will be described with reference to FIG. 4. However, the basic manufacturing method is the same as that of Embodiment 1 except for the formation of the storage capacitance, so details such as materials and processing methods will be omitted. Also, when referring to the same components as in FIG. 1, the same reference numerals as those in FIG. 1 will be used. For these, reference may be made to Embodiment 1. Also, although the processing of some wirings and the formation of contact holes are not shown in FIG. 4, it may be understood that they are performed in the same manner as in Embodiment 1 and FIG. 1.

[0174] First, as in Embodiment 1, after forming a metallic conductive film on a substrate 1 having an insulating surface, the gate electrode layer 2a of the thin film transistor of the active matrix driving circuit is formed by the first photolithography process.

[0175] ​​​​​​ Next, after forming a conductive film having translucency over the gate electrode layer 2a, a second photolithography process is performed to form the gate electrode layer 3 d of the thin film transistor of the pixel of the active matrix and the electrode layer 3c serving as one electrode of the holding capacitor.

[0176] Next, a gate insulating layer 4 is formed over the gate electrode layer 2a, 3d, and the electrode layer 3c. After forming a conductive film having translucency over the gate insulating layer 4, a third photolithography process is performed to form the source electrode layer 5d, the drain electrode layer 5e of the thin film transistor of the pixel, and further the electrode layer 5c serving as the other electrode of the holding capacitor (see Fig. 4(A)). Thus, a capacitor is formed by the electrode layer 3c and the electrode layer 5c. The dielectric of this capacitor is the gate insulating layer 4 used as the gate insulator of the thin film transistor. The gate insulator of the thin film transistor is generally desired to have a high dielectric constant and be thin,

[0177] but the purpose generally coincides with that of the holding capacitor. However, since it is desired that the holding capacitor has a small leakage current, a thickness and a material suitable therefor are required. Next, the gate insulating layer 4 is selectively etched by a fourth photolithography process to form a contact hole reaching the gate electrode layer 2b as shown in Fig. 1(B), but this process is not shown in Fig. 4. Next, an oxide semiconductor film having a film thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more

[0178] and 20 nm or less is formed over the gate insulating layer 4. The thickness of the oxide semiconductor film is set to 50 nm or less.

[0179] ​​​​Even if a heat treatment for dehydration or dehydrogenation is then performed, the oxide semiconductor film remains amorphous. The state can be maintained.

[0180] Next, as shown in FIG. 4(B), the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 6a and 6c by a fifth photolithography process. The oxide semiconductor film can be etched by wet etching or dry etching. Next, dehydration or dehydrogenation of the oxide semiconductor layer as shown in Embodiment 1 is performed. Next, dehydration or dehydrogenation of the oxide semiconductor layer as shown in Embodiment 1 is performed. Next, dehydration or dehydrogenation of the oxide semiconductor layer as shown in Embodiment 1 is performed.

[0181] Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4, the oxide semiconductor layers 6a and 6c, the source electrode layer 5d, the drain electrode layer 5e, and the electrode layer 5c that serves as the other electrode of the storage capacitor. Then, a resist mask is formed by a sixth photolithography process. Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4, the oxide semiconductor layers 6a and 6c, the source electrode layer 5d, the drain electrode layer 5e, and the electrode layer 5c that serves as the other electrode of the storage capacitor. Then, a resist mask is formed by a sixth photolithography process. Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4, the oxide semiconductor layers 6a and 6c, the source electrode layer 5d, the drain electrode layer 5e, and the electrode layer 5c that serves as the other electrode of the storage capacitor. Then, a resist mask is formed by a sixth photolithography process. Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4, the oxide semiconductor layers 6a and 6c, the source electrode layer 5d, the drain electrode layer 5e, and the electrode layer 5c that serves as the other electrode of the storage capacitor. Then, a resist mask is formed by a sixth photolithography process. Selective etching is performed to form the oxide insulating layers 7a and 7b, and then the resist mask is removed (see FIG. 4(C)).

[0182] Next, a metallic conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. Then, a resist mask is formed by a seventh photolithography process, and selective etching is performed to form the source electrode layer 9a and the drain electrode layer 9b (see FIG. 4(D)). Next, a metallic conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. Then, a resist mask is formed by a seventh photolithography process, and selective etching is performed to form the source electrode layer 9a and the drain electrode layer 9b (see FIG. 4(D)). Next, a metallic conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. Then, a resist mask is formed by a seventh photolithography process, and selective etching is performed to form the source electrode layer 9a and the drain electrode layer 9b (see FIG. 4(D)). Also, as shown in FIG. 4(D), a connection electrode layer 9g that is electrically connected to the electrode layer 5c, a connection electrode layer 9f that is electrically connected to the source electrode layer 5d of the thin film transistor of the pixel, and a connection electrode layer 9e that is electrically connected to the drain electrode layer 5e are also formed. Also, as shown in FIG. 4(D), a connection electrode layer 9g that is electrically connected to the electrode layer 5c, a connection electrode layer 9f that is electrically connected to the source electrode layer 5d of the thin film transistor of the pixel, and a connection electrode layer 9e that is electrically connected to the drain electrode layer 5e are also formed. Also, as shown in FIG. 4(D), a connection electrode layer 9g that is electrically connected to the electrode layer 5c, a connection electrode layer 9f that is electrically connected to the source electrode layer 5d of the thin film transistor of the pixel, and a connection electrode layer 9e that is electrically connected to the drain electrode layer 5e are also formed.

[0183] Next, on the oxide insulating layers 7a and 7b, the source electrode layer 9a, the drain electrode layer 9b, and the connection electrode layer An insulating layer 10 is formed on 9e, 9f, and 9g (see Fig. 4(E)).

[0184] Through the above steps, a channel protection type thin film transistor 1 used for a driving circuit, a bottom contact type thin film transistor 42 used for a pixel, and a holding capacitor 41 of the pixel can be fabricated.

[0185] In the above steps, the connection electrode layer 9e connected to the drain electrode layer of the thin film transistor of the pixel is provided, which is different in structure from the thin film transistor shown in Fig. 1, but this does not increase the number of steps here. The reason for providing the connection electrode layer 9e is for the connection of the holding capacitor in this embodiment and will be described later in detail.

[0186] Also, in Fig. 4(E), the connection electrode layer 9g is drawn large so as to cover most of the holding capacitor 41, but only a very limited part of this is necessary, so most of the holding capacitor can be formed of a light-transmissive material.

[0187] In the holding capacitor fabricated in this embodiment, one electrode layer 3c is formed in the same layer as the gate electrode layer 3d of the thin film transistor of the pixel, and the connection electrode layer 9g connected to the other electrode layer 5c is formed in the same layer as the connection electrode layer 9e on the drain side of the thin film transistor of the pixel. As is clearer from Fig. 1, the gate electrode layer 3b (the same as the gate electrode layer 3d in Fig. 4) is connected to the gate electrode layer 2b (gate wiring layer) made of a metal material. Therefore, for example, the gate electrode layer 3d can be connected to a wiring layer in the same layer as the gate electrode layer 2b (gate wiring layer) in Fig. 1 and this can be used as the capacitance line 37 in Fig. 3. In this case, different from what is shown in Fig. 3, it can also be done. ​The capacitance line may be configured to be parallel to the wiring 36. In this case, the thin film of the pixel It is not necessary to provide the connection electrode layer 9e connected to the drain electrode layer of the transistor.

[0188] Also, the connection electrode layer 9g connected to the electrode layer 5c is the same layer as the connection electrode layer 9f on the source side of the thin film transistor of the pixel. Since the connection electrode layer 9f directly becomes the wiring 35 in FIG. 3, similar to the capacitance line 37 in FIG. 3, it can also be arranged parallel to the wiring 35. In this case, the other electrode layer 5c needs to be connected to the drain electrode layer 5e of the thin film transistor. This is because it is the same layer as the connection electrode layer 9e, and the wiring shown as the connection electrode layer 9c in FIG. 1 is connected to the gate electrode layer 3b of the same layer as the electrode layer 3c via the metallic gate electrode layer 2b. It is obvious that this can be easily achieved.

[0189] Regarding the active matrix type liquid crystal display device having the holding capacitance as described above, further the wiring intersection portion and the capacitance portion (holding capacitance) will also be illustrated and described. FIG. 6 is a cross-sectional view showing the state of the substrate before forming the planarization insulating layer in Embodiment 1. Note that the same reference numerals will be used for the same components as those in FIGS. 1 and 2.

[0190] In FIG. 6, the thin film transistor of the pixel is a bottom contact type thin film transistor 13. In the pixel portion, as shown in FIG. 6, a holding capacitance composed of the electrode layer 3c and the electrode layer 5c is formed. The holding capacitance shown in FIG. 6 uses the gate insulating layer 4 as a dielectric.

[0191] Also, in the wiring intersection portion, in order to reduce the parasitic capacitance as shown in FIG. 6, between the gate wiring layer 2c and the source wiring layer 9h, the gate insulating layer 4 and the oxide insulating layer 7b are laminated. is used. In FIG. 6, an example in which the gate wiring layer 2c is a metal conductive film is shown, but if the wiring resistance is not a problem, or if the material has a sufficiently low sheet resistance (for example, silver nano wire ear, etc.), it can also be formed using a conductive film having the same light transmittance as the gate electrode layer 3a of the thin film transistor 13.

[0192] Next, a VA type (Vertical Alignment type, vertical alignment type) liquid crystal display device different from that of the first embodiment will be described with reference to FIGS. 14 to 16.

[0193] FIG. 14 shows the pixel structure of the VA type liquid crystal display panel. FIG. 15 shows the configuration of the counter electrode. Further, FIG. 16 is a circuit diagram of one pixel. In the following description, these drawings will be referred to for explanation.

[0194] This pixel structure has a plurality of pixel electrodes in one pixel, and thin film transistors are connected to each pixel electrode. Each thin film transistor is configured to be driven by a different gate signal. That is, in pixels designed with a multi-domain, the signals applied to individual pixel electrodes have a configuration in which they are independently controlled.

[0195] The thin film transistor 628 and the thin film transistor 629 are both connected to the wiring 690 and the wiring 616. The pixel electrode 624 is connected to the thin film transistor 628 by the wiring 618 at the contact hole 623. Further, the pixel electrode 626 is connected to the thin film transistor 629 by the wiring 619 at the contact hole 627. The gate of the thin film transistor 628 ​​​​​​​​​The gate wiring 602 and the gate wiring 603 of the thin film transistor 629 are separated so that different gate signals can be applied. On the other hand, the wiring 616 that functions as a data line is commonly used by the thin film transistor 628 and the thin film transistor 629. Also, parallel to the pixel electrode, wiring for the holding capacitor shown in this embodiment may be provided. The thin film transistors 628 and 629 may be appropriately used with thin film transistors shown in other embodiments in addition to the thin film transistors shown in this embodiment.

[0196] The shapes of the pixel electrodes 624 and 626 are different and are separated by a slit The pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape . By varying the timing of the voltages applied to the pixel electrodes 624 and 626 by the thin film transistors 6 28 and 629, the alignment of the liquid crystal is controlled. An equivalent circuit of this pixel structure is shown in FIG. 16. The thin film transistor 628 is connected to the gate wiring 602 and the thin film transistor 629 is connected to the gate wiring 603. By applying different gate signals to the gate wiring 602 and the gate wiring 603, the operation timings of the thin film transistor 628 and the thin film transistor 629 can be made different.

[0197] FIG. 15 shows the structure on the counter substrate side. On the counter substrate, a color filter layer and a counter electrode are formed as shown in Embodiment 1 and FIG. 2(B). In order to prevent the alignment disorder of the liquid crystal, it is desirable to provide a planarization film between the color filter layer and the counter electrode. The counter electrode 640 shown in FIG. 15 is an electrode that is shared between different pixels, but a slit 641 is formed ​​is formed. By arranging the slit 641 and the slits on the pixel electrode 624 and pixel electrode 626 sides to alternately engage with each other, an oblique electric field is effectively generated to control the alignment of the liquid crystal. This enables the direction in which the liquid crystal aligns to vary depending on the location, and the viewing angle can be widened.

[0198] The first liquid crystal element 651 is formed by the overlap of the pixel electrode 624, the liquid crystal layer, and the counter electrode 640. Also, the second liquid crystal element 652 is formed by the overlap of the pixel electrode 626, the liquid crystal layer, and the counter electrode 640. That is, it is a multi-domain structure in which the first liquid crystal element 651 and the second liquid crystal element 652 are provided in one pixel.

[0199] (Embodiment 3) In this embodiment, the appearance and cross-section of the active matrix liquid crystal display panel will be described with reference to FIG. 7. FIG. 7(A) is a plan view of the panel in which liquid crystal is sealed with a sealing material between a first substrate having an active matrix circuit composed of thin film transistors and a second substrate (counter substrate). FIG. 7(B) corresponds to a cross-sectional view taken along H-I of FIG. 7(A) and includes the structure shown in FIG. 2(B).

[0200] A sealing material 75 is provided so as to surround the pixel portion 72, the signal line driver circuits 73a and 73b, and the scanning line driver circuits 74a and 74b provided on the first substrate 71. Also, a second substrate 76 is provided on the pixel portion 72, the signal line driver circuits 73a and 73b, and the scanning line driver circuits 74a and 74b. Therefore, the pixel portion 72, the signal line driver circuits 73a and 73b, and the scanning line driver circuits 74a and 74b are formed by the first substrate 71, the sealing material 75, and the second substrate 76. ​​​​​​​​It is sealed together with the liquid crystal 78. In this way, it has high airtightness so as not to be exposed to the outside air. , it is preferable to package (enclose) it with a protective film with little outgassing (such as a laminated film, an ultraviolet curable resin film, etc.) or a cover material.

[0201] Also, the pixel portion 72, the signal line drive circuits 73a and 73b, and the inspection line drive circuits 74a and 74b provided on the first substrate 71 have a plurality of thin film transistors. In FIG. 7(B), the thin film transistor 80 included in the pixel portion 72 and the thin film transistor 79 included in the signal line drive circuit 73a are illustrated. Further, a holding capacitor 81 is also illustrated in the pixel portion 72. . For these, those described in Embodiment 1 or 2 may be used. Regarding the configurations such as each transistor, etc., their descriptions may also be referred to.

[0202] The various signals and potentials given to the signal line drive circuits 73a and 73b, the scan line drive circuits 74a and 74b, or the pixel portion 72 are supplied from the FPCs 77a and 77b.

[0203] The connection terminal electrode 82 is formed of the same conductive film as the pixel electrode layer 83, and the terminal electrode 84 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistor 79.

[0204] The connection terminal electrode 82 is electrically connected to the terminal of the FPC 77a via the anisotropic conductive film 85.

[0205] The signal line drive circuits 73a and 73b, and the scan line drive circuits 74a and 74b are mounted with drive circuits formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. This is also acceptable. Additionally, only the signal line driving circuit, or a part thereof, or only the scanning line driving circuit, or a part thereof may be separately formed and implemented, and it is not limited to the configuration of FIG. 7. This is not limited to the configuration of FIG. 7 and may be implemented by separately forming only the signal line driving circuit, or a part thereof, or only the scanning line driving circuit, or a part thereof.

[0206] An example of the configuration of the terminal portion of the active matrix liquid crystal device as described above is shown in FIG. 5. Note that in FIG. 5, the same reference numerals are used to describe the same portions as in FIGS. 1, 2, and 6.

[0207] FIGS. 5(A1) and 5(A2) respectively show a cross-sectional view and a top view of the gate wiring terminal portion. FIG. 5(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 5(A2). In FIG. 5 (A1), the conductive layer 15e formed on the stack of the insulating layer 10 and the protective layer 16 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 5(A1), in the terminal portion, the first terminal 2d formed of the same material as the gate wiring layer 2c and the connection electrode layer 9i formed of the same material as the source wiring layer 9h overlap via the gate insulating layer 4 and are electrically connected by the conductive layer 15e. Further, the conductive layer 15e has the same light-transmitting property as the pixel electrode layer 15a and can be formed in the same process. process. process. process.

[0208] Also, FIGS. 5(B1) and 5(B2) respectively show a cross-sectional view and a top view of the source wiring terminal portion. Also, FIG. 5(B1) corresponds to a cross-sectional view taken along line C3-C4 in FIG. 5(B2). In FIG. 5(B1), the conductive layer 15f formed on the stack of the insulating layer 10 and the protective layer 16 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 5(B1), in the terminal portion, the electrode layer 2e formed of the same material as the gate wiring layer 2c overlaps via the gate insulating layer 4 below the second terminal 9j that is electrically connected to the source wiring. The electrode layer 2 corresponding to a cross-sectional view taken along line C3-C4 in FIG. 5(B2). In FIG. 5(B1), the conductive layer 15f formed on the stack of the insulating layer 10 and the protective layer 16 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 5(B1), in the terminal portion, the electrode layer 2e formed of the same material as the gate wiring layer 2c overlaps via the gate insulating layer 4 below the second terminal 9j that is electrically connected to the source wiring. The electrode layer 2 layer 15f formed on the stack of the insulating layer 10 and the protective layer 16 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 5(B1), in the terminal portion, the electrode layer 2e formed of the same material as the gate wiring layer 2c overlaps via the gate insulating layer 4 below the second terminal 9j that is electrically connected to the source wiring. The electrode layer 2 layer 15f formed on the stack of the insulating layer 10 and the protective layer 16 is a connection terminal electrode that functions as an input terminal. Also, in FIG. 5(B1), in the terminal portion, the electrode layer 2e formed of the same material as the gate wiring layer 2c overlaps via the gate insulating layer 4 below the second terminal 9j that is electrically connected to the source wiring. The electrode layer 2 is electrically connected to the source wiring and overlaps below the second terminal 9j via the gate insulating layer 4. The electrode layer 2 e is not electrically connected to the second terminal 9j, and the electrode layer 2e is set to a potential different from that of the second terminal 9j, for example, floating, GND, 0V, etc., so that a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 9j is electrically connected to the conductive layer 15f via the insulating layer 10 and the protective layer 16. Further, the conductive layer 15 f can be formed of the same light-transmissive material as the pixel electrode layer 15a and in the same process.

[0209] A plurality of gate wirings, source wirings, common potential lines, and power supply lines are provided according to the pixel density. Also, in the terminal portion, a first terminal having the same potential as the gate wiring, a second terminal having the same potential as the source wiring, a third terminal having the same potential as the power supply line, a fourth terminal having the same potential as the common potential line, etc. are arranged side by side. The number of each terminal can be set to an arbitrary number, and the implementer can make an appropriate decision.

[0210] Next, an example of a block diagram of an active matrix type display device having such a connection is shown in Fig. 9(A). On the substrate 90 of the display device, there are a pixel portion 91, a first scanning line driving circuit 9 2, a second scanning line driving circuit 93, and a signal line driving circuit 94. In the pixel portion 91, a plurality of signal lines extend from the signal line driving circuit 94 and are arranged, and a plurality of scanning lines extend from the first scanning line driving circuit 9 2 and the second scanning line driving circuit 93 and are arranged.

[0211] In the intersection region of the scanning line and the signal line, pixels each having a display element are arranged in a matrix. Also, the substrate 90 of the display device is connected to a timing control circuit 95 (controller, control via a connection portion such as an FPC (Flexible Printed Circuit). (also referred to as an IC).

[0212] In FIG. 9(A), the first scanning line driving circuit 92, the second scanning line driving circuit 93, and the signal line driving circuit 94 are formed on the same substrate 90 as the pixel portion 91. Therefore, the number of components such as the driving circuit provided outside is reduced, so that the cost can be reduced. In addition, the number of connections at the connection portion due to extending the wiring when a driving circuit is provided outside the substrate 90 can be reduced, and the reliability or the yield can be improved. Note that the timing control circuit 95 supplies, as an example, a first start signal (GSP1) for the first scanning line driving circuit and a clock signal (GCK1) for the scanning line driving circuit to the first scanning line driving circuit 92. Further, the timing control circuit 95 supplies, as an example, a second start signal (GSP2) (also referred to as a start pulse) for the second scanning line driving circuit and a clock signal (GCK2) for the scanning line driving circuit to the second scanning line driving circuit 93. The signal line driving circuit 94 is supplied with a start signal (SSP) for the signal line driving circuit, a clock signal (SCK) for the signal line driving circuit, video signal data (simply referred to as a video signal), and a latch signal (LAT). Each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that it is possible to omit one of the first scanning line driving circuit 92 and the second scanning line driving circuit 93. In FIG. 9(B), a circuit with a low driving frequency (for example, the first scanning line driving circuit 92, the second scanning line driving circuit 93)

[0213]

[0214] ​​​​​​​​​​​​​The wiring drive circuit 93) is formed on the same substrate 90 as the pixel portion 91, and the signal line drive circuit 94 is formed on a substrate different from the pixel portion 91. Such a configuration is shown. With such a configuration, it is possible to increase the size of the display device and speed up the display.

[0215] Also, the thin film transistors of the drive circuit shown in Embodiment 1 are n-channel type thin film transistors . In FIGS. 10(A) and 10(B), an example of the configuration and operation of a signal line drive circuit composed of n-channel type thin film transistors will be shown and explained.

[0216] The signal line drive circuit has a shift register 101 and a switching circuit section 102. The switching circuit 102 has a plurality of circuits such as switching circuits 102_1 to 102_N (N is a natural number). The switching circuits 102_1 to 102_N each have a plurality of transistors such as thin film transistors 103_1 to 103_k (k is a natural number). The thin film transistors 103_1 to 103_k will be described as an example of n-channel type thin film transistors.

[0217] The connection relationship of the signal line drive circuit will be described by taking the switching circuit 102_1 as an example. The drains of the thin film transistors 103_1 to 103_k are each connected to wirings 104_1 to 104 _k. The sources of the thin film transistors 103_1 to 103_k are each connected to signal lines S1 to Sk. The gates of the thin film transistors 103_1 to 103_k are connected to wiring 1 05_1.

[0218] The shift register 101 outputs signals of H level (also referred to as H signal, high power supply potential level) to the wirings 105_1 to 105_N in order, and the switching circuits 102_1 to 102_N are thereby controlled. It has a function of selecting in order.

[0219] The switching circuit 102_1 controls the conduction state (conduction between the source and the drain) of the wirings 104_1 to 104_k and the signal lines S1 to Sk, that is, it has a function of controlling whether to supply the potentials of the wirings 104_1 to 104_k to the signal lines S1 to Sk. Thus, the switching circuit 102_1 has a function as a selector. Note that video signal data (DATA) is input to each of the wirings 104_1 to 104_k. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal. Next, the operation of the signal line driving circuit in Fig. 10(A) will be described with reference to the timing chart in Fig. 10(B). Fig. 10(B) shows an example of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 101, and the signals Vdata_1 to Vdata_k are each an example of the signals input to the wirings 104_1 to 104_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row. It should be noted that in the drawings and the like of this embodiment, the blurring of the signal waveforms of each component shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0220] Furthermore, video signal data (DATA) is input to each of the wirings 104_1 to 104_k. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal. Moreover, video signal data (DATA) is input to each of the wirings 104_1 to 104_k. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal. It is often the case.

[0221] Next, regarding the operation of the signal line driving circuit in Fig. 10(A), it will be described with reference to the timing chart in Fig. 10(B). Fig. 10(B) shows an example of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 101, and the signals Vdata_1 to Vdata_k are each an example of the signals input to the wirings 104_1 to 104_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row. In Fig. 10(B), an example of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k is shown. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 101, and the signals Vdata_1 to Vdata_k are each an example of the signals input to the wirings 104_1 to 104_k. respectively. k are each an example of the signals input to the wirings 104_1 to 104_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row.

[0222] Note that in the drawings and the like of this embodiment, the blurring of the signal waveforms of each component shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. It is noted that it is so.

[0223] During periods T1 to TN, the shift register 101 outputs a signal of H level to wirings 105_ 1 to 105_N in order. For example, during period T1, the shift register 101 outputs a high-level signal to wiring 105_1. Then, since the thin film transistors 103_1 to 103_k turn on, wirings 104_1 to 104_k and signal lines S1 to Sk become conductive states. At this time, Data(S1) to Da ta(Sk) are input. Data(S1) to Data(Sk) are respectively the first to kth columns among the pixels belonging to the selected row via the thin film transistors 103_1 to 103_k and are written to the pixels. In this way, during periods T1 to TN, video signal data (DATA) is written to the pixels belonging to the selected row in order of k columns at a time.

[0224] As described above, by writing video signal data (DATA) to the pixels in multiple columns at a time, the number of video signal data (DATA) or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced. Also, by writing the video signal to the pixels in multiple columns at a time, the writing time can be lengthened, and insufficient writing of the video signal can be prevented.

[0225] Note that as the shift register 101 and the switching circuit section 102, a circuit composed of the thin film transistors shown in Embodiment 1 or 2 can be used. In this case, all the transistors of the shift register 101 can be configured with only one of the polarities of N-channel type or P-channel type. ​

[0226] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register and may also have a level shifter, a buffer, etc. in some cases. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. To the scanning line, the gate electrodes of the transistors of one line of pixels are connected. And since the transistors of one line of pixels must be turned on all at once, a buffer capable of passing a large current is used

[0227] A form of the shift register used in part of the scanning line driving circuit and / or the signal line driving circuit will be described with reference to FIGS. 11 and 12. The shift register has a first pulse output circuit 110_1 to an Nth pulse output circuit 110_N (N is a natural number of 3 or more) (see FIG. 11(A)).

[0228] To the first pulse output circuit 110_1 to the Nth pulse output circuit 110_N of the shift register shown in FIG. 11(A), a first clock signal CK1 is supplied from a first wiring 111, a second clock signal CK2 is supplied from a second wiring 112, a third clock signal CK3 is supplied from a third wiring 113, and a fourth clock signal CK4 is supplied from a fourth wiring 114

[0229] Also, in the first pulse output circuit 110_1, a start pulse SP1 (first start pulse) from a fifth wiring 115 is input. Also, in the nth pulse output circuit 11 from the second stage onward ​​​​​​​​​​​For 0_n (where n is a natural number from 2 to N), a signal (referred to as the previous-stage signal OUT(n - 1)) from the pulse output circuit 110_(n - 1) one stage before is input. ) is input.

[0230] Also, in the first pulse output circuit 110_1, a signal from the third pulse output circuit 110_3 two stages after is input. Similarly, in each pulse output circuit 110_n from the second stage onwards, a signal (referred to as the subsequent-stage signal OUT (n + 2)) from the (n + 2)-th pulse output circuit 110_(n + 2) two stages after is input. Therefore, from the n-th pulse output circuit, the first output signals OUT(1)(SR ) to OUT(N)SR for input to the subsequent-stage and / or the pulse output circuit two stages before, and the second output signals OUT(1) to OUT(N) that are electrically input to another circuit or the like are output. / Or, since the subsequent-stage signal O UT(n + 2) is not input to the two final stages of the shift register as shown in Fig. 11(A), as an example, a configuration may be adopted in which a second start pulse SP2 and a third start pulse SP3 are separately input.

[0231] Note that, as shown in Fig. 11(A), since the subsequent-stage signal O UT(n + 2) is not input to the two final stages of the shift register, as an example, a configuration may be adopted in which a second start pulse SP2 and a third start pulse SP3 are separately input.

[0232] Note that the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle (i.e., their phases are shifted by 90 ° from each other). In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal may also be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as C K. K.

[0233] Each of the first pulse output circuit 110_1 to the Nth pulse output circuit 110_N has a first input terminal 121, a second input terminal 122, a third input terminal 123, a fourth input terminal 124, a fifth input terminal 125, a first output terminal 126, and a second output terminal 127 (see Fig. 11(B)). The first input terminal 121, the second input terminal 122, and the third input terminal 123 are electrically connected to any one of the first wiring 111 to the fourth wiring 114.

[0234] For example, in Fig. 11(A), in the first pulse output circuit 110_1, the first input terminal 1 21 is electrically connected to the first wiring 111, the second input terminal 122 is electrically connected to the second wiring 112 , and the third input terminal 123 is electrically connected to the third wiring 113. Also, in the second pulse output circuit 110_2, the first input terminal 121 is electrically connected to the second wiring 11 2, the second input terminal 122 is electrically connected to the third wiring 113, and the third input terminal 123 is electrically connected to the fourth wiring 114.

[0235] In the first pulse output circuit 110_1, a first clock signal CK1 is input to the first input terminal 121, a second clock signal CK2 is input to the second input terminal 122, a third clock signal CK3 is input to the third input terminal 123, a start pulse is input to the fourth input terminal 124, a subsequent stage signal OUT(3) is input to the fifth input terminal 125, a first output signal OUT(1)(SR) is output from the first output terminal 126, and a second output signal OUT(1) is output from the second output terminal 127.

[0236] ​​ In addition to the three-terminal thin film transistors, the first pulse output circuit 110_1 to the Nth pulse output circuit 110_N can use the thin film transistors with a back gate described in the first embodiment above. Figure 11(C) shows the symbol of the thin film transistor 128 with a back gate described in the above embodiment. The symbol of the thin film transistor 128 shown in Figure 11(C) represents the thin film transistor with a back gate described in the first embodiment above, and will be used in the drawings hereinafter. In this specification, when a thin film transistor has two gate electrodes via a semiconductor layer, the gate electrode below the semiconductor layer is also referred to as the lower gate electrode, and the gate electrode above the semiconductor layer with respect to the semiconductor layer is also referred to as the upper gate electrode. The thin film transistor 128 is an element that can perform electrical control between the In terminal and the Out terminal by the first control signal G1 input to the lower gate electrode and the second control signal G2 input to the upper gate electrode. When an oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor, the threshold voltage may shift to the negative side or the positive side during the manufacturing process. Therefore, for a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region, a configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the thin film transistor 128 shown in Figure 11(C) can be controlled to a desired value by providing gate electrodes via gate insulating films above and below the channel formation region of the thin film transistor 128 and controlling the potentials of the upper and / or lower gate electrodes.

[0237]

[0238] ​​​​​​​​​​​​Next, an example of the specific circuit configuration of the pulse output circuit will be described with reference to FIG. 11(D).

[0239] The first pulse output circuit 110_1 includes the first transistor 131 to the thirteenth transistor 143 (see FIG. 11(D)). In addition to the first input terminal 121 to the fifth input terminal 125, and the first output terminal 126 and the second output terminal 127, a power supply line 151 to which the first high power supply potential VDD is supplied, a power supply line 152 to which the second high power supply potential VCC is supplied, and a power supply line 153 to which the low power supply potential VSS is supplied, signals or power supply potentials are supplied to the first transistor 131 to the thirteenth transistor 143. Here, in FIG. 11(D), the magnitude relationship of the power supply potentials of the respective power supply lines is such that the first power supply potential VDD is equal to or higher than the second power supply potential VCC in potential, and the second power supply potential VCC is higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are at VDD when at the H level and at VSS when at the L level. As shown in FIG. 11(D), among the first transistor 131 to the thirteenth transistor 143, for the first transistor 131, the sixth transistor 136 to the ninth transistor 139, it is preferable to use the thin film transistor 128 having the back gate shown in FIG. 11(C). The operations of the first transistor 131, the sixth transistor 13 6 to the ninth transistor 139 are transistors that are required to switch the potential of a node to which one of the electrodes serving as the source or the drain is connected by the control signal of the gate electrode, and have a fast response to the control signal input to the gate electrode (the rise of the on-current is fast). is fast (the rise of the on-current A transistor that can reduce the malfunction of the pulse output circuit due to its steep upward slope. Therefore, by using the thin film transistor 128 having the back gate shown in Fig. 11(C), the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In Fig. 11(D), the first control signal G1 and the second control signal G2 are set to the same circuit configuration, but a configuration where different control signals are input may also be used.

[0240] In Fig. 11(D), for the first transistor 131, the drain is electrically connected to the power supply line 151, the source is electrically connected to the drain of the ninth transistor 139, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 124.

[0241] For the second transistor 132, the drain is electrically connected to the power supply line 153, the source is electrically connected to the drain of the ninth transistor 139, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 134.

[0242] For the third transistor 133, the drain is electrically connected to the first input terminal 121, and the source is electrically connected to the first output terminal 126. For the fourth transistor 134, the drain is electrically connected to the power supply line 153, and the source is electrically connected to the first output terminal 126.

[0243] For the fifth transistor 135, the drain is electrically connected to the power supply line 153, and the source is electrically connected to the gate electrodes of the second transistor 132 and the fourth transistor 134. ​​​​​​​​​​​​​is connected, and the gate electrode is electrically connected to the fourth input terminal 124.

[0244] The sixth transistor 136 has a drain electrically connected to the power supply line 152 and a source connected to the gate electrodes of the second transistor 132 and the fourth transistor 134, and is electrically connected. The gate electrode (lower gate electrode and upper gate electrode) is electrically connected to the fifth input terminal 125.

[0245] The seventh transistor 137 has a drain electrically connected to the power supply line 152 and a source connected to the source of the eighth transistor 138. The gate electrode (lower gate electrode and upper gate electrode) is electrically connected to the third input terminal 123.

[0246] The eighth transistor 138 has a drain electrically connected to the gate electrodes of the second transistor 132 and the fourth transistor 134. The gate electrode (lower gate electrode and upper gate electrode) is electrically connected to the second input terminal 122.

[0247] The ninth transistor 139 has a drain electrically connected to the source of the first transistor 131 and the second transistor 132. The source is electrically connected to the gate electrodes of the third transistor 133 and the tenth transistor 140. The gate electrode (lower gate electrode and upper gate electrode) is electrically connected to the power supply line 152. .

[0248] The tenth transistor 140 has a drain electrically connected to the first input terminal 121, a source electrically connected to the second output terminal 127, and a gate electrode connected to the ninth transistor 1 is electrically connected to the source of 39.

[0249] For the 11th transistor 141, the drain is electrically connected to the power line 153, and the source is electrically connected to the second output terminal 127, and the gate electrode is electrically connected to the gate electrode of the second transistor 132 and the gate electrode of the fourth transistor 134.

[0250] For the 12th transistor 142, the drain is electrically connected to the power line 153, and the source is electrically connected to the second output terminal 127, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 137 (the lower gate electrode and the upper gate electrode).

[0251] For the 13th transistor 143, the drain is electrically connected to the power line 153, and the source is electrically connected to the first output terminal 126, and the gate electrode is electrically connected to the gate electrode of the seventh transistor 137 (the lower gate electrode and the upper gate electrode).

[0252] In FIG. 11(D), the connection point of the gate electrode of the third transistor 133, the gate electrode of the 10th transistor 140, and the source of the ninth transistor 139 is defined as node A. Also, the connection point of the gate electrode of the second transistor 132, the gate electrode of the fourth transistor 134, the source of the fifth transistor 135, the source of the sixth transistor 136, the drain of the eighth transistor 138, and the 11th transistor 141 is defined as node B (see FIG. 12(A)). In FIGS. 11(D) and 12(A), by setting node A to a floating state, boot is achieved. (See FIG. 12(A)).

[0253] Note that in FIGS. 11(D) and 12(A), by making node A in a floating state, boot A capacitive element may be separately provided for performing the bootstrap operation. Also, to hold the potential of node B a capacitive element having one electrode electrically connected to node B may be separately provided.

[0254] Here, the timing chart of a shift register including a plurality of pulse output circuits shown in Fig. 12(A) is shown in Fig. 12(B). When the shift register is a scanning line drive circuit the period 161 in Fig. 12(B) is the vertical blanking period, and the period 62 corresponds to the gate selection period.

[0255] As shown in Fig. 12(A), by providing a ninth transistor 139 to which a second power supply potential VCC is applied to the gate, there are the following advantages before and after the bootstrap operation.

[0256] When there is no ninth transistor 139 to which a second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source of the first transistor 131 rises and becomes larger than the first power supply potential VDD. Therefore, in the first transistor 131, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied and it can become a factor in transistor degradation.

[0257] Therefore, by providing a ninth transistor 139 to which a second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the bootstrap operation, the potential of the source of the first transistor 131 can be prevented from rising. That is, by providing the ninth transistor 139, the gate of the first transistor 131 ​​​​​​​​ The value of the voltage between the source can be reduced. Therefore, the deterioration of the first transistor 131 can be suppressed.

[0258] Regarding the location where the ninth transistor 139 is provided, it may be configured to be connected between the source of the first transistor 131 and the gate of the third transistor 133 via a drain and a source. In the case of a shift register having a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 139 may be omitted. It may be provided so as to be connected via a drain and a source between the source of the first transistor 131 and the gate of the third transistor 133. In the case of a shift register having a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 139 may be omitted. It may be provided so as to be connected via a drain and a source between the source of the first transistor 131 and the gate of the third transistor 133. In the case of a shift register having a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 139 may be omitted. In the case of a shift register having a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 139 may be omitted. In the case of a shift register having a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 139 may be omitted.

[0259] By using an oxide semiconductor as the semiconductor layer of the first transistor 131 to the thirteenth transistor 143, the off-current of the thin-film transistor can be reduced, the on-current and the field-effect mobility can be increased, and the degree of deterioration can be reduced. Therefore, malfunction in the circuit can be reduced. By using an oxide semiconductor as the semiconductor layer of the first transistor 131 to the thirteenth transistor 143, the off-current of the thin-film transistor can be reduced, the on-current and the field-effect mobility can be increased, and the degree of deterioration can be reduced. Therefore, malfunction in the circuit can be reduced. By using an oxide semiconductor as the semiconductor layer of the first transistor 131 to the thirteenth transistor 143, the off-current of the thin-film transistor can be reduced, the on-current and the field-effect mobility can be increased, and the degree of deterioration can be reduced. Therefore, malfunction in the circuit can be reduced. By using an oxide semiconductor as the semiconductor layer of the first transistor 131 to the thirteenth transistor 143, the off-current of the thin-film transistor can be reduced, the on-current and the field-effect mobility can be increased, and the degree of deterioration can be reduced. Therefore, malfunction in the circuit can be reduced.

[0260] In addition, the transistor using an oxide semiconductor has less deterioration of the transistor due to the application of a high potential to the gate electrode compared to the transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line for supplying the second power supply potential VCC, and the number of power supply lines routed between circuits can be reduced. Therefore, the circuit can be miniaturized. In addition, the transistor using an oxide semiconductor has less deterioration of the transistor due to the application of a high potential to the gate electrode compared to the transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line for supplying the second power supply potential VCC, and the number of power supply lines routed between circuits can be reduced. Therefore, the circuit can be miniaturized. In addition, the transistor using an oxide semiconductor has less deterioration of the transistor due to the application of a high potential to the gate electrode compared to the transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line for supplying the second power supply potential VCC, and the number of power supply lines routed between circuits can be reduced. Therefore, the circuit can be miniaturized. In addition, the transistor using an oxide semiconductor has less deterioration of the transistor due to the application of a high potential to the gate electrode compared to the transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line for supplying the second power supply potential VCC, and the number of power supply lines routed between circuits can be reduced. Therefore, the circuit can be miniaturized. In addition, the transistor using an oxide semiconductor has less deterioration of the transistor due to the application of a high potential to the gate electrode compared to the transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line for supplying the second power supply potential VCC, and the number of power supply lines routed between circuits can be reduced. Therefore, the circuit can be miniaturized.

[0261] In FIG. 11(D) (and FIG. 12(A)), the gate electrode of the seventh transistor 137 (the lower gate electrode and the upper gate electrode) is supplied by the third input terminal 123. In FIG. 11(D) (and FIG. 12(A)), the gate electrode of the seventh transistor 137 (the lower gate electrode and the upper gate electrode) is supplied by the third input terminal 123. Input a clock signal and input the clock signal supplied by the second input terminal 122 to the gate electrodes (the lower gate electrode and the upper gate electrode) of the eighth transistor 138. Although it is configured in this way, the connection relationship is changed so that the clock signals supplied by the second input terminal 122 and the clock signal supplied by the third input terminal 123 are respectively obtained, and the same operation can be achieved. When the connection relationship is changed as described above, in the shift register shown in FIG. 12(A), both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is off and the eighth transistor 138 is on, and then the seventh transistor 137 is off and the eighth transistor 138 is off. Accordingly, the potentials of the second input terminal 122 and the third input terminal 123 decrease. As a result, the potential of node B decreases twice. In the shift register shown in FIG. 12(A), when both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is on and the eighth transistor 138 is off, and then the seventh transistor 137 is off and the eighth transistor 138 is off, the decrease in the potential of node B can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 138.

[0262] Therefore, the clock signal supplied by the third input terminal to the gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 137, the eighth transistor 138 In the shift register shown in FIG. 12(A), both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is off and the eighth transistor 138 is on, and then the seventh transistor 137 is off and the eighth transistor 138 is off. Accordingly, the potentials of the second input terminal 122 and the third input terminal 123 decrease. As a result, the potential of node B decreases twice. In the shift register shown in FIG. 12(A), when both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is on and the eighth transistor 138 is off, and then the seventh transistor 137 is off and the eighth transistor 138 is off, the decrease in the potential of node B can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 138. Accordingly, the potentials of the second input terminal 122 and the third input terminal 123 decrease. As a result, the potential of node B decreases twice. As a result, the potential of node B decreases twice.

[0263] In the shift register shown in FIG. 12(A), when both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is on and the eighth transistor 138 is off, and then the seventh transistor 137 is off and the eighth transistor 138 is off, the decrease in the potential of node B can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 138. In the shift register shown in FIG. 12(A), both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is on and the eighth transistor 138 is off, and then the seventh transistor 137 is off and the eighth transistor 138 is off. Accordingly, the potentials of the second input terminal 122 and the third input terminal 123 decrease. As a result, the potential of node B decreases twice. In the shift register shown in FIG. 12(A), when both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is on and the eighth transistor 138 is off, and then the seventh transistor 137 is off and the eighth transistor 138 is off, the decrease in the potential of node B can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 138. In the shift register shown in FIG. 12(A), when both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is on and the eighth transistor 138 is off, and then the seventh transistor 137 is off and the eighth transistor 138 is off, the decrease in the potential of node B can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 138. In the shift register shown in FIG. 12(A), when both the seventh transistor 137 and the eighth transistor 138 change from the on state to the state where the seventh transistor 137 is on and the eighth transistor 138 is off, and then the seventh transistor 137 is off and the eighth transistor 138 is off, the decrease in the potential of node B can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 138.

[0264] Therefore, the clock signal supplied by the third input terminal to the gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 137, the eighth transistor 138 By using the clock signal supplied to the gate electrodes (the lower gate electrode and the upper gate electrode) by the second input terminal, the potential fluctuation of node B is reduced, so that noise can be reduced, which is preferable. By doing so, during the period when the potentials of the first output terminal 126 and the second output terminal 127 are held at the L level, a signal of the H level is periodically supplied to node B, thereby suppressing the malfunction of the pulse output circuit. It is possible to suppress the malfunction of the pulse output circuit.

[0265] Thus, by adopting a configuration in which a signal of the H level is periodically supplied to node B during the period when the potentials of the first output terminal 126 and the second output terminal 127 are held at the L level, the malfunction of the pulse output circuit can be suppressed. During the period when the potentials of the first output terminal 126 and the second output terminal 127 are held at the L level, a signal of the H level is periodically supplied to node B, thereby suppressing the malfunction of the pulse output circuit. It is possible to suppress the malfunction of the pulse output circuit.

[0266] Now, the active matrix type liquid crystal display device disclosed in this specification including the present embodiment can be applied to various electronic devices (including gaming machines). Examples of the electronic devices include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproduction device, and a large game machine such as a pachinko machine. For example, a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproduction device, and a large game machine such as a pachinko machine. For example, a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproduction device, and a large game machine such as a pachinko machine. For example, a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproduction device, and a large game machine such as a pachinko machine. For example, a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproduction device, and a large game machine such as a pachinko machine. For example, a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproduction device, and a large game machine such as a pachinko machine.

[0267] FIG. 13(A) shows an example of a mobile phone. The mobile phone 1100 includes a display unit 1102 incorporated in a housing 1101, operation buttons 1103, an external connection port 1104, a speaker 1105, a microphone 1106, and the like. In addition to the display unit 1102 incorporated in the housing 1101, the mobile phone 1100 includes operation buttons 1103, an external connection port 1104, a speaker 1105, a microphone 1106, and the like. In addition to the display unit 1102 incorporated in the housing 1101, the mobile phone 1100 includes operation buttons 1103, an external connection port 1104, a speaker 1105, a microphone 1106, and the like.

[0268] The mobile phone 1100 shown in FIG. 13(A) can input information by touching the display unit 1102 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1102 with a finger or the like. The mobile phone 1100 shown in FIG. 13(A) can input information by touching the display unit 1102 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1102 with a finger or the like. The mobile phone 1100 shown in FIG. 13(A) can input information by touching the display unit 1102 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1102 with a finger or the like.

[0269] The screen of the display unit 1102 mainly has three modes. The first is the display mode mainly for displaying images, the second is the input mode mainly for inputting information such as characters. The third is the display + input mode in which the two modes of the display mode and the input mode are mixed.

[0270] For example, when making a call or creating an email, the display unit 1102 may be set to the character input mode mainly for character input, and an input operation for the characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1102.

[0271] Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1100 to detect the inclination, the orientation (vertical or horizontal) of the mobile phone 1100 can be determined, and the screen display of the display unit 1102 can be automatically switched.

[0272] Also, the switching of the screen mode is performed by touching the display unit 1102 or operating the operation button 1103 of the housing 1101. Also, it can be switched according to the type of image displayed on the display unit 1102. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0273] Also, in the input mode, the signal detected by the optical sensor of the display unit 1102 is detected, and when there is no input by touch operation of the display unit 1102 for a certain period, the mode of the screen may be controlled to be switched from the input mode to the display mode.

[0274] The display unit 1102 can also function as an image sensor. For example, the display unit 11 By touching the palm or fingers on 02 and imaging palm prints, fingerprints, etc., personal authentication can be performed. Also, if a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, it is also possible to image finger veins, palm veins, etc.

[0275] A plurality of thin film transistors 13 shown in Embodiment 1 are arranged in the display unit 1102. Since the thin film transistor 13 has translucency, when a photosensor is provided in the display unit 1102, it is effective because the incident light is not obstructed by the thin film transistor 13. Also, when a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light is used for the display unit, it is preferable because the thin film transistor 13 does not block the light.

[0276] FIG. 13(B) is also an example of a mobile phone. The portable information terminal taking FIG. 13(B) as an example can have a plurality of functions. For example, in addition to the telephone function, it can incorporate a computer and have various data processing functions.

[0277] The portable information terminal shown in FIG. 13(B) is composed of two housings, a housing 1800 and a housing 1801. The housing 1800 is provided with a display panel 1802, a speaker 1803, a microphone 1804, a pointing device 1806, a camera lens 1807, an external connection terminal 1808, etc. The housing 1801 is provided with a keyboard 1810, an external memory slot 1811, etc. Also, the antenna is built inside the housing 1801.

[0278] Also, the display panel 1802 has a touch panel, and a plurality of operation keys 1805 where images are displayed in FIG. 13(B) are shown by dotted lines. ​

[0279] In addition to the above configuration, a non-contact IC chip, a small recording device, etc. may be incorporated.

[0280] The active matrix liquid crystal display device can be used for the display panel 1802, and the display direction changes appropriately according to the usage form. Also, since a camera lens 1807 is provided on the same plane as the display panel 1802, a video phone is possible. The speaker 1803 and the microphone 1804 can be used not only for voice calls but also for video phones, recording, playback, etc. . Furthermore, the housing 1800 and the housing 1801 can be slid from the state shown in Fig. 13(B) where they are unfolded and overlapped, enabling miniaturization suitable for portability.

[0281] The external connection terminal 1808 can be connected to various cables such as an AC adapter and a USB cable , enabling charging and data communication with a personal computer, etc. Also, by inserting a recording medium into the external memory slot 1811, it is possible to handle larger amounts of data storage and transfer.

[0282] In addition to the above functions, it may be provided with an infrared communication function, a television reception function, etc.

[0283] As described above, the active matrix display device shown in Embodiments 1 and 2 can be arranged on the display panels of various electronic devices as described above. By using the thin film transistor 12 as a drive circuit and the thin film transistor 13 as a switching element of the display panel, it is possible to provide a highly reliable electronic device having a display portion with a high aperture ratio particularly in the case of a bottom emission type. ​

[0284] (Embodiment 4) In this embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from that of Embodiment 1 is shown in FIG. 8 . Since FIG. 8 is the same as FIG. 1 except for the part where the process is different, the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted.

[0285] First, according to Embodiment 1, two types of gate electrode layers 2a, 2b, 3a, 3b and a gate insulating layer 4 are formed on the substrate 1, and a source electrode layer 5a and a drain electrode layer 5b that partially overlap the gate electrode layer 3a are formed through the gate insulating layer 4. Then, a film of the oxide semiconductor film 6 is formed on the gate insulating layer 4, the source electrode layer 5a, and the drain electrode layer 5b.

[0286] Next, dehydration or dehydrogenation of the oxide semiconductor film 6 is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 400°C or higher, preferably 425°C or higher. If it is 425 °C or higher, the heat treatment time may be 1 hour or less, but if it is less than 425°C, the heat treatment time shall be longer than 1 hour.

[0287] Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing heat treatment on the oxide semiconductor film 6 in a nitrogen atmosphere, without exposing it to the atmosphere, while preventing re-mixing of water and hydrogen into the oxide semiconductor film 6, high-purity oxygen gas, high-purity N O gas, or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) is introduced into the same furnace for cooling. It is preferable that the oxygen gas or N 2 O gas does not contain water, hydrogen, etc. Or, the oxygen gas or N introduced into the heat treatment apparatus O gas 2 O gas 2The purity of the O gas is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher, (that is, the impurity 2 concentration in the oxygen gas or N O gas is 1 ppm or lower, preferably 0.1 ppm or lower).

[0288] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor, the oxide semiconductor film 6 may crystallize and become a microcrystalline film or a polycrystalline film. In the case of a microcrystalline film, the proportion of the crystal component in the whole is 80% or more (preferably 90% or more), and it is preferable that the adjacent microcrystalline grains are filled so as to be in contact with each other. Also, all of the oxide semiconductor film 6 may be in an amorphous state.

[0289] Also, after the first heat treatment for dehydration or dehydrogenation, heating treatment may be performed at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower, in an oxygen gas or N 2 O gas atmosphere. The treatment may be carried out.

[0290] By passing through the above steps, the entire oxide semiconductor film 6 is made into an oxygen-excess state, thereby increasing the resistance, that is, making it into the I-type. In this embodiment, an example of performing the first heat treatment for dehydration or dehydrogenation immediately after the formation of the oxide semiconductor film 6 has been shown, but it is not particularly limited, and it may be any step after the formation of the oxide semiconductor film 6.

[0291] Next, a contact hole reaching the gate electrode layer 2b is formed by selectively etching the oxide semiconductor film 6 and the gate insulating layer 4 by a photolithography process. By forming a resist on the oxide semiconductor film 6, contamination at the interface between the gate insulating layer 4 and the oxide semiconductor film 6 is prevented. It can be prevented. The state after removing the resist mask is shown in FIG. 8(A).

[0292] Next, the oxide semiconductor film 6 is selectively etched to obtain island-shaped oxide semiconductor layers 6c and 6d (see FIG. 8(B)). See FIG. 8(B).

[0293] Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). Next, an oxide insulating film is formed by sputtering on the gate insulating layer 4 and the oxide semiconductor layers 6c and 6d. Then, a resist mask is formed by a photolithography process, and selective etching is performed to form oxide insulating layers 7a and 7b, and then the resist mask is removed. At this stage, a region where the oxide semiconductor layer is in contact with the oxide insulating layer is formed. Among this region, the region overlapping the oxide insulating layer 7a via the gate electrode layer 2a and the gate insulating layer 4 becomes the channel formation region. Also, a region overlapping the oxide insulating layer 7b covering the periphery and side surfaces of the oxide semiconductor layer is formed. Also, by this photolithography process, contact holes reaching the gate electrode layer 2b and contact holes reaching the drain electrode layer 5b are formed (see FIG. 8(C)). See FIG. 8(C).

[0294] The oxide insulating film does not contain impurities such as moisture, hydrogen ions, and OH, and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride is used. - The oxide insulating film does not contain impurities such as moisture, hydrogen ions, and OH, and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride is used. The oxide insulating film does not contain impurities such as moisture, hydrogen ions, and OH, and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride is used. The oxide insulating film does not contain impurities such as moisture, hydrogen ions, and OH, and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride is used.

[0295] Next, a stack of an oxide conductive film and a metal conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. By using the sputtering method, the stack of the oxide conductive film and the metal conductive film can be continuously formed without being exposed to the atmosphere. Next, a stack of an oxide conductive film and a metal conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. By using the sputtering method, the stack of the oxide conductive film and the metal conductive film can be continuously formed without being exposed to the atmosphere. Next, a stack of an oxide conductive film and a metal conductive film is formed on the gate insulating layer 4, the oxide insulating layers 7a and 7b, and the oxide semiconductor layer. By using the sputtering method, the stack of the oxide conductive film and the metal conductive film can be continuously formed without being exposed to the atmosphere.

[0296] As the oxide conductive film, those containing zinc oxide as a component are preferable, and those not containing indium are preferably used. Examples of such oxide conductive films include zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride, gallium zinc oxide, and the like. In this embodiment, a zinc oxide film is used.

[0297] Further, as the metal conductive film, an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above-described elements as components, or an alloy combining the above-described elements, etc. are used. Moreover, it is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used. In this embodiment, a three-layer laminate film in which a molybdenum film, an aluminum film, and a molybdenum film are laminated is used.

[0298] Next, a resist mask is formed, and after selectively etching the metal conductive film to form the source electrode layer 2 3a, the drain electrode layer 23b, the connection electrode layers 23c and 23d, the resist mask is removed. Note that the resist stripping solution used for removing the resist mask is an al kaline solution. When using the resist stripping solution, the oxide conductive film is also selectively etched using the source electrode layer 23a, the drain electrode layer 23b, the connection electrode layers 23c and 23d as masks.

[0299] An oxide conductive layer 24a is formed in contact with the lower side of the source electrode layer 23a, and an oxide conductive layer 24b is formed in contact with the lower side of the drain electrode layer 23b. By providing the oxide conductive layer 24a between the source electrode layer 23a and the oxide semiconductor layer, the contact resistance can be reduced and low resistance can be achieved, and a thin film transistor capable of high-speed operation can be realized. Between the source electrode layer 23a and the oxide semi conductor layer, by providing the oxide conductive layer 24a, the contact resistance can be reduced and low resistance can be achieved, and a thin film transistor capable of high-speed operation can be realized. Between the source electrode layer 23a and the oxide semi​​ The oxide conductive layer 24a provided between the conductor layers functions as a source region, and the drain electrode The oxide conductive layer 24b provided between the drain electrode layer 23b and the oxide semiconductor layer functions as a drain region is effective for improving the frequency characteristics of the peripheral circuit (driving circuit).

[0300] In addition, when the molybdenum film is in direct contact with the oxide semiconductor layer, there is a problem that the contact resistance increases This is because Mo is less likely to oxidize than Ti, so the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer is not N-type.

[0301] However, even in such a case, by interposing the oxide conductive layer 24a between the oxide semiconductor layer and the source electrode layer, and interposing the oxide conductive layer 24b between the oxide semiconductor layer and the drain electrode layer, the contact resistance can be reduced, and the frequency characteristics of the peripheral circuit (driving circuit) can be improved. .

[0302] In addition, the oxide conductive layer 24c is formed in contact with the lower part of the connection electrode layer 23c in the same process, and the oxide conductive layer 24d is formed in contact with the lower part of the connection electrode layer 23d (see Fig. 8(D)). By forming the oxide conductive layer 24c between the connection electrode layer 23c and the gate electrode layer 2b, it becomes a buffer, and only the series resistance corresponding to the thickness is obtained, which is preferable. Furthermore, it is preferable because it does not form an oxide that is insulating from the metal.

[0303] Since the oxide semiconductor layer and the oxide conductive layer have a difference in etching rate, the oxide conductive layer in contact with the upper part of the oxide semiconductor layer can be removed by time control.

[0304] After selectively etching the metal conductive film, the resist mask is removed by oxygen ashing treatment​​​​ After removing and leaving the oxide conductive film, the source electrode layer 23a, the drain electrode layer 23b, The oxide conductive film may be selectively etched using the connection electrode layers 23c and 23d as masks. .

[0305] Also, when performing the first heat treatment after selectively etching the metal conductive film, as long as the oxide conductive layers 24a, 24b, 24c, and 24d do not contain a crystallization inhibitor such as silicon oxide, the oxide conductive layers 24a, 24b, 24c, and 24d crystallize. On the other hand, the oxide semiconductor layer does not crystallize by the first heat treatment and remains in an amorphous structure. The crystals of the oxide conductive layer grow columnarly with respect to the underlying surface. As a result, when etching the metal film on the upper layer of the oxide conductive layer to form the source electrode and the drain electrode, it is possible to prevent the formation of undercuts in the lower oxide conductive layer.

[0306] Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, a second heat treatment (preferably at 150°C or higher and lower than 350°C) may be performed in an inert gas atmosphere or in a nitrogen gas atmosphere. For example, a heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Note that by the second heat treatment, oxygen is impregnated and diffused into the oxide semiconductor layer from the oxide insulating film or the like in contact with the oxide semiconductor layer. By the impregnation and diffusion of oxygen into the oxide semiconductor layer, the channel formation region can be made to have a higher resistance (i-type). Thereby, a normally-off thin film transistor can be obtained. Also, by the second heat treatment, the oxide conductive layers 24a, 2 4b, 24c, and 24d can be crystallized to improve the conductivity.

[0307] Next, an insulating layer 10 is formed over the oxide insulating layers 7a and 7b, the source electrode layer 23a, and the drain electrode layer 23b (see Fig. 8(E)).

[0308] Through the above steps, the thin film transistor 25 and the thin film transistor 13 can be fabricated on the same substrate.

[0309] The thin film transistor 25 disposed in the driving circuit includes a gate electrode layer 2a, a gate insulating layer 4, an oxide semiconductor layer, oxide conductive layers 24a and 24b, a source electrode layer 23a, and a drain electrode layer 23b on a substrate 1 having an insulating surface. The oxide semiconductor layer has at least a channel formation region 26. Also, an oxide insulating layer 7a in contact with the channel formation region 26 is provided. Further, an insulating layer 10 is provided over the source electrode layer 23a and the drain electrode layer 23b.

[0310] Also, a first region 27c and a second region 27d of the oxide semiconductor layer 6c in contact with the oxide insulating layer 7b are in the same oxygen-excessive state as the channel formation region 26, and also function to reduce leakage current and parasitic capacitance. Also, a third region 27e of the oxide semiconductor layer 6c in contact with the insulating layer 10 is provided between the channel formation region 26 and the high-resistance source region 27a. Also, a fourth region 27f of the oxide semiconductor layer 6c in contact with the insulating layer 10 is provided between the channel formation region 26 and the high-resistance drain region 27b. The third region 27e and the fourth region 27f of the oxide semiconductor layer 6c in contact with the insulating layer 10 can reduce the off-current.

[0311] The active matrix substrate thus obtained is as described with reference to Fig. 2 of Embodiment 1. ​​​​​​​​​​​​​As shown in , it can be made into an active matrix type liquid crystal display device in combination with a counter substrate. It is possible.

[0312] This embodiment can be freely combined with either Embodiment 2 or Embodiment 3.

Explanation of Reference Numerals

[0313] 1 Substrate 2a Gate electrode layer 2b Gate electrode layer 2e Electrode layer 3a Gate electrode layer 3b Gate electrode layer 3c Electrode layer 3d Gate electrode layer 4 Gate insulating layer 5a Source electrode layer 5b Drain electrode layer 5c Electrode layer 5d Source electrode layer 5e Drain electrode layer 6 Oxide semiconductor film 6a Oxide semiconductor layer 6b Oxide semiconductor layer 6c Oxide semiconductor layer 7a Oxide insulating layer 7b Oxide insulating layer 8a Channel formation region 8b Oxide semiconductor layer 9a Source electrode layer 9b Drain electrode layer 9c Connection electrode layer 9d Connection electrode layer 9e Connection electrode layer 9f Connection electrode layer 9g Connection electrode layer 9i Connection electrode layer 10 Insulating layer 11a High-resistance source region 11b High-resistance drain region 11c First region 11d Second region 11e Third region 11f Fourth region 12 Thin film transistor 13 Thin film transistor 14 Planarization insulating layer 15a Pixel electrode layer 15b Pixel electrode layer 15c Pixel electrode layer 15d Conductive layer (back gate) 15e Conductive layer 15f Conductive layer 15g Pixel electrode layer 16 Protective layer 17 Glass substrate 18 Color filter layer 19 Counter electrode 20 Protective film 21 Liquid crystal layer 22a Polarizer 22b Polarizer 23a Source electrode layer 23b Drain electrode layer 23c Connection electrode layer 23d Connection electrode layer 24a Conductive layer 24b Conductive layer 24c Conductive layer 24d Conductive layer 25 Thin film transistor 26 Channel formation region 27c First region 27d Second region 27e Third region 27f Fourth region 30 Counter substrate 38 Counter substrate 42 Thin film transistor 71 Substrate 76 Substrate 79 Thin film transistor 80 Thin film transistor 83 Pixel electrode layer 90 Substrate 103 Thin film transistor 128 Thin film transistor 201 Counter substrate 202 Electrode layer 628 Thin film transistor 629 thin film transistor 640 counter electrode

Claims

1. A pixel portion and a driver circuit portion, the pixel portion includes a first transistor, the drive circuit unit has a second transistor, the first transistor has a single gate structure; a channel formation region of the first transistor is provided in a first oxide semiconductor layer, the second transistor has a first gate electrode layer and a second gate electrode layer; a channel formation region of the second transistor is provided in a second oxide semiconductor layer, the second gate electrode layer has a region facing the first gate electrode layer with the second oxide semiconductor layer therebetween; the second gate electrode layer is supplied with the same potential as the first gate electrode layer; a conductive layer functioning as a source electrode layer or a drain electrode layer of the first transistor is provided to have a region in contact with a bottom surface of the first oxide semiconductor layer, a first oxide semiconductor layer having a first insulating layer and a second oxide semiconductor layer having a first insulating layer and a second insulating layer, the first oxide semiconductor layer having a first insulating layer and a second insulating layer,

2. A pixel portion and a driver circuit portion, the pixel portion includes a first transistor, the drive circuit unit has a second transistor, the first transistor has a single gate structure; a channel formation region of the first transistor is provided in a first oxide semiconductor layer, the second transistor has a first gate electrode layer and a second gate electrode layer; a channel formation region of the second transistor is provided in a second oxide semiconductor layer, the second gate electrode layer has a region facing the first gate electrode layer with the second oxide semiconductor layer therebetween; the second gate electrode layer is supplied with the same potential as the first gate electrode layer; a conductive layer functioning as a source electrode layer or a drain electrode layer of the first transistor is provided to have a region in contact with a bottom surface of the first oxide semiconductor layer, a region in contact with a top surface of the first oxide semiconductor layer, a region in contact with a side surface of the first oxide semiconductor layer, a region in contact with a top surface of the second oxide semiconductor layer, and a region in contact with a side surface of the second oxide semiconductor layer.

3. A pixel portion and a driver circuit portion, the pixel portion includes a first transistor, the drive circuit unit has a second transistor, the first transistor has a single gate structure; a channel formation region of the first transistor is provided in a first oxide semiconductor layer, the second transistor has a first gate electrode layer and a second gate electrode layer; a channel formation region of the second transistor is provided in a second oxide semiconductor layer, the second gate electrode layer has a region facing the first gate electrode layer with the second oxide semiconductor layer therebetween; the first gate electrode layer has a different material than the second gate electrode layer; the second gate electrode layer is supplied with the same potential as the first gate electrode layer; a conductive layer functioning as a source electrode layer or a drain electrode layer of the first transistor is provided to have a region in contact with a bottom surface of the first oxide semiconductor layer, a first oxide semiconductor layer having a first insulating layer and a second oxide semiconductor layer having a first insulating layer and a second insulating layer, the first oxide semiconductor layer having a first insulating layer and a second insulating layer,

4. A pixel portion and a driver circuit portion, the pixel portion includes a first transistor, the drive circuit unit has a second transistor, the first transistor has a single gate structure; a channel formation region of the first transistor is provided in a first oxide semiconductor layer, the second transistor has a first gate electrode layer and a second gate electrode layer; a channel formation region of the second transistor is provided in a second oxide semiconductor layer, the second gate electrode layer has a region facing the first gate electrode layer with the second oxide semiconductor layer therebetween; the first gate electrode layer has a different material than the second gate electrode layer; the second gate electrode layer is supplied with the same potential as the first gate electrode layer; a conductive layer functioning as a source electrode layer or a drain electrode layer of the first transistor is provided to have a region in contact with a bottom surface of the first oxide semiconductor layer, a region in contact with a top surface of the first oxide semiconductor layer, a region in contact with a side surface of the first oxide semiconductor layer, a region in contact with a top surface of the second oxide semiconductor layer, and a region in contact with a side surface of the second oxide semiconductor layer.

Images