Semiconductor device

Abstract

To provide a semiconductor memory device that stores data by using a transistor having a low leakage current between a source and a drain in an off state as a writing transistor.SOLUTION: A matrix is formed by a plurality of memory cells in which a drain of a writing transistor, a gate and a drain of a reading transistor Wtr, and one electrode of a capacitor C are connected. The gate of the writing transistor is connected to a writing word line Q, a source of the reading transistor and a source of the reading transistor RTr are connected to a bit line R, and the drain of the reading transistor is connected to a bias line S. Here, a conductivity type of the writing transistor is different from that of the reading transistor. In order to increase a degree of integration, the bias line may be substituted by a reading word line P in other row, a memory cell may be connected in series to form a NAND structure, and the reading word line and the writing word line may be shared.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a memory device using a semiconductor. [Background technology]

[0002] There are many types of semiconductor memory devices. For example, dynamic random access memory (DRA) Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) , Electronically Erasable Programmable Read-Only Memory (EEPROM) and Flash Schmemorie et al.

[0003] DRAM stores data by storing electric charge in a capacitor in the memory cell. However, conventionally, transistors used for switching are in the off state. However, a small amount of leakage current occurs between the source and drain, so data is stored for a relatively short time (long Therefore, data is lost in a certain period (generally every tens of milliseconds). It is necessary to write (refresh).

[0004] SRAM also retains data using the bistable state of flip-flop circuits. The flip-flop circuit of M usually uses a CMOS inverter, but Since six transistors are used per chip, the integration rate is lower than that of DRAM. If not, data will be lost.

[0005] On the other hand, EEPROM and flash memory use what is called a floating gate. The floating gate is placed between the channel and the gate, and stores electric charge to store data. The charge stored in the floating gate is retained when power to the transistor is removed. Since they are retained even afterwards, these memories are called non-volatile memories. For flash memories, for example, reference may be made to Patent Document 1.

[0006] In this specification, in particular, memories having a floating gate, such as EEPROMs and flash memories, are referred to as floating gate type non-volatile memories (FGNVMs). In FGNVMs, since multi-level data can be stored in a single memory cell, the storage capacity can be increased. In addition, since NAND type flash memories can significantly reduce the number of contact holes, the degree of integration can be increased to a certain extent.

[0007] However, conventional FGNVMs require a high voltage when injecting or removing charges into / from the floating gate, and due to this, deterioration of the gate insulating film cannot be avoided, and unlimited writing and erasing cannot be repeated.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] As described above, conventional semiconductor memory devices have both advantages and disadvantages, and none of them fully satisfy all the requirements necessary for actual devices. In a memory device, low power consumption is required. If the power consumption is large, the device for supplying power must be made large, and also the driving time with a battery becomes short. Moreover, due to the heat generation of the semiconductor element, ​​​​​The characteristics may deteriorate, and in some cases, the circuit may be damaged. Also, in a memory device, it is preferably not limited in the number of rewrites, and it is desirable to be able to perform 1 billion or more rewrites. Of course, it is also necessary to have a high integration degree.

[0010] In this regard, DRAM always generates a leakage current and performs refreshing, so there is a problem in terms of power consumption. On the other hand, SRAM has another problem that the integration degree cannot be increased because one memory cell has six transistors. Also, in FGNVM, there was no problem in terms of power consumption or integration degree, but the number of rewrites was 100,000 times or less. In view of the above, the first problem is to simultaneously overcome the three conditions of reducing the power used for memory retention in the memory cell to less than that of DRAM, making the number of transistors used in the memory cell five or less, and making the number of rewrites 1 million times or more. Also, the second problem is to simultaneously overcome the two conditions of retaining data for 10 hours or more, preferably 100 hours or more, in a state where there is no power supply, and making the number of rewrites 1 million times or more. In this specification, the data retention time is defined as the time when the amount of charge held in the memory cell becomes 90% of the initial amount of charge.

[0011] In addition to the above problems, an object of the present invention is to provide a novel semiconductor device, particularly a semiconductor memory device. Also, an object of the present invention is to provide a driving method for a novel semiconductor device, particularly a driving method for a semiconductor memory device. Further, an object of the present invention is to provide a manufacturing method for a novel semiconductor device, particularly a manufacturing method for a semiconductor memory device. The present invention solves at least the above problems. The present invention aims to provide a novel semiconductor device, particularly a semiconductor memory device, that simultaneously overcomes the three conditions of reducing the power used for memory retention in the memory cell to less than that of DRAM, making the number of transistors used in the memory cell five or less, and making the number of rewrites 1 million times or more. Also, the present invention aims to simultaneously overcome the two conditions of retaining data for 10 hours or more, preferably 100 hours or more, in a state where there is no power supply, and making the number of rewrites 1 million times or more. In this specification, the data retention time is defined as the time when the amount of charge held in the memory cell becomes 90% of the initial amount of charge. In addition to the above problems, an object of the present invention is to provide a novel semiconductor device, particularly a semiconductor memory device. Also, an object of the present invention is to provide a driving method for a novel semiconductor device, particularly a driving method for a semiconductor memory device. Further, an object of the present invention is to provide a manufacturing method for a novel semiconductor device, particularly a manufacturing method for a semiconductor memory device.

[0012] The present invention aims to provide a novel semiconductor device, particularly a semiconductor memory device, that simultaneously overcomes the three conditions of reducing the power used for memory retention in the memory cell to less than that of DRAM, making the number of transistors used in the memory cell five or less, and making the number of rewrites 1 million times or more. Also, the present invention aims to simultaneously overcome the two conditions of retaining data for 10 hours or more, preferably 100 hours or more, in a state where there is no power supply, and making the number of rewrites 1 million times or more. In addition to the above problems, an object of the present invention is to provide a novel semiconductor device, particularly a semiconductor memory device. Also, an object of the present invention is to provide a driving method for a novel semiconductor device, particularly a driving method for a semiconductor memory device. It also solves the problem of "one".

Means for Solving the Problem

[0013] Hereinafter, the present invention will be described, and the terms used in this specification will be briefly explained. First , regarding the source and drain of a transistor, those having the same or equivalent structure and function Also, even if the structures are different, due to reasons such as the potential applied to them and its polarity not being constant , in this specification, when one of them is called the source for convenience, the other will be called the drain, and no particular distinction will be made. Therefore, it is also possible to read the source as the drain in this specification.

[0014] In this specification, "(orthogonal in the matrix)" does not only mean intersecting at a right angle , but also means orthogonal in the circuit diagram most simply expressed even if it is at other angles physically. "(Parallel in the matrix)" means that even if two wires are physically arranged to intersect, they are parallel in the circuit diagram most simply expressed.

[0015] One aspect of the present invention uses a transistor with low leakage current between the source and drain in the off state as a write transistor, and another transistor (read transistor) and , a capacitor to form one memory cell. The conductivity type of the read transistor is different from that of the write transistor. For example, if the write transistor is an N-channel type , the read transistor is a P-channel type. Also, at least three types of wirings, namely a write word line, a bit line, and a read word line, are used in connection with these. It is used.

[0016] Then, the drain of the write transistor is connected to the gate of the read transistor and one electrode of the capacitor. Furthermore, the gate of the write transistor is connected to the write word line, the source of the write transistor and the source of the read transistor are connected to the bit line, and the other electrode of the capacitor is connected to the read word line.

[0017] The leakage current between the source and the drain in the off state of the write transistor (in the case of an N-channel type, the potential of the gate is lower than that of either the source or the drain) is 1×10 A or less at the temperature during use (for example, 25 °C), preferably 1×10 A or less, or 1×10 -20 A or less at 85 °C, which is desirable. In a normal silicon semiconductor, -21 it is difficult to make the leakage current such a low value, but it can be achieved in a transistor obtained by processing an oxide semiconductor under preferable conditions. Therefore, it is preferable to use an oxide semiconductor as the material of the write transistor. Of course, if the leakage current can be made below the above value in a silicon semiconductor or other semiconductors by some method, -20 it does not prevent their use. As various known materials can be used as the oxide semiconductor, those having a band gap of 3 electron volts or more, preferably 3 electron volts or more and less than 3.6 electron volts are desirable.

[0018] In addition, those having an electron affinity of 4 electron volts or more, preferably 4 electron volts or more and less than 4.9 electron volts are desirable. In particular, an oxide having gallium and indium is the present invention. It is suitable for the purpose of clarity. In such materials, furthermore, the carrier concentration derived from the donor or acceptor is less than 1×10 -14 cm -3 −, preferably less than 1×10 -11 c m -3 −, which is desirable.

[0019] As for the read transistor, there is no limit on the leakage current between the source and the drain in the off state, but it is preferable that the leakage current is small because it can reduce the power consumption. Also, in order to increase the read speed, it is desirable to operate at high speed. Specifically, the switching speed is preferably 10 nsec or less. Also, for the write transistor and the read transistor, it is required that the gate leakage current (the leakage current between the gate and the source or between the gate and the drain) is extremely low, and it is also required that the capacitor has a low internal leakage current ( the leakage current between the electrodes). Any leakage current should be 1×10 A or less, preferably 1×10 A or less, at the operating temperature ( -20 for example, 25 °C), which -21 is desirable.

[0020] Also, the potential of the gate of the read transistor changes according to the potential of the read word line and, as a result, the gate capacitance of the read transistor may vary. That is, the gate capacitance may be larger when the read transistor is in the on state than when it is in the off state. If the variation in the gate capacitance is larger than the capacitance of the capacitor, it causes problems in operating the memory cell.

[0021] Therefore, the capacitance of the capacitor is equal to or greater than the gate capacitance of the read transistor, preferably It is preferably set to be two times or more. Also, for the purpose of operating the semiconductor memory device at high speed, the capacitance of the capacitor is desirably 10 fF or less.

[0022] The write word line, bit line, and read word line form a matrix. For matrix driving, it is desirable that the write word line and the bit line are orthogonal, and the write word line and the read word line are parallel.

[0023] FIG. 1(A) illustrates an example of a memory cell having the above structure. Here, a memory cell at the n-th row and m-th column will be described as an example. n and m may be natural numbers. In FIG. 1(A), a memory cell including a write transistor WTr(n, m), a read transistor RTr(n, m), and a capacitor C (n, m) is shown. Here, the drain of the write transistor WTr(n , m) is connected to the gate of the read transistor RTr(n, m) and one electrode of the capacitor C (n, m). Furthermore, the gate of the write transistor WTr(n, m) is connected to the write word line Qn, the source of the write transistor WTr(n, m) and the source of the read transistor RTr(n, m) are connected to the bit line Rm, and the other electrode of the capacitor C(n, m) is connected to the read word line P n, respectively.

[0024] In addition, the drain of the read transistor RTr(n, m) is connected to the bias line Sn. In FIG. 1(A), the write word line Qn, the read word line Pn, and the bias line Sn are parallel. And the write word line Qn and the bit line Rm are orthogonal.

[0025]

[0026] ​​​​​ Figure 1(B) shows the periphery of the memory cell at the n-th row and the m-th column (n and m are natural numbers of 2 or more). As is clear from the figure, three wirings are required per row and one wiring is required per column. Therefore, in an N-row and M-column matrix, (3N + M) wirings are required.

[0027] In the memory cell shown in Figure 1(A), by applying an appropriate potential to the write word line Qn, the write transistor WTr(n,m) is turned on. At this time, depending on the potential of the bit line Rm, charge is injected into the drain of the write transistor WTr(n,m). The amount of charge injection at this time is determined by the potential of the bit line Rm, the gate capacitance of the read transistor RTr(n,m), the capacitance of the capacitor C(n,m), etc. Therefore, under the same conditions, almost the same result is obtained and the variation is small. In this way, data is written.

[0028] Next, by applying another appropriate potential to the write word line Qn, the write transistor WTr(n,m) is turned off. Even in this case, the charge in the drain of the write transistor WTr(n,m) is held as it is. When reading, by applying appropriate potentials to the read word line Pn, the bias line Sn, etc., and monitoring the state of the read transistor RTr(n,m), the written data can be known.

[0029] In the above configuration, bias lines may be shared between adjacent rows. Figure 5 shows an example of a memory cell having the above structure. Here, the memory cell at the (2n - 1)-th row and the m-th column adjacent to the memory cell at the 2n-th row and the m-th column (n and m are natural numbers) will be described as an example. ​​

[0030] In FIG. 5, a memory cell at the (2n - 1)-th row and the m-th column, which consists of a write transistor WTr(2n - 1,m), a read transistor RTr (2n - 1,m), and a capacitor C(2n - 1,m), and a memory cell at the 2n-th row and the m-th column, which consists of a write transistor WTr(2n,m), a read transistor RTr(2 n,m), and a capacitor C(2n,m), are shown. .

[0031] The drain of the write transistor WTr(2n - 1,m) is connected to the gate of the read transistor RTr (2n - 1,m) and one electrode of the capacitor C(2n - 1,m). Similarly, the drain of the write transistor WTr(2n,m) is connected to the gate of the read trans istor RTr(2n,m) and one electrode of the capacitor C(2n,m).

[0032] Furthermore, the gate of the write transistor WTr(2n - 1,m) is connected to the write word line Q2 n - 1, the gate of the write transistor WTr(2n,m) is connected to the write word line Q2n , the other electrode of the capacitor C(2n - 1,m) is connected to the read word line P2n - 1, the other electrode of the capaci tor C(2n,m) is connected to the read word line P2n, the drains of the read transistors RTr(2n - 1,m) and RTr(2n,m) are connected to the bias line Sn, and the sources of the write transistors WTr(2n - 1,m), WTr(2n,m), the sources of the read transistors RTr(2n - 1, m), and RTr(2n,m) are connected to the bit line Rm, respectively.

[0033] As is clear from the above, since five wirings are required per two rows and one wiring is required per column, two In an N-row M-column matrix, (5N + M) wirings are required. In the semiconductor memory device of FIG. 1 , (6N + M) wirings are required for a matrix of the same scale. Thus, by sharing bias lines in adjacent rows, the number of wirings can be reduced compared to the configuration of FIG. 1 .

[0034] Also, the bias lines in the configuration of FIG. 1 above may be substituted with adjacent write word lines . FIG. 6(A) illustrates an example of a memory cell having the above structure. Here, the n-th row and m-th column (n and m are natural numbers) memory cell will be described as an example. In FIG. 6(A), a write transistor WTr(n,m), a read transistor RTr(n,m), and a capacitor C(n,m ) are shown as a memory cell.

[0035] The drain of the write transistor WTr(n,m) is connected to the gate of the read transistor RTr(n, m) and one electrode of the capacitor C(n,m). Further, the gate of the write transistor WTr(n,m) is connected to the write word line Qn, and the source of the write transistor WTr(n,m) and the source of the read transistor RTr(n,m) are connected to the bit line Rm, the drain of the read transistor RTr(n,m) is connected to the write word line Qn+1 one row below, and the other electrode of the capacitor C(n,m) is connected to the read word line Pn respectively. FIG. 6(B) illustrates the periphery of the memory cell of the n-th row and m-th column. As is clear from the figure , since two wirings are required per row and one wiring is required per column, even the end portions of the matrix require the same number of wirings.

[0036] FIG. 6(B) shows the periphery of the memory cell of the n-th row and m-th column. As is apparent from the figure , since two wirings are required per row and one wiring is required per column, the end portions of the matrix also Considering this, in an N-row and M-column matrix, (2N + M + 1) wirings are required. Thus, by substituting the bias line in the configuration of FIG. 1 with an adjacent write word line, the number of wirings can be further reduced compared to the configuration of FIG. 1.

[0037] Another aspect of the present invention is a semiconductor memory device comprising memory units formed by using a plurality of write transistors, read transistors, and capacitors similar to those used in FIG. 1 above. Here, the conductivity types of the write transistor and the read transistor are different from each other. For example, if the write transistor is an N-channel type, the read transistor is a P-channel type. That is, the drain of the first write transistor is connected to one electrode of the first capacitor and the gate of the first read transistor, and the drain of the second write transistor is connected to one electrode of the second capacitor and the gate of the second read transistor.

[0038] That is, the drain of the first write transistor is connected to one electrode of the first capacitor and the gate of the first read transistor, and the drain of the second write transistor is connected to one electrode of the second capacitor and the gate of the second read transistor. And the drain of the first write transistor is connected to the source of the second write transistor, and the drain of the first read transistor is connected to the source of the second read transistor. Further, the gate of the first write transistor is connected to the first write word line, the gate of the second write transistor is connected to the second write word line, the other electrode of the first capacitor is connected to the first read word line, and the other electrode of the second capacitor is connected to the second read word line.

[0039] Also, the drain of the first write transistor is connected to the source of the second write transistor, and the drain of the first read transistor is connected to the source of the second read transistor. Further, the gate of the first write transistor is connected to the first write word line, the gate of the second write transistor is connected to the second write word line, the other electrode of the first capacitor is connected to the first read word line, and the other electrode of the second capacitor is connected to the second read word line. to the first write word line, the gate of the second write transistor is connected to the second write word line, the other electrode of the first capacitor is connected to the first read word line, and the other electrode of the second capacitor is connected to the second read word line. to the second read word line, respectively.

[0040] ​​​​​​​Also, the source of the first write transistor and the source of the first read transistor may be connected to the bit line. Note that, between the source of the first write transistor and the bit line, or, either one or both of the source of the first read transistor and the bit line may have one or more transistors inserted therebetween.

[0041] The first write word line, the second write word line, the first read word line, and the second read word line are parallel to each other and orthogonal to the bit line.

[0042] FIG. 16(A) illustrates an example of a memory unit having the above structure. The memory unit shown here has a plurality of unit memory cells each including one write transistor, one read transistor, and one capacitor. That is, a memory unit including three memory cells is shown, which are a first memory cell composed of a write transistor WTr1, a read transistor RTr1, and a capacitor C1, a second memory cell composed of a write transistor WTr2, a read transistor RTr2, and a capacitor C2, and a third memory cell composed of a write transistor WTr3, a read transistor RTr3, and a capacitor C3.

[0043] The drain of the write transistor in each memory cell is connected to one electrode of the capacitor and the gate of the read transistor. The potential at the intersection where these transistors and capacitors are connected is related to the on / off of the read transistor, and hereinafter, these intersections are referred to as nodes F1, F2, and F3.

[0044] The drain of the write transistor WTr1 is connected to the source of the write transistor WTr2.​​​​​​​​​​​​ The drain of the read transistor RTr1 is connected to the source of the read transistor RTr2. In addition, the drain of the write transistor WTr2 is connected to the The drain of the read transistor RTr2 is connected to the source of the read transistor WTr3. Connect this pin to the source of transistor RTr3.

[0045] In this example, the drain of the read transistor RTr3 is connected to the bias line S. One or more transistors are placed between the drain of the readout transistor RTr3 and the bias line S. The source of the write transistor WTr1 and the source of the read transistor R The source of Tr1 is connected to the bit line R. The gates of WTr3 are connected to the write word lines Q1, Q2, and Q3, respectively. The other electrodes of the transistors C1, C2, and C3 are connected to read word lines P1, P2, and P3.

[0046] The write word lines Q1, Q2, and Q3 and the read word lines P1, P2, and P3 are parallel to each other. and is perpendicular to the bit line R. Note that the bias line S is always kept at a constant potential. If there is, it is not necessary to make it parallel or perpendicular to other wiring. From the viewpoint of increasing the efficiency, it is preferable that the gate line is perpendicular to the bit line.

[0047] In this way, the three memory cells share the contact between the bit line and the memory cell. By doing so, the area of ​​the contacts per unit memory cell can be reduced. In FIG. 16A, three memory cells are provided in the memory unit. However, one storage unit may be configured with more storage cells. Alternatively, one memory unit may be composed of 16, 32, or other numbers of memory cells.

[0048] Such a structure is similar to the NAND structure of a flash memory. As shown in FIG. 16(A), by connecting the memory cells in series, more memory cells can share a contact provided between one bit line and the memory cells, and the area per unit memory cell can be reduced. For example, when the minimum processing line width is F, the area per unit memory cell in the semiconductor memory device can be reduced to 12F or less. 2

[0049] The circuit diagram shown in FIG. 16(A) is one memory unit used in the semiconductor memory device. However, the semiconductor memory device is obtained by configuring these memory units in a matrix. An example is shown in FIG. 19. Here, eight memory units, namely, the (m - 1)th column, the mth column, the (m + 1)th column, and the (m + 2)th column in the nth row, and the (m - 1)th column, the mth column, the (m + 1)th column, and the (m + 2)th column in the (n + 1)th row, and 24 memory cells are shown.

[0050] For the memory unit in the nth row and the mth column, write word lines Q1n, Q2n, Q3n, read word lines P1n, P2n, P3n, a bias line Sn, and a bit line Rm are provided. The same applies to other memory units.

[0051] Another aspect of the present invention is a memory unit formed by using a plurality of write transistors, read transistors, and capacitors similar to those shown in FIG. 16(A). It is a semiconductor memory device. That is, the drain of the first write transistor is connected to one electrode of the first capacitor and the gate of the first read transistor, and the drain of the second write transistor is connected to one electrode of the second capacitor and the gate of the second read transistor, and the drain of the third write transistor is connected to one electrode of the third cap acitor and the gate of the third read transistor.

[0052] Also, the drain of the first write transistor is connected to the source of the second write transistor and the drain of the first read transistor is connected to the source of the second read transistor . Similarly, the drain of the second write transistor is connected to the source of the third write trans istor and the drain of the second read transistor is connected to the source of the third read trans istor.

[0053] Furthermore, the gate of the first write transistor is connected to the first write word line and the other electrode of the first cap acitor, and the gate of the second write transistor is connected to the second write word line and the other electrode of the second capacitor, and the gate of the third write transistor is connected to the third write word line.

[0054] Also, the source of the first write transistor and the source of the first read transistor may be connected to the bit line. Note that between the source of the first write transistor and the bit line, or either one or both between the source of the first read transistor and the bit line, one or more transistors may be inserted.

[0055] The first write word line, the second write word line, and the third write word line are parallel to each other and orthogonal to the bit lines.

[0056] FIG. 16(B) illustrates an example of a memory unit having the above structure. In FIG. 16(B), the memory unit includes a plurality of unit memory cells each having one write transistor, one read transistor, and one capacitor. That is, a first memory cell including a write transistor WTr1, a read transistor RTr1, and a capacitor C1, a second memory cell including a write transistor W Tr2, a read transistor RTr2, and a capacitor C2, and a third memory cell including a write transistor WTr3, a read transistor RTr3, and a capacitor C3, and a memory unit including three such memory cells is shown. The drain of the write transistor in each memory cell is connected to one electrode of the capacitor , and the gate of the read transistor is connected. The potential at the intersection where these transistors and capacitors are connected is related to the on / off of the read transistor. Therefore, hereinafter, these intersections are referred to as nodes F1, F2, and F3. The drain of the write transistor WTr1 is connected to the source of the write transistor WTr2,

[0057] and the drain of the read transistor RTr1 is connected to the source of the read transistor RTr2. Further, the drain of the write transistor WTr2 is connected to the source of the write transistor WTr3, and the drain of the read transistor RTr2 is connected to the source of the read transistor RTr3. The potential at the intersection where these transistors and capacitors are connected is related to the on / off of the read transistor. Therefore, hereinafter, these intersections are referred to as nodes F1, F2, and F3.

[0058] The drain of the write transistor WTr1 is connected to the source of the write transistor WTr2, and the drain of the read transistor RTr1 is connected to the source of the read transistor RTr2. Further, the drain of the write transistor WTr2 is connected to the source of the write transistor WTr3, and the drain of the read transistor RTr2 is connected to the source of the read transistor RTr3. Furthermore, the drain of the write transistor WTr2 is connected to the source of the write transistor WTr3, and the drain of the read transistor RTr2 is connected to the source of the read transistor RTr3. The drain of the write transistor WTr2 is connected to the source of the write transistor WTr3, and the drain of the read transistor RTr2 is connected to the source of the read transistor RTr3.

[0059] In this example, the drain of the read transistor RTr3 is connected to the bias line S. The read There may be one or more transistors between the drain of the read transistor RTr3 and the bias line S. Also, the source of the write transistor WTr1 and the source of the read transistor R Tr1 are connected to the bit line R. The gates of the write transistors WTr1, WTr2, WTr3 are connected to the write word lines Q1, Q2, Q3, respectively. The other electrodes of the capacitors C1, C2 are also connected to the write word lines Q2, Q3, respectively. Also, the other electrode of the capacitor C3 is connected to the read word line P.

[0060] The write word lines Q1, Q2, Q3 and the read word line P are parallel to each other and orthogonal to the bit line R. Note that if the bias line S is always kept at a constant potential, it is not necessary to make it parallel or orthogonal to the other wirings. However, from the viewpoint of increasing the integration density, it is preferable to make it orthogonal to the bit line.

[0061] Similar to the memory unit shown in FIG. 16(A), by sharing the contacts provided between the bit line and the memory cells among three memory cells, the contact area of this part per unit memory cell can be reduced, and the integration density can be improved. By sharing the contacts provided between one bit line and the memory cells among more memory cells, the area per unit memory cell can be reduced. In addition, in the configuration shown in FIG. 16(B), there is also an effect of reducing the area by substituting a part of the read word line required in the configuration shown in FIG. 16(A) with a write word line. Above all, the area per unit memory cell can be reduced.

[0062] In addition, in the configuration shown in FIG. 16(B), there is also an area reduction effect by substituting a part of the read word line required in the configuration shown in FIG. 16(A) with a write word line. As described above, Due to effects such as the above, for example, the area per unit memory cell in a semiconductor memory device can be reduced to 9 F 2 or less.

[0063] As mentioned above, several configurations have been shown as means for solving the problems. However, in this specification, other solution steps are also disclosed. In addition, even if obvious changes are made by those skilled in the art to the above configurations and other solution means disclosed in this specification, the problems can still be solved. Therefore, the means for solving the problems are not limited to the above three configurations.

Advantages of the Invention

[0064] By adopting any of the above configurations, at least one of the above problems can be solved. Regarding the number of rewrite cycles, in the above configurations, since all write operations are performed by turning on and off the write transistor, deterioration of the insulating film cannot occur. That is, the semiconductor memory device with the above configuration has substantially no restriction on rewriting.

[0065] Also, regarding the period during which data can be stored, the semiconductor memory device with the above configuration exhibits excellent characteristics. By setting the leakage current between the source and drain of the transistor in the off state, the gate leakage current, and the internal leakage current of the capacitor to the above conditions, charges can be retained for 10 hours or more, preferably 100 hours or more. Furthermore, by improving the conditions, charges can be retained

[0066] for 1 month or more, or 1 year or more. When charges are reduced due to leakage, refreshing can be performed in the same manner as in a conventional During this period, since the charge is retained, the refresh interval can be, for example, once a month or once a year. Frequent refreshing, which was necessary in conventional DRAMs, is not required , resulting in a semiconductor memory device with lower power consumption.

[0067] In the semiconductor memory device with the above configuration, data does not disappear due to a read operation. Conventionally, such a feature could be realized in SRAMs, but the semiconductor memory device with the above configuration has fewer transistors used in one memory cell than conventional SRAMs, five or less, typically two. Moreover, if one of the transistors is formed using a thin-film oxide semiconductor, it can be formed by laminating on a conventional silicon semiconductor, thus improving the integration density.

[0068] Regarding the integration density, in the semiconductor memory device with the above configuration, the absolute value of the capacity required for the memory cell can be reduced. For example, in DRAMs, the capacity of the memory cell needs to be at least the same as or greater than the wiring capacitance for normal operation, so a capacity of at least 30 fF is required. However, since the capacity is proportional to the area, as the integration density increases, the area of one memory cell becomes smaller, and it becomes impossible to secure the required capacity. Therefore, in DRAMs, it was necessary to form a large capacity using special shapes or

[0069] On the other hand, in the semiconductor memory device with the above configuration, the capacitance of the capacitor can be determined by the relative ratio to the gate capacitance of the read transistor. That is, even when the integration density increases, this means that the gate capacitance of the read transistor becomes The capacitance required for the pass transistor also decreases at the same ratio. Therefore, even with increasing integration density, capacitors with basically the same structure can be used.

[0070] Furthermore, the semiconductor memory device having the above configuration does not require a necessarily high voltage during writing and erasing in the FGNVM. Among FGNVMs, the so-called flash memory (especially NAND) was advantageous over SRAM and DRAM in terms of integration density, but in order to perform data rewriting even partially, it was necessary to erase a certain area collectively using a high voltage. In this regard, since the semiconductor memory device having the above configuration performs writing (rewriting) for each row, it is completed with the minimum necessary operations. In addition, in FGNVM, the injection of charge into the floating gate during writing is a one-way process and is performed in a non-equilibrium state, so the variation in the amount of charge was large. Although it is possible to store multi-level data depending on the amount of charge held in the floating gate, considering the variation in the amount of charge, about four levels (2 bits) were common. In order to store higher-bit data, it was necessary to use a higher voltage. On the other hand, in the configuration having the above configuration, since the accumulation of charge in the capacitor is performed reversibly, the variation is small. For example, the variation in the threshold value of the read transistor due to charge injection can be reduced to 0.5 volts or less. For this reason, more data can be held in one memory cell in a narrower voltage range, and as a result, the voltage for writing and reading can also be lowered. For example, when writing and reading 4-bit (16-level) data, it is completed with the minimum necessary operations. In addition, in FGNVM, the injection of charge into the floating gate during writing is a one-way process and is performed in a non-equilibrium state, so the variation in the amount of charge was large. Although it is possible to store multi-level data depending on the amount of charge held in the floating gate, considering the variation in the amount of charge, about four levels (2 bits) were common. In order to store higher-bit data, it was necessary to use a higher voltage. it is completed with the minimum necessary operations.

[0071] In contrast, in the configuration having the above configuration, since the accumulation of charge in the capacitor is performed reversibly, the variation is small. For example, the variation in the threshold value of the read transistor due to charge injection can be reduced to 0.5 volts or less. For this reason, more data can be held in one memory cell in a narrower voltage range, and as a result, the voltage for writing and reading can also be lowered. For example, when writing and reading 4-bit (16-level) data, it is completed with the minimum necessary operations. In addition, in FGNVM, the injection of charge into the floating gate during writing is a one-way process and is performed in a non-equilibrium state, so the variation in the amount of charge was large. Although it is possible to store multi-level data depending on the amount of charge held in the floating gate, considering the variation in the amount of charge, about four levels (2 bits) were common. In order to store higher-bit data, it was necessary to use a higher voltage. In contrast, in the configuration having the above configuration, since the accumulation of charge in the capacitor is performed reversibly, the variation is small. For example, the variation in the threshold value of the read transistor due to charge injection can be reduced to 0.5 volts or less. For this reason, more data can be held in one memory cell in a narrower voltage range, and as a result, the voltage for writing and reading can also be lowered. For example, when writing and reading 4-bit (16-level) data, it is completed with the minimum necessary operations.

[0072] In contrast, in the configuration having the above configuration, since the accumulation of charge in the capacitor is performed reversibly, the variation is small. For example, the variation in the threshold value of the read transistor due to charge injection can be reduced to 0.5 volts or less. For this reason, more data can be held in one memory cell in a narrower voltage range, and as a result, the voltage for writing and reading can also be lowered. For example, when writing and reading 4-bit (16-level) data, it is completed with the minimum necessary operations. In addition, in FGNVM, the injection of charge into the floating gate during writing is a one-way process and is performed in a non-equilibrium state, so the variation in the amount of charge was large. Although it is possible to store multi-level data depending on the amount of charge held in the floating gate, considering the variation in the amount of charge, about four levels (2 bits) were common. In order to store higher-bit data, it was necessary to use a higher voltage. In contrast, in the configuration having the above configuration, since the accumulation of charge in the capacitor is performed reversibly, the variation is small. For example, the variation in the threshold value of the read transistor due to charge injection can be reduced to 0.5 volts or less. For this reason, more data can be held in one memory cell in a narrower voltage range, and as a result, the voltage for writing and reading can also be lowered. For example, when writing and reading 4-bit (16-level) data, it is completed with the minimum necessary operations. The voltage to be used can be 10 volts or less.

Brief Description of the Drawings

[0073]

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Embodiments for Carrying Out the Invention

[0074] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description content of the following embodiments.

[0075] Also, items such as the structures and conditions disclosed in the following embodiments can be appropriately combined in other embodiments. In the configurations described below, the same components are denoted by common reference numerals among different drawings, and detailed descriptions of the same parts or parts having the same functions may be omitted.

[0076] Also, in the following embodiments, for ease of understanding, the timing, width, height, etc. of the pulses are written to have constant values. However, from the gist of the present invention, it will be easily understood that the pulses do not necessarily need to have exactly synchronized timing, a constant width, or a constant height. .

[0077] (Embodiment 1) In this embodiment, with reference to FIG. 4, an example of the operation of the semiconductor memory device shown in FIGS. 1(A) and (B) will be described. Here, specific numerical values are given below for the potential, but that is for the purpose of assisting in understanding the technical idea. Needless to say, those values can be changed depending on various characteristics of transistors and capacitors, or depending on the convenience of the implementer. Also, the semiconductor memory device shown in FIG. 1 can write or read data by methods other than the following methods.

[0078] Here, the write transistor WTr(n,m) is of the N-channel type, and the read transistor RTr(n,m) is of the P-channel type. The write transistor WTr(n,m) turns on (conducts current) when the gate potential is 1 V or more higher than the potential of either the source or the drain, and is off (does not conduct current) otherwise. Also, the read transistor RTr(n,m) turns on (conducts current) when the gate potential is 1 V or more lower than the potential of either the source or the drain, and is off (does not conduct current) otherwise.

[0079] Also, among the gate capacitances of the read transistor RTr(n,m), due to the gate bias The fluctuations are considered negligible compared to the capacitance of the capacitor C(n,m). Furthermore, , the parasitic capacitances of the write transistor WTr(n,m) and the read transistor RTr(n ,m), and other capacitances not shown in the figure, such as the parasitic capacitance between wirings, are all considered to be 0. Also, in FIG. 4, a filled circle is marked on the transistor in the on state, and a cross is marked on the transistor in the off state, which are superimposed on the symbol of the transistor. For those that turn on under specific conditions, they may be separately described in the figure.

[0080] At the time of writing, as shown in FIG. 4(A), the potentials of the read word line Pn and the bias line Sn are set to 0V. Also, the potential of the bit line Rm takes on four levels of values: 0V, +1V, , +2V, and +3V according to the data to be written. Then, when the potential of the write word line Qn is set to +4V, the write transistor WTr(n,m) turns on, and the potential of the drain of the write transistor WTr(n,m) approaches the potential of the source of the write transistor (i.e., the bit line Rm). Here, it is assumed to be equal to the potential of the bit line Rm.

[0081] On the other hand, at this stage, the potential of the gate of the read transistor RTr(n,m) is equal to the potential of the drain of the write transistor WTr(n,m). That is, the potential of the gate of the read transistor RTr(n,m) is 0V or higher, and is the same as the potential of the source of the read transistor RTr( n,m) (i.e., the bit line Rm).

[0082] Also, the drain of the read transistor RTr(n,m) (i.e., the bias line Sn) The potential is 0V. Therefore, since the potential of the gate of the read transistor RTr(n,m) is the same as or higher than the potentials of the source and drain, the read transistor RTr(n,m ) is in the off state. In this way, data can be written.

[0083] Note that, as much as possible including during writing, keeping the read transistor RTr(n,m) in the off state is effective in reducing the leakage current from the gate to the source, or alternatively from the gate to the drain of the read transistor RTr(n,m). Generally, such a leakage current increases in the on state and becomes very small in the off state.

[0084] Since such a leakage current is the leakage of the charge held in the capacitor C(n,m), if the amount is large, it means a reduction in the data holding time. In the present embodiment, since the read transistor RTr(n,m) turns on only during reading, it is excellent in terms of data retention.

[0085] Next, when writing to a row other than the n-th row, as shown in Fig. 4(B), the potential of the write word line Qn is set to -3V. Also, the potential of the read word line Pn is set to +3V, and the potential of the bias line Sn is set to 0V. On the other hand, the potential of the bit line Rm takes four levels of values, 0V, +1V, +2V, +3V, according to the data to be written to the row where writing is performed.

[0086] Since the potential of the drain of the write transistor WTr(n,m) is connected via the read word line Pn and the capacitor C(n,m), the potential of the read word line Pn changes ( that is, rises from 0V in Fig. 4(A) to +3V in Fig. 4(B)), causing a 3V rise. ​​​​​​ That is, according to the written data, it becomes one of +3V, +4V, +5V, and +6V. value.

[0087] Also, in this state, the potential of the source (bit line Rm) of the write transistor WTr(n,m) (0 to +3V) and the potential of the drain of the write transistor WTr(n,m) (+3 ~ +6V), the potential of the gate of the write transistor WTr(n,m) (-3V) is lower, so the write transistor WTr(n,m) is turned off.

[0088] Furthermore, the potential of the source of the read transistor RTr(n,m) (i.e., the bit line Rm) (0 to +3V) and the potential of the drain of the read transistor RTr(n,m) (i.e., the bias line Sn) (0V), the potential of the gate of the read transistor RTr(n,m) (+3 to +6V) is higher, so the read transistor RTr(n,m) is turned off. off.

[0089] Next, reading will be described. As shown in Fig. 4(C), the potential of the write word line Qn and the ba bias line Sn is set to -3V. Also, the potential of the read word line Pn is set to 0V. In this state, the potential of the drain of the write transistor WTr(n,m) is according to the written data, one of 0V, +1V, +2V, and +3V, and if the potential of the bit line Rm is between -3V and 0V, both the write transistor WTr(n,m) and the read transistor RTr(n,m) are turned off. That is, for the lines that are not read, in this way, the write transistor and the read transistor are turned off. In this way.

[0090] On the other hand, for the row to be read, the potential of the read word line Pn is set to -3V. As a result, the potential of the gate of the read transistor RTr(n,m) becomes either -3V, -2V, -1V, or 0V according to the written data. Also, the potential of the bit line Rm is set to - 3V. At this time, if the potential of the bias line Sn is -3V, the read transistor RTr(n,m) is off. However, as shown in Fig. 4(D), if the potential of the bias line Sn becomes -2V and the potential of the gate of the read transistor

[0091] RTr(n,m) is -3V, the read transistor R Tr(n,m) turns on. When the read transistor RTr(n,m) turns on, current flows through the bit line Rm. By detecting this, it is possible to know that the read transistor RTr(n,m)

[0092] is in the on state. Alternatively, if the end of the bit line Rm is a capacitor, the initial potential (-3V) approaches the potential of the bias line Sn. Thus, it is still possible to know that the read transistor RTr(n,m) is in the on state. Similarly, as shown in Fig. 4(E), if the potential of the bias line Sn becomes -1V and the potential of the gate of the read transistor RTr(n,m) is -3V or -2V, the read transistor RTr(n,m) turns on.

[0093] Also, as shown in Fig. 4(F), if the potential of the bias line Sn becomes 0V and the potential of the gate of the read transistor RTr(n,m) is -3V, -2V, or -1V, the read transistor RTr(n,m) turns on.

[0094] Moreover, as shown in Fig. 4(F), if the potential of the bias line Sn becomes 0V, the read transistor RTr(n,m) turns on when the potential of the gate of the read transistor The output transistor RTr(n,m) turns on.

[0095] Even if the potential of the bias line is set to 0V, if the read transistor RTr(n,m) remains off then the potential of the gate of the read transistor RTr(n,m) can be estimated to be 0V.

[0096] In this way, 4-level data (2 bits) can be written and read. Of course, in the same manner, even more data, for example, 8-level data (3 bits), 16-level data (4 bits) can be written and read.

[0097] In the above description, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) were ignored with respect to the capacitance of the capacitor C(n,m), but in a real memory cell, it is necessary to determine the applied potential considering them.

[0098] The gate capacitance of the read transistor RTr(n,m) varies greatly between the on-state and the off-state, so the potential of the gate of the read transistor RTr(n,m) is affected by it. The larger the ratio of the gate capacitance of the read transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) should be set to be at least twice the gate capacitance of the read transistor RTr(n,m).

[0099] Note that in order to store multi-level data (multi-valued data) by making the amount of charge held in the memory cell multi-level, it is necessary that the variation in the amount of charge held is small. The semiconductor memory circuit and the semiconductor memory device shown in this embodiment have a small variation in the amount of charge held.​ Since the latency is small, it is suitable for this purpose.

[0100] (Embodiment 2) In this embodiment, regarding the writing method and the reading method to the semiconductor memory device shown in Embodiment 1, the timing of signals applied to various wirings will be described. First, the writing method will be described with reference to FIG. 2.

[0101] As described in Embodiment 1, signals corresponding to data are applied to bit lines (··, Rm-1, Rm, Rm+1, ··). Here, the potential of the bit lines is set to be equal to or higher than VRM and equal to or lower than VRH. Also, signals that turn on the write transistors are sequentially applied to the write word lines (for example, Qn) of the row where the memory cells to be written are located. Further, signals that set appropriate potentials are applied to the read word lines (for example, Pn) and the bias lines (for example, Sn) of the same row. Let the potential of the write word line at this time be VQH, the potential of the read word line be VPM, and the potential of the bias line be VSM. On the other hand, signals that turn off the write transistors are applied to the write word lines of the other rows, and signals that set appropriate potentials are applied to the read word lines and the bias lines, respectively. Let the potential of the write word line at this time be VQL, the potential of the read word line be VPM, and the potential of the bias line be VSH.

[0102] Here, in order to turn off the read transistor, the potential VPH of the read word line must be equal to or higher than (VPM+(VRH-VRM)), and the potential VSH of the bias line must be

[0103] It is preferably below (VRM+(VPH-VPM)). For example, when the potential of the bit line takes four levels of values of VRM, VRM+α, VRM+2α, VRM+3α (α>0), then, since VRH = VRM+3α, the potential VPH of the read word line is preferably equal to or higher than (VPM+3α).

[0104] In Embodiment 1, VRM = 0 [V], α = 1 [V], VPM = 0 [V], VSM = 0 V], VPH = +3 [V], VSH = 0 [V], which satisfies the above conditions. In Embodiment 1, the potentials (VSM, VSH) of the bias lines are always held at 0 V during writing (i.e., VSM = VSH = 0), but may be varied depending on whether data is written to the row or not.

[0105] A timing chart of the signals considering the above is shown in FIG. 2. FIG. 2 shows examples of the pulses applied to the write word lines (Qn-1, Qn, Qn+1), the bit lines (Rm-1, Rm, Rm+1), and the read word lines (Pn-1, Pn, Pn+1). The peak and amplitude of the pulses are conceptual. The duration of the pulses may be determined in consideration of the characteristics of the write transistor.

[0106] In the figure, the pulses applied to the write word lines (Qn-1, Qn, Qn+1) are shown not to overlap. However, for example, a part of the time when a pulse is applied to the write word line Qn-1 may overlap with the time when a pulse is applied to the write word line Qn. Also, VQL needs to be below the threshold of the write transistor. In Embodiment 1, it is It was necessary, and in Embodiment 1, it was set to +4 volts. However, it is also possible to take values other than these.

[0107] The signals applied to the bit lines (Rm-1, Rm, Rm+1) consist of a plurality of pulses, and their heights can be various. Here, it is set to four levels of VRM, VRM+α, VRM+2α, VRM+3α (α>0). These pulses do not completely synchronize with the pulses of 1 the write word line. Instead, it is preferable that they start after a certain time (τ 2 ) after the pulses of the write word line start, and it is also preferable that 1 they end after a certain time (τ 2 ) after the pulses of the write word line end. Here, τ <τ 1 >τ 2 is also possible, but for circuit design, it is preferable to set τ 1 =τ 2 . Preferably.

[0108] Also, the pulses applied to the read word lines (Pn-1, Pn, Pn+1) may be synchronized with the pulses applied to the write word lines or delayed slightly. To ensure that the potential of the drain of the write transistor is set to the set value, the pulses applied to the read word lines (Pn- 1, Pn, Pn+1) preferably end after a certain time has elapsed after the

[0109] pulses applied to the write word lines of the same row have ended. In this way, the potential of the drain of the write transistor of each memory 、For the amounts of charge corresponding to the potentials VRL, VRL+α, VRL+2α, and VRL+3α, respectively 、if they are Q0, Q1, Q2, and Q3, the amounts of charge of the respective memory cells are as shown in Table 1. As the write gate transistors, those with low leakage current between the source and the drain in the off state are used so that these charges can be retained for a considerably long time (10 hours or more) even after the power supply to this semiconductor memory device is stopped.

[0110]

Table 1

[0111] Next, the read method will be described with reference to FIGS. 3(A) and (B). In FIG. 3(B) shows the principle of an example of the method for performing the read operation. As shown in FIG. 3(B), at the end of the bit line Rm, a capacitor 13, means 11 for measuring the potential of the electrode of the capacitor 13, means 12 for applying a potential to the capacitor 13, and a switch 14 are provided.

[0112] First, the switch 14 is turned on, and by means 12 for applying a potential to the capacitor 13, the potential of the electrode on the memory cell side of the capacitor 13 (the upper side in the figure), that is, the potential of the bit line Rm is set to a specific potential VRL. Then, the switch 14 is turned off. After that, if for some reason the potential of the bit line Rm fluctuates, the change in potential can be observed by means 11 for measuring the potential of the electrode of the capacitor. After a series of operations is completed, the potential of the bit line Rm is set to VRL again.

[0113] In the row where the read operation is performed, the read transistor is turned on by the potential of the bias line ​It turns on or off. For example, as shown in FIG. 3(A), pulses of three types of heights (VS1, VS2, VS3) are sequentially input to bias lines Sn-1 , Sn, and Sn+1.

[0114] In Embodiment 1, as is clear from the description related to FIGS. 4(D) to (F), depending on the potential of the gate of the read transistor and the potential of the bias line, the read transistor can be in an on state or an off state. Here, for a pulse of height VS1, when the charge held in the memory cell is Q0, the read transistor turns on, and for a pulse of height VS2, when the charge held in the memory cell is Q0 and Q1, the read transistor turns on, and for a pulse of height VS3, when the charge held in the memory cell is Q0, Q1, and Q2, it is assumed that the read transistor turns on.

[0115] If the read transistor turns on, the potential of the bit line approaches or becomes the same as the potential of the bias line. By measuring this variation with means 11 for measuring the potential of the electrode of the capacitor in FIG. 3(B), it is possible to observe whether or not the read transistor has turned on.

[0116] For example, when pulses of three different heights are applied to the same memory cell, if the charge held in the memory cell is Q0, the potential of the capacitor varies in response to pulses of all heights. That is, three pulses are observed.

[0117] However, if the charge held in the memory cell is Q1, it does not respond to the lowest pulse and responds to the remaining two pulses, so two pulses are observed. Similarly, for the same memory If the charge held in the cell is Q2, it responds only to the highest pulse, so only one pulse is observed. If the charge held in the memory cell is Q3, it does not respond to any pulse and no pulse is observed at all.

[0118] In this way, by recording how many pulses have occurred for each memory cell, the information written in the memory cell can be known. For example, according to Fig. 3(A), the memory cell in the (n + 1)-th row and the (m - 1)-th column generates pulses three times in a series of readouts. This is because, since the held charge was Q0, in response to all the pulses applied to the bias line Sn, it becomes on state and the potential of the bit line Rm becomes the same as or close to the potential of the bias line Sn.

[0119] Conversely, the memory cell in the n-th row and the m-th column did not generate any pulses. This is because the charge amount of this memory cell was most Q3, so it did not become on state even with the highest VS3 pulse. By tabulating the pulses emitted by each memory cell in this way, it becomes as shown in Table 2. As described above, the data stored in each memory cell can be read out. In the above example, an example of sequentially reading data row by row was shown, but in the same way, only the data of a specific

[0120]

Table 2

[0121] Note that by the number of pulses generated as described above, the charge amount held in In addition, the voltage can also be directly measured and known. For example, as shown in FIG. 3(C), when reading the potential of the word line Pn is set to -3V and the potential of the write word line Qn is set to -3V, then writing transistor WTr(n,m) is in the off state, and the potential of the gate of the read transistor RTr(n,m ) will be between -3V and 0V.

[0122] Also, the capacitor 13 in FIG. 3(B) is connected to the end of the bit line Rm, and it is assumed that the potential of the bit line Rm is 0V. Also, initially, it is assumed that the potential of the bias line Sn is 0V. Then , in this state, if the potential of the gate of the read transistor RTr(n,m) is -3V, -2 V, or -1V, the read transistor RTr(n,m) is in the on state, but since the potentials of the source and the drain are equal, no current flows. Also, if the potential of the gate of the read transistor RTr (n,m) is 0V, the read transistor RTr(n,m) is in the off state.

[0123] Next, when the potential of the bias line Sn is lowered to -3V, when the potential of the gate of the read transistor RTr(n, m) is other than 0V, a current flows between the source and the drain of the read transistor RTr(n,m). However, since the end of the bit line Rm is the capacitor 13 , and when the potential of the bit line Rm reaches a certain value, the current stops flowing. For example, if the potential of the gate of the read transistor RTr(n,m) is -2V,

[0124] then the potential of the bit line Rm decreases from 0V. When the potential of the bit line Rm reaches -1V, at this stage, the potential of the gate of the read transistor RTr(n,m) (-2V) is the same as the potential of the source , and the potential of the bit line Rm starts to decrease. When the potential of the bit line Rm reaches -1V, Since it is 1V lower than the bit (-1V), the read transistor RTr(n,m) is in the on state. However, when the potential of the bit line Rm further decreases, the read transistor RTr( n,m) turns off because the difference between the potential of the gate (-2V) and the potential of the source (less than -1V, which is the potential of the bit line Rm) is less than 1V. As a result, the charge amount of the bit line Rm does not change, and the potential of the bit line Rm becomes almost constant.

[0125] In this case, the potential of the bit line Rm is lower than -1V, but before it drops to -2V, the read transistor RTr (n,m) turns off. Therefore, the potential of the bit line Rm is not less than -2V and less than -1V. At this time, the potential of the bit line Rm can be detected by the means 11 for measuring the potential in Fig. 3(B). That is, if the potential of the bit line Rm is not less than -2V and less than -1V, it can be inferred that the potential of the gate of the read transistor RTr(n,m) was -2V. From this, the data written in this memory cell can be known.

[0126] Similarly, if the potential of the gate of the read transistor RTr(n,m) is -3V or -1V, the potential of the bit line Rm is not less than -3V and less than -2V, and not less than -1V and less than 0V, respectively. If the potential of the gate of the read transistor RTr(n,m) is 0V, since the read transistor RTr(n,m) remains in the off state, the potential of the bit line Rm does not change from 0V. Even in this way, the charge amount at the time of writing can be known.

[0127] (Embodiment 3) In this embodiment, the shape and manufacturing method of the semiconductor memory device described in Embodiments 1 and 2 An example will be described. In the present embodiment, the write transistor WTr uses an oxide semiconductor containing zinc and indium. As the read transistor RTr, a single crystal silicon semiconductor is used. Therefore, the write transistor WTr is provided by being stacked on the read transistor RTr.

[0128] That is, an insulated gate type transistor using a single crystal silicon semiconductor provided on a single crystal silicon substrate is used as the read transistor RTr, and on top of that, a transistor using an oxide semiconductor is formed and used as the write transistor WTr. Note that in the present embodiment, an example of forming a semiconductor memory device on a single crystal silicon substrate will be described, but it is also possible to provide it on other substrates. FIG. 7 shows a layout example of a memory cell of the semiconductor memory device according to the present embodiment. FIG. 7(A) shows main wirings, electrodes, etc. provided on a single crystal silicon substrate. An element isolation region 1 02 is formed on the substrate. On the substrate, conductive regions 106a and 106b using a conductive material or doped silicon are formed, and a part of them serves as the source and

[0129] drain of the read transistor RTr. A part of the conductive region 106b serves as a bias line. The conductive regions 106a and 106b are separated by the read gate 110 of the read transistor RTr. A first connection electrode 111 is provided in the conductive region 106a. region 106a. drain of the read transistor RTr. A part of the conductive region 106b serves as a bias line. The conductive regions 106a and 106b are separated by the read gate 110 of the read transistor RTr. A first connection electrode 111 is provided in the conductive region 106a.

[0130] FIG. 7(B) shows main wirings, electrodes, etc. centered on a transistor using an oxide semiconductor formed on the circuit of FIG. 7(A). An island-shaped oxide semiconductor region 112 and a first wiring 114 are shown. a. Form 114b. Here, the first wiring 114a is a write word line, and the first wiring 1 14b is a read word line. A part of the first wiring 114a overlaps with the oxide semiconductor region 112 and serves as the gate electrode of the write transistor WTr. Also, the oxide semiconductor region 1 12 is connected to the lower read gate 110. The first wiring 114b forms a capacitor at the overlapping portion with the read gate 110. Further, a second connection electrode 117 for connecting from the oxide semiconductor region 11 2 to the upper layer (for example, a bit line) is provided. .

[0131] As the read gate 110, a material that forms an ohmic contact with the oxide semiconductor to be formed later is preferable. Such materials include those whose work function W is approximately the same as or smaller than the electron affinity φ (the energy difference between the lower limit of the conduction band of the oxide semiconductor and the vacuum level) of the oxide semiconductor. That is, a material that satisfies the relationship W < φ + 0.3 [electron volts] is sufficient. For example, it is titanium, molybdenum, titanium nitride, etc.

[0132] When FIGS. 7(A) and (B) are superimposed, it becomes as shown in FIG. 7(C). Here, for the sake of showing the overlap, they are intentionally shifted a little and superimposed. Further, the second wiring 118 (such as a bit line) formed on the transistor using the oxide semiconductor is also shown.

[0133] Note that points A and B in FIGS. 7(A) to (C) indicate the same position. The design rules for such elements can be appropriately selected by the implementer. However, in terms of increasing the integration density, it is preferable that the channel width of each transistor is 10 nm or more and 0.1 μm or less, and the channel length is 10 nm or more and 0.1 μm or less.

[0134] Next, a method for manufacturing the semiconductor memory device having the above structure will be described. FIGS. 8 and 9 are cross-sections connecting point A and point B in FIG. 7. In the present embodiment, an n-type single crystal silicon substrate is used, but an n-type well may be formed in a p-type single crystal silicon substrate, and the transistors of the present embodiment may be provided thereon. Hereinafter, the manufacturing process will be described according to the figure numbers.

[0135] <FIG. 8(A)> First, using a known semiconductor manufacturing technology, on an n-type single crystal silicon substrate 101, as shown in FIG. 8(A ), an element isolation region 102, conductive regions 106a and 106b made of silicon doped p-type, a first gate insulating film 103, a dummy gate 104, and a first interlayer insulating film 107 are formed. In FIG. 8(A), two dummy gates 104 are shown, but as is clear from FIG. 7, these are continuous. Sidewalls may be provided on the side surfaces of the dummy gate 104 as shown in FIG. 8(A). As the dummy gate 104, polycrystalline silicon is preferably used. The thickness of the first gate insulating film 10 3 is preferably 10 nm or more in order to suppress leakage current. Also,

[0136] in order to make the gate capacitance smaller than the capacitance of the capacitor formed later, a material having a relatively low dielectric constant such as silicon oxide is preferably used as the dielectric of the first gate insulating film 103. insulating film 103. For the purpose of making the gate capacitance smaller than the capacitance of the capacitor to be formed later, it is preferable to use a material with a relatively low dielectric constant, such as silicon oxide, as the dielectric of the first gate insulating film 103.

[0137] Silicide regions 105a and 105b may be provided on the surfaces of the conductive regions 106a and 106b to enhance conductivity. Also, as described in relation to FIG. 7(A), ​​​The conductive region 106b forms part of the bias line.

[0138] The first interlayer insulator 107 may be a single layer or a multilayer, and may also include a stress liner for applying strain to the channel of the transistor. If the topmost film is made into a flat film by the spin coating method, it is advantageous in subsequent processes. For example, as the first interlayer insulator 107, a multilayer film formed by forming a silicon nitride film by plasma CVD method and then forming a flat silicon oxide film obtained by spin coating method thereon may be used. When forming a silicon nitride film by plasma CVD method as the first interlayer insulator 107 and forming a flat silicon oxide film obtained by spin coating method thereon, it may be used.

[0139] <Figure 8(B)> When the surface of the first interlayer insulator 107 is sufficiently flat, the first interlayer insulator 107 is etched by a dry etching method, and the dry etching is stopped when the upper surface of the dummy gate 104 appears. Instead of the dry etching method, a chemical mechanical polishing (CMP) method may be used, or after first flattening the surface of the first interlayer insulator 107 by the CMP method, the etching may be further advanced by the dry etching method. Alternatively, conversely, after etching the interlayer insulator to a certain extent by the dry etching method, it may be flattened by the CMP method. Thus, the first interlayer insulator 107a having a flat surface is obtained. After that, the dummy gate 104 is selectively etched to form an opening 108. When polycrystalline silicon is used as the material of the dummy gate 104, 2 to 40%, preferably 20 to 25% of TMAH (tetramethylammonium hydroxide) may be used.

[0140] <Figure 8(C)> Next, the dummy gate 104 is selectively etched to form an opening 108. When polycrystalline silicon is used as the material of the dummy gate 104, 2 to 40%, preferably 20 to 25% of TMAH (tetramethylammonium hydroxide) may be used. In addition, an opening 109 reaching the silicide region 105a is also formed in the first interlayer insulator 107a having a flat surface. And. The opening 109 reaching the silicide region 105a is also formed in the first interlayer insulator 107a having a flat surface.

[0141] <Figure 8(D)> Deposit a film of single-layer or multi-layer conductive material. As the conductive material, a material that forms an ohmic contact with the oxide semiconductor to be formed later is preferred. Also, since this conductive film is also the gate electrode of the read transistor (here, a P-channel type), appropriate physical property values such as work function are preferred in determining its threshold value. If a single material cannot satisfy these two requirements, a multi-layer film may be used to satisfy each condition. For example, a multi-layer film of titanium nitride and tantalum nitride may be used as the conductive material. requirements, a multi-layer film may be used to satisfy each condition. For example, a multi-layer film of titanium nitride and tantalum nitride may be used as the conductive material. Next, while planarizing the film of the conductive material by CMP, etching is performed. This operation may be stopped when the first interlayer insulator 107a having a flat surface appears. Thus, as shown in Figure 8(D), the read gate 110 and the first connection electrode 111 of the read transistor are formed. Then, in order to reduce hydrogen contained near the surface of the first interlayer insulator 107a having a flat surface, surface treatment with plasma containing fluorine is performed. If the hydrogen concentration of the first interlayer insulator 107a having a flat surface is sufficiently low, such treatment is not necessary. The hydrogen concentration in the region 100 nm from the surface of the first interlayer insulator 107a having a flat surface should be less than 1×10 requirements, a multi-layer film may be used to satisfy each condition. For example, a multi-layer film of titanium nitride and tantalum nitride may be used as the conductive material. cm Next, while planarizing the film of the conductive material by CMP, etching is performed. This operation may be stopped when the first interlayer insulator 107a having a flat surface appears. Thus, as shown in Figure 8(D), the read gate 110 and the first connection electrode 111 of the read transistor are formed. Then, in order to reduce hydrogen contained near the surface of the first interlayer insulator 107a having a flat surface, surface treatment with plasma containing fluorine is performed. If the hydrogen concentration of the first interlayer insulator 107a having a flat surface is sufficiently low, such treatment is not necessary. The hydrogen concentration in the region 100 nm from the surface of the first interlayer insulator 107a having a flat surface should be less than 1×10

[0142] Next, while planarizing the film of the conductive material by CMP, etching is performed. This operation may be stopped when the first interlayer insulator 107a having a flat surface appears. Thus, as shown in Figure 8(D), the read gate 110 and the first connection electrode 111 of the read transistor are formed. Then, in order to reduce hydrogen contained near the surface of the first interlayer insulator 107a having a flat surface, surface treatment with plasma containing fluorine is performed. If the hydrogen concentration of the first interlayer insulator 107a having a flat surface is sufficiently low, such treatment is not necessary. The hydrogen concentration in the region 100 nm from the surface of the first interlayer insulator 107a having a flat surface should be less than 1×10 cm <Figure 9(A)> Next, while planarizing the film of the conductive material by CMP, etching is performed. This operation may be stopped when the first interlayer insulator 107a having a flat surface appears. Thus, as shown in Figure 8(D), the read gate 110 and the first connection electrode 111 of the read transistor are formed. Then, in order to reduce hydrogen contained near the surface of the first interlayer insulator 107a having a flat surface, surface treatment with plasma containing fluorine is performed. If the hydrogen concentration of the first interlayer insulator 107a having a flat surface is sufficiently low, such treatment is not necessary. The hydrogen concentration in the region 100 nm from the surface of the first interlayer insulator 107a having a flat surface should be less than 1×10 cm Next, while planarizing the film of the conductive material by CMP, etching is performed. This operation may be stopped when the first interlayer insulator 107a having a flat surface appears. Thus, as shown in Figure 8(D), the read gate 110 and the first connection electrode 111 of the read transistor are formed. Then, in order to reduce hydrogen contained near the surface of the first interlayer insulator 107a having a flat surface, surface treatment with plasma containing fluorine is performed. If the hydrogen concentration of the first interlayer insulator 107a having a flat surface is sufficiently low, such treatment is not necessary. The hydrogen concentration in the region 100 nm from the surface of the first interlayer insulator 107a having a flat surface should be less than 1×10 cm 18 -3 cm -3 16 16 cm -3 -3

[0143] <Figure 9(A)> Form an oxide semiconductor film with a thickness of 3 to 30 nm by sputtering. The formation of the oxide semiconductor film The manufacturing method may be other than the sputtering method. The oxide semiconductor preferably contains gallium and indium. To improve the reliability of the semiconductor memory device, the hydrogen concentration in the oxide semiconductor film should be less than 1×10 18 cm -3 and preferably less than 1×10 16 cm -3 .

[0144] This oxide semiconductor film is etched to form island-shaped oxide semiconductor regions 112. Heat treatment may be performed on the oxide semiconductor regions 112 to improve semiconductor characteristics. Thus, a structure in which the read gate 110 is in contact with the oxide semiconductor region 112 and the first connection electrode 111 is in contact with the oxide semiconductor region 112 is obtained.

[0145] Thereafter, the second gate insulating film 113 is formed by a known film-forming method such as the sputtering method. For the purpose of reducing the leakage current, the thickness of the second gate insulating film 113 is preferably 10 nm or more, and the hydrogen concentration in the gate insulating film is less than 1×10 cm -18 and preferably less than 1×10 -3 cm 16 -3 .

[0146] As the gate insulating film, silicon oxide, aluminum oxide, hafnium oxide, lanthanum oxide, aluminum nitride, etc. may be used. Not only these single-layer films but also multilayer films may be used. The second gate insulating film 113 is also the dielectric of the capacitor formed by the read gate 110 and the first wiring 114b. In order to make the capacitance of the capacitor larger than the gate capacitance of the read transistor, it is preferable to use a material with a relative dielectric constant of 10 or more. Heat treatment may be performed to improve the characteristics of the oxide semiconductor region 112 even after the gate insulating film is formed. ​

[0147] <Fig.9(B)> The first wiring 114a (write word line) and the first wiring 114b (read A part of the first wiring 114a is a transistor using an oxide semiconductor. The first wirings 114a and 114b are made of a material having a work function of oxide. A material with an electron affinity 0.5 eV or higher than that of the semiconductor is preferred. For example, tungsten These include silicon, gold, platinum, and p-type silicon.

[0148] Between the read gate 110 and the first wiring 114b, a second gate insulating film 113 is provided as a dielectric. The capacitance of this capacitor is determined by the read gate 110 and the first wiring 114b, the area of ​​the overlap is 100 nm 2 More than 0.01 μm 2 It is preferable that:

[0149] In FIG. 9B, one end of the first connection electrode 111 and the gate electrode of the write transistor are One end of the first wiring 114a, and one end of the read gate 110 and the other end of the first wiring 114a The edges are shown to coincide exactly. However, in reality, the accuracy of the mask alignment is important. Depending on the angle, the first wiring 114a may be on the left side (first connection electrode 111 side) or the right side (reading In that case, the first distribution may be shifted toward the opposite side of the shifted side. The line 114a and either the first connection electrode 111 or the read gate 110 Since an offset state occurs between the transistor and the on-state transistor, the resistance of the transistor increases.

[0150] To prevent this, the width of the first wiring 114a is increased so that the wiring can overlap even with a slight misalignment. Although a method can be considered, parasitic capacitances are generated between the first wiring 114a and the first connection electrode 111 and the read gate 11 0, which is disadvantageous for high-speed operation. Also, increasing the width of the wiring is also contrary to the reduction of design rules.

[0151] To solve these problems, an n-type region may be formed self-alignedly using the first wiring 114a as a mask in the oxide semiconductor region. For this purpose, ions of an element that is more easily oxidized than the oxide semiconductor are implanted using a known ion implantation method. Such elements include titanium, zinc, magnesium, silicon, phosphorus, boron, etc. Generally, boron and phosphorus are easy to use because they are used in conventional semiconductor processes. In particular, for implantation into the thin second gate insulating film 113 and the oxide semiconductor region 112 as described above, phosphorus having a larger atomic weight than boron is desirable. titanium, zinc, magnesium, silicon, phosphorus, boron, etc. are mentioned. Generally, boron and phosphorus are easy to use because they are used in conventional semiconductor processes. In particular, for implantation into the thin second gate insulating film 113 and the oxide semiconductor region 112 as described above, phosphorus having a larger atomic weight than boron is desirable. phosphorus are easy to use because they are used in conventional semiconductor processes. In particular, for implantation into the thin second gate insulating film 113 and the oxide semiconductor region 112 as described above, phosphorus having a larger atomic weight than boron is desirable. phosphorus having a larger atomic weight than boron is desirable.

[0152] It is desirable that these ions contain as little hydrogen as possible. The concentration of hydrogen in the ions is preferably 0.1% or less. Although hydrogen is known to be a donor in oxide semiconductors, if hydrogen is contained in the ions, the hydrogen implanted into the oxide semiconductor moves in the oxide semiconductor and degrades the reliability of the device. It is desirable that these ions contain as little hydrogen as possible. The concentration of hydrogen in the ions is preferably 0.1% or less. Although hydrogen is known to be a donor in oxide semiconductors, if hydrogen is contained in the ions, the hydrogen implanted into the oxide semiconductor moves in the oxide semiconductor and degrades the reliability of the device. It is known that hydrogen is a donor in oxide semiconductors. However, if hydrogen is contained in the ions, the hydrogen implanted into the oxide semiconductor moves in the oxide semiconductor and degrades the reliability of the device. moves in the oxide semiconductor and degrades the reliability of the device.

[0153] In oxide semiconductors, since the implanted ions combine with oxygen, oxygen deficiencies occur and n-type conductivity is exhibited. The difference from silicon semiconductors is that in silicon semiconductors, heat treatment is required to recover crystallinity after ion implantation, but in many oxide semiconductors, high conductivity can be obtained without performing such heat treatment. In oxide semiconductors, since the implanted ions combine with oxygen, oxygen deficiencies occur and n-type conductivity is exhibited. The difference from silicon semiconductors is that in silicon semiconductors, heat treatment is required to recover crystallinity after ion implantation, but in many oxide semiconductors, high conductivity can be obtained without performing such heat treatment. In oxide semiconductors, since the implanted ions combine with oxygen, oxygen deficiencies occur and n-type conductivity is exhibited. The difference from silicon semiconductors is that in silicon semiconductors, heat treatment is required to recover crystallinity after ion implantation, but in many oxide semiconductors, high conductivity can be obtained without performing such heat treatment. In oxide semiconductors, since the implanted ions combine with oxygen, oxygen deficiencies occur and n-type conductivity is exhibited. The difference from silicon semiconductors is that in silicon semiconductors, heat treatment is required to recover crystallinity after ion implantation, but in many oxide semiconductors, high conductivity can be obtained without performing such heat treatment.

[0154] Thus, regions 115a and 115b that exhibit n-type conductivity are formed in the oxide semiconductor region 112. The carrier (electron) concentration in these regions is 1×10 -19 cm -3 or more, and it is preferable to set the ion implantation conditions accordingly. With this, the basic device structure is completed.

[0155] <Fig. 9(C)> Thereafter, a second interlayer insulator 116 made of a single-layer or multi-layer thin film is formed. Then, the surface is planarized to form a contact hole that reaches the region 115a exhibiting n-type conductivity, and the second connection electrode 117 is embedded. Thereafter, a second wiring 118 (bit line) is formed. Similar wirings may be formed in parallel with the first wirings 114a and 114b. Thus, as shown in Fig. 9( C), a memory cell of a semiconductor memory device having a write transistor 119, a read transistor 120, and a capacitor 121 is fabricated.

[0156] (Embodiment 4) In this embodiment, an example of the semiconductor memory device shown in Fig. 5 will be described with reference to Fig. 10. In this embodiment, the write transistor WTr uses an oxide semiconductor containing gallium and indium, and the read transistor RTr uses a single-crystal silicon semiconductor. Therefore, the write transistor WTr is provided laminated on the read transistor RTr. That is, an insulated gate type transistor using a single-crystal silicon semiconductor provided on a single-crystal silicon substrate is used as the read transistor RTr, and on top of that, a transistor using an oxide semiconductor

[0157] is provided. is used as the read transistor RTr, and on top of that, a transistor using an oxide semiconductor A transistor is formed and used as a write transistor WTr. In this embodiment an example in which a single-crystalline silicon semiconductor is used as a read transistor RTr will be described although it is also possible to use other semiconductors.

[0158] Fig. 10 shows a layout example of a memory cell of the semiconductor memory device according to this embodiment. Fig. 10(A ) shows main wirings, electrodes, etc. provided on a single-crystalline silicon substrate. In Fig. 10(A) the regions 200a and 200b surrounded by dotted lines each indicate the region occupied by one memory cell. For example, region 200a corresponds to the region occupied by the memory cell at the (2n - 1)-th row and the m-th column in Fig. 5, and region 200b corresponds to the region occupied by the memory cell at the 2n-th row and the m-th column in Fig. 5.

[0159] An element isolation region 202 is formed on the substrate. Also, conductive regions 206a and 206b are formed on the substrate using a conductive material or doped silicon. A part of them becomes the drain and source of the read transistor RTr. The wiring continuing from the conductive region 206a becomes a bias line (··, Sn, Sn + 1, ···). The conductive regions 206a and 206b are separated by a read gate 210. A first connection electrode 211 is provided in the conductive region 206b and connected to an upper-layer circuit.

[0160] Fig. 10(B) shows main wirings, electrodes, etc. centered on transistors using an oxide semiconductor formed on the circuit of Fig. 10(A). An island-shaped oxide semiconductor region 212 and a conductive material form a first wiring 214. The first wiring 214 is, for example, a write word line (··, Q2n - 1, Q2n, Q2n + 1, ···), a read word line (··, P2n ···), a read bit line (··, Bm - 1, Bm, Bm + 1, ···), etc. ···), a read bit line (··, Bm - 1, Bm, Bm + 1, ···), etc. -1, P2n, P2n + 1, ···).

[0161] A part of the write word line overlaps with the oxide semiconductor region 212 to form the gate electrode of the write transistor W Tr. Also, the oxide semiconductor region 212 is connected to the lower read gate 21 0. The read word line forms a capacitor in the overlapping portion with the read gate 210.

[0162] The oxide semiconductor region 212 is connected to the source (conductive region 206b) of the read transistor RTr by the first connection electrode 211. Also, a second connection electrode 217 for connecting from the oxide semiconductor region 212 to the upper layer ( bit line) is provided. If the second connection electrode 217 is provided at the same position as the first connection electrode 211 that connects the lower layer and the oxide semiconductor region 212, it is preferable for reducing the area of the memory cell.

[0163] When FIGS. 10(A) and (B) are superimposed, it becomes as shown in FIG. 10(C). Here, for clarity of the overlap, they are intentionally shifted slightly and superimposed. Further, the second wiring 218 using the conductive material formed on the transistor using the oxide semiconductor is also shown. The second wiring 218 becomes the bit line (··, Rm - 1, Rm, Rm + 1, ···) and is connected to the oxide semiconductor region 212 by the second connection electrode 217.

[0164] For manufacturing the semiconductor memory device having the above structure, the method shown in Embodiment 3 can be used.

[0165] (Embodiment 5) In this embodiment, in a method different from that of Embodiment 1, the semiconductor shown in FIGS. 1(A) and (B) ​​​​​An example of operating the body memory circuit will be described with reference to FIG. 11. As for the potential, specific numerical values are given below for the purpose of assisting in understanding the technical idea of the present invention. Needless to say, these values will be changed depending on various characteristics of transistors, capacitors, etc., or according to the convenience of the implementer. Hereinafter, specific numerical values are given, but the purpose is to help understand the technical idea of the present invention. Needless to say, these values will be changed depending on various characteristics of transistors, capacitors, etc., or according to the convenience of the implementer.

[0166] Here, the write transistor WTr(n,m) is of the N-channel type, and the read transistor RTr(n,m) is of the P-channel type. The write transistor WTr(n,m) is turned on when the potential of the gate is 1 V or more higher than the potential of either the source or the drain, and is off otherwise. Also, the read transistor RTr(n,m) is turned on when the potential of the gate is 1 V or more lower than the potential of either the source or the drain, and is off otherwise.

[0167] Also, among the gate capacitances of the read transistor RTr(n,m), the portion that varies due to the gate bias is considered negligible compared to the capacitance of the capacitor C(n,m). Further, all capacitances not shown in the figure, such as the parasitic capacitances of the write transistor WTr(n,m) and the read transistor RTr(n,m), and the parasitic capacitances between wirings, are considered to be 0.

[0168] In FIG. 11, a transistor in the on state is represented by a circle mark in the symbol, and a transistor in the off state is represented by an x mark superimposed on the symbol. For those that turn on under specific conditions, they may be described separately in the figure.

[0169] <FIG. 11(A)> (Writing to the n-th row) ​​​​​​​​​​​​In the write operation, as shown in FIG. 11(A), the read word line Pn and the bias line Sn The potential of the bit line Rm is set to 0 V. The potential of the bit line Rm is set to 0 V, +1 The voltage of the write word line Qn is set to four levels: V, +2V, and +3V. When the potential is set to +4V, the write transistor WTr(n,m) turns on and the write The drain potential of the transistor WTr(n,m) is the source potential of the write transistor (i.e. In this case, the potential of the bit line Rm approaches that of the bit line Rm. Let us assume that.

[0170] On the other hand, at this stage, the gate potential of the read transistor RTr(n,m) is It is equal to the drain potential of the read transistor WTr(n,m). The potential of the gate of the read transistor RTr(n,m) is 0V or higher. n, m) (i.e., the potential of bit line Rm).

[0171] Also, the drain of the read transistor RTr(n,m) (i.e., the bias line Sn) The potential at the gate of the read transistor RTr(n,m) is 0V. Since the potential is the same as or higher than the source and drain potentials, the read transistor RTr(n,m ) is in the off state. In this way, data can be written.

[0172] <Figure 11(B)> (Writing on a line other than the nth line) Next, when writing to a line other than the nth line, the writing is performed as shown in FIG. The potential of the write word line Qn is set to 0 V. The potential of the read word line Pn is set to +3 V. Set the potential of the bias line Sn to 0V. On the other hand, the potential of the bit line Rm takes four values of 0V, +1V, +2V, and +3V according to the data to be written in the row where writing is performed.

[0173] Since the potential of the drain of the write transistor WTr(n,m) is connected via the read word line Pn and the capacitor C(n,m), due to the change in the potential of the read word line Pn (i.e., the rise from 0V in Fig. 11(A) to +3V in Fig. 11(B)), it rises by 3V. That is, depending on the written data, it becomes any value of +3V, +4V, +5V, or +6V.

[0174] Also, in this state, since the potential of the source (bit line Rm) of the write transistor WTr(n,m) (0 to +3V) and the potential of the drain of the write transistor WTr(n,m) (+3 to +6V) are lower than the potential of the gate of the write transistor WTr(n,m), the write transistor WTr(n,m) is turned off.

[0175] Furthermore, since the potential of the gate of the read transistor RTr(n,m) is higher than the potential of the source (bit line Rm) of the read transistor RTr(n,m) (0 to +3V) and the potential of the drain (bias line Sn) of the read transistor RTr(n,m) (0V), the read transistor RTr(n,m) is turned off.

[0176] <Fig. 11(C)> (Read) Next, the reading will be described. As shown in Fig. 11(C), set the potential of the write word line Qn to 0V. Also, set the potentials of the read word line Pn and the bias line Sn to +3V. ​​​​​​​​​​​​This is the case. In this state, the potential of the drain of the write transistor WTr(n,m) becomes either +3V, +4V, +5V, or +6V according to the written data. If the potential of the bit line Rm is between 0V and +3V, both the write transistor WTr(n,m) and the read transistor RTr(n,m) are off. That is, for the rows that are not read, the write transistor and the read transistor are turned off in this way. Depending on the written data, it becomes one of +3V, +4V, +5V, +6V. If the potential of the bit line Rm is between 0V and +3V, both the write transistor WTr(n,m) and the read transistor RTr(n,m) are off. That is, for the rows that are not read, the write transistor and the read transistor are turned off in this way. On the other hand, for the rows to be read, the potential of the bias line Sn is made greater than +3 volts. For example, as shown in Fig. 11(D), when the potential of the bias line Sn is +4V, if the potential of the gate of the read transistor RTr(n,m) is +3V, the read transistor RTr(n,m) turns on. If the potential of the bit line is set to +3V in advance, a current flows through the bit line Rm. By detecting this, it can be known that the read transistor RTr(n,m) is in the on state. Or, if the end of the bit line Rm is a capacitor, it approaches the potential of the bias line Sn. Thus, it can also be known that the read transistor RTr(n,m) is in the on state.

[0177] <Fig. 11(D)> (Readout) On the other hand, for the rows to be read, the potential of the bias line Sn is made greater than +3 volts. For example, as shown in Fig. 11(D), when the potential of the bias line Sn is +4V, if the potential of the gate of the read transistor RTr(n,m) is +3V, the read transistor RTr(n,m) turns on. For example, as shown in Fig. 11(D), when the potential of the bias line Sn is +4V, if the potential of the gate of the read transistor RTr(n,m) is +3V, the read transistor RTr(n,m) turns on. If the potential of the gate of the read transistor RTr(n,m) is +3V, the read transistor RTr(n,m) turns on. That is, for the rows that are not read, the write transistor and the read transistor are turned off in this way.

[0178] If the potential of the bit line is set to +3V in advance, a current flows through the bit line Rm. By detecting this, it can be known that the read transistor RTr(n,m) is in the on state. By detecting this, it can be known that the read transistor RTr(n,m) is in the on state. Or, if the end of the bit line Rm is a capacitor, it approaches the potential of the bias line Sn. Thus, it can also be known that the read transistor RTr(n,m) is in the on state. Or, if the end of the bit line Rm is a capacitor, it approaches the potential of the bias line Sn. Thus, it can also be known that the read transistor RTr(n,m) is in the on state. That is, for the rows that are not read, the write transistor and the read transistor are turned off in this way.

[0179] <Fig. 11(E)> (Readout) Similarly, as shown in Fig. 11(E), when the potential of the bias line Sn becomes +5V, if the potential of the gate of the read transistor RTr(n,m) is between +3V and +4V, the read transistor RTr(n,m) turns on. If the potential of the gate of the read transistor RTr(n,m) is between +3V and +4V, the read transistor RTr(n,m) turns on. That is, for the rows that are not read, the write transistor and the read transistor are turned off in this way.

[0180] <Figure 11(F)> (Readout) Also, as shown in Figure 11(F), when the potential of the bias line Sn becomes +6V, readout If the potentials of the gates of the transistors RTr(n,m) are +3V, +4V, and +5V, read out transistor RTr(n,m) turns on.

[0181] Even if the potential of the bias line Sn is set to +6V and the readout transistor RTr(n,m) remains off If so, it can be inferred that the potential of the drain of the write transistor WTr(n,m) (= the potential of the gate of the readout transistor RTr(n,m)) is +6V.

[0182] In this way, four - level data (2 bits) can be written and read. Of course, in the same manner, even more data, for example, eight - level data (3 bits), sixteen - level data (4 bits) can be written and read. In this embodiment, as described above, In writing and reading, only positive potentials can be used.

[0183] In the above description, the parasitic capacitance and the gate capacitance of the readout transistor RTr(n,m) were ignored with respect to the capacitance of the capacitor C(n,m). However, in a real memory cell, it is necessary to determine the applied potential taking these into account. Since the gate capacitance of the readout transistor RTr(n,m) varies greatly between the on - state and the off - state, the potential of the gate of the readout transistor RTr(n ,m) is affected. The larger the ratio of the gate capacitance of the readout transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) is larger than the gate capacitance of the readout transistor RTr(n, ,m). The larger the ratio of the gate capacitance of the readout transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) is larger than the gate capacitance of the readout transistor RTr(n, ,m). The larger the ratio of the gate capacitance of the readout transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) is larger than the gate capacitance of the readout transistor RTr(n, ,m). The larger the ratio of the gate capacitance of the readout transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) is larger than the gate capacitance of the readout transistor RTr(n, ,m). The larger the ratio of the gate capacitance of the readout transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) is larger than the gate capacitance of the readout transistor RTr(n, It is preferably set to be at least twice the gate capacitance of (m).

[0184] (Embodiment 6) In this embodiment, an example of operating the semiconductor memory circuit shown in FIG. 5 will be described with reference to FIGS. 12 and FIG. 13. Here, the write transistors WTr(2n - 1, m) and WTr(2n, m) are of N-channel type, and the read transistors RTr(2n - 1, m) and RTr(2n, m) are of P-channel type.

[0185] The write transistors WTr(2n - 1, m) and WTr(2n, m) turn on when the potential of the gate is 1 V or more higher than the potential of either the source or the drain, and are off otherwise. Also, the read transistors RTr(2n - 1, m) and RTr(2n, m) turn on when the potential of the gate is 1 V or more lower than the potential of either the source or the drain, and are off otherwise. Of the gate capacitances of the read transistors RTr(2n - 1, m) and RTr(2n, m), the portion that varies due to the gate bias is considered negligible compared to the capacitance of the capacitor C(n, m). Furthermore, the parasitic capacitances of the write transistors WTr(2n - 1, m) and WTr( 2n, m), the parasitic capacitances of the read transistors RTr(2n - 1, m) and RTr(2n, m), and other capacitances such as the parasitic capacitances between wirings that are not shown in the figures are all considered to be 0.

[0186] 2n, m), the parasitic capacitances of the read transistors RTr(2n - 1, m) and RTr(2n, m), and other capacitances such as the parasitic capacitances between wirings that are not shown in the figures are all considered to be 0 and are taken into account. All capacitances not shown in the figures, such as the parasitic capacitances of the write transistors WTr(2n - 1, m) and WTr(2n, m), the parasitic capacitances of the read transistors RTr(2n - 1, m) and RTr(2n, m), and the parasitic capacitances between wirings, are considered to be 0 and are taken into account.

[0187] Also, in FIGS. 12 and 13, a transistor in the on state is marked with a circle in the symbol, and a transistor in the off state is marked with a cross in the symbol. For those that turn on under specific conditions This may be described separately.

[0188] <Figure 12(A)> (Writing to the (2n - 1)-th row) When writing to the (2n - 1)-th row, as shown in Figure 12(A), the potential of the read word line P 2n - 1, the write word line Q2n, and the bias line Sn are set to 0V. The potential of the read word line P2n is set to +3V. Also, the potential of the bit line Rm takes four values of 0V, +1V, +2V, and +3V according to the data to be written. At this time, the potential of the drain of the write transistor WTr(2n,m) is set to +3V.

[0189] Then, when the potential of the write word line Q2n - 1 is set to +4V, the write transistor WTr(2n - 1,m) turns on, and the potential of the drain of the write transistor WTr(2n - 1,m) approaches the potential of the source of the write transistor (i.e., the bit line Rm). Here, it is assumed to be equal to the potential of the bit line Rm.

[0190] On the other hand, at this stage, the potential of the gate of the read transistor RTr(2n - 1,m) is equal to the potential of the drain of the write transistor WTr(2n - 1,m). That is, the potential of the gate of the read transistor RTr(2n - 1,m) is 0V or higher and is the same as the potential of the source of the read transistor RTr(2n - 1,m) (i.e., the bit line Rm).

[0191] Also, the potential of the drain of the read transistor RTr(2n - 1,m) (i.e., the bias line Sn) is 0V. Therefore, the read transistor RTr(2n - 1,m) ​The potential of the gate is the same as or higher than the potentials of the source and drain, so the read transistor R Tr(2n - 1,m) is in the off state.

[0192] Furthermore, the potential of the gate (0V) of the write transistor WTr(2n,m) is lower than the potential (0V or more and +3V or less) of its source (i.e., the bit line Rm) and the potential of its drain (+3V ). Therefore, the write transistor WTr(2n,m) is in the off state. Also, the potential of the gate (i.e., the drain of the write transistor W Tr(2n,m)) of the read transistor RTr(2n,m) (+3V) is higher than the potential (0V or more and +3V or less) of its source (i.e., the bit line R m) and the potential of its drain (0V). So, it is also in the off state. In this way, data can be written to the memory cells in the (2n - 1)-th row.

[0193] <Figure 12(B)> (Writing to the 2n-th row) Next, when writing to the 2n-th row, as shown in Figure 12(B), the potentials of the write word line Q2n - 1 and the read word line P2n are set to 0V. Also, the potential of the read word line P2n - 1 is set to +3V, and the potential of the bias line Sn is set to 0V. On the other hand, the potential of the bit line Rm takes four levels of values, 0V, +1V, +2V, and +3V, according to the data to be written.

[0194] Since the drain of the write transistor WTr(2n - 1,m) is connected to the read word line P 2n - 1 via the capacitor C(2n - 1,m), the potential fluctuation of the read word line P2n - 1 (i.e., from 0V in Figure 12(A) to +3V in Figure 12(B)) This means that the voltage will rise by 3V, i.e. +3V, +4V depending on the data written. , +5V, or +6V.

[0195] If the potential of the write word line Q2n is set to +4V, the write transistor WT r(2n,m) turns on, and the drain voltage of the write transistor WTr(2n,m) The potential approaches that of the source of the write transistor (i.e., bit line Rm). is assumed to be equal to the potential of the bit line Rm.

[0196] On the other hand, at this stage, the potential of the gate of the read transistor RTr(2n,m) is The drain potential of the read transistor WTr(2n,m) is equal to the drain potential of the read transistor WTr(2n,m). The potential of the gate of the read transistor RTr(2n,m) is 0V or higher. This is the same as the potential of the source of Tr(2n,m) (that is, the bit line Rm).

[0197] In addition, the drain of the read transistor RTr(2n,m) (i.e., the bias line Sn ) is 0V. Therefore, the gate potential of the read transistor RTr(2n-1,m) The potential of the gate is the same as or higher than the potential of the source and drain, so the read transistor RTr (2n,m) is in the off state. Also, the write transistor WTr(2n-1,m), The read transistor RTr(2n-1,m) is also in an off state. Data can be written to n rows of memory cells.

[0198] <Figure 12(C)> (Writing on other lines) Next, when writing to a line other than the above, the write operation is performed as shown in FIG. 12(C). Set the potentials of word lines Q2n-1 and Q2n to 0V. Also, set the potential of read word lines P2n- 1 and P2n to +3V, and the potential of bias line Sn to 0V. On the other hand, the potential of bit line Rm takes four levels of values, 0V, +1V, +2V, +3V, according to the data to be written in the row where writing is performed.

[0199] Since the potential of the drain of write transistor WTr(2n,m) is connected via read word line P2n and capacitor C(2n,m), due to the change in the potential of read word line P2n (i.e., the rise from 0V in Fig. 12(B) to +3V in Fig. 12(C)), it rises by 3 V. That is, it becomes one of the values +3V, +4V, +5V, +6V according to the written data. The potential of the drain of write transistor WTr(2n-1,m) also becomes one of the values +3V, +4V, +5V, +6V in the same way.

[0200] Also, in this state, the potential of the source (bit line Rm) of write transistors WTr(2n-1,m) and WTr(2n ,m) (0 to +3V) and the potential of the drain of write transistors WTr( 2n-1,m) and WTr(2n,m) (+3 to +6V) are lower than the potential of the gates of write transistors WTr(2n-1,m) and write transistor WTr(2n, m) (0V). Therefore, write transistors WTr(2n-1,m) and WTr(2n,m) turn off.

[0201] Furthermore, the potential of the source (bit line Rm) of read transistors RTr(2n-1,m) and RTr(2n,m) (0 to +3V) and the read transistor RTr(2n-1,m and higher than the potential (0 V) of the drain ((bias line Sn) of RTr(2n,m)), the potential of the gates of read transistors RTr(2n-1,m) and RTr(2n,m) (+3 to +6 V) is high, so read transistors RTr(2n-1,m) and read transistors RTr(2n,m) turn off.

[0202] <Figure 13(A)> (read) Next, read will be described. As shown in Figure 13(A), for read word lines P2n -1 and P2n, set the potential to 0 V, and for write word lines Q2n-1, Q2n, and bias line Sn set the potential to -3 V. In this state, the potential of the gates of read transistors RTr(2n-1,m), R Tr(2n,m) will be either 0 V, +1 V, +2 V, or +3 V according to the written data.

[0203] If the potential of bit line Rm is -3 V or higher and 0 V or lower, write transistors WTr(2n -1,m), WTr(2n,m), read transistors RTr(2n-1,m), and RTr (2n,m) are all off. That is, for the lines not to be read, in this way, turn off the transistors of that line.

[0204] <Figure 13(B)> (read of the 2n-th row [1]) Next, set the potential of read word line P2n to -3 V and the potential of bit line Rm to -3 V. This results in the potential of the gate of read transistor RTr(2n,m) being either -3 V, -2 V, -1 V, or 0 V according to the written data. In this state, write transistor WTr(2n,m) and read transistor RTr(2n,m) are both off in this state. However, when the potential of the bias line Sn is changed, the read transistor RT r(2n,m) can be turned on. For example, as shown in FIG. When the potential of the bias line Sn becomes -2V, the gate of the read transistor RTr(2n,m) When the potential of the port is -3V, the read transistor RTr(2n,m) is turned on. do.

[0205] <Figure 13(C)> (Reading the 2nth row [2]) Similarly, as shown in FIG. 13(C), when the potential of the bias line Sn becomes −1 V, When the gate potential of the transistor RTr(2n,m) is -3V and -2V, the read The output transistor RTr(2n,m) turns on.

[0206] <Figure 13(D)> (Reading the 2nth row [3]) Also, as shown in FIG. 13(D), when the potential of the bias line Sn becomes 0V, the read When the gate potential of transistor RTr(2n,m) is -3V, -2V, and -1V, The read transistor RTr(2n,m) is turned on.

[0207] Even if the potential of the bias line Sn is set to 0V, the read transistor RTr(2n,m) is off. If this state remains the same, the potential of the gate of the read transistor RTr(2n,m) will be 0V. It can be inferred that this was the case.

[0208] Similarly, the data in the memory cell in the (2n-1)th row can be read out. We have shown an example of writing and reading four levels of data (2 bits), but in the same way, A lot of data, for example, 8-level data (3 bits), 16-level data (4 bits) It can be written and read. In the above description, the parasitic capacitance and the gate capacitance of the read transistor RTr( n,m) were ignored with respect to the capacitance of the capacitor C(n,m), but in an actual memory cell, it is necessary to determine the applied potential after considering them.

[0209] (Embodiment 7) In this embodiment, an example of operating the semiconductor memory circuit shown in FIGS. 6(A) and (B) will be described with reference to FIGS. 14 and 15. Specific numerical values are given below as the potential, but that is for the purpose of assisting in understanding the technical idea of the present invention. Needless to say, those values will be changed depending on various characteristics of the transistors and capacitors, or depending on the convenience of the implementer.

[0210] Here, the write transistor WTr is of the N-channel type, and the read transistor RTr is of the P-channel type. The write transistor WTr is assumed to turn on when the potential of the gate is 1 V or more higher than the potential of either the source or the drain, and to be off otherwise. Also, the read transistor RTr is assumed to turn on when the potential of the gate is 1 V or more lower than the potential of either the source or the drain, and to be off otherwise.

[0211] Also, among the gate capacitances of the read transistor RTr, the portion that varies due to the gate bias is assumed to be negligible compared to the capacitance of the capacitor C. Further, the parasitic capacitances of the write transistor WTr and the read transistor RTr, and other capacitances such as the parasitic capacitances between wirings that are not shown in the figures are all considered to be 0.

[0212] ​​​​​​​​​​Also, in FIGS. 14 and 15, a transistor in the on state is marked with a circle in the symbol, and a transistor in the off state is marked with an 'x' superimposed on the symbol. Those that turn on under specific conditions will be described separately. In the following description, the memory cell in the (n - 1)-th row and m-th column and the memory cell in the n-th row and m-th column will be described with attention.

[0213] <FIG. 14(A)> (Writing to the (n - 1)-th row) When writing to the memory cells in the (n - 1)-th row, as shown in FIG. 14(A), the potential of the read wire Pn - 1 and the write word lines Qn, Qn + 1 is set to 0V, and the potential of the read word lines Pn and Pn + 1 is set to +4V. Also, the potential of the bit line Rm takes on four levels of values, 0V, +1V, +2V, and +3V, depending on the data to be written. Also, the drain of the write transistor WTr(n, m) (i.e., the gate of the read transistor RTr(n, m ) is assumed to have an initial potential of +4V or more and +7V or less. And when the potential of the write word line Qn - 1 is set to +4V, the write transistor W Tr(n - 1, m) turns on, and the potential of the drain of the write transistor WTr(n - 1, m) approaches the potential of the source of the write transistor (i.e., the bit line Rm). Here, it is assumed to be equal to the potential of the bit line Rm.

[0214] On the other hand, at this stage, the potential of the gate of the read transistor RTr(n - 1, m) is equal to the potential of the drain of the write transistor WTr(n - 1, m). That is, the potential of the gate of the read transistor RTr(n - 1, m) is the same as the potential of the source of the read transistor RTr(n - 1, m) (i.e., the bit line Rm). That is, the potential of the gate of the read transistor RTr(n - 1, m) is the same as the potential of the source of the read transistor RTr(n - 1, m) (i.e., the bit line Rm).

[0215] On the other hand, at this stage, the potential of the gate of the read transistor RTr(n - 1, m) is equal to the potential of the drain of the write transistor WTr(n - 1, m). That is, the potential of the gate of the read transistor RTr(n - 1, m) is the same as the potential of the source of the read transistor RTr(n - 1, m) (i.e., the bit line Rm). - 1, m) (i.e., the bit line Rm). - 1, m) (i.e., the bit line Rm).

[0216] Also, the potential of the drain of the read transistor RTr(n - 1, m) (i.e., the write word line Qn) is 0V. Therefore, since the potential of the gate of the read transistor RTr(n - 1, m) is the same as or higher than the potential of the source and the drain, the read transistor RTr(n - 1, m) is in the off state. ) is in the off state. RTr(n - 1, m) is in the off state.

[0217] Note that the potential of the gate of the write transistor WTr(n, m) (0V) is the same as or lower than the potential of its source ( i.e., the bit line Rm) (0 to +3V) and the drain (+4 to +7V), so the write transistor WTr(n, m) is in the off state, and the potential of the gate of the read transistor RTr(n, m) (+4 to +7V) is higher than the potential of its source (i.e., the bit line Rm) (0 to +3V) and the drain (i.e., the write word line Qn + 1) (0V), so the read transistor RTr(n, m) is also in the off state. In this way, data can be written into the memory cell in the (n - 1)-th row. Rm) (0 to +3V) and the drain (i.e., the write word line Qn + 1) (0V), so the read transistor RTr(n, m) is also in the off state. In this way, data can be written into the memory cell in the (n - 1)-th row. (0V), so the read transistor RTr(n, m) is also in the off state. In this way, data can be written into the memory cell in the (n - 1)-th row. In this way, data can be written into the memory cell in the (n - 1)-th row.

[0218] <Figure 14(B)> (Writing to the n-th row) When writing to the memory cell in the n-th row, as shown in Figure 14(B), the potentials of the read word line P n and the write word lines Qn - 1 and Qn + 1 are set to 0V, and the potentials of the read word lines Pn - 1 and P n + 1 are set to +4V. Also, the potential of the bit line Rm takes on four levels of values: 0V, +1V, +2V, and +3V according to the data to be written. 0V, +1V, +2V, and +3V according to the data to be written.

[0219] Since the potential of the read word line Pn - 1 has increased by 4V, the gate of the read transistor RTr(n - 1, m) (i.e., the drain of the write transistor WTr(n - 1, m) ) The potential also rises similarly and becomes +4V or more and +7V or less.

[0220] Then, when the potential of the write word line Qn is set to +4V, the write transistor WTr (n,m) turns on, and the potential of the drain of the write transistor WTr(n,m) approaches the potential of the source of the write transistor (i.e., the bit line Rm). Here, it is assumed to be equal to the potential of the bit line Rm. It is assumed to be equal to the potential of the bit line Rm.

[0221] On the other hand, at this stage, the potential of the gate of the read transistor RTr(n,m) is equal to the potential of the drain of the write transistor WTr(n,m). That is, the potential of the gate of the read transistor RTr(n,m) is the same as the potential of the source of the read transistor RTr(n,m) (i.e., the bit line Rm). It is the same as the potential of the source (i.e., the bit line Rm).

[0222] Also, the potential of the drain of the read transistor RTr(n,m) (i.e., the write word line Qn+1) is 0V. Therefore, since the potential of the gate of the read transistor RTr(n,m) (the potential of the bit line Rm) is the same as or higher than the potential of the source or drain, the read transistor RTr(n,m) is in the off state.

[0223] Note that the potential of the gate of the write transistor WTr(n-1,m) (0V) is the same as or lower than the potential of its source (i.e., the bit line Rm) (0~+3V) and drain (+4~+7V), so the write transistor WTr(n-1,m) is in the off state, and the potential of the gate of the read transistor RTr(n-1,m) (+4~+7V) is the same as the potential of its source (i.e., the bit line Rm) (0~+3V) and drain (i.e., the write word line Qn ), so the read transistor RTr(n-1,m) is in the off state.​​​​ ) is at the same potential as (+4V) or higher than that of, so it is in the off state. In this way, data can be written into the memory cell of the n-th row.

[0224] <Figure 14(C)>(Writing to the (n + 1)-th row) When writing to the memory cell of the (n + 1)-th row, as shown in Figure 14(C), the potentials of the read word line Pn+1 and the write word lines Qn-1 and Qn are set to 0V, and the potentials of the read word lines Pn-1 and Pn are set to +4V. Also, the potential of the bit line Rm takes on four levels of values, 0V, +1V, +2V, and +3V, according to the data to be written.

[0225] Since the potential of the read word line Pn has risen by 4V, the potential of the gate of the read transistor RTr(n,m ), that is, the drain of the write transistor WTr(n,m), also rises accordingly and becomes between +4V and +7V.

[0226] Then, by setting the potential of the write word line Qn+1 to +4V, data can be written into the memory cell of the (n + 1)-th row.

[0227] At this stage, the potential of the gate of the write transistor WTr(n,m) (0V) is equal to or lower than the potential of its drain (+4 to +7V) and the source (i.e., the bit line Rm) (0 to +3V ), so the write transistor WTr(n,m) is in the off state.

[0228] Also, the potential of the gate of the read transistor RTr(n,m) (+4 to +7V) is equal to or higher than the potential of its drain (i.e., the write word line Qn+1) (+4V) and the source (i.e., the bit line Rm) (0 to +3V), so the read transistor RTr( n,m) is in the on state. Both n and m are in the off state.

[0229] Furthermore, the potential (0V) of the gate of the write transistor WTr(n - 1, m) is the same as or lower than the potential (0~+3V) of its source (i.e., bit line Rm) and the potential (+4~+7V) of its drain. Therefore, the write transistor WTr(n - 1, m) is in the off state. The potential (0~+3V) of its source (i.e., bit line Rm) and the potential (+4~+7V) of its drain. Therefore, the write transistor WTr(n - 1, m) is in the off state. Since it is the same or lower, the write transistor WTr(n - 1, m) is in the off state. The potential (+4~+7V) of the gate of the read transistor RTr(n - 1, m) is higher than the potential (0~+3V) of its source (i.e., bit line Rm) and the potential (0V) of its drain (i.e., write word line Qn). Therefore, it is in the off state. In this way, data can be written into the memory cells of the (n + 1)-th row. The potential (+4~+7V) of the gate of the read transistor RTr(n - 1, m) is higher than the potential (0~+3V) of its source (i.e., bit line Rm) and the potential (0V) of its drain (i.e., write word line Qn). Therefore, it is in the off state. In this way, data can be written into the memory cells of the (n + 1)-th row. That is, the potential (0~+3V) of bit line Rm and the potential (0V) of the drain (i.e., write word line Qn). Therefore, it is in the off state. In this way, data can be written into the memory cells of the (n + 1)-th row. In this way, data can be written into the memory cells of the (n + 1)-th row. In this way, data can be written into the memory cells of the (n + 1)-th row.

[0230] <Figure 14(D)> (Writing to other rows) When writing to the memory cells of rows other than the above, as shown in Figure 14(D), the potentials of the write word lines Qn - 1, Qn, and Qn + 1 are set to 0V, and the potentials of the read word lines Pn - 1, Pn, and Pn + 1 are set to +4V. Also, the potential of the bit line Rm takes on four levels of values: 0V, +1V, +2V, and +3V, depending on the data to be written to the row where the writing is performed. The potentials of the write word lines Qn - 1, Qn, and Qn + 1 are set to 0V, and the potentials of the read word lines Pn - 1, Pn, and Pn + 1 are set to +4V. Also, the potential of the bit line Rm takes on four levels of values: 0V, +1V, +2V, and +3V, depending on the data to be written to the row where the writing is performed. The potentials of the write word lines Qn - 1, Qn, and Qn + 1 are set to 0V, and the potentials of the read word lines Pn - 1, Pn, and Pn + 1 are set to +4V. Also, the potential of the bit line Rm takes on four levels of values: 0V, +1V, +2V, and +3V, depending on the data to be written to the row where the writing is performed. The potentials of the write word lines Qn - 1, Qn, and Qn + 1 are set to 0V, and the potentials of the read word lines Pn - 1, Pn, and Pn + 1 are set to +4V. Also, the potential of the bit line Rm takes on four levels of values: 0V, +1V, +2V, and +3V, depending on the data to be written to the row where the writing is performed.

[0231] In this state, the potential (0V) of the gate of the write transistor WTr(n, m) is the same as or lower than the potential (+4~+7V) of its drain and the potential (0~+3V) of its source (i.e., bit line Rm). Therefore, the write transistor WTr(n, m) is in the off state. The potential (+4~+7V) of its drain and the potential (0~+3V) of its source (i.e., bit line Rm). Therefore, the write transistor WTr(n, m) is in the off state. Therefore, the write transistor WTr(n, m) is in the off state.

[0232] Also, the potential (+4~+7V) of the gate of the read transistor RTr(n, m) is higher than the potential (0V) of its drain (i.e., write word line Qn + 1) and the potential (i.e., bit line Rm) of its source. That is, the potential (0V) of its drain (i.e., write word line Qn + 1) and the potential (i.e., bit line Rm) of its source. Since the potential of the bit line Rm is higher than the potential (0 to +3V), the read transistor RTr(n,m) is also in the off state.

[0233] Furthermore, the potential (0V) of the gate of the write transistor WTr(n-1,m) is The potential of the source (i.e., bit line Rm) is 0 to +3V, and the drain is +4 to +7V. Since the voltage is low, the write transistor WTr(n-1,m) is in the off state, and the read transistor The potential (+4 to +7 V) of the gate of the transistor RTr(n-1,m) is That is, the potential (0 to +3V) of the bit line Rm, the drain (i.e., the write word line Q n) is higher than the potential (0 V), so it is in the off state.

[0234] <Figure 15(A)> (Readout) Next, the reading will be described. The reading of the memory cell in the nth row will be described below. However, the readout of memory cells in other rows can be performed in the same manner. As shown in FIG. 15(A), the potentials of the write word lines Qn-1, Qn, and Qn+1 are set to 0V. The potential of the read word lines Pn-1, Pn, and Pn+1 is set to +3V.

[0235] In this state, the drain potential of the write transistor WTr(n,m) is Depending on the data input, the voltage will be +3V, +4V, +5V, or +6V. If the potential is between 0V and +3V, the write transistor WTr(n,m) The transistors RTr(n,m) are also off. Similarly, the write transistors WTr( n-1,m) and the read transistor RTr(n-1,m) are also off. For rows that do not include the write transistor and the read transistor, Turn it off.

[0236] <Figure 15(B)> (Readout) On the other hand, for the row to be read, the potential of the read word line Pn is made smaller than +3 volts. For example, as shown in Figure 15(B), with the potential of the bit line Rm being +3V, the potential of the read word line Pn is set to +2V. At this time, the potential of the gate of the read transistor RTr(n,m) is between +2V and +5V. Among them, when it is +2V, since the potential of the source (i.e., the bit line Rm) is (+3V), the read transistor RTr(n,m) turns on. Tr(n,m) is on. ,m) is on. (i.e., the bit line Rm) is lower than the potential (+3V), the read transistor R Tr(n,m) turns on.

[0237] During writing, four types of potentials, 0V, +1V, +2V, and +3V, were applied. Here, it turns on when a potential of 0V is applied during writing. That the read transistor RTr(n,m) turns on can be known in various ways as in the case of other embodiments. During writing, four types of potentials, 0V, +1V, +2V, and +3V, were applied. Here, it turns on when a potential of 0V is applied during writing. That the read transistor RTr(n,m) turns on can be known in various ways as in the case of other embodiments. During writing, four types of potentials, 0V, +1V, +2V, and +3V, were applied. Here, it turns on when a potential of 0V is applied during writing. That the read transistor RTr(n,m) turns on can be known in various ways as in the case of other embodiments. During writing, four types of potentials, 0V, +1V, +2V, and +3V, were applied. Here, it turns on when a potential of 0V is applied during writing. That the read transistor RTr(n,m) turns on can be known in various ways as in the case of other embodiments.

[0238] <Figure 15(C)> (Readout) Similarly, as shown in Figure 15(C), when the potential of the read word line Pn becomes +1V, the potential of the gate of the read transistor RTr(n,m) is between +1V and +4V. Among them, in the cases of +1V and +2V, the read transistor RTr(n,m) turns on. Here, it turns on when a potential of 0V or +1V is applied during writing. Similarly, as shown in Figure 15(C), when the potential of the read word line Pn becomes +1V, the potential of the gate of the read transistor RTr(n,m) is between +1V and +4V. Among them, in the cases of +1V and +2V, the read transistor RTr(n,m) turns on. Here, it turns on when a potential of 0V or +1V is applied during writing. Similarly, as shown in Figure 15(C), when the potential of the read word line Pn becomes +1V, the potential of the gate of the read transistor RTr(n,m) is between +1V and +4V. Among them, in the cases of +1V and +2V, the read transistor RTr(n,m) turns on. Here, it turns on when a potential of 0V or +1V is applied during writing. Similarly, as shown in Figure 15(C), when the potential of the read word line Pn becomes +1V, the potential of the gate of the read transistor RTr(n,m) is between +1V and +4V. Among them, in the cases of +1V and +2V, the read transistor RTr(n,m) turns on. Here, it turns on when a potential of 0V or +1V is applied during writing. Similarly, as shown in Figure 15(C), when the potential of the read word line Pn becomes +1V, the potential of the gate of the read transistor RTr(n,m) is between +1V and +4V. Among them, in the cases of +1V and +2V, the read transistor RTr(n,m) turns on. Here, it turns on when a potential of 0V or +1V is applied during writing.

[0239] <Figure 15(D)> (Readout) Also, as shown in Figure 15(D), when the potential of the read word line Pn becomes 0V, the read The potential of the gate of the output transistor RTr(n,m) is 0V or more and +3V or less. Among them, when it is 0V, +1V, and +2V, the read transistor RTr(n,m) is on. Here, it turns on when a potential of 0V, +1V, or +2V is applied during writing. This is the case when a potential of +3V is applied during writing.

[0240] Even if the potential of the read word line Pn is set to 0V, if the read transistor RTr(n,m) remains off, it can be inferred that the potential of the gate of the read transistor RTr(n,m) is +3V. This is the case when a potential of +3V is applied during writing.

[0241] In the above process, the write transistors WTr(n,m), WTr(n - 1,m), and the read transistor RTr(n - 1,m) remain in the off state. In this way, 4 - step data (2 bits) can be written and read. Of course, in the same way, even more data, for example, 8 - step data (3 bits), 16 - step data (4 bits) can be written and read.

[0242] In the above description, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) are ignored with respect to the capacitance of the capacitor C(n,m). However, in a real memory cell, it is necessary to determine the applied potential considering them.

[0243] (Embodiment 8) In this embodiment, an example of the operation of the semiconductor memory circuit shown in Fig. 16(A) will be described with reference to Figs. 17 and 18. Here, specific numerical values are given below as the potential, but they are for the purpose of helping the understanding of the technical idea. Needless to say, these values It can be changed according to various characteristics of transistors and capacitors, or according to the convenience of the implementer. . Also, the semiconductor memory device shown in FIG. 16(A) can also write or read data by methods other than the following methods.

[0244] Here, the write transistors WTr1, WTr2, and WTr3 are of N-channel type, and the read transistors RTr1, RTr2, and RTr3 are of P-channel type. Also, the write tr ansistors turn on when the gate potential is 1 V or more higher than the lower potential of either the source or the drain, and are off otherwise. Also, the read transistors turn on when the gate potential is 1 V or more lower than the higher potential of either the source or the drain, and are off otherwise.

[0245] Also, among the gate capacitances of the read transistors, the portion that varies due to the gate bias is considered negligible with respect to the capacitance of the capacitor C. Further, the parasitic capacitances of the write transistor WT r, the parasitic capacitances of the read transistors RTr, and other parasitic capacitances between wirings, etc., all capacitances not shown in the figure are considered to be 0. Also, in FIGS. 17 and 18, a circle is marked on the transistors in the on state, and an x is marked on the transistors in the off state, respectively, overlaid on the symbols of the transistors. For those that turn on under specific conditions, they may be separately described in the figure. In the following example, it is assumed that the potential of the bias line S is always 0 V.

[0246] First, the writing to this memory unit will be described. The writing starts from the rightmost memory cell. At the time of writing, as shown in FIG. 17(A), the read word lines P1, P ​ 2. Set the potential of P3 to 0V. Also, the potential of bit line R shall take on four levels of values: 0 V, +1V, +2V, and +3V according to the data to be written.

[0247] Then, when the potentials of write word lines Q1, Q2, and Q3 are set to +4V, write transistors WTr1, WTr2, and WTr3 turn on, and the potential of the drain of write transistor WTr3 (i.e., the potential of node F3) approaches the potential of bit line R. Here, it is assumed to be equal to the potential of bit line R.

[0248] On the other hand, at this stage, read transistors RTr1, RTr2, and RTr3 are in the off state. And as shown in FIG. 17(B), set the potential of write word line Q3 to 0V. Then, since write transistor WTr3 turns off, the potential of the immediately previous bit line R is retained at node F3. In this way, data can be written into the rightmost memory cell.

[0249] Next, write data into the central memory cell. In the state of FIG. 17(B), the potential of node F2 is equal to the potential of bit line R. Then, when the potential of write word line Q2 is set to 0V (see FIG. 17(C)) and write transistor WTr2 turns off, the potential of the immediately previous bit line R is retained at node F2. In this way, data can be written into the central memory cell.

[0250] In this way, data can be written into all memory cells. When there is no need to perform the writing operation within the memory unit (when writing data to a memory unit other than the said memory unit) ​​​​​When writing or the like), as shown in Fig. 17(D), the potential of the read word line P1 is set to +3V This is preferable. At this time, the potential of node F1 is +3V or more and +6V or less. Since the potential of bit line R is 0V or more and +3V or less, the read transistor RTr1 can maintain the off state .

[0251] Next, reading will be described with reference to Fig. 18. First, when performing reading of rows other than the memory unit , as shown in Fig. 18(A), the potentials of the write word lines Q1, Q2, Q 3 are set to 0V, and the potentials of the read word lines P1, P2, P3 are set to +4V. By doing so , the write transistors WTr1, WTr2, WTr3 turn off. Also, the potentials of nodes F1 , F2, F3 are +4V or more and +7V or less. And since the potential of bit line R is 0V or more and +4V or less as will be described later , the read transistors RTr1, RT r2, RTr3 can maintain the off state

[0252] To perform reading of the memory unit, as shown in Fig. 18(B), the potentials of the write word lines Q1, Q2, Q3 are set to 0V, and the potentials of the read word lines P1, P2, P3 are set to 0V . Also, the potential of the bit line is set to +4V. At this time, the write transistors WT r1, WTr2, WTr3 turn off, but the potentials of nodes F1, F2, F3 are 0V or more and + 3V or less, and the read transistors RTr1, RTr2, RTr3 turn on. Therefore , a current flows between bit line R and bias line S .

[0253] If the end of bit line R is a capacitor, a current flows between bit line R and bias line S When it flows, the initial potential (+4V) will approach the potential (0V) of the bias line S. The final potential is determined by the minimum value of the potentials of nodes F1, F2, and F3. In any case, the potential of the bit line R will vary between 0V and +4V.

[0254] Hereinafter, among the memory units, it is assumed that the data of the central memory cell is read. As shown in Fig. 18 (C), when the potential of the read word line P2 is raised to +1V, the potential of node F2 will be either +1V, +2V, +3V, or +4V according to the written data. Here, if the potential of node F2 is +4V, the read transistor RTr2 will turn off so that no current will flow between the bit line R and the bias line S.

[0255] At this stage, the reason why the potential of node F2 is +4V is that the potential of the bit line was + 3V during writing. That is, when the potential of the read word line P2 is +1V, if the read transistor RTr2 is off, it can be known that the potential of the bit line R was +3 V during writing. In this way, the value of the stored data can be known.

[0256] Furthermore, as shown in Fig. 18(D), when the potential of the read word line P2 is raised to +2V, the potential of node F2 will be either +2V, +3V, +4V, or +5V according to the written data. Here, if the potential of node F2 is +4V or +5V, the read transistor RTr2 will turn off so that no current will flow between the bit line R and the bias line S. .

[0257] By detecting this, the value of the data can be known. That is, at this stage, the read transistor The potential of the gate of transistor RTr2 is +4V or +5V when writing This is the case when the potential of bit line R is +2V or +3V, and the potential of read word line P2 is +1V (i.e., the state in Fig. 18(C)). It was in the on state, but when it becomes +2V and turns off, it means that the potential of bit line R was +2V when writing. That's it.

[0258] Similarly, as shown in Fig. 18(E), when the potential of read word line P2 is raised to +3V , the potential of node F2 will be either +3V, +4V, +5V, or +6V according to the written data. Here, if the potential of node F2 is +4V, +5V, or +6V, the read transistor RTr2 will turn off, so no current will flow between bit line R and bias line S. That is, this is the case when the potential of the bit line was +1V, +2V, or +3V when writing. That is, this is the case when the potential of the bit line was +1V, +2V, or +3V when writing. That's it.

[0259] When the potential of the bit line is 0V when writing, if the potential of read word line P2 is set to +3V, the potential of node F2 is +3V and it is still on. That is , when the potential of read word line P2 is +3V and current still flows between bit line R and bias line S, it can be known that the potential of the bit line was 0V when writing. That's it.

[0260] The above is a method of knowing the value of data by changing the potential of read word line P2 step by step , but the value of data can also be known by measuring the potential. For example, as shown in Fig. 18(F ), a capacitor is provided at the end of the bit line and the potential on the memory cell side is set to 0V. That's it.

[0261] Also, set the potentials of the write word lines Q1, Q2, Q3 and the read word lines P1, P3 to -3V. In this state, since the potentials of both nodes F1 and F3 are -3V or higher and 0V or lower, by setting the potential of node F2 to an appropriate value, the read transistors RTr1, RTr 2, RTr3 can be turned on, and the potential of bit line R can be made closer to the potential of bias line S (0V). For example, if node F2 is 0V or lower, the potential of the capacitor of bit line R will be 0V or higher and less than +1V.

[0262] First, when the read word line P2 is set to +3V, the potential of node F2 is +3V or higher and +6 V or lower. So, at this stage, the read transistor RTr2 is off. However, Next, when the potential of the read word line P2 is lowered to 0V, the potential of node F2 becomes 0V or higher and +3 V or lower, and the read transistor RTr2 turns on.

[0263] As described above, if the potential of node F2 is 0V, the potential of the capacitor of bit line R will be 0V or higher and less than +1V. Here, the potential of node F2 becomes 0V when the potential of the bit line during writing was 0V.

[0264] Similarly, if the potential of node F2 is +1V, the potential of the capacitor of bit line R is +1V or higher and less than +2V. If the potential of node F2 is +2V, the potential of the capacitor of bit line R is + 2V or higher and less than +3V. If the potential of node F2 is +3V, the potential of the capacitor of bit line R will be +3V or higher and less than +4V. And in each case, the potential of the bit line during writing can be determined. That is, by measuring the potential of the capacitor of bit line R, Thus, the potential of node F2 can be known, and from this, the potential of the bit line during writing can be known.

[0265] In this way, 4-level data (2 bits) can be written and read. Of course, similarly, more data, for example, 8-level data (3 bits), 16-level data (4 bits) can be written and read.

[0266] In the above description, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) were ignored with respect to the capacitance of the capacitor C(n,m). However, in an actual memory cell, it is necessary to determine the potential to be applied considering these.

[0267] The gate capacitance of the read transistor RTr(n,m) varies greatly between the on state and the off state. Therefore, the potential of the gate of the read transistor RTr(n,m) is affected by this. The larger the ratio of the gate capacitance of the read transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) should be twice or more the gate capacitance of the read transistor RTr(n,m).

[0268] (Embodiment 9) In this embodiment, an example of the shape and manufacturing method of the semiconductor memory device described in Embodiment 8 will be described. In this embodiment, the writing transistor uses an oxide semiconductor containing gallium and indium, and the read transistor uses a single crystal silicon semiconductor. Therefore, the writing transistor is provided laminated on the read transistor. Note that regarding the detailed manufacturing method and the like, known semiconductor manufacturing technologies or Embodiment 3 may be referred to.

[0269] Fig. 22 shows a layout example of a memory unit of the semiconductor memory device according to the present embodiment. In the present embodiment, the unit memory unit has four memory cells.

[0270] Fig. 22(A) shows main wirings, electrodes, etc. provided on a single-crystal silicon substrate. An element isolation region 302 is formed on the substrate. On the substrate, a conductive region 306 using a conductive material (such as silicide) or doped silicon is formed. A part of the conductive region 306 serves as the source and drain of a read transistor. Also, a part of the conductive region 306 also serves as a part of the bias line S. There is also a part of the conductive region 306 separated by the read gate 310 of the read transistor. A first connection electrode 311 is provided on a part of the conductive region 306. When the bias line S is formed using the conductive region 306, the integration degree can be increased. However, in that case, it is preferable that the bias line S is parallel to the write word line and the read word line (that is, orthogonal to the bit line). As shown in the figure, the integration degree can be increased by sharing the bias line S with an adjacent memory unit (the memory unit on the right side with the bias line S in between). As the material of the read gate 310 and the first connection electrode 311, the materials used for the read gate 110 and the first connection electrode 111 described in Embodiment 3 (or Fig. 8) may be used. 8) may be used. 8) may be used. 8) may be used.

[0271] When the bias line S is formed using the conductive region 306, the integration degree can be increased. However, in that case, it is preferable that the bias line S is parallel to the write word line and the read word line (that is, orthogonal to the bit line). As shown in the figure, the integration degree can be increased by sharing the bias line S with an adjacent memory unit (the memory unit on the right side with the bias line S in between). 8) may be used. 8) may be used. 8) may be used. 8) may be used.

[0272] As the material of the read gate 310 and the first connection electrode 311, the materials used for the read gate 110 and the first connection electrode 111 described in Embodiment 3 (or Fig. 8) may be used. 8) may be used.

[0273] Figure 22(B) shows the main wirings, electrodes, etc. centered around a transistor using an oxide semiconductor formed on the circuit of Figure 22(A). A plurality of island-shaped oxide semiconductor regions 312 and a plurality of first wirings 314 are formed. The first wiring 314 becomes a write word line Q1, Q2, Q3, Q4, or a read word line P1, P2, P3, P4.

[0274] A part of the first wiring 314 overlaps with the oxide semiconductor to become the gate electrode of the write transistor. Also, the oxide semiconductor region 312 is in contact with the lower read gate 310. A part of the first wiring 314 overlaps with the read gate 310 to form a capacitor. Also, a second connection electrode 317 for connection to the upper layer (for example, bit line R) is provided in a part of the oxide semiconductor region 312.

[0275] When Figure 22(A) and (B) are superimposed, it becomes as shown in Figure 22(C). Here, for the sake of showing the overlap, they are intentionally shifted a little and superimposed. Furthermore, a second wiring 318 formed on the transistor using an oxide semiconductor is also shown. A part of the second wiring 318 becomes a bit line R. Note that points A and B in Figures 22(A) to (C) indicate the same position.

[0276] In Figure 22, the width of the conductive region 306 and the first wiring 314 are processed with the minimum processing line width F. That is, the line width and the line interval are F. In that case, the size of the unit memory cell becomes 12F 2 Since there is also a part shared by each memory cell in the memory unit, in reality, the area per memory cell is larger than 12F 2 The memory unit shown in Figure 22 has four memory cells ​​​Although a loop is provided, if the number of memory cells in the memory unit is increased, the area per memory cell approaches 12F. The area approaches 12F. 2

[0277] (Embodiment 10) In this embodiment, an example of the operation of the semiconductor memory circuit shown in FIG. 16(B) will be described with reference to FIGS. 20 and 21. Note that specific numerical values are given below as potentials for the purpose of facilitating understanding of the technical idea. Needless to say, these values may be changed depending on various characteristics of the transistors and capacitors, or depending on the convenience of the implementer. Also, the semiconductor memory device shown in FIG. 16(B) can write or read data by methods other than the following method. Here, write transistors WTr1, WTr2, WTr3 are of N-channel type, and read transistors RTr1, RTr2, RTr3 are of P-channel type. Also, it is assumed that the write transistor turns on when the potential of the gate is 1V or more higher than the potential of either the source or the drain, and is off otherwise. Also, it is assumed that the read transistor turns on when the potential of the gate is 1V or more lower than the potential of either the source or the drain, and is off otherwise.

[0278] Here, write transistors WTr1, WTr2, WTr3 are of N-channel type, and read transistors RTr1, RTr2, RTr3 are of P-channel type. Also, it is assumed that the write transistor turns on when the potential of the gate is 1V or more higher than the potential of either the source or the drain, and is off otherwise. Also, it is assumed that the read transistor turns on when the potential of the gate is 1V or more lower than the potential of either the source or the drain, and is off otherwise.

[0279] Also, among the gate capacitances of the read transistors, the portion that varies due to the gate bias is assumed to be negligible with respect to the capacitance of capacitor C. Further, all capacitances not shown in the figure, such as the parasitic capacitances of the write transistors WTr and the read transistors RTr, and the parasitic capacitances between wirings, are considered to be 0. Also, in FIGS. 20 and 21, on ​​​​​​​​​​​​​ A transistor in the on state is marked with a circle, and a transistor in the off state is marked with a cross, respectively, which are overwritten on the symbol of the transistor. For those that turn on under specific conditions, they may be described separately in the figure. In the following example, it is assumed that the potential of the bias line S is always 0V.

[0280] Writing starts from the rightmost memory cell. At the time of writing, as shown in Fig. 20(A), the potentials of the write word lines Q1, Q2, and Q3 are set to +4V, and the potential of the read word line P is set to -4 V. Also, the potential of the bit line R takes four levels of values: 0V, +1V, +2V, +3V, according to the data to be written.

[0281] In this state, the write transistors WTr1, WTr2, and WTr3 turn on, and the potential of the node F3 approaches the potential of the bit line R. Here, it is assumed to be equal to the potential of the bit line R.

[0282] On the other hand, at this stage, the read transistors RTr1, RTr2, and RTr3 are in the off state. And, as shown in Fig. 20(B), the potential of the write word line Q3 is set to -4V. Then, since the write transistor WTr3 turns off, the potential of the previous bit line R is held at the node F3. In this way, data can be written into the rightmost memory cell.

[0283] Next, data is written into the middle memory cell. In the state of Fig. 20(B), the potential of the node F2 is equal to the potential of the bit line R. Then, the potential of the write word line Q2 is set to -4V (see Fig. 20(C)), and the write transistor WTr2 turns off. At the node F2, The potential of the immediately preceding bit line R is retained. In this way, data can be written into the central memory cell. Subsequently, data can be written in the same order, and data can be written into all the memory cells.

[0284] When there is no need to perform the operation of writing into the memory unit, as shown in Fig. 20(D), the potentials of the write word lines Q1, Q2, Q3 may be set to 0V, and the potential of the read word line P may be set to 0V. At this time, the potential of node F1 will be +4V or more and +7V or less. Since the potential of bit line R is 0V or more and +3V or less, the read transistors RTr1, RTr2, RTr3 can maintain the off state.

[0285] Next, reading will be described with reference to Fig. 21. First, when reading a row other than the memory unit in question, as shown in Fig. 21(A), the potentials of the write word lines Q1, Q2, Q3 are set to 0V, and the potential of the read word line P is set to 0V. In this way, the write transistors WTr1, WTr2, WTr3 turn off. Also, the potentials of nodes F1, F2, F3 are +4V or more and +7V or less. And since the potential of bit line R is 0V or more and +4V or less, as will be described later, the read transistors RTr1, RTr2, RTr3 can maintain the off state.

[0286] To read the memory unit in question, as shown in Fig. 21(B), the potentials of the write word lines Q1, Q2, Q3 are set to -4V, and the potential of the read word line P is set to -4V. Also, the potential of the bit line is set to +4V. At this time, the write transistors WTr1, WTr2, WTr3 turn off. Also, the potentials of nodes F1, F2, F3 are 0V or more and +3V or more. ​​​​​​​​​​​​​Since it is as described below, the read transistors RTr1, RTr2, and RTr3 are turned on. This causes a current to flow between the bit line R and the bias line S.

[0287] If the end of the bit line R is a capacitor, when a current flows between the bit line R and the bias line S, the initial potential (+4V) will approach the potential of the bias line S (0V). The final potential is determined by the minimum value of the potentials of nodes F1, F2, and F3. In any case, the potential of the bit line R will vary between 0V and +4V.

[0288] In the following, assume that data of the central memory cell in the memory unit is read. As shown in Fig. 21 (C), when the potential of the write word line Q3 is raised to -3V, the potential of node F2 will be either +1V, +2V, +3V, or +4V according to the written data. Here, if the potential of node F2 is +4V, the read transistor RTr2 turns off, so no current flows between the bit line R and the bias line S.

[0289] At this stage, the potential of node F2 being +4V is the case when the potential of the bit line was + 3V during writing. That is, when the potential of the write word line Q3 is +1V and the read transistor RTr2 is off, it can be known that the potential of the bit line R was +3 V during writing. In this way, the value of the data can be known.

[0290] Furthermore, as shown in Fig. 21(D), when the potential of the write word line Q3 is raised to -2V, the potential of node F2 will be either +2V, +3V, +4V, or +5V according to the written data. Here, if the potential of node F2 is +4V or +5V, the read trans Since the dista RTr2 is turned off, no current flows between the bit line R and the bias line S. The potential of the node F2 becomes +4V or +5V when the potential of the bit line during writing is +2V or +3V.

[0291] Similarly, as shown in Fig. 21(E), when the potential of the write word line Q3 is raised to -1V, the potential of the node F2 becomes +3V, +4V, +5V, or +6V depending on the written data. Here, if the potential of the node F2 is +4V, +5V, or +6V, the read transistor RTr2 is turned off, so no current flows between the bit line R and the bias line S. That is, this is the case when the potential of the bit line during writing is +1V, +2V, or +3V.

[0292] When the potential of the bit line during writing is 0V, if the potential of the write word line Q3 is set to -1V, the potential of the node F2 is +3V and remains on. That is, even when the potential of the write word line Q3 is -1V and current flows between the bit line R and the bias line S, it can be seen that the potential of the bit line R was 0V during writing.

[0293] In addition, in Embodiment 8, multi-valued data can also be read by measuring the potential in the same way as described using Fig. 18(F).

[0294] In this way, 4-level data (2 bits) can be written and read. Of course, similarly, more data, for example, 8-level data (3 bits), 16-level data (4 bits) can be written and read.

[0295] In the above description, the parasitic capacitance and the gate capacitance of the read transistor RTr(n,m) were ignored with respect to the capacitance of the capacitor C(n,m), but in an actual memory cell, it is necessary to consider them and determine the potential to be applied as described above.

[0296] The gate capacitance of the read transistor RTr(n,m) varies greatly between the on-state and the off-state, so the potential of the gate of the read transistor RTr(n,m) is affected by it. The larger the ratio of the gate capacitance of the read transistor RTr(n,m) to the capacitance of the capacitor C(n,m), the greater the influence. Therefore, preferably, the capacitance of the capacitor C(n,m) should be set to be at least twice the gate capacitance of the read transistor RTr(n,m).

[0297] (Embodiment 11) In this embodiment, an example of the shape and manufacturing method of the semiconductor memory device described in Embodiment 10 will be described. FIG. 23 shows a layout example of the memory unit of the semiconductor memory device of this embodiment. In this embodiment, a unit memory unit

[0298] has four memory cells. FIG. 23(A) shows main wirings, electrodes, etc. provided on a single-crystal silicon substrate. An element isolation region 402 is formed on the substrate. Also, a conductive region 406 is formed using a conductive material or doped silicon, and a part of it serves as the source and drain of the read transistor. A part of the conductive region 406 serves as a part of the bias line S. There is a part of the conductive region 406 separated by the read gate 410 of the read transistor. A first connection electrode 411 is provided on a part of the conductive The integration degree can be increased by sharing with adjacent memory units. Read gate 410 As the material of the first connection electrode 411, those satisfying the conditions of the read gate 310 and the first connection electrode 311 shown in Embodiment 9 may be used.

[0299] FIG. 23(B) shows main wirings, electrodes, etc. centered on a transistor using an oxide semiconductor formed on the circuit of FIG. 23(A). A plurality of island-shaped oxide semiconductor regions 412 and a plurality of first wirings 414 are formed. The first wiring 414 serves as a write word line Q1, Q2, Q3, Q4, or a read word line P. A part of the first wiring 414 overlaps with the oxide semiconductor to become the gate electrode of the write transistor

[0300] and the oxide semiconductor region 412 is in contact with the underlying read gate 410. A part of the first wiring 414 overlaps with the read gate 410 to form a capacitor. Further, a second connection electrode 417 for connection to an upper layer (for example, bit line R) is provided in the oxide semiconductor region 412. When FIGS. 23(A) and (B) are superimposed, it becomes as shown in FIG. 23(C). Here, for clarity of overlap, they are intentionally shifted and superimposed slightly. Further, a second wiring 418 formed on the transistor using an oxide semiconductor is also shown. A part of the second wiring 418

[0301] serves as a bit line R. Points A and B in FIGS. 23(A) to (C) indicate the same position. In FIG. 23, the width of the conductive region 406 is processed with the minimum processing line width F. That is, the line width and the line pitch are F and in that case, the size of the unit memory cell is 9F

[0302] 2 ​​​​This results. Since there are also portions shared among the memory cells in the memory unit, in reality, the area per memory cell becomes larger than 9F. Since there are also portions shared among the memory cells , in reality, the area per memory cell is larger than 9F. 2 becomes larger. In the memory unit shown in FIG. 23, four memory cells are provided. However, if the number of memory cells in the memory unit is increased, the area per memory cell approaches 9F. In the memory unit shown in FIG. 23, four memory cells are provided. However, if the number of memory cells in the memory unit is increased, the area per memory cell approaches 9F. 2 approaches.

[0303] Hereinafter, a method for manufacturing the semiconductor memory device having the above structure will be described. FIG. 24 is a cross-sectional process view connecting point A and point B in FIG. 23. Hereinafter, the manufacturing process will be described according to the figure numbers. Hereinafter, a method for manufacturing the semiconductor memory device having the above structure will be described. FIG. 24 is a cross-sectional process view connecting point A and point B in FIG. 23. Hereinafter, the manufacturing process will be described according to the figure numbers.

[0304] <FIG. 24(A)> First, using a known semiconductor manufacturing technology, on an n-type single crystal silicon substrate 401, an element isolation region 402, a conductive region 406 formed by a silicon region doped with p-type, a first gate insulating film 403, a dummy gate 404, and a first interlayer insulator 407 are formed. Sidewalls may be provided on the side surfaces of the dummy gate 404 as shown in the figure. The conductive region 406 may have a structure in which a silicide region is provided on its surface to enhance conductivity. First, using a known semiconductor manufacturing technology, on an n-type single crystal silicon substrate 401, an element isolation region 402, a conductive region 406 formed by a silicon region doped with p-type, a first gate insulating film 403, a dummy gate 404, and a first interlayer insulator 407 are formed. Sidewalls may be provided on the side surfaces of the dummy gate 404 as shown in the figure. The conductive region 406 may have a structure in which a silicide region is provided on its surface to enhance conductivity. First, using a known semiconductor manufacturing technology, on an n-type single crystal silicon substrate 401, an element isolation region 402, a conductive region 406 formed by a silicon region doped with p-type, a first gate insulating film 403, a dummy gate 404, and a first interlayer insulator 407 are formed. Sidewalls may be provided on the side surfaces of the dummy gate 404 as shown in the figure. The conductive region 406 may have a structure in which a silicide region is provided on its surface to enhance conductivity. First, using a known semiconductor manufacturing technology, on an n-type single crystal silicon substrate 401, an element isolation region 402, a conductive region 406 formed by a silicon region doped with p-type, a first gate insulating film 403, a dummy gate 404, and a first interlayer insulator 407 are formed. Sidewalls may be provided on the side surfaces of the dummy gate 404 as shown in the figure. The conductive region 406 may have a structure in which a silicide region is provided on its surface to enhance conductivity. First, using a known semiconductor manufacturing technology, on an n-type single crystal silicon substrate 401, an element isolation region 402, a conductive region 406 formed by a silicon region doped with p-type, a first gate insulating film 403, a dummy gate 404, and a first interlayer insulator 407 are formed. Sidewalls may be provided on the side surfaces of the dummy gate 404 as shown in the figure. The conductive region 406 may have a structure in which a silicide region is provided on its surface to enhance conductivity.

[0305] <FIG. 24(B)> Using the method described in Embodiment 3, after embedding and forming the read gate 410 and the first connection electrode 411 of the read transistor, an oxide semiconductor region 412 is formed. Here, in order to make the thickness of the oxide semiconductor region 30 to 50 nm several times larger than the thickness of 10 nm of the second gate insulating film 413 to be formed later, for the purpose of relaxing the step, the end portion of the oxide semiconductor region 412 is processed into a tapered shape. The taper angle at the end of the oxide semiconductor region may be set to 30 degrees to 60 degrees. Using the method described in Embodiment 3, after embedding and forming the read gate 410 and the first connection electrode 411 of the read transistor, an oxide semiconductor region 412 is formed. Here, in order to make the thickness of the oxide semiconductor region 30 to 50 nm several times larger than the thickness of 10 nm of the second gate insulating film 413 to be formed later, for the purpose of relaxing the step, the end portion of the oxide semiconductor region 412 is processed into a tapered shape. The taper angle at the end of the oxide semiconductor region may be set to 30 degrees to 60 degrees. Using the method described in Embodiment 3, after embedding and forming the read gate 410 and the first connection electrode 411 of the read transistor, an oxide semiconductor region 412 is formed. Here, in order to make the thickness of the oxide semiconductor region 30 to 50 nm several times larger than the thickness of 10 nm of the second gate insulating film 413 to be formed later, for the purpose of relaxing the step, the end portion of the oxide semiconductor region 412 is processed into a tapered shape. The taper angle at the end of the oxide semiconductor region may be set to 30 degrees to 60 degrees. Using the method described in Embodiment 3, after embedding and forming the read gate 410 and the first connection electrode 411 of the read transistor, an oxide semiconductor region 412 is formed. Here, in order to make the thickness of the oxide semiconductor region 30 to 50 nm several times larger than the thickness of 10 nm of the second gate insulating film 413 to be formed later, for the purpose of relaxing the step, the end portion of the oxide semiconductor region 412 is processed into a tapered shape. The taper angle at the end of the oxide semiconductor region may be set to 30 degrees to 60 degrees. Using the method described in Embodiment 3, after embedding and forming the read gate 410 and the first connection electrode 411 of the read transistor, an oxide semiconductor region 412 is formed. Here, in order to make the thickness of the oxide semiconductor region 30 to 50 nm several times larger than the thickness of 10 nm of the second gate insulating film 413 to be formed later, for the purpose of relaxing the step, the end portion of the oxide semiconductor region 412 is processed into a tapered shape. The taper angle at the end of the oxide semiconductor region may be set to 30 degrees to 60 degrees. Using the method described in Embodiment 3, after embedding and forming the read gate 410 and the first connection electrode 411 of the read transistor, an oxide semiconductor region 412 is formed. Here, in order to make the thickness of the oxide semiconductor region 30 to 50 nm several times larger than the thickness of 10 nm of the second gate insulating film 413 to be formed later, for the purpose of relaxing the step, the end portion of the oxide semiconductor region 412 is processed into a tapered shape. The taper angle at the end of the oxide semiconductor region may be set to 30 degrees to 60 degrees.

[0306] <Figure 24(C)> A plurality of first wirings 414 are formed of a conductive material. The first wirings 414 are writing word lines Q1, Q2, Q3, etc. Some of the writing word lines Q1, Q2, Q3 serve as gate electrodes of transistors using an oxide semiconductor . Further, a region 415 exhibiting n-type conductivity, a second interlayer insulator 416, a second connection electrode 417, and a second wiring 418 are formed. The second wiring 418 is a bit line R. Thus, as shown in Figure 24(C), a memory cell of a semiconductor memory device having writing transistors 419a, 419b, a reading transistor 420, and a capacitor 421 is fabricated.

[0307] As shown in the figure, the writing word line Q2 is formed as an electrode of the capacitor 421 and a gate electrode of the writing transistor 419b. The oxide semiconductor region 412 of the capacitor 421 (i.e., the portion sandwiched between the writing word line Q2 and the reading gate 410) is not doped, but since its thickness is 50 nm or less, more than half of the portion functions as a weakly n-type conductor.

Explanation of Reference Numerals

[0308] 11 Means for measuring potential 12 Means for applying potential 13 Capacitor 14 Switch 101 Single crystal silicon substrate 102 Element isolation region 103 First gate insulating film 104Dummy gate 105a Silicide region 105b Silicide region 106a Conductive region 106b Conductive region 107 First interlayer insulator The first interlayer insulator having a flat surface 107a Opening 108 Opening 109 Read gate 110 The first connection electrode 111 Oxide semiconductor region 112 The second gate insulating film 113 The first wiring 114a The first wiring 114b Region showing n-type conductivity 115a Region showing n-type conductivity 115b The second interlayer insulator 116 The second connection electrode 117 The second wiring 118 Write transistor 119 Read transistor 120 Capacitor 121 Region of unit memory cell 200a Region of unit memory cell 200b Element isolation region 202 Conductive region 206a Conductive region 206b Read gate 210 The first connection electrode 211 Oxide semiconductor region 212 The first wiring 214 The second connection electrode 217 The second wiring 218 Element isolation region 302 Conductive region 306 Read gate 310 The first connection electrode 311 Oxide semiconductor region 312 The first wiring 314 The second connection electrode 317 The second wiring 318 Single crystal silicon substrate 401 Element isolation region 402 The first gate insulating film 403 Dummy gate 404 Conductive region 406 The first interlayer insulator 407 410 Read gate 411 First connection electrode 412 Oxide semiconductor region 413 Second gate insulating film 414 First wiring 415 Region showing n-type conductivity 416 Second interlayer insulator 417 Second connection electrode 418 Second wiring 419a Write transistor 419b Write transistor 420 Read transistor 421 Capacitor P Read word line Q Write word line R Bit line S Bias line WTr Write transistor RTr Read transistor C Capacitor

Claims

1. A semiconductor device having a first transistor and a second transistor, a first semiconductor having a channel formation region of the first transistor; a first insulating film having a region overlapping the first semiconductor; a first wiring having a region overlapping with a channel formation region of the first transistor via the first insulating film; a second semiconductor having a channel formation region of the second transistor and a region in contact with the first wiring; a second insulating film having a region in contact with the second semiconductor; a second wiring having a region overlapping a channel formation region of the second transistor via the second insulating film and having a region in contact with the second insulating film; a third wiring having a region overlapping the first semiconductor and a region in contact with the second insulating film; a fourth wiring having a region in contact with the second semiconductor; the second semiconductor is provided in a layer different from the first wiring; The second semiconductor includes an oxide semiconductor.

2. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first semiconductor having a channel formation region of the first transistor; a first insulating film having a region overlapping the first semiconductor; a first wiring having a region overlapping with a channel formation region of the first transistor via the first insulating film; a second semiconductor having a channel formation region of the second transistor and a region in contact with the first wiring; a second insulating film having a region in contact with the second semiconductor; a second wiring having a region overlapping a channel formation region of the second transistor via the second insulating film and having a region in contact with the second insulating film; a third wiring having a region overlapping the first semiconductor and a region in contact with the second insulating film; a fourth wiring having a region in contact with the second semiconductor; the first wiring has a region that functions as an electrode of the capacitance element, the second semiconductor is provided in a layer different from the first wiring; The second semiconductor includes an oxide semiconductor.

3. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor contains zinc and indium.

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