Semiconductor device and memory system

Abstract

To improve the reliability.SOLUTION: A semiconductor device according to an embodiment includes a first substrate, a semiconductor chip provided in a first region of a first surface of the first substrate, and a first structure provided in a second region of the first surface, the first substrate includes wiring embedded in the first substrate, a first conductor connected to the semiconductor chip and the wiring and exposed on the first surface, and a second conductor connected to the first conductor via the wiring and exposed on a second surface of the first substrate, and with respect to the first surface, a height of the first structure in a first direction perpendicular to the first surface is greater than a height of the semiconductor chip in the first direction.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a memory system.

Background Art

[0002] A semiconductor device configured to be mountable on a printed circuit board (PCB) or the like via a redistribution substrate is known. A semiconductor chip constituting an electronic component is mounted on the redistribution substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve reliability.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first substrate, a semiconductor chip provided in a first region on a first surface of the first substrate, and a first structure provided in a second region on the first surface. The first substrate includes wiring embedded in the first substrate, a first conductor connected to the semiconductor chip and exposed on the first surface, and a second conductor connected to the first conductor via the wiring and exposed on a second surface of the first substrate. Based on the first surface, a height in a first direction perpendicular to the first surface of the first structure is higher than a height in the first direction of the semiconductor chip.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Note that the dimensions and ratios in the drawings are not necessarily the same as those in reality. Also, in the following description, components having substantially the same functions and configurations are denoted by the same reference numerals.

[0008] 1 Embodiment A memory system according to an embodiment will be described.

[0009] 1.1 Memory System First, an example of the configuration of a memory system will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the configuration of a storage system including a memory system and a host device according to an embodiment.

[0010] The memory system 1 includes, for example, a substrate 3, a semiconductor device 10, a DRAM (Dynamic Random Access Memory) 20, and one or more NAND flash memories 30. Hereinafter, the NAND flash memory 30 is also referred to as the NAND memory 30.

[0011] The memory system 1 is, for example, an SSD (solid state drive) or an SD TM card. The memory system 1 communicates with an external host device 2, for example. The memory system 1 stores data from the host device 2. Also, the memory system 1 reads out data to the host device 2.

[0012] The substrate 3 is, for example, a printed circuit board or the like. On the substrate 3, for example, the semiconductor device 10, the DRAM 20, and one or more NAND memories 30 are mounted. The substrate 3 is an example of a second substrate.

[0013] The semiconductor device 10 is, for example, a controller. Hereinafter, the semiconductor device 10 is also referred to as the controller 10. The controller 10 is composed of, for example, an integrated circuit such as a SoC (system-on-a-chip). The controller 10 receives commands from the host device 2. The controller 10 causes the DRAM 20 and the NAND memory 30 to execute operations, for example, based on the commands received from the host device 2. The functions of each part of the controller 10 can be realized by dedicated hardware, a processor that executes a program (firmware), or a combination thereof.

[0014] Note that, in the embodiment, the case where the semiconductor device 10 is a controller is shown, but it is not limited thereto. The semiconductor device 10 may include, for example, at least one of a controller, a DRAM, and a NAND type flash memory. When the semiconductor device 10 includes a DRAM and a NAND type flash memory respectively, the DRAM 20 and the NAND memory 30 may not be mounted on the substrate 3.

[0015] The DRAM 20 is a volatile memory. Note that, in the memory system 1, another volatile memory or a non-volatile memory may be included instead of the DRAM 20. The DRAM 20 is configured to be communicable with the controller 10. The DRAM 20 temporarily stores data read by the controller 10 from the NAND memory 30, write data received from the host device 2, and the like.

[0016] The NAND memory 30 is a non-volatile storage medium. In the memory system 1, a non-volatile storage medium other than the NAND type flash memory may be included instead of the NAND memory 30. The NAND memory 30 is configured to be communicable with the controller 10. The NAND memory 30 stores the data received from the host device 2 by the controller 10 in a non-volatile manner. Also, the NAND memory 30 reads out the data stored in a non-volatile manner and transmits it to the controller 10.

[0017] 1.2 Functional Configuration of the Controller The functional configuration of the controller 10 will be continuously described with reference to FIG. 1.

[0018] The controller 10 includes a host I / F (host interface) 11, a CPU (processor) 12, a DRAM I / F (DRAM interface) 13, a NAND I / F (NAND interface) 14, and an SRAM (Static Random Access Memory) 15.

[0019] The host interface 11 controls the communication between the controller 10 and the host device 2. The host interface 11 is configured to be able to transmit and receive differential serial signals, for example. The host interface 11 transfers the commands and data received from the host device 2 to the CPU 12 and the DRAM I / F 13, respectively.

[0020] The CPU 12 controls the overall operation of the controller 10. The CPU 12 issues commands for instructing the execution of various operations including write operations, read operations, and erase operations to the NAND memory 30, for example.

[0021] The DRAM interface 13 is connected to the DRAM 20. The DRAM interface 13 controls the DRAM 20. The DRAM interface 13 transmits and receives data to and from the DRAM 20 via signal lines.

[0022] The NAND interface 14 is connected to the NAND memory 30. The NAND interface 14 controls the NAND memory 30. One NAND interface 14 can control a plurality of NAND memories 30. The NAND interface 14 transmits and receives data to and from the NAND memory 30 via signal lines. The NAND interface 14 transmits data (such as commands, addresses, and write data) corresponding to, for example, a read operation, a write operation, or an erase operation, etc. to the NAND memory 30. Also, the NAND interface 14 receives read data from the NAND memory 30, for example, during a read operation.

[0023] The SRAM 15 is a volatile memory. In the memory system 1, for example, instead of the SRAM 15, other memories with a faster access speed than the DRAM 20 may be included. The SRAM 15 is used as a working area for the CPU 12.

[0024] 1.3 Structure of the semiconductor device Next, the structure of the semiconductor device 10 will be described.

[0025] 1.3.1 Appearance First, the appearance of the semiconductor device 10 according to the embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 is a perspective view showing an example of the appearance of the semiconductor device according to the embodiment. FIG. 3 is a side view showing an example of the appearance of the semiconductor device mounted on the substrate in the memory system according to the embodiment. In FIG. 3, an example of a side view when the semiconductor device 10 mounted on the substrate 3 is viewed in the Y direction is shown.

[0026] The semiconductor device 10 includes a redistribution substrate 40, a semiconductor chip 50, and one or more structures 60.

[0027] In the following description, the thickness direction of the rewiring substrate 40 is referred to as the Z direction or the vertical direction. Also, when the components in the semiconductor device 10 have two surfaces facing each other in the vertical direction, these two surfaces are referred to as the upper surface and the lower surface, respectively. Further, in a plane perpendicular to the Z direction, two mutually perpendicular directions are referred to as the X direction and the Y direction.

[0028] The rewiring substrate 40 has a laminated structure formed using rewiring technology. Wiring is embedded in the rewiring substrate 40. Although not shown in FIGS. 2 and 3, electrodes connected by the embedded wiring are provided on the upper surface and the lower surface of the rewiring substrate 40, as will be described later. The electrodes have exposed surfaces. The rewiring substrate 40 has, for example, a rectangular parallelepiped shape. The rewiring substrate 40 is an example of the first substrate.

[0029] A semiconductor chip 50 is provided on the upper surface of the rewiring substrate 40. The upper surface of the rewiring substrate 40 is also referred to as the chip mounting surface. The semiconductor chip 50 includes, for example, the configuration of the main electric circuit of the semiconductor device 10. The electrodes provided on the lower surface of the semiconductor chip 50 are electrically connected to the electrodes provided on the upper surface of the rewiring substrate 40. As shown in FIG. 3, the height of the semiconductor chip 50 along the Z direction with respect to the upper surface (chip mounting surface) of the rewiring substrate 40 is the height h1. The semiconductor chip 50 has, for example, a rectangular parallelepiped shape.

[0030] On the upper surface of the redistribution substrate 40, one or more structures 60 are provided in a region excluding the region where the semiconductor chip 50 is provided. In the embodiment, a case where the semiconductor device 10 includes four structures 60 is shown, but the present invention is not limited thereto. The number of the structures 60 may be one or more, and may be 1 to 3, or 5 or more. When the number of the structures 60 is two or more, the plurality of structures 60 are provided as independent structures. Each structure 60 has, for example, a columnar shape. However, the shape of the structure 60 is not limited to the columnar shape, and may be, for example, a conical shape that becomes thinner as it moves away from the redistribution substrate 40. As shown in FIG. 3, the height along the Z direction of each structure 60 when the upper surface (chip mounting surface) of the redistribution substrate 40 is used as a reference is the height h2. The height h2 is higher than the height h1. The one or more structures 60 are, for example, resin, ceramic, glass, or a resistor. The resistor is, for example, a resistor including at least one of metal and silicon, or a resistor or the like. When the structure 60 is a resistor, the structure 60 includes, for example, electrodes 61 and 62 arranged to face each other in the Z direction. Although not shown, the structure 60 is electrically connected to, for example, an electrode to which a ground potential or a power supply potential is supplied among the electrodes provided on the upper surface of the redistribution substrate 40. When the structure 60 is a resistor, the electrode 62 is electrically connected to the above electrode to which a ground potential or a power supply potential is supplied. Although not shown, each structure 60 is arranged, for example, so as to be separated from the signal wiring provided on the upper surface of the redistribution substrate 40 when viewed in the Z direction. That is, each structure 60 is arranged, for example, at a position that does not overlap with the signal wiring when viewed in the Z direction.

[0031] Note that the one or more structures 60 are provided so that the semiconductor device 10 stands on its own when the semiconductor device 10 turned upside down is placed on a plane. Further, the one or more structures 60 are provided so that at least a part of the semiconductor chip 50 does not contact the above plane when the semiconductor device 10 is placed as described above. Therefore, it is preferable to provide two or more structures 60.

[0032] As shown in FIG. 3, in the memory system 1, the semiconductor device 10 is mounted on the substrate 3 via a plurality of conductors 70 provided below the redistribution substrate 40. That is, the semiconductor device 10 is mounted on the substrate 3 by flip chip bonding or soldering. The plurality of conductors 70 are formed, for example, by bumps or solder. Each of the plurality of conductors 70 is electrically connected to an electrode provided on the lower surface of the redistribution substrate 40.

[0033] 1.3.2 Cross-sectional Structure The structure of the semiconductor device 10 according to the embodiment will be further described with reference to FIG. 4. FIG. 4 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor device according to the embodiment. In FIG. 4, the cross-sectional structure of the portion of the semiconductor device 10 in the XZ plane is shown together with the portions of the conductor 70 and the substrate 3. Hereinafter, the cross-sectional structure of the redistribution substrate 40 will be mainly described.

[0034] The redistribution substrate 40 includes a plurality of conductor layers 41, 43, 45, and 47, a plurality of contact plugs 42, 44, and 46, and an insulator 48.

[0035] On the lower surface of the redistribution substrate 40, a plurality of conductor layers 41 are provided. Each of the plurality of conductor layers 41 has a portion exposed on the lower surface of the redistribution substrate 40. Each of the plurality of conductor layers 41 is connected to a corresponding one of the plurality of conductors 70, for example. The plurality of conductor layers 41 function as electrodes for electrically connecting the substrate 3 and the redistribution substrate 40 via the plurality of conductors 70.

[0036] On the upper surfaces of the plurality of conductor layers 41, a plurality of contact plugs 42 are provided. Each of the plurality of contact plugs 42 is connected to a corresponding one of the plurality of conductor layers 41, for example.

[0037] On the upper surfaces of the plurality of contact plugs 42, a plurality of conductor layers 43 are provided. In FIG. 4, one of the plurality of conductor layers 43 connected to two contact plugs 42 is illustrated.

[0038] On the upper surfaces of the plurality of conductor layers 43, a plurality of contact plugs 44 are provided. In FIG. 4, one contact plug 44 connected to the conductor layer 43 among the plurality of contact plugs 44 is illustrated.

[0039] On the upper surface of the contact plug 44, a plurality of conductor layers 45 are provided. In FIG. 4, one conductor layer 45 connected to the contact plug 44 among the plurality of conductor layers 45 is illustrated.

[0040] On the upper surface of the conductor layer 45, a plurality of contact plugs 46 are provided. In FIG. 4, two contact plugs 46 connected to the conductor layer 45 among the plurality of contact plugs 46 are illustrated.

[0041] On the upper surfaces of the plurality of contact plugs 46, a plurality of conductor layers 47 are provided. Each of the plurality of conductor layers 47 is connected to a corresponding contact plug 46 among the plurality of contact plugs 46. Each of the plurality of conductor layers 47 has a portion exposed on the upper surface of the rewiring substrate 40. The plurality of conductor layers 47 function as electrodes for electrically connecting the rewiring substrate 40 and the semiconductor chip 50.

[0042] In the configuration having the plurality of conductor layers 41, 43, 45, and 47, and the plurality of contact plugs 42, 44, and 46 as described above, the plurality of conductor layers 43 and 45, and the plurality of contact plugs 42, 44, and 46 function as wirings embedded in the rewiring substrate 40. These wirings electrically connect, for example, the plurality of conductor layers 41 and the plurality of conductor layers 47.

[0043] The insulator 48 is provided to protect the plurality of conductor layers 41, 43, 45, and 47, and the plurality of contact plugs 42, 44, and 46, for example, except for the portions of the plurality of conductor layers 41 exposed on the lower surface of the rewiring substrate 40 and the portions of the plurality of conductor layers 47 exposed on the upper surface of the rewiring substrate 40.

[0044] In the memory system 1, a plurality of conductors 51 are provided between the redistribution substrate 40 and the semiconductor chip 50. The plurality of conductors 51 electrically connect the redistribution substrate 40 and the semiconductor chip 50. Each of the plurality of conductors 51 is connected to a corresponding conductor layer 47 among the plurality of conductor layers 47.

[0045] With the above configuration, the semiconductor chip 50 and the substrate 3 are electrically connected via the redistribution substrate 40, and the plurality of conductors 51 and 70.

[0046] 1.4 Effects According to the embodiment, the reliability of the semiconductor device and the memory system can be improved. Hereinafter, the effects of the semiconductor device 10 and the memory system 1 according to the embodiment will be described.

[0047] The semiconductor device 10 according to the embodiment includes a redistribution substrate 40, a semiconductor chip 50 provided on the upper surface of the redistribution substrate 40, and a structure 60 provided in a region of the upper surface of the redistribution substrate 40 excluding the region where the semiconductor chip 50 is provided. The redistribution substrate 40 includes wiring embedded in the redistribution substrate 40, a conductor layer 47 that is electrically connected to the semiconductor chip 50 and exposed on the upper surface of the redistribution substrate 40, and a conductor layer 41 that is electrically connected to the conductor layer 47 via the wiring and exposed on the lower surface of the redistribution substrate 40. The height h2 in the Z direction of the structure 60 when the upper surface of the redistribution substrate 40 is used as a reference is higher than the height h1 in the Z direction of the semiconductor chip 50. With the above configuration, electrostatic breakdown of the semiconductor device 10 due to the device charging model (CDM) can be suppressed.

[0048] Supplementally, when mounting the semiconductor device on the substrate, the mounting robot picks up, for example, the semiconductor device placed stationary on the tray with the chip mounting surface as the lower surface of the rewiring substrate. At this time, the semiconductor device may be charged due to the friction between the tray and the semiconductor device. As a result, electrostatic breakdown of the semiconductor device due to CDM may occur. According to the embodiment, since the height h2 of the structure 60 is higher than the height h1 of the semiconductor chip 50, when the chip mounting surface is used as the lower surface of the rewiring substrate 40 and placed stationary on the tray, the distance between the rewiring substrate 40 and the tray can be increased as compared with the case where such a structure is not present. Thereby, an increase in the capacitance of the parallel plate capacitor formed by the tray and the metal housing of the mounting robot on which the tray is disposed can be suppressed. For this reason, electrostatic breakdown due to CDM can be suppressed. Therefore, the reliability of the semiconductor device 10 and the memory system 1 can be improved.

[0049] Further, when the semiconductor device 10 is turned upside down and placed stationary on a plane parallel to the XY plane, the one or more structures 60 are provided so that the semiconductor chip 50 does not contact the plane. Also with such a configuration, for example, an increase in the capacitance of the parallel plate capacitor formed by the tray and the metal housing of the mounting robot on which the tray is disposed when mounting the semiconductor device on the substrate can be suppressed. Further, when the semiconductor device 10 has a plurality of structures 60, also with such a configuration, the semiconductor chip 50 can suppress an increase in the capacitance of the parallel plate capacitor. Also by the above, the reliability of the semiconductor device 10 and the memory system 1 can be improved.

[0050] Further, the one or more structures 60 are arranged, for example, so as to be separated from the signal wiring provided on the upper surface of the rewiring substrate 40. According to such a configuration, interference between the structure 60 and the signal wiring can be suppressed. For this reason, the occurrence of signal loss is suppressed.

[0051] Also, each structure 60 is a resistor or a resistance device. And each structure 60 is provided on the upper surface of the redistribution substrate 40 and can be connected to an electrode to which a ground potential or a power supply potential is supplied. With these configurations, a discharge path of the semiconductor device 10 can be secured.

[0052] Also, in the semiconductor device 10 according to the embodiment, the chip mounting surface of the redistribution substrate 40 is not entirely covered by the mold. Thus, according to the embodiment, the heat dissipation performance of the semiconductor device 10 can be improved as compared with the case where the chip mounting surface of the redistribution substrate is entirely covered by the mold. Also, the occurrence of signal loss due to the mold is suppressed as compared with the case where the chip mounting surface of the redistribution substrate is entirely covered by the mold.

[0053] 2 Modification Example The above-described embodiment can be variously modified. The modification examples will be described below.

[0054] In the above-described embodiment, the case where each structure 60 is a resistor or a resistance device is shown, but it is not limited thereto. Each structure 60 may be, for example, a capacitor.

[0055] The configuration of the memory system according to the modification example can be the same as the configuration of the memory system according to the embodiment. Hereinafter, the configuration of the semiconductor device 10a according to the modification example that is different from the configuration of the semiconductor device 10 according to the embodiment will be described.

[0056] The structure of the semiconductor device 10a according to the modification example will be described with reference to FIG. 5. FIG. 5 is a perspective view showing an example of the appearance of the semiconductor device according to the modification example.

[0057] In a modified example, each structure 60 is a capacitor. Electrodes 61 and 62 of each structure 60 are arranged to face each other, for example, in a direction parallel to the XY plane. FIG. 5 shows an example in which electrodes 61 and 62 of each structure 60 are arranged side by side in the X direction or the Y direction. Although not shown, on the upper surface of the rewiring substrate 40, the plurality of conductor layers 47 include, for example, two different conductor layers 47 corresponding to either electrode 61 or 62 of each structure 60. Electrodes 61 and 62 are each electrically connected to two different conductor layers 47. Thereby, the structure 60 functions as a capacitor included in the electric circuit provided in the semiconductor device 10a. Each structure 60 is arranged, for example, in the same manner as in the embodiment, so as to be separated from the signal wiring provided on the upper surface of the rewiring substrate 40 when viewed in the Z direction.

[0058] Note that, in FIG. 5, the case where the semiconductor device 10a includes three structures 60 is shown. However, as in the embodiment, the number of structures 60 may be one or more.

[0059] With the above configuration, as in the embodiment, the reliability of the semiconductor device 10a and the memory system 1 can be improved.

[0060] 3 Others In the above-described embodiment, an example in which all the structures 60 are resistors or resistors is shown, and in the above-described modified example, an example in which all the structures 60 are capacitors is shown. However, the present invention is not limited thereto. The semiconductor device 10 of the embodiment may include a structure 60 that functions as a capacitor, and the semiconductor device 10a of the modified example may include a structure 60 that functions as a resistor.

[0061] Also, in semiconductor devices 10 and 10a, the semiconductor chip 50 may be covered by a layered mold. That is, for example, in the embodiments and variations, the upper surface and side surfaces of the semiconductor chip 50 may be covered by a thin layered or film-like mold. In this case, the mold is provided so as to be separated from the signal wiring provided on the upper surface of the redistribution substrate 40, for example, when viewed in the Z direction. That is, the mold is provided so as not to overlap the signal wiring, for example, when viewed in the Z direction. According to such a configuration, interference between the mold and the signal wiring can be suppressed. Thereby, the occurrence of signal loss is suppressed.

[0062] Also, in the above-described embodiments and variations, the case where the semiconductor chip 50 and one or more structures 60 are provided on the upper surface of the redistribution substrate 40 has been shown, but it is not limited to this. In addition to the semiconductor chip 50 and one or more structures 60, other elements such as capacitors and resistors can be provided on the upper surface of the redistribution substrate 40.

[0063] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0064] 1... Memory system, 2... Host device, 3... Substrate, 10... Semiconductor device (controller), 11... Host I / F, 12... CPU, 13... DRAM I / F, 14... NAND I / F, 15... SRAM, 20... DRAM, 30... NAND memory, 40... Redistribution substrate, 50... Semiconductor chip, 51, 70... Conductor, 60... Structure.

Claims

1. A first substrate; A semiconductor chip provided in a first region on a first surface of the first substrate; A first structure provided in a second region on the first surface; Comprising; The first substrate is; Wiring embedded in the first substrate; A first conductor connected to the semiconductor chip and the wiring and exposed on the first surface; A second conductor connected to the first conductor via the wiring and exposed on a second surface of the first substrate; Including; Based on the first surface, a height in a first direction perpendicular to the first surface of the first structure is higher than a height in the first direction of the semiconductor chip. Semiconductor device.

2. When the semiconductor device is placed on a third surface with the first surface as the lower surface of the first substrate, the semiconductor chip does not contact the third surface. The semiconductor device according to Claim 1.

3. Further comprising a second structure provided in the second region, independently of the first structure. The semiconductor device according to Claim 1.

4. The first substrate further includes a third conductor exposed on the first surface to which a ground potential or a power supply potential is supplied. Including; The first structure is a resistor and is connected to the third conductor. The semiconductor device according to Claim 1.

5. The first structure has a first electrode and a second electrode arranged in the first direction. The first electrode is connected to the third conductor. The semiconductor device according to Claim 4.

6. The first substrate further includes a third conductor and a fourth conductor exposed on the first surface and provided spaced apart from each other. Including; The first structure is a capacitor provided between the third conductor and the fourth conductor. The semiconductor device according to Claim 1.

7. The second region is a region of the first surface excluding the first region. The semiconductor device according to Claim 1.

8. The semiconductor chip includes a memory controller. The semiconductor device according to any one of Claims 1 to 7.

9. The semiconductor device according to Claim 8; A second substrate on which the semiconductor device is mounted; Comprising; Memory system.

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