Semiconductor-superconductor hybrid device and fabricating the same

Abstract

To provide a method of fabricating a semiconductor-superconductor hybrid device.SOLUTION: A method of etching a workpiece including a lead component includes the steps of: forming a mask on the lead component, in which the mask defines an exposed area of the lead component; and bringing the exposed area into contact with an etchant composition, in which the etchant composition includes acetic acid and propan-2-ol. The workpiece may further include an aluminum component. Additionally, the workpiece may further include a semiconductor component.SELECTED DRAWING: Figure 3

Description

Background Art

[0001] Certain semiconductor - superconductor hybrid devices have applicability in quantum computing, for example, topological quantum computing.

[0002] Topological quantum computing is based on the phenomenon that in the region where a semiconductor is coupled to a superconductor, non - abelian anyons in the form of "Majorana zero modes" (MZM) can be formed. Non - abelian anyons are a type of quasiparticle, meaning excitations in an electron liquid that behave at least partially like particles rather than the particles themselves. MZM is a specific bound state of such quasiparticles. Under certain conditions, these states can be formed near the semiconductor - superconductor interface in a nanowire formed from a certain length of semiconductor coated with a superconductor. When MZM is induced in the nanowire, it is said to be in the "topological regime". In some examples, to induce this, a magnetic field is applied externally as conventionally, and further, the nanowire needs to be cooled below the temperature at which superconducting behavior in the superconductor material is induced. It may further include gating a part of the nanowire with an electrostatic potential.

[0003] By forming such a network of nanowires and inducing the topological regime in a part of the network, it is possible to generate qubits (quantum bits) that can be manipulated for the purposes of quantum computing. A qubit, or quantum bit, is an element that can perform a measurement with two possible outcomes, but at any given time (when not being measured), is actually a quantum superposition of two states corresponding to different outcomes.

[0004] To induce the MZMs, the device is cooled to a temperature at which the superconductor (e.g., aluminum) exhibits superconducting behavior. Under appropriate conditions, the superconductor induces a proximity effect in the adjacent semiconductor, such that a region of the semiconductor near the interface with the superconductor also exhibits superconducting properties. That is, topological phase behavior is induced not only in the superconductor but also in the adjacent semiconductor. The location where the MZMs are formed is within this region of the semiconductor.

[0005] Another condition for inducing the topological phase in which MZMs can be formed is the application of a magnetic field to lift the spin degeneracy in the semiconductor. Degeneracy in the context of a quantum system refers to the case where different quantum states have the same energy level. Lifting the degeneracy means causing such states to have different energy levels. Spin degeneracy refers to the case where different spin states have the same energy level. Spin degeneracy can be lifted using a magnetic field, splitting the energy levels between electrons with differently spin-polarized states. This is known as the Zeeman effect. The g-factor refers to the coefficient between the applied magnetic field and the spin splitting. Typically, the magnetic field is applied by an external electromagnet.

[0006] [Cross - reference to related applications] This application claims the benefit and priority of U.S. Provisional Application No. 62 / 944,093, filed on December 5, 2019, and U.S. Application No. 16 / 796,671, filed on February 20, 2020, each titled "SEMICONDUCTOR - SUPERCONDUCTOR HYBRID DEVICE AND ITS FABRICATION", and both are hereby incorporated herein by reference in their entirety as if fully set forth herein for all purposes. [Summary of the Invention]

[0007] A method for manufacturing a semiconductor-superconductor hybrid device is provided. The method includes providing a workpiece including a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the layer of the first superconductor material, wherein the second superconductor material is different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidizing the exposed portion of the first superconductor material to form a passivating layer on the semiconductor component.

[0008] Furthermore, a semiconductor-superconductor hybrid device is provided. The device includes a semiconductor component; a first superconductor component extending over a first portion of the semiconductor component, the first superconductor component including a first superconductor material; a second superconductor component on the first superconductor component, the second superconductor component including a second superconductor material different from the first superconductor material; and a passivating layer extending over a second portion of the semiconductor component, the passivating layer including an oxide of the first superconductor material.

[0009] Furthermore, a method for etching a workpiece including a lead component is provided. The method includes forming a mask on the lead component, the mask defining an exposed region of the lead component; and contacting the exposed region with an etchant composition. The etchant composition includes acetic acid and propan-2-ol.

[0010] This summary is provided to introduce selected concepts from the following detailed description in a simplified form. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all of the disadvantages described herein.

Brief Description of the Drawings

[0011] To assist in understanding the embodiments of the present disclosure and to show how such embodiments may be implemented, reference is made, by way of example only, to the accompanying drawings.

Figure 1

Figure 2a

Figure 2b

Figure 2c

Figure 2d

Figure 2e

Figure 2f

Figure 2g

Figure 3

Figure 4

Figure 5a

Figure 5b

Best Mode for Carrying Out the Invention

[0012] I. General Considerations and Overview As used herein, the verb "comprising" is used as a shorthand expression for "including or consisting of". In other words, while the verb "comprising" is intended to be an open-ended term, its replacement with the closed term "consisting of" is explicitly contemplated, particularly when used in relation to chemical compositions.

[0013] Directional terms such as "upper", "bottom", "left", "right", "above", "below", "horizontal", and "vertical" are used herein for convenience of explanation and are related to the device as viewed in the orientation shown in Figure 2. To avoid ambiguity, this terminology is not intended to limit the orientation of the device in an external reference system.

[0014] When used to describe the relationship between components, the term "on" typically means "directly on", unless the context clearly indicates otherwise.

[0015] As used herein, the term "superconductor" refers to a material that becomes superconducting when cooled to a temperature below its critical temperature Tc. The use of this term is not intended to limit the temperature of the device.

[0016] As referred to herein, a "nanowire" is an elongated member having a nanoscale width and a length-to-width ratio of at least 100, or at least 500, or at least 1000. Typical examples of nanowires have widths in the range of 10 - 500 nm, optionally 50 - 100 nm or 75 - 125 nm. The length is typically on the order of micrometers, for example, at least 1 μm, or at least 10 μm.

[0017] In the context of the present disclosure, the term "bonding" specifically refers to the formation of a hybrid of energy levels between two materials or components.

[0018] Volumes are measured at 25 °C and a pressure of 1 atm (101325 Pa).

[0019] The term "workpiece" can in particular refer to an unfinished device obtained after one or more manufacturing steps.

[0020] When used in connection with a number, the term "about" means that its value can vary by ± 10% of the indicated value.

[0021] The content of all documents cited in this specification is hereby incorporated by reference in its entirety into this specification.

[0022] Semiconductor-superconductor hybrid devices using aluminum as a superconductor component are being studied. Aluminum has various favorable properties including good lattice matching and good bonding with various semiconductor materials.

[0023] In this specification, a semiconductor-superconductor hybrid device is described in which a first superconductor connects a further superconductor to a semiconductor and a passivation layer protects the semiconductor component from degradation.

[0024] Next, with reference to FIGS. 1 and 2, a method of manufacturing a semiconductor-superconductor hybrid device will be described.

[0025] In block 101, a layer of a first superconductor material is formed on a semiconductor component. Typically, the layer of the first superconductor material grows epitaxially on the semiconductor component.

[0026] This step forms a workpiece schematically shown in FIG. 2a. FIG. 2a shows a semiconductor component 20 having a layer 22 of a first superconductor material disposed directly on the semiconductor component 20.

[0027] The properties of the materials for forming the semiconductor components are not particularly limited.

[0028] For example, silicon, germanium, or a silicon / germanium semiconductor may be used.

[0029] Alternatively, the semiconductor component may include a group III-V semiconductor. Examples of useful group III-V semiconductor materials include those of the following general formula. InAs x Sb 1-x (Formula 1) Here, x is in the range of 0 to 1. In other words, the semiconductor component 20 may include indium antimonide (x = 0), indium arsenide (x = 1), or a ternary mixture containing 50% indium and variable ratios of arsenic and antimony (0 < x < 1) on a molar basis.

[0030] Indium arsenide (InAs) has been found to have good handling characteristics and provides devices with good performance. Indium antimonide (InSb) provides further improvement in device performance but may have less favorable handling characteristics. The ternary mixture has intermediate characteristics between those of the binary compounds InAs and InSb. When x is in the range of 0 to 0.7, or 0.01 to 0.7, an improvement in device performance compared to InAs can be observed. A value of x in the range of 0.35 to 0.45 can provide a particularly good balance between the performance and handling characteristics of the device.

[0031] The semiconductor component may include indium arsenide. Since the components of the hybrid device can be manufactured by an epitaxial growth process, good lattice matching between the component materials may sometimes be desirable. Indium arsenide has particularly good compatibility with aluminum.

[0032] Figure 2 shows a single semiconductor layer. There may be multiple semiconductor components. For example, there may be a first semiconductor component in the form of a nanowire supported by a second semiconductor component in the form of a wafer. More sophisticated devices may include a network of nanowires disposed on a wafer or a semiconductor heterostructure containing a two-dimensional electron gas.

[0033] Indium phosphide is an example of a semiconductor that can be useful as a wafer material. Indium phosphide has a higher bandgap than the materials of Formula 1 and thus may not interfere with the operation of devices based on these materials.

[0034] The first superconducting material is selected to be a material that can be easily grown on the semiconductor material. Good lattice matching between the first superconducting material and the semiconductor material can be useful in this regard. The first superconducting material is further selected to be selectively etchable with respect to the second superconducting component. For example, the first superconducting component may be selected such that an etchant for the second superconducting material does not etch the first superconducting material. The first superconducting component may be selected to etch the first superconducting component at a rate slow enough to allow for the selective removal of the second superconducting material while retaining the first superconducting material.

[0035] The first superconducting material may be a material that undergoes self-limiting oxidation to a certain depth, for example, when exposed to oxygen in the atmosphere. The first superconducting material preferably forms an oxide that acts as a dielectric.

[0036] Aluminum may be particularly preferred as the first superconducting material. One variation uses indium as the first superconducting material.

[0037] The thickness of the layer of the first superconducting material is selected to enable the formation of a passivation layer later in the process. The passivation layer is a layer that protects the semiconductor component from reactive species while enabling access to the semiconductor component. "Access" in this context means that an electrostatic field can be applied to the semiconductor component through the passivation layer.

[0038] The thickness of the layer of the first superconducting material may be selected such that the complete thickness of the exposed portion of the first superconducting material oxidizes at block 104. The exact thickness to achieve this varies depending, among other things, on the superconducting material selected, the reaction conditions chosen, and the crystal orientation of the first superconducting material.

[0039] In an example where the first superconducting material is aluminum, the layer of the first superconducting material typically has a thickness of 4 nm or less, for example 2 - 3 nm. An aluminum layer with a thickness of 3 nm or less typically oxidizes completely when exposed to oxygen in the air. The aluminum layer may have a thickness of at least 2 nm because it is more difficult to produce a continuous layer thinner than this.

[0040] In an example where the first superconducting material is indium, the layer of the first superconducting material may have a thickness of 10 nm or less, optionally 8 nm or less. When exposed to oxygen in the air, the indium layer oxidizes downward to a depth of about 10 nm.

[0041] If the subsequent etching step in block 104 partially etches the first superconducting layer, the thickness of the starting layer may be increased to compensate for this.

[0042] In block 102, a layer 24 of a second superconducting material is formed on top of the layer 22 of the first superconducting material. The second superconducting material is different from the first superconducting material. Figure 2(b) shows the workpiece obtained in this step.

[0043] Aluminum has good compatibility with semiconductor materials but has a relatively small superconducting gap. A further superconducting layer having a larger superconducting gap may be formed on the aluminum layer. The aluminum layer may facilitate the epitaxial growth of the layer of the second superconductor. The aluminum layer may provide good bonding between the semiconductor component and the second superconductor.

[0044] The semiconductor material and the first superconducting material may be selected to avoid a large Schottky barrier, in other words, a high resistance, at the interface between the semiconductor material and the first superconducting material. For example, the material of Formula 1 typically does not form a large Schottky barrier when interfacing with a metal such as aluminum. Instead, the conduction band at the surface of the semiconductor can be pulled down below the chemical potential. This can enable good transport and a good proximity effect across the interface when the first superconducting material is in the superconducting phase.

[0045] Generally, metals have many occupied available electronic states around the chemical potential that ensure good transport across the metal-metal interface.

[0046] Consequently, by providing a layer of the first superconductor between the semiconductor component and the layer of the second superconductor, an improved energy bond of the second superconductor to the semiconductor component can be achieved.

[0047] Examples of materials useful as the second superconductor include Pb, Sn, V, In, Nb, Ta, Re, NbN, NbTiN, MgB 2 , MoRe, and Fe-based superconductors. In principle, the second superconducting material may be any superconducting material that can be selectively etched from the first superconducting material.

[0048] The second superconducting material may be selected from, for example, indium, vanadium, niobium, and lead, more specifically from, for example, indium, vanadium, and lead, and even more specifically from lead. Layers of these materials can be grown at low temperatures, for example, temperatures below 0 °C. The use of low temperatures may be preferred when aluminum is used as the first superconducting material. Thin layers of aluminum tend to become discontinuous when exposed to excessive heat.

[0049] Lead may be particularly preferred for some applications. Lead has a superconducting gap that is approximately six times larger than that of aluminum. The large superconducting gap may be useful in the context of devices for topological quantum computing because it can increase the energy gap between computationally useful Majorana zero modes and higher energy states. It is desirable to avoid the transfer of electrons from Majorana zero modes to higher energy states because this can result in information loss.

[0050] In block 103, a portion of the layer of the second superconducting material is etched to expose a portion of the first superconducting material. This may include lithography using a mask. Workpieces obtained at various stages of the lithography process are schematically shown in FIGS. 2C - 2E.

[0051] A layer 26 of resist can be applied to the layer 24 of the second superconducting material to provide the workpiece shown in FIG. 2C.

[0052] An exemplary technique for applying the layer of resist is spin coating.

[0053] A portion of the layer 26 of resist is selectively exposed. Due to the exposure, the material of the exposed portion in the resist undergoes a reaction that changes the solubility of the resist in the developer. The nature of the exposure is appropriately selected based on the nature of the resist.

[0054] The portion of the resist layer to be exposed is selected based on the desired device structure and further on the properties of the resist. The resist may be a positive resist. A positive resist becomes more soluble in the developer when exposed. Alternatively, the resist may be a negative resist. A negative resist becomes less soluble in the developer when exposed.

[0055] The resist 26 is developed, for example, by bringing the resist into contact with a suitable solvent. This forms a mask that exposes a portion of the second superconducting material, as shown in FIG. 2d.

[0056] The exposed portion of the metal component is etched to form a structure as in FIG. 2e. The reagent and conditions used for etching are selected such that the second superconducting material is selectively removed without removing the first superconducting material.

[0057] In block 104, the exposed portion of the first superconducting material 22 is oxidized to form a passivation layer 28 on the semiconductor component 20, as shown in FIG. 2f.

[0058] The oxidation may be the result of exposing the first semiconductor material to an etchant. Thus, the etching and oxidation may be performed as a single process step.

[0059] Alternatively, the oxidation may be the result of exposing the first semiconductor material to oxygen, for example oxygen in air.

[0060] After oxidation, the remaining resist 26 can be stripped, for example, by immersing the workpiece in a suitable solvent.

[0061] Next, referring to FIG. 2g, an example of a semiconductor-superconductor hybrid device will be described.

[0062] The semiconductor / superconductor hybrid device shown in Fig. 2g includes a semiconductor component 20, a first superconductor component 22 on a first portion of the semiconductor component 20, a passivation layer 28 on a second portion of the semiconductor component 20, and a second superconductor component 24 on the first superconductor component 22. The first and second superconductor components each include a first and a second superconductor material, respectively. The first and second superconductor materials are different from each other. The passivation layer includes an oxide of the first superconductor material.

[0063] The first superconductor component 22 couples the second superconductor component 24 to the semiconductor component 20. The passivation layer 28 covers a portion of the semiconductor component 20 where no superconductor component is provided. This protects the semiconductor component 20 from its environment. Oxygen from the atmosphere and certain reagents used during manufacturing could otherwise degrade the semiconductor component 20.

[0064] Since the passivation layer 28 includes an oxide rather than a metal, an electrostatic field may be applied to the semiconductor component 20 through the passivation layer 28 when the device is in use.

[0065] Fig. 2g is a simplified schematic diagram of the device. Examples of semiconductor / superconductor hybrid devices include Josephson junctions and devices capable of generating Majorana zero modes.

[0066] Next, referring to Fig. 3, an exemplary method for etching a workpiece including a lead component will be described.

[0067] In block 301, a mask is formed on the lead component. The mask exposes a portion of the lead component.

[0068] Forming a mask typically involves applying a resist to a workpiece, selectively exposing the resist, and developing the resist. Such a process has been discussed above with reference to FIG. 2.

[0069] In block 302, the exposed portions of the lead components are contacted with an etchant composition. The etching composition includes a solution of acetic acid in propan-2-ol. Propan-2-ol is sometimes also called isopropyl alcohol (IPA).

[0070] The amount of acetic acid present in the etchant composition may be in the range of 5% to 20% by volume, optionally 10% to 20%, 14% to 18%, 15% to 17% based on the total volume of the etchant composition, or may be about 16%.

[0071] When propan-2-ol is included in the etchant composition, it has been found that damage to the mask can be prevented. In particular, improvements have been observed for poly(methacrylic acid) masks.

[0072] II. Exemplary Embodiments Indium arsenide nanowires were grown on a chip using the vapour-liquid-solid (VLS) technique. The indium arsenide was coated with a layer of aluminium having a thickness of about 1 nm by epitaxial growth. Then, a layer of lead grew epitaxially on the aluminium layer. FIG. 4 shows a scanning electron microscope (SEM) micrograph of the nanowires.

[0073] The chip is spin-coated with an electron beam lithography (ELB) resist. Exemplary resists include poly(methyl methacrylate) and methylmethacrylate.

[0074] The selected area of the resist was exposed to an electron beam. The resist was developed chemically, forming small structures in the resist and exposing the selected area of the lead.

[0075] The exposed lead was etched using an etchant selective to aluminum. All of the lead not covered by the resist was removed, exposing the aluminum layer within these areas. A solution containing approximately 16% acetic acid by volume in propan - 2 - ol is particularly useful for this process. Such a solution may not attack the EBL resist.

[0076] The exposed aluminum was oxidized to form Al 2 O 3 This oxidation can occur by reaction with the etchant and / or by contact with oxygen in the atmosphere.

[0077] The resist was then stripped using a solvent.

[0078] It will be understood that the above embodiments are merely illustrative by way of example.

[0079] More generally, according to one aspect disclosed herein, a method of manufacturing a semiconductor - superconductor hybrid device is provided, the method comprising: providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; oxidizing the exposed portion of the first superconductor material to form a passivation layer on the semiconductor; It includes. By including a layer of the first superconducting material, the layer of the second superconducting material can be sufficiently bonded to the semiconductor component. The first superconducting material protects the semiconductor component during etching and enables the formation of a passivation layer. The passivation layer protects the semiconductor component while at the same time enabling an electrostatic field to be effectively applied to the semiconductor component. The semiconductor can have improved electron transport properties because it is protected from etchants and atmospheric corrosion by the passivation layer.

[0080] The step of providing the workpiece is to form a layer of the first superconducting material by epitaxial growth on the semiconductor component and to form a layer of the second superconducting material by epitaxial growth on the layer of the first superconducting material, and the second superconducting material may include being different from the first superconducting material. Such steps may be performed in advance from the remaining steps of the method.

[0081] The first superconducting material may be aluminum. Aluminum has good compatibility with various semiconductor materials, especially those of Formula 1.

[0082] In one variation, the first semiconductor material may be indium.

[0083] The layer of the first superconducting material may have a thickness selected to enable the formation of a passivation layer. The thickness may be selected such that the exposed portion of the first superconducting material is substantially completely oxidized.

[0084] In the example where the first semiconductor material is aluminum, the thickness of the layer of the first superconducting material is typically 4 nm or less, and optionally 3 nm or less. An aluminum layer having a thickness within these ranges can be completely oxidized, for example, when exposed to air.

[0085] The aluminum layer typically has a thickness of 2 nm or more. In principle, layers with smaller thicknesses can be used, but with a 2 nm thick layer, complete oxidation has already been achieved, and it may be difficult to manufacture a continuous layer with a thickness less than 2 nm.

[0086] In an example where the first semiconductor material is indium, the layer of the first superconducting material may have a thickness of 10 nm or less, or 8 nm or less. Indium layers with thicknesses in these ranges can, for example, completely oxidize when exposed to air.

[0087] The properties of the second superconducting material are not particularly limited, provided that the layer of this material can be manufactured on the layer of the first superconducting material without disrupting the structure of the layer of the first superconducting material. Typically, the second superconducting material is selected to have a superconducting gap larger than that of aluminum.

[0088] Examples of materials useful as the second superconducting material include materials selected from lead, indium, vanadium, niobium, tantalum, tin, and rhenium. These materials can, in particular, grow on aluminum without exposing aluminum to excessive temperatures.

[0089] The second superconducting material may be lead. Lead has a superconducting gap more than six times larger than that of aluminum (C. Kittel (2004) Introduction to Solid State Physics. Wiley. ISBN: 9780471415268).

[0090] The thickness of the layer of the second superconducting material may be appropriately selected depending on the material chosen. For some materials, the layer thickness may affect superconductivity. The thickness is selected such that the material can exhibit superconductivity at the operating temperature of the device.

[0091] In an example where lead is used, the thickness of the lead layer is not particularly limited. A single layer of lead can maintain superconducting properties (Cherkez et al., Phys. Rev. X 4, 011033 (2014)). The resistance to the applied magnetic field effect can increase as the thickness decreases. Providing a lead layer as thin as possible may be preferable in some applications.

[0092] Niobium can be a second superconducting material that is preferable for some applications. Niobium is the superconductor of the strongest element, that is, it has a particularly large superconducting gap.

[0093] Etching is performed using conditions selected such that a part of the second superconducting material is removed to expose a part of the first superconducting material. Partial removal of a part of the first superconducting material, that is, reduction of the thickness, can be tolerated as long as the etching does not expose any part of the semiconductor material and the passivation layer is thick enough to protect the semiconductor component from oxidation. The thickness of the first superconducting layer may be increased to compensate for the partial removal in the etching step.

[0094] In an example where the second superconductor is lead, the etching may include contacting the second superconducting material with an etchant composition containing an acid selected from nitric acid and acetic acid.

[0095] In an example where the acid is acetic acid, the etchant composition may be glacial acetic acid. Alternatively, the etchant composition may include acetic acid and propan-2-ol. This etchant composition has been found to be particularly useful. It has been observed that the attack of the mask used in lithography by the etchant is reduced when propan-2-ol is included in the etchant composition.

[0096] Acetic acid may be present in the etchant composition in an amount in the range of 5% to 20% by volume, for example, 10% to 20%, 14% to 18%, or 15% to 17%, based on the total volume of the etchant composition, or in an amount of about 16%. These concentration ranges are particularly effective in avoiding mask degradation while still providing a good etching rate.

[0097] This etchant composition can be particularly advantageous when used in combination with a resist containing an acrylate polymer. Examples of acrylate polymers include poly(methacrylic acid), poly(acrylic acid), poly(methyl acrylate), and methylmethacrylate-methacrylic acid copolymers.

[0098] In a variation where the second superconducting material contains niobium, the etching may include reactive ion etching using chloride ions. Reactive ion etching using chloride ions selectively removes niobium without removing aluminum.

[0099] The method described herein can be performed at a temperature of 0°C or below. This is particularly applicable when the first superconducting material contains aluminum. It has been found that it is preferable to keep the temperature of aluminum as low as possible during manufacturing. An aluminum layer not coated with another component tends to degrade and become discontinuous when exposed to excessive heat, forming discrete blobs of aluminum. Therefore, controlling the temperature during manufacturing can improve the characteristics of the finished device.

[0100] The method provided herein, prior to etching, forming a layer of resist on the second superconducting material layer, selectively exposing the layer of resist, Developing the resist to form a mask on the layer of the second superconducting material It may further include . In other words, the etching may be a lithography process.

[0101] The resist may be a photoresist. In other words, the etching may include optical lithography. The developer used in optical lithography may damage certain materials, especially aluminum. However, in the method provided herein, the second superconducting component covers the first superconducting component, thereby protecting the first superconducting component from the developer. Therefore, the workpiece used may be compatible with the optical lithography process.

[0102] Optical lithography enables rapid exposure of the resist. Therefore, optical lithography may be preferred for the manufacture of larger devices.

[0103] Alternatively, the resist may be an electron beam resist. In other words, the etching may include electron beam lithography. Electron beam lithography may enable higher resolution than optical lithography.

[0104] Examples of electron beam resists include acrylate polymers such as poly(methacrylic acid), poly(methyl acrylate), and methyl methacrylate-methacrylic acid copolymers.

[0105] The nature of the exposure step and the development step may be appropriately selected depending on the resist chosen. Those skilled in the art will be proficient in the lithography process.

[0106] The method provided herein may further include the step of manufacturing a gate electrode that applies an electrostatic field to a semiconductor component. Electrostatic gate control is useful for various types of semiconductor-superconductor hybrid devices. Since the passivation layer obtained using the method described herein contains an oxide, the semiconductor component of the device can be electrostatically gate-controlled through the passivation layer.

[0107] Another aspect provides a semiconductor-superconductor hybrid device, the device comprising a semiconductor component, and a first superconductor component on a first portion of the semiconductor component, the first superconductor component comprising a first superconductor material, the first superconductor component; and a second superconductor component on the first superconductor component, the second superconductor component comprising a second superconductor material different from the first superconductor material, the second superconductor component; and a passivation layer on a second portion of the semiconductor component, the passivation layer comprising an oxide of the first superconductor material, the passivation layer; and The layer of the first superconductor material can improve the bonding of the second superconductor material to the semiconductor component. The second superconductor material can have a larger superconducting gap than the first superconductor material. The passivation layer can protect the semiconductor component, for example, from oxidation. As a result, the semiconductor can have improved electron transport characteristics compared to a device without the passivation layer.

[0108] The passivation layer can be obtained by the method described above.

[0109] The first superconductor component and the passivation layer can be integrally formed with each other. In other words, a continuous layer may be disposed on the semiconductor component, the continuous layer including a portion corresponding to the passivation layer and a portion corresponding to the first superconductor component.

[0110] The first superconducting material may be aluminum.

[0111] The second superconducting material may be selected from lead, indium, vanadium, niobium, tantalum, tin, and rhenium. For example, the second superconducting material may be lead.

[0112] The semiconductor component may include a material of Formula 1, for example, indium arsenide.

[0113] The device may further include one or more additional components. The additional component may be provided on a third portion of the semiconductor component with a passivation layer extending over the additional component. Examples of such additional components include ferromagnetic insulator components.

[0114] The semiconductor-superconductor hybrid device may further include a gate electrode for applying an electrostatic field to the semiconductor component.

[0115] Examples of semiconductor-superconductor hybrid devices include Josephson junctions and devices capable of generating Majorana zero modes.

[0116] Yet another aspect provides a method of etching a workpiece including a lead component, the method comprising: forming a mask on the lead component, the mask defining an exposed region of the lead component; contacting the exposed region with an etchant composition; The etchant composition includes acetic acid and propan-2-ol. The etching composition including acetic acid and propan-2-ol may enable etching of lead without developing a resist material. This may enable etching with improved resolution.

[0117] Acetic acid may be present in the etchant composition in an amount of 5% to 20% by volume, such as 10% to 20%, optionally 14% to 18%, further optionally 15% to 17%, or about 16%, based on the total volume of the etchant composition. These concentration ranges are particularly effective in avoiding mask degradation while still providing a good etching rate.

[0118] The mask may include an acrylate polymer. Examples of acrylate polymers include poly(methacrylic acid), poly(acrylic acid), poly(methyl acrylate), and methyl methacrylate-methacrylic acid copolymers.

[0119] The workpiece may further include an aluminum component. In such an example, the method may further include contacting the aluminum component with the etchant composition to oxidize the aluminum component. The aluminum component may be configured to be completely oxidized. For example, the aluminum component may have a thickness of 4 nm or less.

[0120] The workpiece may further include a semiconductor component. The semiconductor component may be disposed under the aluminum component, whereby the aluminum component protects the semiconductor component from the etchant composition.

[0121] Related aspects provide for the use of propan-2-ol in an etchant composition to prevent degradation of a mask by the etchant composition, the etchant composition including acetic acid.

[0122] Acetic acid may be present in the etchant composition in an amount of 5% to 20% by volume, optionally 10% to 20%, optionally 14 to 18%, further optionally 15 to 17%, or about 16%, based on the total volume of the etchant composition. These concentration ranges are particularly effective in avoiding mask degradation while still providing a good etching rate

[0123] The mask may include an acrylate polymer. Examples of acrylate polymers include poly(methacrylic acid), poly(acrylic acid), poly(methyl acrylate), and methyl methacrylate-methacrylic acid copolymers.

[0124] Yet a further aspect provides a kit comprising an etchant composition and a composition for forming a lithography mask, wherein the etchant composition comprises acetic acid and propan-2-ol. The acetic acid may be present in the etchant composition in an amount of 10 to 20% by volume. The composition for forming a lithography resist may be for forming a photoresist or for forming an electron beam resist.

[0125] The composition for forming a lithography mask may include a composition for forming a layer of acrylate polymer on a workpiece. Examples of acrylate polymers include poly(methacrylic acid), poly(acrylic acid), poly(methyl acrylate), and methyl methacrylate-methacrylic acid copolymers.

[0126] The following articles are provided herein. [Article 1] A method of manufacturing a semiconductor / superconductor hybrid device, comprising the step of providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, wherein the second superconductor material is different from the first superconductor material, the step of etching the layer of the second superconductor material to expose a portion of the first superconductor material, and the step of oxidizing the portion of the first superconductor material to form a passivation layer on the semiconductor. A method comprising the above steps. [Article 2] The method according to Article 1, wherein the first superconductor material is aluminum. [Article 3] The method according to item 1 or item 2, wherein the layer of the first superconducting material has a thickness of 3 nm or less. [Item 4] The method according to item 3, wherein the second superconducting material is selected from lead, indium, vanadium, tantalum, tin, rhenium, and niobium. [Item 5] The method according to item 4, wherein the second superconducting material is lead. [Item 6] The method according to item 5, wherein the etching includes bringing the second superconducting material into contact with an etchant composition containing an acid selected from nitric acid and acetic acid. [Item 7] The method according to item 6, wherein the acid is acetic acid, the etchant composition further contains propan-2-ol, and the concentration of the acetic acid in the etchant composition is 5% to 20% by volume. [Item 8] The method according to item 4, wherein the second superconducting material is niobium, and the etching includes reactive ion etching using chloride ions. [Item 9] The method according to any one of items 1 to 8, which is performed at a temperature of 0 °C or lower. [Item 10] Before the etching, forming a resist layer on the layer of the second superconducting material; selectively exposing the resist layer; developing the resist to form a mask on the layer of the second superconducting material; The method according to any one of items 1 to 9, further including the above steps. [Item 11] The method according to any one of items 1 to 10, further including manufacturing a gate electrode for applying an electrostatic field to the semiconductor component. [Item 12] A semiconductor-superconductor hybrid device, a semiconductor component, and A first superconducting component extending over a first portion of the semiconductor component, the first superconducting component including a first superconducting material, the first superconducting component and, A second superconducting component on the first superconducting component, the second superconducting component including a second superconducting material different from the first superconducting material, the second superconducting component and, A passivation layer extending over a second portion of the semiconductor component, the passivation layer including an oxide of the first superconducting material, the passivation layer and, A semiconductor-superconductor hybrid device including. [Article 13] The semiconductor-superconductor hybrid device according to Article 12, wherein the first superconducting material is aluminum. [Article 14] The semiconductor-superconductor hybrid device according to Article 12 or Article 13, wherein the second superconducting material is selected from lead, indium, vanadium, tantalum, tin, rhenium, and niobium. [Article 15] Further including a further component on the semiconductor component, wherein the first superconducting component and the passivation layer are disposed on the further component, the semiconductor-superconductor hybrid device according to any one of Articles 12 to 14. [Article 16] The semiconductor-superconductor hybrid device according to any one of Articles 12 to 15, further including a gate electrode for applying an electrostatic field to the semiconductor component. [Article 17] A method of etching a workpiece including a lead component, Forming a mask on the lead component, the mask defining an exposed area of the lead component, the step and, Contacting the exposed area with an etchant composition, including the step and, The method, wherein the etchant composition includes acetic acid and propan-2-ol. [Item 18] The acetic acid is present in the etchant composition in an amount within the range of 10 to 20% by volume, the method according to Item 17. [Item 19] The workpiece further includes an aluminum component, and the method further includes the step of contacting the aluminum component with the etchant composition to oxidize the aluminum component, the method according to Item 17 or Item 18. [Item 20] The workpiece further includes a semiconductor component, and the semiconductor component is disposed under the aluminum component, whereby the aluminum component protects the semiconductor component from the etchant composition, the method according to Item 19.

[0127] Other variations or uses of the disclosed techniques may become apparent to those skilled in the art upon giving the disclosure herein. The scope of the present disclosure is not limited by the described embodiments, but is limited only by the appended claims.

Claims

1. 1. A method for etching a workpiece including a lead component, comprising: forming a mask on the lead component, the mask defining an exposed area of ​​the lead component; contacting the exposed area with an etchant composition; Including, The etchant composition comprises acetic acid and propan-2-ol; method.

2. The method of claim 1 , wherein the acetic acid is present in the etchant composition in an amount in the range of 10-20% by volume.

3. 3. The method of claim 1 or 2, wherein the workpiece further comprises an aluminum component, the method further comprising contacting the aluminum component with the etchant composition to oxidize the aluminum component.

4. 4. The method of claim 3, wherein the workpiece further comprises a semiconductor component, the semiconductor component being disposed below the aluminum component, whereby the aluminum component protects the semiconductor component from the etchant composition.

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