Semiconductor package structure with hybrid core structure and method for manufacturing the same

Abstract

To provide a semiconductor package structure with a hybrid core structure, and methods for manufacturing the same.SOLUTION: In a package substrate and a method of fabrication thereof including a hybrid substrate core having different material properties in different portions of the core, a first portion of the hybrid substrate core has a lower coefficient of thermal expansion (CTE) than a second portion of the hybrid substrate core. The CTE of the first portion of the hybrid substrate core is close to the CTE of semiconductor integrated circuit dies mounted on a first side of the package substrate in an assembled semiconductor package. The CTE of the second portion of the hybrid substrate core is close to the CTE of a supporting substrate, such as a printed circuit board, on which the semiconductor package is mounted. The package substrate helps to balance stress, such as thermally-induced stress, in the semiconductor package, thereby improving package reliability.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor package structure having a hybrid core structure and a method for manufacturing the same, and more particularly, to a package substrate having a hybrid substrate core having different material characteristics at different positions of the core and a method for manufacturing the same.

Background Art

[0002] Semiconductor devices are used in various electronic devices. Some examples include personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically formed by successively depositing an insulating layer, or a dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically formed on a single semiconductor wafer, and each die on the wafer is singulated by cutting between the integrated circuits along a scribe line. The individual dies are usually packaged separately, for example, in multi-chip modules or other types of packaging.

[0003] As semiconductor packages become larger and more complex by integrating a large number of semiconductor IC dies, ensuring the mechanical integrity of the semiconductor package is becoming increasingly important. In many semiconductor packages, stresses, including thermally-induced stresses, increase the failure rate and reduce the reliability of the semiconductor package.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention provides a package substrate having a hybrid substrate core with different material properties at different positions of the core, and a method for manufacturing the same, and aims to solve the above problems.

Means for Solving the Problems

[0005] In some embodiments, a substrate of a semiconductor package is provided. The substrate of the semiconductor package has a first surface, a substrate core having a second substrate opposite to the first surface, a plurality of conductive vias extending in the substrate core between the first surface and the second surface of the substrate core, a first redistribution layer on the first surface of the substrate core, and a second redistribution layer on the second surface of the substrate core. The substrate core has a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first portion has a coefficient of thermal expansion (CTE) less than 10 ppm / °C, and the second portion has a CTE of 10 ppm / °C to 30 ppm / °C.

[0006] In some embodiments, a semiconductor package is provided. The semiconductor package has a semiconductor package structure, a package substrate, and a support substrate. The semiconductor package structure has one or more semiconductor IC dies. The package substrate has a first side, a second side opposite to the first side, and an electrical interconnection structure extending between the first side and the second side. The package substrate has a hybrid substrate core having a first portion closest to the first side of the package substrate and a second portion closest to the second side of the package substrate. The semiconductor package structure is mounted on the first side of the package substrate. The second side of the package substrate is mounted on the support substrate. The first portion of the hybrid substrate core of the package substrate has a CTE within 5 ppm / °C of the coefficient of thermal expansion (CTE) of the semiconductor IC die of the semiconductor package structure. The second portion of the hybrid substrate core of the package substrate has a CTE within 10 ppm / °C of the CTE of the support substrate.

[0007] In some embodiments, a method of manufacturing a package substrate is provided. First, a hybrid substrate core is formed having a first portion adjacent to a first surface of the hybrid substrate core and a second portion adjacent to a second surface of the hybrid substrate core. The first portion of the hybrid substrate core has a coefficient of thermal expansion (CTE) of less than 10 ppm / °C. The second portion of the hybrid substrate core has a CTE between 10 ppm / °C and 30 ppm / °C. Next, a plurality of conductive vias are formed through the hybrid substrate core between the first surface and the second surface of the hybrid substrate core. Further, a first redistribution layer is formed on the first surface of the hybrid substrate core. Finally, a second redistribution layer is formed on the second surface of the hybrid substrate core.

Advantages of the Invention

[0008] A package substrate having a hybrid substrate core with different material properties at different positions of the core helps to maintain stress equilibrium between the package substrate, a package structure having one or more semiconductor IC dies coupled to a first side of the package substrate, and a support substrate coupled to a second side of the package substrate. This improves the reliability of the semiconductor package and reduces the failure rate.

Brief Description of the Drawings

[0009] As will be better understood with reference to the following detailed description when considered in conjunction with the accompanying drawings, aspects of the present invention will be better understood. It should be noted that, in relation to standard industry techniques, various features are not drawn to scale. In fact, the dimensions of the various features are arbitrarily increased or decreased for clarity of discussion.

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Embodiments for Carrying Out the Invention

[0020] The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. The elements and arrangements of specific examples are described below to simplify the present invention. These are of course merely examples and are not intended to be limiting. For example, when it is described that the first feature is formed on or above the second feature, this includes embodiments in which the first and second features are formed in contact, and also includes embodiments in which additional features are formed between the first and second features and the first and second features do not directly contact. Different embodiments disclosed below reuse the same reference numerals and / or symbols. These duplications are for the purpose of being concise and clear and are not intended to limit the specific relationships between various embodiments and / or the structures disclosed below.

[0021] Furthermore, spatial relative terms, such as "below", "beneath", "lower", "above", "on top", "higher", etc., are used for ease of description to depict the relationship between one element or feature in the drawing and another element or feature. Spatial relative terms include different orientations during use and operation and the orientations shown in the drawing. As the device rotates to different orientations (a 90-degree rotation or other orientations), the spatial correlative adjectives used here are similarly interpreted accordingly. Unless specifically stated otherwise, it is presumed that each element having the same reference numeral has the same material composition and a thickness within the same thickness range.

[0022] The various embodiments disclosed herein are directed to semiconductor devices, particularly substrates of semiconductor packages having hybrid substrate cores with different material properties at different positions of a substrate core, and methods for manufacturing them.

[0023] Typically, in a semiconductor package, multiple semiconductor integrated circuit (IC) dies (i.e., “chips”) are mounted on a common substrate, also referred to as a “package substrate”. In certain packages, such as a fan-out wafer level package (FOWLP) and / or a fan-out panel level package (FOPLP), the multiple semiconductor IC dies are mounted on an interposer, such as an organic interposer or a semiconductor (e.g., silicon) interposer, having interconnect structures that extend therethrough. The package structure having the interposer and the semiconductor IC dies mounted thereon is then mounted on the package substrate surface using solder joints to form a semiconductor package. The semiconductor package having the package substrate and the package structure mounted thereon is then mounted on a support substrate, such as a printed circuit board (PCB).

[0024] As semiconductor packages become larger and more complex by integrating a large number of semiconductor IC dies, ensuring the mechanical stability of the semiconductor package is becoming increasingly important. In many semiconductor packages, stresses, including thermally induced stresses, increase the failure rate of the semiconductor package and reduce reliability.

[0025] The various embodiments disclosed herein include a package substrate and a method of manufacturing a package substrate having a hybrid substrate core. The hybrid substrate core has a plurality of portions (e.g., sub-layers) of substrates having different material properties. In various embodiments, the hybrid substrate core has a first portion closest to the semiconductor package structure and a second portion closest to a support substrate (e.g., a PCB) within an assembled semiconductor package. The first portion of the hybrid substrate core is also referred to as the "chip side" portion of the hybrid substrate core, and the second portion of the hybrid substrate core is also referred to as the "board side" portion of the hybrid substrate core. The first portion of the hybrid substrate core has a lower coefficient of thermal expansion (CTE) than the CTE of the second portion of the hybrid substrate core. In various embodiments, the CTE of the first portion of the hybrid substrate core is relatively close to the CTE of the semiconductor IC die of the package structure (e.g., in the range of 0 to 5 ppm / °C), and the CTE of the second portion of the hybrid substrate core is relatively close to the CTE of the support substrate (e.g., a PCB) (e.g., in the range of 0 to 10 ppm / °C). In some embodiments, the first portion of the hybrid substrate core has a higher Young's modulus than the second portion of the hybrid substrate core. In some embodiments, the hybrid substrate core further has a third portion (also referred to as the "buffer portion") located between the first and second portions of the hybrid substrate core. The third portion has a CTE greater than the CTE of the first portion of the hybrid substrate core and less than the CTE of the second portion of the hybrid substrate core.

[0026] A package substrate according to various embodiments includes the hybrid substrate core described above, a plurality of conductive interconnect structures (e.g., metal vias) extending over the hybrid substrate core between a first surface and a second surface of the hybrid substrate core, first and second redistribution layers having conductive interconnect structures incorporated within a dielectric material matrix located on each of the first and second surfaces of the hybrid substrate core, and optional first and second external coating layers located on each of the first and second redistribution layers.

[0027] A package substrate having a hybrid substrate core with different material properties at different positions of the core helps maintain stress equilibrium between the package substrate, one or more semiconductor IC dies coupled to a first side of the package substrate, and a package structure having a support substrate coupled to a second side of the package substrate. This improves the reliability of the semiconductor package and reduces the failure rate.

[0028] Figures 1 to 5 are sequential cross-sectional views of exemplary intermediate structures formed during the manufacturing process of a package substrate according to various embodiments of the present invention. Referring to Figure 1, a hybrid substrate core 101 is described having a first portion 102 adjacent to a first surface 105 of the hybrid substrate core 101 and a second portion 104 adjacent to a second surface 106 of the hybrid substrate core 101. Any third portion 103 of the hybrid substrate core 101 is located between the first portion 102 and the second portion 104. The first portion 102, the second portion 104, and any third portion 103 each have a thin sheet of structural material joined together using a suitable adhesive, such as an adhesive film, to form the hybrid substrate core 101. In some embodiments, the first portion 102, the second portion 104, and any third portion 103 are joined together using a partially cured epoxy resin, such as a B-stage material. The B-stage material has one or more (i.e., plies) of prepreg material, the prepreg material having glass fibers impregnated with resin or a cloth material, and the resin being partially dried by heat and / or ultraviolet radiation. In various embodiments, the first portion 102, the second portion 104, and any third portion 103 are each stacked with one or more B-stage prepreg materials located between the first portion 102, the second portion 104, and the third portion 103, and are subjected to a press lamination process and a final cure to form the hybrid substrate core 101. In some embodiments, during the press lamination process, copper foil layers are provided on the upper and lower surfaces of the stack to provide a hybrid substrate core 101 having copper material layers on the first surface 105 and the second surface 106 of the hybrid substrate core 101. Thus, in the embodiment shown in Figure 1, the first portion 102, the second portion 104, and the third portion 103 each form a first sublayer 102, a second sublayer 104, and a third sublayer 103 of the hybrid substrate core 101 of the joined laminate structure.It is understood that another arrangement for use in the hybrid substrate core 101 is within the expected scope of the present invention, and the hybrid substrate core 101 includes embodiments formed as a single structure having a first portion 102 adjacent to the first surface 105, a second portion 104 adjacent to the second surface 106, and any third portion 103 between the first portion 102 and the second portion 104.

[0029] In some embodiments, the first portion 102, the second portion 104, and any third portion 103 of the hybrid substrate core 101 are each composed of a sheet of laminate reinforced resin. The laminate reinforced resin sheet has a reinforcing material (e.g., glass fiber or cloth) impregnated with a resin system, such as an epoxy-based resin system, and cures under heat and pressure to form a sheet of laminate reinforced resin. Other suitable materials and structures for use in the first portion 102, the second portion 104, and any third portion 103 of the hybrid substrate core 101 are within the scope of the present invention. In various embodiments, the first portion 102 of the hybrid substrate core 101 has a thickness T in the range of about 0.2 mm to about 0.6 mm 1 although thicker or thinner dimensions may be used. In various embodiments, the second portion 104 of the hybrid substrate core 101 has a thickness T in the range of about 0.2 mm to about 0.6 mm 2 although thicker or thinner dimensions may be used. Any third portion 103 of the hybrid substrate core 101 has a thickness T in the range of about 0.01 mm to about 0.2 mm 3 although thicker or thinner dimensions may be used. The hybrid substrate core 101 has a total thickness T in the range of about 0.4 mm to about 1.0 mm c although thicker or thinner dimensions may be used.

[0030] In various embodiments, in embodiments where the first portion 102, the second portion 104, and the third portion 103 of the hybrid substrate core 101 are present, they have different material properties, for example, different coefficients of thermal expansion (CTEs), and / or different elastic forces (i.e., Young's moduli) of different modules. In various embodiments, the first portion 102 of the hybrid substrate core 101 has a CTE smaller than the CTE of the second portion 104 of the hybrid substrate core 101. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a CTE of less than 10 ppm / °C at a temperature lower than its glass transition temperature (T g ), for example, from about 0.1 ppm / °C to about 6 ppm / °C. In some embodiments, when the second portion 104 of the hybrid substrate core 101 is at a temperature lower than its glass transition temperature (T g ), it has a CTE of 10 ppm / °C or more, for example, between 10 ppm / °C and about 30 ppm / °C. In various embodiments, when the third portion 103 is present, the CTE of the third portion 103 of the hybrid substrate core 101 has a CTE between the CTEs of the first portion 102 and the second portion 102 of the hybrid substrate core 101.

[0031] In various embodiments, the first portion 102 of the hybrid substrate core 101 has a Young's modulus higher than the Young's modulus of the second portion 104 of the hybrid substrate core 101. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a Young's modulus between about 30 GPa and about 50 GPa at room temperature (e.g., ~20°C). The second portion 104 of the hybrid substrate core 101 has a Young's modulus between about 10 GPa and about 40 GPa at room temperature. In embodiments where the third portion 103 of the hybrid substrate core 101 is present, the third portion 103 has a Young's modulus between about 1 GPa and about 50 GPa at room temperature.

[0032] When the package substrate is incorporated into a semiconductor package, the difference in material properties between the first portion 102 and the second portion 104 of the hybrid substrate core 101 helps to maintain the balance of the effects of stresses, such as thermally induced stresses. The first portion 102 of the hybrid substrate core 101 is closest to the semiconductor package structure having one or more semiconductor IC dies in the assembled semiconductor package. Thus, the even lower CTE of the first portion 102 of the hybrid substrate core 101 more closely matches the relatively low CTE of the components of the semiconductor package structure having one or more semiconductor IC dies. The relatively high Young's modulus of the first portion 102 of the hybrid substrate core 101 provides high resistance to mechanical strain and helps to maintain the structural integrity of the bond between the package substrate and the semiconductor package structure.

[0033] In addition, the relatively high CTE of the second portion 104 of the hybrid substrate core 101 more closely matches the CTE of the support substrate of the assembled semiconductor package, such as a printed circuit board (PCB), and typically has a higher CTE than the components of the semiconductor package structure having semiconductor IC dies. The relatively low Young's modulus of the second portion 104 of the hybrid substrate core 101 provides a "cushioning" effect and helps to reduce the stresses resulting from the CTE mismatch between the semiconductor package structure bonded to the first side of the package substrate and the support substrate (such as a PCB) bonded to the second side of the package substrate. In embodiments where any third portion 103 of the hybrid substrate core 101 is present, the third portion 103 acts as a "buffer" between the first portion 102 and the second portion 104 of the hybrid substrate core 101.

[0034] The different material properties of the first portion 102, the second portion 104, and any optional third portion 103 of the hybrid substrate core 101 are obtained by varying different process parameters and / or the materials used to form the first portion 102, the second portion 104, and any optional third portion 103 of the hybrid substrate core 101. In the case of a laminated reinforced resin material, for example, such variations include, but are not limited to, changes in the composition of the reinforcing material (such as the type of reinforcing material used, e.g., E-glass, S-Glass, LowDk-glass, silica, quartz, aramid, etc.), changes in the physical properties of the reinforcing material (such as the use of a woven or non-woven fiber reinforcing material, the weave of the woven fiber reinforcing material, the diameter, length, and / or alignment of the fiber reinforcing material, etc.), changes in the composition of the resin system used, changes in the curing process, and changes in the relative concentration of the reinforcing material and the resin in the laminated reinforced resin product. A plurality of commercially available products are suitable for use in various embodiments of the present invention. For example, in recent years, a plurality of substrate core materials characterized by low or ultra-low CTE and high Young's modulus have been on the market and are suitable for use as the first portion 102 of the hybrid substrate core 101. Examples of suitable products for the first portion 102 of the hybrid substrate core 101 include, but are not limited to, the MCL-E-705G series and MCL-E-795G series of Showa Denko Materials Co., Ltd., the HL832NSA (LCA) of Mitsubishi Chemical Corp., and the R-1515V of Panasonic Holdings Corp. Other suitable materials for use as the first portion 102 of the hybrid substrate core 101 are within the expected scope of the present invention. Examples of suitable materials for use as the second portion 104 of the hybrid substrate core 101 include, for example, the MCL-HE-679G (Type S) of Showa Denko Materials and the HL832NX of Mitsubishi Chemical. Other suitable materials for use as the second portion 104 of the hybrid substrate core 101 are within the expected scope of the present invention.The material of any third portion 103 of the hybrid substrate core 101 is selected such that the CTE of the any third portion 103 is between the CTEs of the first portion 102 and the second portion 104 of the hybrid substrate core 101.

[0035] FIG. 2 is a cross-sectional view of an exemplary intermediate structure during a manufacturing process of a package substrate illustrating a plurality of conductive vias 107 extending through a hybrid substrate core 101 according to various embodiments of the present invention. Referring to FIG. 2, a plurality of through-holes are formed through the hybrid substrate core 101, extending between a first surface 105 and a second surface 106 of the hybrid substrate core 101. In the embodiment of FIG. 2, after the first portion 102, the second portion 104, and the third portion 103 are joined together, the plurality of through-holes are formed through the first portion 102, the second portion 104, and the third portion 103 of the hybrid substrate core 101. In other embodiments, the through-holes are formed through one or more of the first portion 102, the second portion 104, and the third portion 103 before they are joined together to form the hybrid substrate core 101. The through-holes are formed by a photolithography pattern mask using any suitable process, such as a mechanical drill, a laser drill, or an etching process. Other suitable processes for forming the through-holes are within the contemplated scope of the present invention.

[0036] Referring again to FIG. 2, since a plurality of conductive vias 107 are formed in each through hole, the conductive vias 107 extend between the first surface 105 and the second surface 106 of the hybrid substrate core 101. The conductive vias 107 are formed of a suitable conductive material, such as Cu, Ni, W, Al, Co, Mo, Ru, etc., and combinations or alloys thereof. Other suitable materials used for the conductive vias 107 are within the expected scope of the present invention. The plurality of conductive vias 107 are formed using a suitable deposition process, such as an electrochemical deposition process (e.g., electroplating). Other suitable deposition processes are within the expected scope of the present invention. In the embodiment shown in FIG. 2, after the first portion 102, the second portion 104, and the third portion 103 are joined together to form the hybrid substrate core 101, the plurality of conductive vias 107 are formed. Alternatively, the conductive vias may be formed through the first portion 102, the second portion 104, and the third portion 103 of one or more hybrid substrate cores 101 such that when the first portion 102, the second portion 104, and the third portion 103 are joined together, the plurality of conductive vias 107 extend continuously through the first portion 102, the second portion 104, and the third portion 103 between the first surface 105 and the second surface 106 of the hybrid substrate core 101 before they are joined together.

[0037] FIG. 3 is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating a first redistribution layer 110a formed on the first surface 105 of a hybrid substrate core 101 according to various embodiments of the present invention. The first redistribution layer 110a has a plurality of conductive interconnect structures 109 (e.g., metal lines 116 and vias 117) incorporated in a dielectric material matrix 108. The conductive interconnect structures 109 contact a plurality of conductive vias 107 that extend into the hybrid substrate core 101.

[0038] In some embodiments, the first redistribution layer 110a is formed by providing a first layer of conductive material (e.g., a copper-clad laminate) on the first surface 105 of the hybrid substrate core 101 using a suitable deposition process, such as an electroplating process. In some embodiments, the first layer of conductive material on the first surface 105 of the hybrid substrate core 101 is formed in whole or in part by the above-described press lamination process used to form the hybrid substrate core 101. The first layer of conductive material is patterned by an etching process implemented by a photolithography pattern mask to form a plurality of first metal lines 116 (e.g., copper traces) on the first surface 105 of the hybrid substrate core 101. Thereafter, a first layer of dielectric material 108 is formed on the plurality of first metal lines 116. The first layer of dielectric material 108 has a polymer-based dielectric material, such as Ajinomoto's Build-up Film (ABF) (registered trademark). Other suitable dielectric materials are within the contemplated scope of the present invention. In some embodiments, the first layer of dielectric material 108 is applied as a film on the first surface 105 of the hybrid substrate core 101. The film is vacuum laminated on the first surface 105 of the hybrid substrate core 101 and is partially cured (e.g., by a high-temperature compression process). A plurality of through-holes are formed through the first layer of dielectric material 108 using a suitable process, such as a mechanical drill, a laser drill, and / or an etching process. The metal lines 116 and / or the conductive vias 107 are exposed at the bottom of each through-hole.

[0039] A metallization process is used to form a plurality of first vias 117 in the through-holes through the first layer of the dielectric material 108. The plurality of first vias 117 are formed using a suitable deposition process, such as electroplating. The deposition process further forms a second layer of conductive material on the first layer of the dielectric material 108. Alternatively, a separate deposition process is used to form the second layer of conductive material on the first layer of the dielectric material 108. The second layer of conductive material is patterned by an etching process performed by a photolithographic pattern mask to form a plurality of second metal lines 116 (e.g., copper traces) on the surface of the first layer of the dielectric material 108. As described above, the second layer of the dielectric material 108 is formed on the plurality of second metal lines 116, and a plurality of through-holes are formed through the second layer of the dielectric material 108. An additional metallization process is used to form a plurality of second vias 117 in the through-holes formed through the second layer of the dielectric material 108. These processes are optionally repeated multiple times to form a first redistribution layer 110a having a plurality of conductive interconnect structures 109 (e.g., metal lines 116 and vias 117) incorporated into the dielectric matrix 108. The layers of the dielectric material 108 are optionally subjected to a curing process at an elevated temperature (e.g., 170 - 200 °C) to form a solid dielectric material matrix 108 surrounding the conductive interconnect structures 109. A plurality of first bonding pads 112 are formed on the uppermost layer of the dielectric material 108.

[0040] FIG. 4 is a cross-sectional view of an exemplary intermediate structure during the manufacturing process of a package substrate illustrating a second redistribution layer 110b formed on a second surface 106 of a hybrid substrate core 101 according to various embodiments of the present invention. Referring to FIG. 4, the second redistribution layer 110b on the second surface 106 of the hybrid substrate core 101 has a plurality of conductive interconnect structures 109 (e.g., metal lines 116 and vias 117) incorporated in a dielectric material matrix 108. As described in connection with FIG. 3, the second redistribution layer 110b on the second surface 106 of the hybrid substrate core 101 has a similar or the same structure and is formed using a similar or the same process as the first redistribution layer 110a formed on the first surface 105 of the hybrid substrate core 101. Thus, for the sake of brevity, repeated discussion of similar features is omitted. Further, FIGS. 3 and 4 illustrate an embodiment in which the first redistribution layer 110a is formed on the first surface 105 of the hybrid substrate core 101 before the second redistribution layer 110b is formed on the second surface 106 of the hybrid substrate core 101. It is understood, however, that the second redistribution layer 110b on the second surface 106 of the hybrid substrate core 101 may be formed before the first redistribution layer 110a on the first surface 105 of the hybrid substrate core 101, or that the first redistribution layer 110a and the second redistribution layer 110b (collectively, redistribution layer 110) may be formed simultaneously on the first surface 105 and the second surface 106 of the hybrid substrate core 101.

[0041] Referring again to FIG. 4, a plurality of second bonding pads 113 are formed on the second redistribution layer 110b located on the second surface 106 of the hybrid substrate core 101. In various embodiments, a plurality of first bonding pads 112 are provided to electrically connect a semiconductor package structure having a package substrate and at least one semiconductor IC die, and a plurality of second bonding pads 113 are provided to electrically connect the package substrate and a support substrate, e.g., a PCB.

[0042] FIG. 5 is a cross-sectional view of a package substrate 120 having external coating layers 111 located above and below each redistribution layer 110 according to various embodiments of the present invention. Referring to FIG. 5, the external coating layer 111 of the package substrate 120 has a layer of dielectric material formed on each redistribution layer 110 and defines corresponding first outer surface 114 and second outer surface 115 of the package substrate 120. Each external coating layer 111 provides a protective coating to the package substrate 120, and the underlying bonding pads 112, 113, and conductive interconnect structure 109 in the package substrate 120. The external coating layer 111 further inhibits solder material from adhering to each of the first outer surface 114 and the second outer surface 115 of the package substrate 120 during a subsequent solder reflow process.

[0043] In various embodiments, the external coating layer 111 has a solder resist material. The external coating layer 111 formed of the solder resist material is also referred to as a "solder mask". The solder resist material of the external coating layer 111 has a suitable resin material that is resistant to moisture and high temperature and does not strongly adhere to the solder material. The solder resist material of the external coating layer 111 is formed using a suitable deposition process, such as screen printing, spraying, and / or vacuum lamination. Other suitable deposition processes are within the contemplated scope of the present invention.

[0044] FIG. 6 is a cross-sectional view of a semiconductor package 140 having a package structure 130 mounted above a first side 114 of a package substrate 120 according to various embodiments of the present invention. Referring to FIG. 6, the package structure 130 has one or more semiconductor IC dies 131. In the embodiment shown in FIG. 6, the package structure 130 has two semiconductor IC dies 131, and it is understood that in other embodiments, the package structure 130 may have two or more semiconductor IC dies 131, or a single semiconductor IC die 131. One or more semiconductor IC dies 131 of the package structure 130 have at least one system-on-chip (SoC) die. The SoC die has, for example, an application processor die, a central processing unit die, and / or a graphics processing unit die. In some embodiments, one or more semiconductor IC dies 131 have at least one memory die. The at least one memory die has a high bandwidth memory (HBM) die. In some embodiments, the HBM die has vertically stacked interconnected memory dies. Alternatively, or in addition, the at least one memory die has a dynamic random access memory (DRAM) die. In some embodiments, the package structure 130 has a plurality of semiconductor IC dies 131 that are homogeneous, which means that all the semiconductor IC dies 131 are of the same type (e.g., all SoC dies, all HBM dies, all DRAM dies, etc.). Alternatively, the package structure 130 has a plurality of semiconductor IC dies 131 that are heterogeneous, which means that the plurality of semiconductor IC dies 131 have different types of semiconductor IC dies 131 (e.g., at least one SoC die and at least one memory die).

[0045] In various embodiments, one or more semiconductor IC dies 131 of the package structure 130 are mounted on an interposer 133, such as an organic interposer or a semiconductor (e.g., silicon) interposer. The interposer 133 is mounted on a first outer surface 114 of the package substrate 120 to form the semiconductor package 140. The interposer 133 has a plurality of interconnect structures 134 (e.g., metal lines and vias) in an insulating matrix. The one or more semiconductor IC dies 131 are mounted on the interposer 133 by a plurality of bonding structures 135 having a microbump (e.g., C2) bonding structure. A first underfill material portion 138 is disposed between the one or more semiconductor IC dies 131 and the interposer 133 and surrounds the bonding structures 135. For example, a mold portion 139 having an epoxy molding compound (EMC) laterally surrounds the one or more semiconductor IC dies 131.

[0046] Referring again to FIG. 6, an etching process is used to selectively remove a portion of the external coating layer 111 (e.g., solder mask) from the first side 114 of the package substrate 120 to expose the first bonding pads 112 below the package substrate 120. The pattern of the first bonding pads 112 exposed in the first side 114 of the package substrate 120 corresponds to the pattern of the bonding pads 137 located on the lower surface of the interposer 133. The package structure 130 is aligned on the first side 114 of the package substrate 120, and an array of solder material portions 136 is located between the first bonding pads 112 of the package substrate 120 and the corresponding first bonding pads 137 on the lower surface of the interposer 133. A reflow process is performed to reflow the solder material portions 136, thereby forming a bond between the interposer 133 and the package substrate 120 of the package structure 130. Each solder material portion 136 is bonded to a corresponding one of the first bonding pads 112 of the package substrate 120 and a corresponding one of the first bonding pads 137 on the lower surface of the interposer 133. In some embodiments, the solder material portions 136 comprise C4 solder balls, and the package structure 130 is bonded to the package substrate 120 by an array of C4 solder balls.

[0047] In another embodiment, the interposer 133 is omitted, and one or more semiconductor IC dies 131 are mounted directly on the first side 114 of the package substrate 120, for example, by a plurality of microbump (e.g., C2) bonding structures.

[0048] FIG. 7 is a cross-sectional view of a semiconductor package 140 having a second underfill material portion 141 located between a first side 114 of a package substrate 120 and a lower surface of an interposer 133 according to various embodiments of the present invention. Referring to FIG. 7, the second underfill material portion 141 is applied to a space between the first side 114 of the package substrate 120 and the lower surface of the interposer 133. The second underfill material portion 141 laterally surrounds and contacts each of the solder material portions 136 that join the interposer 133 and the package substrate 120.

[0049] FIG. 8 is a cross-sectional view of a semiconductor package 140 mounted on a support substrate 150 according to various embodiments of the present invention. Referring to FIG. 8, the support substrate 150 is a PCB having an array of bonding pads 153 exposed on the upper surface 151 of the support substrate 150. An etching process is used to selectively remove a portion of the external coating layer 111 (e.g., solder mask) from the second side 115 of the package substrate 120 and expose the lower second bonding pads 113 of the package substrate 120. The pattern of the second bonding pads 113 of the package substrate 120 corresponds to the pattern of the bonding pads 153 on the upper surface 151 of the support substrate 150. The semiconductor package 140 is aligned on the upper surface 151 of the support substrate 150, and an array of solder material portions 154 is positioned between the second bonding pads 113 of the package substrate 120 and the corresponding bonding pads 153 on the upper surface 151 of the support substrate 150. A reflow process is performed to reflow the solder material portions 154, thereby achieving bonding between the package substrate 120 and the support substrate 150 of the semiconductor package 140. Each solder material portion 154 is bonded to a corresponding one of the second bonding pads 113 of the package substrate 120 and a corresponding one of the bonding pads 153 on the upper surface 151 of the support substrate 150. In some embodiments, a third underfill material portion 160 is added to the space between the second side 115 of the package substrate 120 and the upper surface 151 of the support substrate 150. The third underfill material portion 160 surrounds and contacts, in the lateral direction, each solder material portion 154 that bonds the package substrate 120 and the support substrate 150.

[0050] Referring back to FIG. 8, the semiconductor package 140 according to various embodiments has a package structure 130, and the package structure 130 has one or more semiconductor IC dies 131 mounted on the first side 114 of the package substrate 120. The second side 115 of the package substrate 120 is mounted on the upper surface 151 of a support substrate 150, such as a PCB. The package substrate 120 has a hybrid substrate core 101, and the hybrid substrate core 101 has a first portion 102 closest to the first side 114 of the package substrate 120, a second portion 104 closest to the second side 115 of the package substrate 120, and any third portion 103 located between the first portion 102 and the second portion 104. In various embodiments, the first portion 102 of the hybrid substrate core 101 has a CTE within 5 ppm / °C, such as within 3 ppm / °C including within 2 ppm / °C, of the CTE of the semiconductor IC die 131 of the semiconductor package 140. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a CTE within 1 ppm / °C, such as within 0.1 ppm / °C including within 0.5 ppm / °C, of the CTE of the semiconductor IC die 131 of the semiconductor package 140. In some embodiments, the semiconductor package 140 has a plurality of semiconductor IC dies 131, and the first portion 102 of the hybrid substrate core 101 has a CTE within 5 ppm / °C, such as 3 ppm / °C, 2 ppm / °C, 1 ppm / °C, 0.5 ppm / °C, or 0.1 ppm / °C, of the CTE of the semiconductor IC die 131 of each semiconductor package 140. In various embodiments, the second portion 104 of the hybrid substrate core 101 has a CTE within 10 ppm / °C, within 5 ppm / °C, such as within 3 ppm / °C, of the CTE of the support substrate (such as a PCB) on which the package substrate 120 is mounted. The third portion 103 of the hybrid substrate core 101 has a CTE that is between the CTEs of the first portion 102 and the second portion 104 of the hybrid substrate core 101.

[0051] FIG. 9 is a cross-sectional view of a semiconductor package 140 mounted on a support substrate 150 according to another embodiment of the present invention. The semiconductor package 140 shown in FIG. 9 is substantially the same as the semiconductor package 140 described in connection with FIG. 8. Therefore, for the sake of brevity, duplicate discussions of similar features are omitted. The difference between the semiconductor package 140 of FIG. 9 and the semiconductor package 140 of FIG. 8 is that in another embodiment shown in FIG. 9, any third portion 103 of the hybrid substrate core 101 is omitted from the package substrate 120. Thus, in the embodiment shown in FIG. 9, the hybrid substrate core 101 of the package substrate 120 has a first portion 102 closest to the first side 114 of the package substrate 120 and a second portion 104 closest to the second side 115 of the package substrate 120, and the first portion 102 and the second portion 104 of the hybrid substrate core 101 are adjacent to each other.

[0052] As discussed above, the package substrate 120 having the hybrid substrate core 101 helps to maintain the stress balance in the assembled semiconductor package 140 shown in, for example, FIGS. 8 and 9. The first portion 102 of the hybrid substrate core 101 is closest to the semiconductor package structure 130 having one or more semiconductor IC dies 131 and has a CTE (e.g., within 5 ppm / ° C.) close to the CTE of the one or more semiconductor IC dies 131. The second portion 104 of the hybrid substrate core 101 is closest to the support substrate 150 (e.g., a PCB) and has a CTE (e.g., within 10 ppm / ° C.) close to the CTE of the support substrate 150. In some embodiments, the first portion 102 of the hybrid substrate core 101 has a relatively high Young's modulus (e.g., ≧ 30 GPa) that provides high resistance to mechanical strain, and the second portion 104 of the hybrid substrate core 101 has a Young's modulus smaller than that of the first portion 102, providing a "cushioning" effect to reduce the stress caused by the CTE mismatch between the semiconductor package structure 130 and the support substrate 150 in the assembled semiconductor package 140.

[0053] FIG. 10 is a flowchart illustrating a method 200 for manufacturing a package substrate 120 according to various embodiments of the present invention. Referring to FIGS. 1 and 10, in step 201 of method 200 of the present invention, a hybrid substrate core 101 is formed having a first portion 102 adjacent to a first surface 105 of the hybrid substrate core 101 and a second portion 104 adjacent to a second surface of the hybrid substrate core 101. The first portion 102 of the hybrid substrate core 101 has a coefficient of thermal expansion (CTE) of less than 10 ppm / °C, and the second portion 104 of the hybrid substrate core 101 has a CTE between 10 ppm / °C and 30 ppm / °C.

[0054] Referring to FIGS. 2 and 10, in step 203 of method 300, a plurality of conductive vias 107 are formed through the hybrid substrate core 101 between a first surface 105 and a second surface 106 of the hybrid substrate core 101. Referring to FIGS. 3, 4, and 10, in step 205 of method 200, a redistribution layer 110 is formed on the first surface 105 and the second surface 106 of the hybrid substrate core 101.

[0055] Referring to the entire drawings and according to various embodiments of the present invention, a substrate 120 of a semiconductor package 140 has a substrate core 101 having a first surface 105 and a second surface 106 opposite the first surface 105. The substrate core 101 has a first portion 102 adjacent to the first surface 105 and a second portion 104 adjacent to the second surface 106. The first portion 102 has a coefficient of thermal expansion (CTE) of less than 10 ppm / °C, and the second portion 104 has a CTE of 10 ppm / °C to 30 ppm / °C. A plurality of conductive vias 107 extend between the first surface 105 and the second surface 106 of the substrate core 101, and to a first redistribution layer 110a on the first surface 105 of the substrate core 101 and a second redistribution layer 110b on the second surface 106 of the substrate core 101.

[0056] In one embodiment, the first portion 102 of the substrate core 101 has a CTE of 0.1 ppm / °C to 10 ppm / °C.

[0057] In another embodiment, the first portion 102 of the substrate core 101 has a Young's modulus higher than that of the second portion 104 of the substrate core 101.

[0058] In another embodiment, the Young's modulus of the first portion 102 of the substrate core 101 is 30 GPa to 50 GPa, and the Young's modulus of the second portion 104 of the substrate core 101 is 10 GPa to 40 GPa.

[0059] In another embodiment, the first portion 102 of the substrate core 101 has a first laminated reinforcing resin sheet, the second portion 104 of the substrate core 101 has a second laminated reinforcing resin sheet, and the first laminated reinforcing resin sheet and the second laminated reinforcing resin sheet are joined together to form the substrate core 101.

[0060] In another embodiment, the first laminated reinforcing resin sheet and the second laminated reinforcing resin sheet each have a thickness between 0.2 mm and 0.6 mm.

[0061] In another embodiment, the substrate core 101 further has a third portion 103 located between the first portion 102 and the second portion 104. The third portion 103 has a CTE greater than that of the first portion 102 and less than that of the second portion 104, and the third portion 103 has a Young's modulus of 1 GPa to 50 GPa.

[0062] In another embodiment, the first portion 102, the second portion 104, and the third portion 103 each have a laminated reinforcing resin sheet joined together to form the substrate core 101.

[0063] In another embodiment, the first redistribution layer 110a and the second redistribution layer 110b each have a conductive interconnect structure 109 in an insulating matrix 108, and the package substrate 120 further has an external coating layer 111 on each of the first redistribution layer 110a and the second redistribution layer 110b.

[0064] Another embodiment describes a semiconductor package 140 having a semiconductor package structure 130 with one or more semiconductor IC dies 131, a first side 114, a second side 115 opposite the first side 114, and a package substrate 120 having an electrical interconnect structure 109 extending between the first side 114 and the second side 115. The package substrate 120 has a hybrid substrate core 101, and the hybrid substrate core 101 has a first portion 102 closest to the first side 114 of the package substrate 120 and a second portion 104 closest to the second side 115 of the package substrate 120. The semiconductor package structure 130 is mounted on the first side 114 of the package substrate 120 and a support substrate 150, and the second side 115 of the package substrate 120 is mounted on the support substrate 150. The first portion 102 of the hybrid substrate core 101 of the package substrate 120 has a coefficient of thermal expansion (CTE) within 5 ppm / °C of the CTE of the semiconductor IC die 131 of the semiconductor package structure 130, and the second portion 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE within 10 ppm / °C of the CTE of the support substrate 150.

[0065] In one embodiment, the first portion 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE within 0.1 ppm / °C of the CTE of the semiconductor IC die 131 of the semiconductor package structure 130, and the second portion 102 of the hybrid substrate core 101 of the package substrate 120 has a CTE within 3 ppm / °C of the CTE of the support substrate 150.

[0066] In another embodiment, the support substrate 150 has a printed circuit board (PCB), and the second side 115 of the package substrate 120 is mounted on the PCB by a plurality of solder joints 154.

[0067] In another embodiment, the second portion 104 of the hybrid substrate core 101 of the package substrate 120 has a Young's modulus smaller than the Young's modulus of the first portion 102 of the hybrid substrate core 101 of the package substrate 120.

[0068] In another embodiment, the semiconductor package structure 130 has a plurality of semiconductor IC dies 131, and the first portion 102 of the hybrid substrate core 101 of the package substrate 120 has a coefficient of thermal expansion (CTE) within 5 ppm / °C of the CTE of the semiconductor IC dies 131 of each semiconductor package structure 130.

[0069] In another embodiment, the semiconductor package structure 130 further includes an interposer 133, a plurality of semiconductor IC dies 131 mounted on the upper surface of the interposer 133, and a plurality of solder connections 136 extending between the lower surface of the interposer 133 and the first side 114 of the package substrate 120, and the semiconductor package structure 130 is mounted on the first side 114 of the package substrate 120.

[0070] In another embodiment, the hybrid substrate core 101 of the package substrate 120 has a third portion 103 located between the first portion 102 and the second portion 104, and the CTE of the third portion 103 of the hybrid substrate core 101 is greater than the CTE of the first portion 102 of the hybrid substrate core 101 and less than the CTE of the second portion 104 of the hybrid substrate core 101.

[0071] In another embodiment, a method for manufacturing a package substrate is described, which includes a step of forming a hybrid substrate core 101 having a first portion 102 adjacent to the first surface of the hybrid substrate core 101 and a second portion 104 adjacent to the second surface 106 of the hybrid substrate core 101. The first portion 102 of the hybrid substrate core 101 has a coefficient of thermal expansion (CTE) less than 10 ppm / °C, the second portion 104 of the hybrid substrate core 101 has a CTE of 10 ppm / °C to 30 ppm / °C, a plurality of conductive vias 107 are formed through the hybrid substrate core 101 between the first surface 105 and the second surface 106 of the hybrid substrate core 101, a first redistribution layer 110a is formed on the first surface 105 of the hybrid substrate core 101, and a second redistribution layer 110b is formed on the second surface 106 of the hybrid substrate core 101.

[0072] In one embodiment, a method for forming a hybrid substrate core 101 includes forming a plurality of laminated reinforced resin sheets and joining the plurality of laminated reinforced resin sheets together to form the hybrid substrate core 101. The first laminated reinforced resin sheet forms a first portion 102 of the hybrid substrate core 101, and the second laminated reinforced resin sheet forms a second portion 104 of the hybrid substrate core 101.

[0073] In another embodiment, a third laminated reinforced resin sheet of the plurality of laminated reinforced resin sheets forms a third portion 103 of the hybrid substrate core 101. The CTE of the third portion 103 of the hybrid substrate core 101 is greater than the CTE of the first portion 102 of the hybrid substrate core 101 and less than the CTE of the second portion 104 of the hybrid substrate core 101.

[0074] In another embodiment, the Young's modulus of the first portion 102 of the hybrid substrate core 101 is 30 GPa to 50 GPa, the Young's modulus of the second portion 104 of the hybrid substrate core 101 is 10 GPa to 40 GPa, and the Young's modulus of the first portion 102 of the hybrid substrate core 101 is greater than the Young's modulus of the second portion 104 of the hybrid substrate core 101.

[0075] Although the preferred embodiments of the present invention have been disclosed as above, these are by no means intended to limit the present invention. Any person skilled in the art can make various modifications without departing from the spirit of the present invention.

Explanation of Reference Numerals

[0076] 101... Hybrid substrate core 102... First portion (first sublayer) 103... Third portion (third sublayer) 104... Second portion (second sublayer) 105... First surface (first side of the hybrid substrate core) 106... Second surface (second side of the hybrid substrate core) 107... Plurality of conductive vias 108…Dielectric material matrix (first layer of dielectric material) 109…Conductive interconnection structure 110a…First redistribution layer 110b…Second redistribution layer 111…External coating layer 112…First bonding pad 113…Second bonding pad 114…First outer surface (first side of package substrate) 115…Second outer surface (second side of package substrate) 116…Metal wire 117…Conductive via 120…Package substrate 130…Package structure 131…Semiconductor IC die 133…Interposer 134…Interconnection structure 136, 154…Solder material portion 137, 153…Bonding pad 138…First underfill material portion 139…Mold portion 140…Semiconductor package 141…Second underfill material portion 150…Support substrate 151…Upper surface 153…Bonding pad 160…Third underfill material portion T…Thickness

Claims

1. A substrate for a semiconductor package, a first surface and a second surface opposite the first surface; a first portion adjacent the first surface; and a substrate core having a second portion adjacent the second surface, the first portion having a Young's modulus between 30 GPa and 50 GPa and higher than the Young's modulus of the second portion; a plurality of conductive vias extending through the substrate core between the first surface and the second surface of the substrate core; a first redistribution layer on the first surface of the substrate core; a second redistribution layer on the second surface of the substrate core; A substrate for a semiconductor package comprising:

2. The substrate of claim 1, wherein the Young's modulus of the second portion of the substrate core is between 10 GPa and 40 GPa.

3. 2. The substrate of claim 1, wherein the first portion of the substrate core has a first laminated reinforced resin sheet and the second portion of the substrate core has a second laminated reinforced resin sheet, the first laminated reinforced resin sheet and the second laminated reinforced resin sheet being bonded together to form the substrate core.

4. The substrate according to claim 3, wherein the first laminated reinforced resin sheet and the second laminated reinforced resin sheet each have a thickness of 0.2 mm to 0.6 mm.

5. The substrate of claim 1, wherein the substrate core further comprises a third portion located between the first portion and the second portion, the third portion having a coefficient of thermal expansion (CTE) greater than the CTE of the first portion and less than the CTE of the second portion, and the third portion having a Young's modulus between 1 GPa and 50 GPa.

6. 6. The substrate of claim 5, wherein the first portion, the second portion, and the third portion each comprise laminated reinforced resin sheets bonded together to form the substrate core.

7. 1. A semiconductor package comprising: A semiconductor package structure, a package substrate, and a support substrate, The semiconductor package structure includes one or more semiconductor IC dies; The package substrate has a first side, a second side opposite the first side, and an electrical interconnect structure extending between the first side and the second side, the package substrate having a hybrid substrate core, the hybrid substrate core comprising: a first portion of the package substrate closest to the first side; and a second portion proximate the second side of the package substrate, the semiconductor package structure being mounted to the first side of the package substrate; A semiconductor package, characterized in that the second side of the package substrate is mounted to the support substrate, and the first portion of the hybrid substrate core of the package substrate has a Young's modulus of 30 GPa to 50 GPa and higher than the Young's modulus of the second portion of the hybrid substrate core of the package substrate.

8. 8. The semiconductor package of claim 7, wherein the Young's modulus of the second portion of the hybrid substrate core of the package substrate is between 10 GPa and 40 GPa.

9. 9. The semiconductor package of claim 7 or 8, wherein the hybrid substrate core of the package substrate has a third portion located between the first portion and the second portion, and the coefficient of thermal expansion (CTE) of the third portion of the hybrid substrate core is greater than the CTE of the first portion of the hybrid substrate core and less than the CTE of the second portion of the hybrid substrate core.

10. A method for manufacturing a package substrate, comprising the steps of: forming a hybrid substrate core having a first portion adjacent a first surface of the hybrid substrate core and a second portion adjacent a second surface of the hybrid substrate core, the first portion of the hybrid substrate core having a Young's modulus that is between 30 GPa and 50 GPa and the second portion of the hybrid substrate core having a Young's modulus that is between 10 GPa and 40 GPa; forming a plurality of conductive vias through the hybrid substrate core between the first surface and the second surface of the hybrid substrate core; forming a first redistribution layer on the first surface of the hybrid substrate core; forming a second redistribution layer on the second surface of the hybrid substrate core; A method for manufacturing a package substrate, comprising:

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