Circuit layout data generation system

Abstract

To provide a novel circuit layout data generation system.SOLUTION: A circuit layout data generation system comprises a data storage unit, a data processing unit, a prompt data generation unit, and a circuit layout data generation unit. The data storage unit has a function to store TEG name list data, TEG constraint condition data, and first list data. The data processing unit has the following functions to: output the name list data, constraint condition data, and first list data to the prompt data generation unit to acquire prompt data; output the prompt data to an information processing device including a language model via a network to acquire second list data; and output the second list data to the circuit layout data generation unit to acquire circuit layout data. The first list data and second list data are data representing coordinates on a substrate where TEGs are placed. The second list data is generated by updating the first list data in accordance with the prompt data.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a system for generating circuit layout data. In particular, one aspect of the present invention relates to a system for generating circuit layout data of a Test Element Group (hereinafter referred to as TEG).

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, their driving methods, or their manufacturing methods.

Background Art

[0003] A semiconductor device is configured by forming circuit elements such as transistors, resistor elements, and capacitor elements on a semiconductor substrate and connecting between the respective circuit elements so as to perform required circuit operations and functions. In order to perform the required circuit operations and circuit functions, it is necessary to evaluate whether transistors, resistor elements, capacitor elements, etc. have the required characteristics at the manufacturing stage. The pattern for evaluation and analysis formed on the semiconductor substrate is called TEG. The number of TEGs is increasing with the miniaturization and high functionality of semiconductor devices.

[0004] Therefore, it is necessary to arrange circuit elements with a large number of TEGs packed in a limited area. Patent Document 1 discloses a pattern layout method of TEG.

[0005] In recent years, large language models (LLMs) have also attracted attention. A large language model is a natural language processing model trained using a large amount of data. With large language models, for example, a dialogue model that answers user instructions can be realized (see, for example, Non-Patent Document 1).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] It is possible to attempt to generate circuit layout data of a TEG using a large language model. However, in order to generate circuit layout data equivalent to that of a TEG created manually, a large amount of learning data is required. In addition, for TEG circuit layout data, when emphasizing ease of measurement or symmetry such as arranging the same type of TEGs in a well-balanced manner, there are no prioritized rules for the arrangement method, and the arrangement methods considered optimal vary depending on the creator. Therefore, it has been difficult to generate TEG circuit layout data with excellent convenience, usefulness, or reliability.

[0009] In view of the above problems, one aspect of the present invention aims to provide a novel circuit layout data generation system with excellent convenience, usability, or reliability. Or, one aspect of the present invention aims to provide a novel TEG circuit layout data generation system with excellent convenience, usability, or reliability. Or, one aspect of the present invention aims to provide a novel circuit layout data generation system or a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention includes a data storage unit, a data processing unit, a prompt data creation unit, and a circuit layout data creation unit. The data storage unit has a function of storing TEG name list data, TEG constraint condition data, and first list data. The data processing unit has functions of outputting the name list data, constraint condition data, and first list data to the prompt data creation unit to obtain prompt data, outputting the prompt data to an information processing device having a language model via a network to obtain second list data, and outputting the second list data to the circuit layout data creation unit to obtain circuit layout data. The first list data and the second list data are data representing coordinates on a substrate on which the TEG is arranged, and the second list data is data generated by updating the first list data according to the prompt data. It is a circuit layout data generation system.

[0012] One aspect of the present invention includes a data storage unit, a data processing unit, a prompt data creation unit, and a circuit layout data creation unit. The data storage unit has a function of storing TEG name list data, TEG constraint condition data, and first list data. The data processing unit has functions of outputting the name list data, the constraint condition data, and the first list data to the prompt data creation unit to obtain first prompt data; outputting the first prompt data to an information processing apparatus having a language model via a network to obtain second list data; updating the first list data stored in the data storage unit with the second list data; outputting the name list data, the constraint condition data, and the second list data to the prompt data creation unit to obtain second prompt data; outputting the second prompt data to an information processing apparatus having a language model via a network to obtain third list data; and outputting the third list data to the circuit layout data creation unit to obtain circuit layout data. The first to third list data are data representing coordinates on a substrate on which TEGs are arranged. The second list data is data generated by updating the first list data according to the first prompt data. The third list data is data generated by updating the second list data according to the second prompt data. It is a circuit layout data generation system.

[0013] In one aspect of the present invention, it is preferable that the TEG is a circuit element for element characteristic evaluation, and the system is a circuit layout data generation system.

[0014] In one aspect of the present invention, it is preferable that the TEGs are grouped according to the use of the TEGs, and in the data processing unit, the name list data and the constraint condition data are output to the prompt data creation unit for each grouped use of the TEGs, and the system is a circuit layout data generation system.

[0015] Other aspects of the present invention are described in the following embodiments and the drawings.

Advantages of the Invention

[0016] One aspect of the present invention can provide a novel circuit layout data generation system that is excellent in convenience, usability, or reliability. Or, a novel TEG circuit layout data generation system that is excellent in convenience, usability, or reliability can be provided. Or, a novel circuit layout data generation system or a novel semiconductor device can be provided.

[0017] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are effects not mentioned in this item as described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and / or other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above.

Brief Description of the Drawings

[0018]

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Best Mode for Carrying Out the Invention

[0019] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

[0020] In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description thereof will be omitted. Also, when referring to the same function, the hatching pattern may be the same, and there may be cases where no reference numerals are particularly assigned.

[0021] Also, the positions, sizes, ranges, etc. of the respective components shown in the drawings may not represent the actual positions, sizes, ranges, etc. for the sake of simplicity of understanding. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

[0022] In this specification and the like, ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of components (for example, the process order or the stacking order). Also, the ordinal number attached to a component in one part of this specification may not match the ordinal number attached to the same component in another part of this specification or in the claims.

[0023] (Embodiment 1) In one aspect of the present invention, a system for generating circuit layout data of a TEG will be described with reference to FIGS. 1 to 11(B).

[0024] FIG. 1 is a conceptual diagram for explaining a system for generating circuit layout data. Note that the circuit layout data may be referred to as circuit layout data or layout data. Also, the circuit layout data generation system may be referred to as a circuit layout data generation system or a data generation system.

[0025] In FIG. 1, a circuit layout data generation system 10 is connected to an information processing device 40 via a network 30. Also, the circuit layout data generation system 10 is connected to a plurality of information terminals 20 via networks 31, respectively. In FIG. 1, as an example of the information terminal 20, information terminals 20a, 20b, 20c, and 20d are shown.

[0026] A user (such as a designer) of the circuit layout data generation system 10 can access the circuit layout data generation system 10 from the information terminals 20a to 20d and the like. And the user can receive services related to the circuit layout data using the circuit layout data generation system of one aspect of the present invention.

[0027] The circuit layout data generation system 10 can generate prompt data (instructions) using the name list data of TEGs, the constraint condition data of TEGs, and the list data input from the information terminal 20a via the network 31. The circuit layout data generation system 10 can transmit the prompt data to the information processing device 40 via the network 30. The information processing device 40 can generate updated list data using the transmitted prompt data. The circuit layout data generation system 10 can generate circuit layout data using the updated list data. The circuit layout data generation system 10 can transmit the circuit layout data to the information terminal 20a via the network 31. Thereby, the burden of generating prompt data at the information terminal 20a and the burden of generating updated list data at the information processing device 40 can be reduced. Here, the information terminal 20a has been described as an example, but the same can be said for the information terminals 20b to 20d.

[0028] Note that the TEG is mainly provided for element characteristic evaluation, such as circuit elements, for example, field effect transistors (hereinafter referred to as FETs), wiring for transmitting electrical signals, capacitive elements for holding electrical signals, and resistive elements to which electrical signals are supplied. The circuit layout data is data in which the arrangement of TEGs for alignment of needle points for measurement is determined, in addition to being used for FET evaluation, confirmation of wiring processes, measurement of resistance values, etc.

[0029] The TEG name list data is data regarding the TEG names of each TEG, grouped by application. For example, the TEG names for the needle alignment for measurement include "TEG_START", "TEG_ENDA", "TEG_ENDB", "TEG_ENDC", etc. For example, the TEG names for the TEG for FET evaluation include "TEG_FETA", "TEG_FETB", "TEG_FETC", etc. For example, the TEG names for the TEG for wiring process confirmation include "TEG_PROA_A", "TEG_PROA_B", "TEG_PROA_C", etc. For example, the TEG names for the TEG for resistance value measurement include "TEG_PROB_A", "TEG_PROB_B", "TEG_PROB_C", etc.

[0030] The TEG constraint condition data is data regarding the constraint conditions determined for each application of each TEG. For example, the constraint condition data for the TEG for the needle alignment for measurement includes "· Process the input data in order from the top. · Search for the part where the value is "0" and insert the input data. · Insert TEG_START at the upper left in the list. · Insert TEG_ENDA at the lower right in the list. · Insert TEG_ENDB at the upper right in the list. · Insert TEG_ENDC at the lower left in the list.", etc. For example, the constraint condition data for the TEG for FET evaluation includes "· Process the input data in order from the top. · Search for the part where the value is "0" and insert the input data. · Insert the first one at the leftmost in the 3rd row in the list. · Insert the second one at the rightmost in the 3rd row in the list. · Insert the third one at the center in the list.", etc. For example, the constraint condition data for the TEG for wiring process confirmation includes "· Process the input data in order from the top. · Search for the part where the value is "0" and insert the input data. · Insert from the upper part in the list.", etc. For example, the constraint condition data for the TEG for resistance value measurement includes "· Process the input data in order from the top. · Search for the part where the value is "0" and insert the input data.", etc.

[0031] The list data is list data for generating circuit layout data for the placement of TEGs. The list data is data that simply represents the coordinates on the substrate where the TEGs are to be placed. The coordinates on the substrate where the TEGs are to be placed can be referred to as regions.

[0032] For example, the region for placing a 1-row and 5-column TEG is represented by "[0,0,0,0,0]". For example, the region for placing a 5-row and 5-column TEG is represented by data in which "[0,0,0,0,0]" is described across 5 rows. In the list data, "0" indicates that the TEG to be placed is blank, and in the initial state, any region can be represented by "0". The list data in the initial state may be referred to as the first list data. Also, the list data updated within the circuit layout data generation system 10 may be referred to as the nth (n is a natural number of 2 or more) list data. Note that n is a number that increases according to the number of times the list data is updated.

[0033] The information terminals 20a to 20d are each information terminal devices such as a computer used by a user, and can also be called client computers, etc. In FIG. 1, as an example, an information terminal 20a which is a desktop computer, an information terminal 20b which is a notebook computer, an information terminal 20c which is a smartphone, and an information terminal 20d which is a tablet computer are illustrated. The number of information terminals connected to the circuit layout data generation system 10 is not particularly limited. In FIG. 1, 4 information terminals are shown, but the number of information terminals may be 1, 2, 3, or 5 or more. Examples of such information terminals include desktop information terminals, notebook information terminals, tablet information terminals, and portable information terminals such as smartphones.

[0034] The circuit layout data generation system 10 is a large computer such as a server computer or a supercomputer. The circuit layout data generation system 10 is a computer with high processing power compared to the information terminal 20. The circuit layout data generation system 10 may be able to perform processing using a natural language processing model using artificial intelligence (AI: Artificial Intelligence).

[0035] The information processing device 40 is a large computer such as a server computer or a supercomputer. The information processing device 40 is a computer with high processing power compared to the information terminal 20 and the circuit layout data generation system 10. The information processing device 40 can perform, for example, large-scale calculations necessary for AI learning and inference.

[0036] The information processing device 40 can perform processing using a natural language processing model using AI. Examples of the natural language processing model using AI include BERT (Bidirectional Encoder Representations from Transformers) and T5 (Text-to-Text Transfer Transformer). Further, the information processing device 40 can perform processing using a model (such as a text generation model or a dialogue model) using a large language model (also simply referred to as a language model). Examples of the large language model include GPT-3, GPT-3.5, GPT-4, LaMDA (Language Model for Dialogue Applications), PaLM (Pathways Language Model), and PaLM2, and it is preferable to use GPT-4.

[0037] Network 31 is a computer network smaller in scale than network 30. Typically, network 30 is a global network, and network 31 is a local network. As network 30, it is preferable to use the Internet, which is the foundation of the World Wide Web (WWW). As network 31, it is preferable to use an intranet or an extranet. In the present embodiment, mainly, the case where the Internet is used as network 30 and an intranet is used as network 31 will be described as an example.

[0038] In addition, as network 31, computer networks such as PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area Network), and GAN (Global Area Network) can be used.

[0039] When performing wireless communication, as a communication protocol or communication technology, communication standards such as the 4th generation mobile communication system (4G), the 5th generation mobile communication system (5G), and the 6th generation mobile communication system (6G), or specifications standardized by the IEEE such as Wi-Fi (registered trademark) and Bluetooth (registered trademark) can be used.

[0040] FIG. 2 is a block diagram for explaining a circuit layout data generation system. In FIG. 2, the circuit layout data generation system 10 is connected via network 30 to an information processing device 40. Further, the circuit layout data generation system 10 is connected via network 31 to an information terminal 20.

[0041] In the block diagram shown in FIG. 2, the circuit layout data generation system 10 includes a data storage unit 110, a prompt data creation unit 120, a data processing unit 130, a circuit layout data creation unit 140, and a data transmission unit 150.

[0042] In the drawings attached to this specification, the components are classified by function and shown as independent blocks in a block diagram. However, in reality, it is difficult to completely separate the components by function, and one component may be related to multiple functions. For example, a part of the data processing unit 130 may function as the data storage unit 110. Also, one function may be related to multiple components. For example, the processing performed in the data processing unit 130 may be executed on different servers.

[0043] The data storage unit 110 has a function of storing the data received via the networks 30 and 31, that is, the name list data of the TEG, the constraint condition data of the TEG, and the list data. Also, the data storage unit 110 has a function of storing the list data updated within the circuit layout data generation system 10. Note that the update of the list data can be performed by overwriting and storing the previous list data, or by additionally storing the generated list data in addition to the previous list data.

[0044] The data storage unit 110 has at least one of a volatile memory and a non-volatile memory. Examples of the volatile memory include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Examples of the non-volatile memory include ReRAM (Resistive Random Access Memory, also referred to as a resistive change memory), PRAM (Phase change Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory, also referred to as a magnetic resistive memory), and flash memory. Further, the data storage unit 110 may have a recording medium drive. Examples of the recording medium drive include a hard disk drive (HDD) and a solid state drive (SSD).

[0045] The prompt data creation unit 120 has a function of creating prompt data according to the TEG name list data, the TEG constraint condition data, and the list data. The prompt data creation unit 120 can create prompt data by a script or a program for creating prompt data. The prompt data is an instruction book in a sentence described in natural language created based on the TEG name list data, the TEG constraint condition data, and the list data. The information processing apparatus 40 that performs processing based on a large language model can generate list data updated according to the prompt data.

[0046] The data processing unit 130 has a function of performing processes such as calculation and analysis using the data received via the networks 30 and 31, that is, the name list data of the TEG, the constraint condition data of the TEG, and the list data. The data processing unit 130 can input and output data (for example, prompt data, list data, etc.) between the data storage unit 110, the prompt data creation unit 120, the circuit layout data creation unit 140, and / or outside the circuit layout data generation system 10 to acquire the data.

[0047] The data processing unit 130 can have, for example, an arithmetic circuit. The data processing unit 130 can have, for example, a central processing unit (CPU). Also, the data processing unit 130 can have a graphics processing unit (GPU).

[0048] The circuit layout data creation unit 140 has a function of creating the circuit layout data of the TEG according to the list data. The circuit layout data creation unit 140 can create the circuit layout data by a script or program for creating the circuit layout data. The circuit layout data is the circuit layout data of the TEG determined according to the updated list data. The updated list data is the list data updated according to the prompt data in the information processing device 40 that performs processing based on the large language model.

[0049] The data transmission unit has a function of transmitting data. The data transmission and reception between the data storage unit 110, the prompt data creation unit 120, the data processing unit 130, and the circuit layout data creation unit 140 can be performed via the data transmission unit 150.

[0050] Figure 3(A) is a flowchart for explaining the circuit layout data generation system. The circuit layout data generation system can be explained by a plurality of steps from step S1 to step S8.

[0051] In step S1, the circuit layout data generation system 10 receives the list data of TEG names, the constraint condition data of TEG, and the list data of the initial state. The received list data of TEG names, the constraint condition data of TEG, and the list data of the initial state are stored in the data storage unit 110.

[0052] In step S2, the circuit layout data generation system 10 outputs the list data of TEG names, the constraint condition data of TEG, and the list data of the initial state to the prompt data creation unit 120 under the control of the data processing unit 130.

[0053] In step S3, the circuit layout data generation system 10 obtains the prompt data created by the prompt data creation unit 120 in the data processing unit 130.

[0054] In step S4, the circuit layout data generation system 10 outputs the prompt data obtained by the data processing unit 130 to the information processing device 40.

[0055] In step S5, the circuit layout data generation system 10 obtains, in the data processing unit 130, the list data updated by the information processing device 40 based on the prompt data.

[0056] In step S6, the circuit layout data generation system 10 outputs the updated list data to the circuit layout data creation unit 140 under the control of the data processing unit 130.

[0057] In step S7, the circuit layout data generation system 10 creates circuit layout data in the circuit layout data creation unit 140, and obtains the created circuit layout data in the data processing unit 130.

[0058] In step S8, the circuit layout data generation system 10 outputs the circuit layout data obtained by the data processing unit 130 to the information terminal 20.

[0059] Steps S2 to S5 for obtaining the updated list data shown in FIG. 3(A) are preferably performed for each piece of data regarding the TEG name of each TEG grouped by the use of the TEG. In this case, the output of the list data of the TEG name list in step S2 is output for each use of the TEG. Further, as the constraint condition data of the TEG, the constraint condition data corresponding to the output list data of the TEG name list is output. With such a configuration, every time the list data is updated, the user can check the circuit design data being generated, so that the circuit design data being generated can be easily corrected by the dialogue (chat) between the information terminal 20 operated by the user and the information processing apparatus.

[0060] For example, the updated list data (second list data) is obtained by steps S2 to S5 for arranging the TEG for the alignment of the needle contact position for measurement. Subsequently, the updated list data (third list data) is obtained by steps S2 to S5 for arranging the TEG for FET evaluation. Subsequently, the updated list data (fourth list data) is obtained by steps S2 to S5 for arranging the TEG for wiring process confirmation. Subsequently, the updated list data (fifth list data) is obtained by steps S2 to S5 for arranging the TEG for resistance value measurement. With such a configuration, in the information processing apparatus 40, the update of the desired list data can be efficiently performed, and the degree of coincidence between the circuit layout data created using the circuit layout data generation system 10 and the circuit layout data created manually can be increased.

[0061] The configuration of repeating the update of the list data in steps S2 to S5 as described above branches depending on the determination in step J1 shown in FIG. 3(B). In step J1, if there is a "0" in the list data, that is, if there is a blank in the area where the TEG circuit layout is to be performed (Yes), steps S2 to S5 are repeated. Also in step J1, if there is no "0" in the list data, that is, if there is no blank in the area where the TEG circuit layout is to be performed (No), the process proceeds to step S6.

[0062] Accordingly, circuit layout data can be created using the list data of TEG names, the constraint condition data of TEGs, and the list data described in natural language. Also, even when the types of TEGs increase, circuit layout data can be created by updating the list data of TEG names. Also, even when there is a change in the use of TEGs, circuit layout data can be created by updating the constraint condition data of TEGs. Also, even when there is a change in the area where the TEG layout is performed, circuit layout data can be created by updating the list data. Also, it becomes possible for even a user with little experience to create the circuit layout data of TEGs created by a user with advanced expertise. As a result, it is possible to provide a novel circuit layout data generation system excellent in convenience, usefulness, or reliability.

[0063] FIGS. 4(A) to 11(B) are schematic diagrams and block diagrams for explaining steps S1 to S8 described in FIGS. 3(A) and 3(B).

[0064] The block diagram of FIG. 4(A) is a block diagram schematically representing step S1. In FIG. 4(A), the list data of names NLD, the constraint condition data RCD, and the first list data LD1 are illustrated, and the movement of each data is visualized by dotted arrows. Step S1 is a step in which the circuit layout data generation system 10 receives the list data of names NLD, the constraint condition data RCD, and the first list data LD1, which are data from the information terminal 20. Each received data is held in the data storage unit 110.

[0065] Figure 4(B) is a diagram schematically showing the data structure of the name list data NLD. The name list data NLD is text data regarding the TEG names belonging to TEGs (TEG_1 to TEG_4) grouped for each use of the TEG. TEG_1 is a TEG for needle alignment for measurement, to which "TEG_START", "TEG_ENDA", "TEG_ENDB", and "TEG_ENDC" belong. TEG_2 is a TEG for device characteristic evaluation, to which "TEG_FETA", "TEG_FETB", and "TEG_FETC" belong. Details of TEG_3 and TEG_4 will be described later, but they are TEGs for wiring process confirmation and resistance value measurement, respectively.

[0066] Figure 4(C) is a diagram schematically showing the data structure of the constraint condition data RCD. The constraint condition data RCD is text data in which constraint conditions are described for each TEG (TEG_1 to TEG_4) grouped for each use of the TEG. For TEG_1, the constraint condition RCD_1 is described. For TEG_2, the constraint condition RCD_2 is described. For TEG_3, the constraint condition RCD_3 is described. For TEG_4, the constraint condition RCD_4 is described.

[0067] When TEG_1 is a TEG for needle alignment for measurement, the constraint condition RCD_1 is exemplified by "· Process the input data in order from the top · Search for the part where the value is "0" and insert the input data · TEG_STARTG is inserted at the upper left in the list · TEG_ENDA is inserted at the lower right in the list · TEG_ENDB is inserted at the upper right in the list · TEG_ENDGC is inserted at the lower left in the list".

[0068] When TEG_2 is a TEG for device characteristic evaluation, the constraint condition RCD_2 is exemplified by "· Process the input data in order from the top · Search for the part where the value is "0" and insert the input data · The first one is inserted at the leftmost in the third row in the list · The second one is inserted at the rightmost in the third row in the list · The third one is inserted at the center in the list".

[0069] When TEG_3 is a TEG for wiring process confirmation, Constraint RCD_3 exemplifies "· Process input data in order from top · Search for parts with value "0" and insert input data · Insert from the top in the list".

[0070] When TEG_4 is a TEG for resistance value measurement, Constraint RCD_4 exemplifies "· Process input data in order from top · Search for parts with value "0" and insert input data · Insert from the top in the list".

[0071] Figure 4(D) is a diagram schematically showing the data structure of the first list data LD1. The first list data LD1 corresponds to text data representing coordinates within the area where the TEG provided on the substrate is arranged. For example, the area for circuit arrangement of a 5-row and 5-column TEG is represented by data in which "[0,0,0,0,0]" is described over 5 rows as shown in Figure 4(D).

[0072] The block diagram of Figure 5(A) is a block diagram schematically showing steps S2 and S3. In Figure 5(A), name list data NLD, constraint data RCD, first list data LD1, and first prompt data PD1 are illustrated, and the movement of each data is visualized by dotted arrows. Step S2 outputs the name list data NLD, constraint data RCD, and first list data LD1, which are data held in the data storage unit 110, to the prompt data creation unit 120. Step S3 outputs the first prompt data PD1 created by the prompt data creation unit 120 to the data processing unit 130.

[0073] Figure 5(B) is a diagram schematically showing the data structure of the first prompt data PD1. The first prompt data PD1 is text data arranged in the format of an instruction book processed by the language model that the information processing apparatus 40 has for the name list data NLD, constraint data RCD, and first list data LD1.

[0074] The first prompt data PD1 is composed of, for example, "#Instruction", "#Constraints", "#List", and "#Input Data". Text data OD is described in "#Instruction". Constraint condition RCD_1 is described in "#Constraints". First list data LD1 is described in "#List". Grouped TEG, i.e., TEG_1, is described in "#Input Data". The text data OD is a fixed-form sentence, and an example is "Update the list according to the following constraint conditions."

[0075] The block diagram of Fig. 6(A) is a block diagram schematically representing steps S4 and S5. In Fig. 6(A), name list data NLD, constraint condition data RCD, first list data LD1, first prompt data PD1, and second list data LD2 are illustrated, and the movement of each data is visualized by dotted arrows. In step S4, the first prompt data PD1 acquired by the data processing unit 130 is output to the information processing device 40 via the network 30. In step S5, the second list data LD2 updated based on the first prompt data PD1 in the information processing device 40 is output to the data processing unit 130 and the data storage unit 110. The data processing unit 130 makes a determination in step J1 based on the acquired second list data LD2. Also, in the data storage unit 110, the first list data LD1 is updated to the second list data LD2.

[0076] Fig. 6(B) is a diagram schematically representing the data structure of the second list data LD2. The "#List" of the first prompt data PD1 is updated based on "#Constraints" and "#List", and becomes the second list data LD2 having "TEG_START", "TEG_ENDA", "TEG_ENDB", and "TEG_ENDC". The TEG name of TEG_1 is replaced from "0" in the list according to the constraint condition RCD_1 of "· Process the input data in order from top to bottom. · Search for the part where the value is "0" and insert the input data. · TEG_START is inserted at the upper left in the list. · TEG_ENDA is inserted at the lower right in the list. · TEG_ENDB is inserted at the upper right in the list. · TEG_ENDC is inserted at the lower left in the list".

[0077] In the determination of step J1 performed on the second list data LD2 acquired by the data processing unit 130, since "0" is present in the list, steps S2 to S5 are repeated again. The second time steps S2 to S5 are performed are referred to as steps S2_2 to S5_2. Steps S2 to S5 after the third time are referred to as steps S2_3 to S5_3. Steps S2 to S5 after the k-th (where k is an integer of 2 or more) time are referred to as steps S2_k to S5_k.

[0078] The block diagram of FIG. 7(A) is a block diagram schematically showing steps S2_2 and S3_2. In FIG. 7(A), the name list data NLD, the constraint condition data RCD, the second list data LD2, and the second prompt data PD2 are illustrated, and the movement of each data is visualized by dotted arrows. In step S2_2, the name list data NLD, the constraint condition data RCD, and the second list data LD2, which are the data held in the data storage unit 110, are output to the prompt data creation unit 120. In step S3_2, the second prompt data PD2 created by the prompt data creation unit 120 is output to the data processing unit 130.

[0079] FIG. 7(B) is a diagram schematically showing the data structure of the second prompt data PD2. The second prompt data PD2 is text data arranged in the format of an instruction book for the language model that the information processing apparatus 40 has for the name list data NLD, the constraint condition data RCD, and the second list data LD2.

[0080] The second prompt data PD2 is composed of, for example, "# instruction book", "# constraint condition", "# list", and "# input data". In "# instruction book", the text data OD is described. In "# constraint condition", the constraint condition RCD_2 is described. In "# list", the second list data LD2 is described. In "# input data", the grouped TEG, which is TEG_2, is described.

[0081] The block diagram of FIG. 8(A) is a block diagram schematically showing steps S4_2 and S5_2. In FIG. 8(A), name list data NLD, constraint condition data RCD, second list data LD2, second prompt data PD2, and third list data LD3 are illustrated, and the movement of each data is visualized by dotted arrows. In step S4_2, the second prompt data PD2 acquired by the data processing unit 130 is output to the information processing apparatus 40 via the network 30. In step S5_2, the third list data LD3 updated based on the second prompt data PD2 in the information processing apparatus 40 is output to the data processing unit 130 and the data storage unit 110. In the data processing unit 130, the determination in step J1 is made based on the acquired third list data LD3. Also, in the data storage unit 110, the second list data LD2 is updated to the third list data LD3.

[0082] FIG. 8(B) is a diagram schematically showing the data structure of the third list data LD3. The “# list” of the second prompt data PD2 is updated based on the “# constraint condition” and the “# list” to become the third list data LD3 having “TEG_FETA”, “TEG_FETB”, and “TEG_FETC”. The TEG name of TEG_2 is replaced from “0” in the list according to the constraint condition RCD_2 of “· Process the input data in order from the top · Search for the part where the value is “0” and insert the input data · For the first one, insert it at the leftmost position in the third row of the list · For the second one, insert it at the rightmost position in the third row of the list · For the third one, insert it at the center of the list”.

[0083] In the determination of step J1 performed on the third list data LD3 acquired by the data processing unit 130, since “0” is included in the list, steps S2 and S5 are repeated again.

[0084] FIG. 9(A) is a diagram schematically showing the data structure of the name list data NLD used in steps S2_3 to S5_3. TEG_3 is a TEG for wiring process confirmation, to which "TEG_PROA_A", "TEG_PROA_B", "TEG_PROA_C", "TEG_PROA_D", "TEG_PROA_E", "TEG_PROA_F", "TEG_PROA_G", "TEG_PROA_H", "TEG_PROA_I", and "TEG_PROA_J" belong.

[0085] FIG. 9(B) is a diagram schematically showing the data structure of the third prompt data PD3 used in steps S3_3 to S5_3. The third prompt data PD3 is text data arranged in a format of an instruction book for the information processing apparatus 40 to process the name list data NLD, the constraint condition data RCD, and the third list data LD3 using a language model.

[0086] The third prompt data PD3 is composed of, for example, "#instruction book", "#constraint condition", "#list", and "#input data". Text data OD is described in "#instruction book". Constraint condition RCD_3 is described in "#constraint condition". The third list data LD3 is described in "#list". The grouped TEG, TEG_3, is described in "#input data".

[0087] FIG. 9(C) is a diagram schematically showing the data structure of the fourth list data LD4 generated based on the third prompt data PD3. The "# list" of the third prompt data PD3 is updated based on the "# constraint conditions" and the "# list", and becomes the fourth list data LD4 having "TEG_PROA_A", "TEG_PROA_B", "TEG_PROA_C", "TEG_PROA_D", "TEG_PROA_E", "TEG_PROA_F", "TEG_PROA_G", "TEG_PROA_H", "TEG_PROA_I", "TEG_PROA_J". The TEG name of TEG_3 is replaced from "0" in the list according to the constraint condition RCD_3 of "· Process the input data in order from the top · Search for the part where the value is "0" and insert the input data · Insert from the top in the list".

[0088] In the determination of step J1 performed on the fourth list data LD4 acquired by the data processing unit 130, since "0" is present in the list, steps S2 and S5 are repeated again.

[0089] FIG. 10(A) is a diagram schematically showing the data structure of the name list data NLD used in steps S2_4 to S5_4. TEG_4 is a TEG for resistance value measurement, to which "TEG_PROB_A", "TEG_PROB_B", "TEG_PROB_C", "TEG_PROB_D", "TEG_PROB_E", "TEG_PROB_F", "TEG_PROB_G", "TEG_PROB_H" belong.

[0090] FIG. 10(B) is a diagram schematically showing the data structure of the fourth prompt data PD4 used in steps S3_4 to S5_4. The fourth prompt data PD4 is text data arranged in the format of an instruction book for the information processing apparatus 40 to process the name list data NLD, the constraint condition data RCD, and the fourth list data LD4 using the language model.

[0091] The third prompt data PD4 is composed of, for example, "# Instruction Manual", "# Constraints", "# List", and "# Input Data". Text data OD is described in the "# Instruction Manual". Constraint condition RCD_4 is described in the "# Constraints". The fourth list data LD4 is described in the "# List". Grouped TEG, namely TEG_4, is described in the "# Input Data".

[0092] Figure 10(C) is a diagram schematically showing the data structure of the fifth list data LD5 generated based on the fourth prompt data PD4. The "# List" of the fourth prompt data PD4 is updated based on the "# Constraints" and the "# List", and becomes the fifth list data LD5 having "TEG_PROB_A", "TEG_PROB_B", "TEG_PROB_C", "TEG_PROB_D", "TEG_PROB_E", "TEG_PROB_F", "TEG_PROB_G", "TEG_PROB_H". The TEG name of TEG_4 is replaced from "0" in the list according to the constraint condition RCD_4 of "· Process the input data in order from top to bottom · Search for the part where the value is "0" and insert the input data".

[0093] In the determination of step J1 performed on the fifth list data LD5 acquired by the data processing unit 130, since there is no "0" in the list, the process proceeds to step S6.

[0094] The block diagram of Figure 11(A) is a block diagram schematically showing steps S6 to S8. In Figure 11(A), name list data NLD, constraint condition data RCD, the fifth list data LD5, and circuit layout data CLD are illustrated, and the movement of each data is visualized by dotted arrows. In step S6, the fifth list data LD5 acquired by the data processing unit 130 is output to the circuit layout data creation unit 140. In step S7, the circuit layout data CLD created based on the fifth list data LD5 in the circuit layout data creation unit 140 is output to the data processing unit 130. In the data processing unit 130, the acquired circuit layout data CLD is output to the information terminal 20.

[0095] FIG. 11(B) is a diagram schematically showing circuit layout data CLD. The circuit layout data CLD is created by replacing the circuit layout data of the designed TEG based on the name of the TEG of the updated list data LD(LD5) determined by updating the initial list data LD(LD1). In FIG. 11(B), a TEG map arranged in a 5-row and 5-column layout corresponding to the fifth list data LD5 and arranged within the area for arranging the TEG is illustrated.

[0096] As described above, in the circuit layout data generation system according to an aspect of the present invention, circuit layout data can be created using the list data of TEG names described in natural language, the constraint condition data of the TEG, and the list data. Further, even when the types of TEGs increase, circuit layout data can be created by updating the list data of TEG names. Also, even when there is a change in the use of the TEG, circuit layout data can be created by updating the constraint condition data of the TEG. Further, even when there is a change in the area where the circuit layout of the TEG is performed, circuit layout data can be created by updating the list data. Also, it becomes possible for a user with little experience to create the circuit layout data of the TEG created by a user having advanced expertise. As a result, it is possible to provide a novel circuit layout data generation system excellent in convenience, usefulness, or reliability.

[0097] Note that the present embodiment can be appropriately combined with other embodiments described in this specification.

[0098] (Embodiment 2) In the present embodiment, a modification example of the circuit layout data generation system described in the above Embodiment 1 will be described. In the description of the present embodiment, the configurations overlapping with those in the above-described Embodiment 1 may be incorporated by reference to the description of the above Embodiment 1, and the description may be omitted.

[0099] The circuit layout data generation system 10 shown in FIG. 12 includes a data storage unit 110, a prompt data creation unit 120, a data processing unit 130, a circuit layout data creation unit 140, and a data transmission unit 150, similar to FIG. 1. The circuit layout data generation system 10 is connected to an information terminal 20 via a network 31 and to an information processing apparatus 40 via a network 30. The information terminal 20 includes a data analysis unit 50 having a data storage unit 210 via a network 32.

[0100] The data storage unit 210 accumulates log data of circuit layout data manually performed by a user in the information terminal. The data analysis unit 50 analyzes the log data (operation log) accumulated in the data storage unit 210 and generates the constraint condition data described in the first embodiment.

[0101] The applications of TEG cover a wide range, such as FET characteristic confirmation, process confirmation, and consideration of new process development. Also, for TEGs for device evaluation, there are TEGs for examining individual components such as pixel circuits and memory cells, and TEGs of circuits in which a part of the circuit is partially cut out. Therefore, when trying to create constraint conditions for each application of TEG, it is costly.

[0102] Therefore, a configuration that creates a standardization (template) of constraint conditions based on the past log data designed by the user and the completed circuit layout data is effective.

[0103] In the data analysis unit 50, based on the log data accumulated in the data storage unit 210, the circuit layout data and the log data are compared, and information on which TEG the user arranged in which order can be obtained.

[0104] For example, FIG. 13(A) shows a schematic diagram of circuit layout data in which the user has placed TEGs. As the order in which the user creates the circuit layout data, the user places "TEG_START", "TEG_ENDA", "TEG_ENDB", and "TEG_ENDC" (the hatched areas in the figure). Next, as the order in which the user creates the circuit layout data, the user places "TEG_FETA", "TEG_FETB", and "TEG_FETC" (the areas surrounded by thick lines in the figure).

[0105] FIG. 13(B) shows the log data 112 when the TEGs in FIG. 13(A) are placed. As the log data 112, ">add cell TEG_START", ">add cell TEG_ENDA", ">add cell TEG_ENDB", ">add cell TEG_ENDC", ">add cell TEG_FETA", ">add cell TEG_FETB", and ">add cell TEG_FETC" are recorded.

[0106] By comparing the log data 112 with the actual circuit layout data, information regarding the order in which the TEGs are placed and information regarding the positions of the TEGs can be obtained. This information regarding the order in which the TEGs are placed and information regarding the positions of the TEGs can be used as constraint conditions.

[0107] For example, "TEG_START", "TEG_ENDA", "TEG_ENDB", and "TEG_ENDC" are placed at "upper left", "lower right", "upper right", and "lower left", respectively, and these are the TEGs placed earliest. Next, "TEG_FETA", "TEG_FETB", and "TEG_FETC" are placed in order, and information regarding the order and positions of the TEGs such as "center within the area", "center and left end", and "center and right end" can be obtained.

[0108] Also, when classifying the order and position information of the TEGs for each application, it is effective to include an identification word for the application in the TEG name. For example, identification words such as "START" and "END" are used as identification words for needle alignment. That is, "TEG_START", "TEG_ENDA", "TEG_ENDB", and "TEG_ENDC" can be classified for each use of the TEG in the form of a TEG for needle alignment for measurement. From this information, templates such as "TEG_START is at the upper left", "TEG_ENDA is at the lower right", "TEG_ENDB is at the upper right", and "TEG_ENDC is at the lower left" for needle alignment for measurement can be created.

[0109] Also, for example, an identification word such as "FET" is used as an identification word for FET evaluation. "TEG_FETA", "TEG_FETB", and "TEG_FETC" can be classified for each use of the TEG in the form of a TEG for FET evaluation. From this information, templates such as "TEG_FETA is at the center within the region", "TEG_FETB is at the center and the left end", and "TEG_FETC is at the center and the right end" for FET evaluation can be created.

[0110] By reusing the created templates, the constraint conditions RCD_1 and RCD_2 described in Embodiment 1 can be easily created.

[0111] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

Description of Reference Numerals

[0112] CLD: Circuit Configuration Data, NLD: Name List Data, OD: Text Data, RCD: Constraint Condition Data, RCD_1: Constraint Condition, RCD_2: Constraint Condition, RCD_3: Constraint Condition, RCD_4: Constraint Condition, 10: Circuit Configuration Data Generation System, 20: Information Terminal, 20a: Information Terminal, 20b: Information Terminal, 20c: Information Terminal, 20d: Information Terminal, 30: Network, 31: Network, 32: Network, 40: Information Processing Device, 50: Data Analysis Unit, 110: Data Storage Unit, 112: Log Data, 120: Prompt Data Creation Unit, 130: Data Processing Unit, 140: Circuit Configuration Data Creation Unit, 150: Data Transmission Unit, 210: Data Storage Unit

Claims

1. A data storage unit, A data processing unit, A prompt data creation unit, A circuit layout data creation unit, and has, The data storage unit has a function of storing the name list data of the TEG, the constraint condition data of the TEG, and the first list data, The data processing unit, A function of outputting the name list data, the constraint condition data, and the first list data to the prompt data creation unit to obtain prompt data, A function of outputting the prompt data to an information processing device having a language model via a network to obtain second list data, A function of outputting the second list data to the circuit layout data creation unit to obtain circuit layout data, The first list data and the second list data are each data representing coordinates on a substrate on which the TEG is arranged, The second list data is data generated by updating the first list data according to the prompt data, A circuit layout data generation system.

2. In Claim 1, The TEG is a circuit element for element characteristic evaluation, A circuit layout data generation system.

3. In Claim 2, The TEGs are grouped according to the use of the TEGs, In the data processing unit, the name list data and the constraint condition data are output to the prompt data creation unit for each use of the grouped TEGs, A circuit layout data generation system.

4. A data storage unit, A data processing unit, A prompt data creation unit, A circuit layout data creation unit, and has, The data storage unit has a function of storing the name list data of the TEG, the constraint condition data of the TEG, and the first list data, The data processing unit, A function of outputting the name list data, the constraint condition data, and the first list data to the prompt data creation unit to obtain first prompt data, A function of outputting the first prompt data to an information processing device having a language model via a network to obtain second list data, A function of updating the first list data stored in the data storage unit to the second list data, A function of outputting the name list data, the constraint condition data, and the second list data to the prompt data creation unit to obtain second prompt data, A function of outputting the second prompt data to the information processing apparatus having the language model via the network to obtain third list data; A function of outputting the third list data to the circuit layout data creation unit to obtain circuit layout data; The first to third list data are each data representing coordinates on a substrate on which the TEG is arranged; The second list data is data generated by updating the first list data according to the first prompt data; The third list data is data generated by updating the second list data according to the second prompt data; A circuit layout data generation system.

5. In claim 4, The TEG is a circuit element for element characteristic evaluation; A circuit layout data generation system.

6. In claim 5, The TEGs are grouped according to the use of the TEGs, In the data processing unit, the name list data and the constraint condition data are output to the prompt data creation unit for each use of the grouped TEGs; A circuit layout data generation system.

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