Complementary transistor device and control method thereof

Abstract

To provide a complementary transistor device capable of forming an inner spacer using sacrificial layers having different Ge contents, and a manufacturing method thereof.SOLUTION: A complementary transistor device 52 includes: a substrate sp; a lower transistor l_tr positioned on the substrate sp and including a lower channel layer l_ch, a lower gate l_mg, and a lower source / drain region p_SD; an upper transistor u_tr positioned on the lower transistor l_tr and including an upper channel layer u_ch, an upper gate u_mg, and an upper source / drain region n_SD; and an inner spacer s_de configured to insulate the lower transistor l_tr from the upper transistor u_tr. The inner spacer s_de may be formed by removing a portion of each of a first sacrificial layer and a second sacrificial layer, which are formed above and below the lower channel layer l_ch and the upper channel layer u_ch and have different Ge contents, to a depth according to a Ge content and then depositing an insulating material.SELECTED DRAWING: Figure 52

Description

Technical Field

[0001] Various embodiments disclosed in this document are related to semiconductor manufacturing technology.

Background Art

[0002] As electronic devices are miniaturized and highly integrated, the semiconductor elements mounted thereon are also highly integrated and ultra-miniaturized. Conventionally, since FETs with a GAA (gate all around) structure are horizontally arranged on a wafer substrate, the number of transistors applicable per unit area of the wafer substrate has been limited.

[0003] To improve this, recently, a CFET (complementary-FET) in a form in which n-MOSFETs and p-MOSFETs with a GAA structure are vertically stacked has been disclosed.

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, since CFET elements have so far been only an idea technology, detailed manufacturing processes have not been disclosed.

[0005] Various embodiments disclosed in this document can provide a complementary transistor element capable of forming an internal spacer using sacrificial layers with different Ge contents and a control method thereof.

Means for Solving the Problems

[0006] The transistor element according to one embodiment disclosed in this document includes a substrate; a lower transistor located on the upper part of the substrate and including a lower channel layer, a lower gate, and a lower source / drain region; an upper transistor located on the upper part of the lower transistor and including an upper channel layer, an upper gate, and an upper source / drain region; and an internal spacer formed by depositing an insulating material after removing a part of each of a first sacrificial layer and a second sacrificial layer having different Ge contents formed above and below the lower channel layer and the upper channel layer at depths corresponding to the Ge contents.

[0007] The method for manufacturing a transistor element according to one embodiment disclosed in this document includes an operation of forming a nanosheet stack including a lower channel layer, an upper channel layer, a first sacrificial layer separating between the lower channel layer and the upper channel layer, and a plurality of second sacrificial layers; the first and second sacrificial layers have different Ge contents from each other, and an operation of forming an internal spacer in a space provided by removing a part of the first sacrificial layer and a part of the second sacrificial layer through an etching process at a speed corresponding to the Ge content; and an operation of forming a lower gate around the lower channel layer and an upper gate around the upper channel layer in a space provided by removing the remaining parts of the first and second sacrificial layers, respectively.

[0008] Also, the transistor element according to one embodiment disclosed in this document includes a substrate; a lower transistor located on the upper part of the substrate and including a lower channel layer, a lower gate, and a lower source / drain region; an upper transistor located on the upper part of the lower transistor and including an upper channel layer, an upper gate, and an upper source / drain region; and between the lower channel layer and the upper channel layer, an upper end portion of the lower gate, an insulator (s_de), and a lower end portion of the upper gate are provided, and when viewed from one side of the transistor element, a width of a part of at least one of the upper end portion of the lower gate, the insulator, and the lower end portion of the upper gate may be formed thinner than the remaining widths of the lower gate and the upper gate formed at the lower part of the lower channel layer and the upper part of the upper channel layer, respectively.

Effects of the Invention

[0009] According to various embodiments disclosed in this document, internal spacers can be formed using sacrificial layers with different Ge contents. In addition, various effects directly or indirectly understood through this document can be provided.

Brief Description of the Drawings

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[0011] In relation to the description of the drawings, the same or similar reference numerals may be used for the same or similar components.

Best Mode for Carrying Out the Invention

[0012] FIG. 1 and FIG. 2 show a process of forming a nanosheet stack of a semiconductor element according to an embodiment.

[0013] Referring to FIG. 1, a lower isolation layer can be formed on the semiconductor substrate sp.

[0014] The semiconductor substrate sp can include a silicon substrate and an SOI (Si-on-Insulator) substrate. The semiconductor substrate sp can be p-type or n-type, or can include an intrinsic silicon substrate.

[0015] The lower isolation layer can be formed by forming an insulating material on the upper part of the semiconductor substrate sp, or can be formed through appropriate ion implantation (Ground Plane Doping) on the semiconductor substrate sp. The lower isolation layer of the semiconductor substrate sp can act to reduce leakage current in the off state of the channel formed in the semiconductor substrate sp.

[0016] The lower isolation layer can form a metal gate around the Si channel layer after selective etching of the SiGe sacrificial layer with a replacement metal gate (RMG) module. Then, the metal gate of the lower isolation layer is in contact with the semiconductor substrate sp and the source / drain is formed below the lower isolation layer, so that the lower isolation layer has a planar FET structure.

[0017] As shown in FIG. 2, a nanosheet stack ns_s can be formed by repeatedly and continuously growing a Si epitaxial layer (Si) and SiGe epitaxial layers (SiGe1 and SiGe2) on the semiconductor substrate sp. In this regard, the Si epitaxial layer can constitute the channel layers of the stacked n-MOSFET and p-MOSFET elements of the CFET structure. The first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 can be sacrificial layers that are all removed through selective etching in subsequent process steps. The first sacrificial layer SiGe1 is formed on the upper and lower parts of at least the lower channel layer l_ch and the upper channel layer u_ch respectively, and the second sacrificial layer SiGe2 can be formed between the first sacrificial layer SiGe1 that is between at least the lower channel layer l_ch and the upper channel layer u_ch.

[0018] In FIG. 2, the case where two channel layer Si of n-MOSFET and p-MOSFET elements are formed respectively is illustrated as an example. However, it is not limited thereto. For example, the number of channel layer Si can be one or three or more, and the number of Si channels can be determined through the repeated growth of SiGe epitaxial layer and Si epitaxial layer. Similarly, the number and type of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 are not limited to those in FIG. 2. For example, it can further include at least one type of sacrificial layer. And the number of the second sacrificial layer (SiGe2) or the first and second sacrificial layers SiGe1 and SiGe2 can be different from that in FIG. 2.

[0019] Since silicon (Si) and germanium (Ge) have a lattice constant difference of about 4.3%, stress may occur in the thin film during the repeated growth of SiGe epitaxial layer and Si epitaxial layer. When the thin film exceeds the critical thickness due to the stress generation state, the stress is relaxed by releasing the accumulated stress energy. Then, a potential (dislocation) is generated at the interface, which may cause a decrease in the device performance and leakage current.

[0020] To prevent this, the Si epitaxial layer (Si) and the SiGe epitaxial layers SiGe1 and SiGe2 can be grown in at least one process capable of low vacuum among RPCVD, UHVCVD, MBE, and ALD growth methods. Thereby, the crystallinity of the channel layer can be ensured and the composition and thickness can be precisely controlled.

[0021] The thickness of the Si epitaxial layer (Si) (channel layer) can be formed to be 5 nm to 30 nm. The thickness of the SiGe1 and SiGe2 epitaxial layers (SiGe1 and SiGe2) (sacrificial layers) can be formed to be 5 nm to 30 nm. The SiGe1 epitaxial layer located at the top can be formed thicker than other layers in consideration of the thickness reduction in subsequent processes. For example, the top SiGe1 epitaxial layer can be formed with a thickness of 5 nm to 100 nm.

[0022] According to an embodiment, the epitaxial layer can be formed so as to prevent the generation of a space left during the formation of an internal space (internal spacer) in a subsequent process. For example, the Ge content of the SiGe1 layer can progress epitaxial growth at a ratio of 10% to 30%. The Ge content of the SiGe2 layer can progress epitaxial growth at a ratio 20% or more higher than the Ge content of the SiGe1 layer. That is, the first sacrificial layer SiGe1 can be a SiGe layer having a Ge content of 10% to 30%. The second sacrificial layer SiGe2 can be a SiGe layer having a Ge content 20% or more higher than that of the first sacrificial layer.

[0023] FIGS. 3 to 7 show a process of forming a STI (Shallow Trench Isolation) module of a semiconductor device according to an embodiment.

[0024] As shown in FIG. 3, an upper layer portion up_l including a part of the nanosheet stack ns_s and the semiconductor substrate sp is etched in a protruding form using, for example, a hard mask. The upper layer portion up_l process is a process for forming a trench isolation portion for separating elements and can be the same as or similar to the process of forming the Fin of a Fin-FET.

[0025] As shown in FIG. 4, a silicon nitride film (SixNy) liner layer ln1 is formed on the upper layer portion up_l by a deposition method such as LPCVD, PECVD, or ALD. The liner layer ln1 can be formed with a thickness of 30 nm or less. The liner layer ln1 can prevent the oxidation of the Si epitaxial layer and the SiGe1 / SiGe2 epitaxial layer and prevent the diffusion of germanium during a subsequent trench isolation portion formation process.

[0026] As shown in FIG. 5, a silicon oxide film sl1 is grown on the front surface of the semiconductor substrate 4 of FIG. 4 to fill the region etched through FIG. 3. Thereafter, a part of the silicon oxide film sl1 is planarized in a chemical mechanical polishing (CMP) process. Here, the silicon oxide film sl1 can be densified through a high-temperature heat treatment process before the planarization process of the silicon oxide film sl1. The high-temperature heat treatment is carried out at a temperature of 900° C. or lower to prevent Ge diffusion from the SiGe layer to the Si channel layer. At this time, the silicon nitride film liner layer ln1 can be used as an etch stop layer in the planarization process of the silicon oxide film sl1. Or the planarization process can be carried out until the silicon nitride film liner layer ln1 is exposed.

[0027] As shown in FIG. 6, a part of the silicon oxide film sl1 can be etched in an etch-back process. At this time, the etch-back process can be carried out to a depth at which the silicon nitride film liner layer ln1 is not etched. In this regard, the etch-back process can be carried out by utilizing a process having a high etch selectivity to silicon nitride film (Si x N y ). At this time, the STI module STI corresponding to the remaining silicon oxide film sl1 can be provided lower than the starting height of the Si, SiGe1, and SiGe2 epitaxial layers. Thereby, the Si, SiGe1, and SiGe2 epitaxial layers can all be exposed in subsequent processes.

[0028] As shown in FIG. 7, a silicon nitride film liner layer ln2 can be grown on the upper part of the STI module STI with a thickness of 30 nm or less. In this case, in FIG. 6, the liner layer ln1 etched together with the silicon oxide film sl1 can also be regrown. In the following description, the case where FIG. 7 is not carried out will be taken as an example for explanation. However, it is not limited thereto.

[0029] FIGS. 8 to 15 show a dummy gate layer module forming process of a semiconductor device according to an embodiment.

[0030] As shown in FIG. 8, a dummy gate layer (Dummy Gate) Dg can be grown on the entire upper surface of the semiconductor substrate sp. Subsequently, the dummy gate layer Dg is planarized in a chemical mechanical polishing process. The dummy gate layer can be formed using polycrystalline Si or SiGe, amorphous Si or SiGe. Alternatively, the dummy gate layer Dg may be formed using a silicon nitride film protective layer and other substances having a high etching selectivity. Here, the planarization process of the dummy gate layer Dg can be performed so that the liner layers ln1 and ln2 are not exposed. The remaining dummy gate layer Dg after planarization can be an area where a high-k dielectric film and a gate metal are deposited through subsequent processes to form a gate stack.

[0031] As shown in FIG. 9, a dummy gate cap layer Dgc can be deposited on the upper part of the planarized dummy gate layer dg using a silicon nitride film. The dummy gate cap layer Dgc can be utilized as a hard mask during the etching of the channel layer.

[0032] Referring to FIG. 10, for example, the dummy gate cap layer Dgc, which is a silicon nitride film, is patterned through a dry etching process. The etching process can proceed, for example, in a photolithography and dry etching process according to the silicon channel length (or the gate width of the region where the source / drain is formed) of the semiconductor element according to an embodiment.

[0033] Referring to FIG. 11, the dummy gate layer dg is etched according to the silicon channel length of the semiconductor element according to an embodiment by utilizing the dummy gate cap layer Dgc as a hard mask.

[0034] Hereinafter, the process of forming an external spacer on the side surface of the dummy gate layer Dg will be described with reference to FIGS. 12 to 15.

[0035] As shown in FIG. 12, an external spacer os1 is formed on the side surface of the dummy gate layer Dg. The external spacer os1 forms a silicon oxide film by a thermal oxidation process at a temperature of 900° C. or lower. During the thermal oxidation process, since the silicon oxide film grows simultaneously in a direction away from the horizontal center of the semiconductor substrate sp from the initial interface, the thickness of the external spacer os1 can be formed in consideration of the width of the channel layer.

[0036] Alternatively, as shown in FIGS. 13 to 14, the external spacer os2 can be formed by a process different from that in FIG. 12. As shown in FIG. 13, the external spacer os2 can be formed by growing a specified material using ALD or CVD method over the entire wafer surface. The specified material can include at least one material among silicon oxide films such as SiN, SiO, SiC, SiCO, SiCN, silicon nitride films, and silicon carbide. Additionally, as shown in FIG. 14, the upper portion of the grown external spacer layer os2 is etched by an anisotropic etching process so that the external spacer os2 remains only on the side surfaces of the dummy gate layer dg and the dummy gate cap layer Dgc. In the following description, the case where the external spacer os1 in FIG. 12 is applied is illustrated as an example. However, it is not limited thereto.

[0037] As shown in FIG. 15, the silicon nitride film ln2 is selectively wet-etched or dry-etched using a high selectivity to the silicon oxide film os1. By etching the silicon nitride film ln2, the upper portion of the SiGe sacrificial layer SiGe1 can be exposed. At this time, the dummy gate cap layer Dgc is also etched simultaneously with the silicon nitride film, but the process is controlled so that the dummy gate cap layer Dgc is not completely removed.

[0038] Hereinafter, with reference to FIGS. 16 to 21, a process for forming an inner spacer module of a semiconductor device according to an embodiment will be described.

[0039] As shown in FIG. 16, using the dummy gate cap layer Dgc, which is a silicon nitride film, and the external spacer os1 as a hard mask, a part of the Si channel layer Si, the first sacrificial layer SiGe1, and the second sacrificial layer SiGe2 is etched. In FIG. 16, the process can be controlled so that only the Si channel layer Si, the first sacrificial layer SiGe1, and the first sacrificial layer SiGe2 are selectively etched using a process with a high etch selectivity with respect to the silicon oxide film and the silicon nitride film. In FIG. 16, the etch depth can proceed to a depth at which the nano-sheet stack ep including the Si channel layer Si, the first and second sacrificial layers SiGe1 and SiGe2 is all exposed and the trench isolation part (STI module STI) is exposed.

[0040] As shown in FIG. 16, in a structure in which the Si channel layer Si and the first and second sacrificial layers SiGe1 and SiGe2 are exposed, as shown in FIG. 17, the cavity etching process of the first and second sacrificial layers SiGe1 and SiGe2 for forming the internal spacer is1 proceeds.

[0041] In the cavity etching process, not all of the first and second sacrificial layers SiGe1 and SiGe2 are etched, and only the first and second sacrificial layers SiGe1 and SiGe2 having a width of the internal spacer can be selectively wet-etched or dry-etched. Since the internal spacer is1 determines the Si channel length and serves as a self-aligned mask during source / drain formation, uniformity is always necessary.

[0042] The cavity etching process of the first and second sacrificial layers SiGe1 and SiGe2 has a very high selectivity for the dummy gate cap layer Dgc, the external spacer os1, and the Si channel layer Si, and the etching rate must increase according to the Ge content in the first and second sacrificial layers SiGe1 and SiGe1.

[0043] Through such an etching process, the etching depth in the SiGe2 layer having a Ge content 20% or more higher than that of SiGe1 must be greater than the etching depth of the SiGe1 layer.

[0044] As shown in FIG. 18, the internal spacer is1 is deposited on the entire surface where the SiGe cavity etching process has proceeded by using the ALD deposition method. The internal spacer is1 can be formed using a specified material. The specified material can include at least one material among silicon oxide films such as SiN, SiO, SiC, SiCO, SiCN, silicon nitride films, and silicon carbide.

[0045] As shown in FIG. 19, when the specified material is formed on the remaining side surfaces of the first and second sacrificial layers SiGe1 and SiGe2 in FIG. 16 by using the ALD deposition method, the side surfaces of the internal spacer is1 can gradually become flat.

[0046] FIG. 20 shows the deposition result of the specified material when only the first sacrificial layer SiGe1 according to another embodiment is used.

[0047] Referring to FIG. 20, it can be seen that, different from one embodiment, when only the SiGe sacrificial layer SiGe1 with the same Ge content is used, no insulating material is deposited on the side surface of the first sacrificial layer SiGe1. In this case, since the gap between the n-MOSFET and the p-MOSFET stacked up and down in subsequent processes is not electrically insulated, the CFET structure cannot be formed. Specifically, in the case of FIG. 20, the thickness of the inner spacer formed on the side surface of the first sacrificial layer SiGe1 between the upper channel layer and the lower channel layer is the same as the thickness of the inner spacer on the side surface of the Si channel layer. Accordingly, since the etching proceeds at the same thickness when the formed internal spacer is etched, there may be a space left in the internal spacer. Therefore, there may be a problem that the source / drain is formed in an unnecessary portion during subsequent source / drain epitaxial growth.

[0048] FIG. 21 is a drawing for explaining the internal spacer of a semiconductor element.

[0049] Referring to FIG. 21, a part of the internal spacer material deposited on the semiconductor substrate sp is removed through an etching process. In the etching process, the internal spacer material deposited on the side surfaces of the Si channel layer Si, the upper and side surfaces of the dummy gate layer Dg and the dummy gate cap layer Dgc is etched. The material of the internal spacer is deposited thicker than the Si channel layer Si on the first and second sacrificial layers SiGe1 and SiGe2. In the etching process, the etching of the internal spacer is1 can be adjusted so that only the side surfaces of the Si channel layer Si are exposed. The etching process can proceed, for example, through wet and dry etching processes or an ALE (atomic layer etch) process. The material of the internal spacer remaining through the above-described etching process can form the internal spacer is1 as shown in FIG. 21.

[0050] Hereinafter, with reference to FIG. 22, the source / drain formation process of the n-MOSFET and the p-MOSFET will be described.

[0051] FIG. 22 is a drawing for explaining an epitaxial growth process for forming a lower source / drain according to an embodiment.

[0052] Referring to FIG. 22, selective epitaxial growth is performed on the source / drain regions p_S0 and p_SD using the exposed silicon in the Si channel layer Si and the lower isolation layer of the silicon substrate sp as seed layers. The selective epitaxial growth does not proceed on the silicon oxide film (e.g., the internal spacer is1), but only on the portions where silicon is exposed. The lower p-MOSFET of the CFET element according to an embodiment is formed. For this purpose, a SiGe epitaxial layer with real-time doping of a p-type dopant can be selectively grown. Alternatively, doping can be performed through an ion implantation process of a p-type dopant after selectively growing the SiGe epitaxial layer. At this time, the Ge content of the source / drain regions p_S0 and p_SD can be provided at 20% or more.

[0053] In Fig. 22, it can be seen that not only in the lower p-MOSFET but also in the upper Si channel layer, an unnecessary p-type dummy source / drain region is formed together with the p-type source / drain region p_SD. However, depending on the structure of the designed CFET device, the upper dummy source / drain p_S0 is removed through subsequent processes.

[0054] Hereinafter, the n-MOSFET and p-MOSFET device formation and isolation processes will be described with reference to Figs. 23 to 28.

[0055] Fig. 23 is a drawing showing the process of covering a semiconductor substrate with an insulator (organic solvent) according to an embodiment.

[0056] Referring to Fig. 23, an organic solvent l_de is formed at a height that covers the entire dummy gate layer on the semiconductor substrate. The organic solvent l_de is an organic solvent for semiconductors and can contain, for example, PGMEA (propylene glycol methyl ether acetate), PGPE (propylene glycol propyl ether), cyclohexanone, EL (ethyl lactate), GBL (γ-butyrolactone), or NMP (N-methylpyridine). The organic solvent can be one used for PR, BARC, or SoC (spin on carbon), etc.

[0057] Fig. 24 shows the etch-back process of the organic solvent l_de for semiconductors.

[0058] As shown in Fig. 24, a part of the organic solvent l_de for semiconductors can be removed through the etch-back process. As a result, the source / drain region p_S0 formed in the upper n-MOSFET is completely exposed, and the source / drain region p_SD formed in the lower p-MOSFET can be formed in a state covered by the organic solvent l_de for semiconductors.

[0059] Fig. 25 is a drawing for explaining the etching process of the upper source / drain SiGe epitaxial layer.

[0060] As shown in FIG. 25, the dummy source / drain region p_S0 formed in the upper n-MOSFET is selectively removed by a wet or dry etching process. The etching process can be precisely advanced so as not to affect the Si channel layer Si by using a process having a high selectivity ratio with respect to the Si channel layer Si.

[0061] FIG. 26 is a drawing for explaining the removal process of the organic solvent l_de for semiconductors.

[0062] As shown in FIG. 26, the organic solvent l_de for semiconductors formed on the upper part of the lower p-MOSFET can be removed. For example, the organic solvent l_de for semiconductors can be removed by an etch-back process.

[0063] FIG. 27 is a drawing for explaining the insulation process of the n-MOSFET and P-MOSFET according to an embodiment.

[0064] Referring to FIG. 27, as in the first step (S27_1), a silicon oxide film sl2 is formed on the entire surface of the semiconductor substrate (for example, the space where the dummy source / drain region p_S0 and the organic solvent l_de are removed). Thereafter, as in the second step (S27_2), a part of the silicon oxide film sl2 is removed by an etch-back process. As a result, the silicon oxide film sl2 remains only on the upper part of the p-MOSFET, and the Si channel layer Si of the upper n-MOSFET element is completely exposed.

[0065] FIG. 28 is a drawing for explaining the source / drain formation process of the upper n-MOSTFET according to an embodiment.

[0066] As shown in FIG. 28, a source / drain region n_SD of an n-MOSFET is formed in the upper Si channel layer Si where silicon is exposed. For example, a Si epitaxial layer in which an n-type dopant is doped in real time can be selectively grown. As another example, by performing doping through an ion implantation process of an n-type dopant after selectively growing a Si epitaxial layer, the source / drain region n_SD of the n-MOSFET can be formed.

[0067] Hereinafter, a replace metal gate (RMG) formation process will be described with reference to FIGS. 29 to 44. This can be a process in which a dummy gate layer Dg is converted into an actual metal gate region.

[0068] FIGS. 29 and 30 are drawings for explaining an ILD formation process.

[0069] As shown in FIG. 29, an inter layer dielectric (ILD), which is a silicon oxide film layer, is formed on the entire surface of the semiconductor substrate (for example, with a thickness that covers the silicon oxide film sl2 and the dummy gate cap layer Dgc on the upper surface of the upper source / drain region n_S / D).

[0070] As shown in FIG. 30, the dummy gate cap layer Dgc is exposed by planarizing the ILD formed on the semiconductor substrate sp through a CMP process. At this time, the dummy gate cap layer Dgc, which is a silicon nitride film, can be used as a stop layer for the planarization process. After the planarization process, the upper surface of the dummy gate cap layer Dgc can be completely exposed.

[0071] FIGS. 31, 32, and 33 are drawings for explaining an exposure process of first and second sacrificial layers SiGe1 and SiGe2.

[0072] As shown in FIG. 31, the dummy gate cap layer Dgc is completely removed by utilizing a wet or dry etching process having a high etching selectivity ratio in the ILD (silicon oxide film) layer ILD1.

[0073] As shown in FIG. 32, the dummy gate layer Dg is completely removed by utilizing an etching process having a high etching selectivity with respect to the silicon oxide film. The silicon nitride film protective layer ln2 below the dummy gate layer Dg completely surrounds the Si channel layer Si. Therefore, the dummy gate layer Dg can be removed by wet etching.

[0074] As shown in FIG. 33, a designated etching process is utilized to remove the silicon nitride film protective layer ln2 so that the Si channel layer Si, the inner spacer is1, and the first and second sacrificial layers SiGe1, SiGe2 are exposed. The etching process of FIG. 33 can utilize an etching process having a high etching selectivity with respect to the silicon nitride film.

[0075] FIG. 34 is a drawing for explaining the first and second sacrificial layer SiGe1, SiGe2 etching process.

[0076] As shown in FIG. 34, the first and second sacrificial layers SiGe1, SiGe2 are selectively etched with the sides of the first and second sacrificial layers SiGe1, SiGe2 and the Si channel layer Si exposed. It is important that the etching process of the first and second sacrificial layers SiGe1, SiGe2 has a very high selectivity with respect to the ILD layer ILD1, the outer spacer os1, the inner spacer is1, and the Si channel layer Si. Selective etching of the first and second sacrificial layers SiGe1, SiGe2 is possible by either dry etching or wet etching methods. The first and second sacrificial layers SiGe1, SiGe2 are selectively etched on both sides of the silicon channel width.

[0077] FIG. 35 is a drawing for explaining the gate dielectric insulating film forming process.

[0078] As shown in FIG. 35, a gate dielectric insulating film sl3 is formed on all surfaces of the Si channel layer Si, both side cross-sections of the internal spacer is1, and the surfaces where the semiconductor substrate is exposed. The gate dielectric insulating film sl3 can be formed of silicon oxide, silicon nitride, or a high-k dielectric material. The high-k dielectric material can include metal oxides and silicates made of Hf, Zr, Al, La, Mg, Ba, Ti respectively, or combinations of Hf, Zr, Al, La, Mg, Ba, Ti respectively. The gate dielectric insulating film sl3 can be deposited with the same thickness on the three-dimensional channel by the ALD (Atomic layer deposition) method.

[0079] FIG. 36 is a drawing for explaining the p-type work function metal formation process.

[0080] As shown in FIG. 36, a p-type work function metal is formed on all surfaces outside the gate dielectric insulating film sl3. Since the p-type work function metal Wf1 must be formed very thinly and with a constant thickness, it can be formed by the ALD method.

[0081] FIG. 37 is a drawing for explaining the metal gate formation process.

[0082] As shown in FIG. 37, the gate dielectric insulating film Sl3 and the p-type work function metal Wf1 of the semiconductor substrate are formed, and the remaining part is filled entirely with the metal gate L_mg.

[0083] The metal gate L_mg can be formed in at least one form containing at least one of the materials Ti, Al, Cu, W. The metal gate L_mg can be formed in the same ALD process as the gate dielectric insulating film sl3 and the p-type work function metal Wf1. Alternatively, the metal gate l_mg can be formed by methods such as electroplating or electroless plating.

[0084] FIG. 38 is a drawing for explaining the etch-back process of the metal gate.

[0085] As shown in FIG. 38, an etch-back process for the metal gate l_mg is performed. The height of the metal gate l_mg is adjusted at the height between the n-MOSFET and the p-MOSFET. The metal gate l_mg can be advanced by wet etching for the etching process of the three-dimensional complex structure.

[0086] FIG. 39 is a drawing for explaining the etching process of the p-type work function metal Wf1.

[0087] As shown in FIG. 39, the portions formed around and on the sidewalls of the Si channel layer where the upper n-MOSFET is formed in the p-type work function metal Wf1 can be selectively etched.

[0088] FIGS. 40 and 41 are drawings for explaining the insulator formation process for separating between the n-MOSFET and the p-MOSFET.

[0089] As shown in FIG. 40, an insulator s_de is formed at a high thickness over the entire semiconductor substrate.

[0090] As shown in FIG. 41, the insulator s_de formed over the entire surface of the semiconductor substrate (e.g., on the upper surface of the metal gate l_mg) is removed by an etch-back process to form up to the upper part of the p-MOSFET metal gate.

[0091] FIG. 42 is a drawing for explaining the n-type work function metal formation process.

[0092] As shown in FIG. 42, an n-type work function metal (work function metal) Wf2 is formed on all surfaces of the gate dielectric insulating film of the upper n-MOSFET Si channel layer. Since the n-type work function metal Wf2 must be formed very thinly and with a constant thickness, it can be formed by the ALD method.

[0093] FIGS. 43 and 44 are drawings for explaining the gate metal formation process.

[0094] As shown in FIG. 43, the remaining portion where the gate dielectric insulating film sl3 and the n-type work function metal are formed is entirely filled with the metal gate u_mg. The metal gate u_mg can be formed in the form of at least one layer containing at least one material among Ti, Ti, Al, Cu, and W. The metal gate u_mg can be formed by at least one method among ALD, electroplating, or electroless plating.

[0095] As shown in FIG. 44, the portion where the gate dielectric insulating film sl3, the n-type work function metal Wf2, and the metal gate u_mg exceed the upper part of the ILD layer can be planarized by utilizing a metal CMP process.

[0096] Hereinafter, the metal wiring formation process will be described with reference to FIGS. 45 to 51.

[0097] As shown in FIG. 45, a second ILD layer ILD2 is formed on the entire surface of the semiconductor substrate (e.g., the upper surface of the gate dielectric insulating film sl3 and the metal gate u_mg).

[0098] As shown in FIG. 46, a metal contact portion Mc1 is formed in the source / drain region of the lower p-MOSFET (hereinafter, may be referred to as the "lower source / drain region") p_SD and the metal gate region L_mg. The (metal) metal contact portion Mc1 can be formed through photolithography and dry etching processes for at least a part of each of the second ILD layer ILD2, the lower source / drain region p_SD, and the lower gate region L_mg.

[0099] FIGS. 47 to 48 show the metal plug formation process.

[0100] As shown in FIG. 47, a first metal plug Mp1 is formed in the upper source / drain region n_SD and the metal contact portion Mc1.

[0101] As shown in FIG. 48, the portion of the first metal plug Mp1 formed on the upper part of the second ILD layer ILD2 can be sufficiently planarized by utilizing a metal CMP process. Thereafter, a metal wiring process for the first metal plug Mp1 is advanced.

[0102] FIGS. 48 to 51 show a second metal plug forming process.

[0103] As shown in FIG. 48, only the source / drain contact portion Mc2 of the first metal plug Mp1 is exposed and a metal etch-back process is advanced.

[0104] As shown in FIG. 49, an insulating film De2 is formed over the entire wafer (e.g., at least a part of the source / drain contact portion Mc2).

[0105] As shown in FIG. 50, an etch-back process of the insulating film De2 is advanced so that the source / drain regions of the upper n-MOSFET elements are exposed.

[0106] As shown in FIG. 51, a second metal plug Mp2 can be formed in the source / drain regions of the upper n-MOSFET elements. Thereafter, a metal wiring process for the second metal plug Mp2 can be advanced.

[0107] Thus, the CFET (Complementary-FET) semiconductor device 51 according to one embodiment can form the source / drain regions of the n-MOSFET and the p-MOSFET through a relatively simple process.

[0108] Also, the CFET semiconductor device 51 according to one embodiment can be fabricated by laminating SiGe sacrificial layers having different Ge contents so that no space is created during the formation of internal spacers, and by repeatedly laminating the SiGe sacrificial layers, the distance between the n-MOSFET and the p-MOSFET can be sufficiently formed as desired.

[0109] FIG. 52 shows the structure of a complementary transistor device according to one embodiment.

[0110] Referring to FIG. 52, a complementary transistor element 52 according to an embodiment may include a substrate sp, a lower transistor u_tr, an upper transistor u_tr, and an internal spacer is1. In FIG. 52, the case where the complementary transistor element 52 includes a total of two upper transistors u_tr and lower transistors u_tr is taken as an example for explanation. However, it is not limited thereto.

[0111] The lower transistor u_tr is located above the substrate sp and may include a lower channel layer l_ch, a lower gate l_mg, and a lower source / drain region p_SD.

[0112] The upper transistor u_tr is located above the lower transistor u_tr and may include an upper channel layer u_ch, an upper gate u_mg, and an upper source / drain region n_SD.

[0113] Although the lower channel layer l_ch and the upper channel layer u_ch are formed by epitaxial growth, after being formed to include a first sacrificial layer SiGe1 and a second sacrificial layer SiGe2 between the lower channel layer l_ch and the upper channel layer u_ch, they can be formed to correspond to each transistor u_tr, l_tr through etching in the y direction corresponding to the channel length and removal of the first and second sacrificial layers SiGe1, SiGe2.

[0114] Although the lower source / drain region p_SD selectively grows a Si epitaxial layer on the sidewalls of the lower channel layer on the substrate, it can be formed by doping a first dopant (e.g., a p-type dopant).

[0115] The upper source / drain region n_SD can be formed after removing the dummy source / drain region formed on the sidewalls of the upper channel layer together with the lower source / drain region while covering the lower source / drain region p_SD with an organic solvent l_de, and then removing the organic solvent. The upper source / drain region n_SD can be formed by epitaxially growing the upper channel layer in a state where a silicon oxide film is formed only on the upper part of the lower transistor from which the organic solvent l_de has been removed.

[0116] The internal spacer is1 can be formed by depositing an insulating material after removing a part of each of the first sacrificial layer SiGe1 and the second sacrificial layer SiGe2 with different Ge contents formed above and below the lower channel layer l_ch and the upper channel layer at depths corresponding to the Ge contents. The internal spacer is1 insulates between the lower gate u_mg and the lower source / drain region p_SD and between the upper gate u_mg and the upper source / drain region n_SD, so that it can function as a side wall that prevents the gate length (or channel length) from becoming lower than a certain value. The internal spacer is1 is further formed between the lower transistor u_tr and the upper transistor u_tr to separate the lower transistor u_tr and the upper transistor u_tr from each other.

[0117] The internal spacer is1 can be located between the lower channel layer l_ch and the upper channel layer u_ch to insulate between the lower transistor u_tr and the upper transistor u_tr.

[0118] Side walls of a part of the internal spacer is1 can be formed thicker than the side walls of the lower gate u_mg and the upper gate u_mg formed above and below the lower channel layer l_ch and the upper channel layer u_ch, respectively.

[0119] The first sacrificial layer SiGe1 can be a SiGe layer having a Ge content of 10% to 30%. The second sacrificial layer SiGe2 can be a SiGe layer having a Ge content 20% or more higher than that of the first sacrificial layer.

[0120] The internal spacer is1 has a higher etching selectivity with respect to the first and second sacrificial layers SiGe1 and SiGe2 than the channel layers u_ch and l_ch, and etches the second sacrificial layer SiGe2 deeper than the first sacrificial layer SiGe1 through cavity etching at a rate corresponding to the Ge content, and can be formed by depositing the insulating material outside the remaining layers after etching.

[0121] The first sacrificial layer SiGe1 is formed at least on the upper and lower portions of the lower channel layer l_ch and the upper channel layer u_ch respectively, and the second sacrificial layer SiGe2 can be formed between the first sacrificial layers SiGe1 that are at least between the lower channel layer l_ch and the upper channel layer u_ch.

[0122] The complementary transistor element 52 can further include a silicon oxide film sl2. The silicon oxide film sl2 can insulate the lower source / drain region p_SD and the upper source / drain region p_SD between the upper surface of the lower source / drain region p_SD and the lower surface of the upper source / drain region p_SD by connecting to the upper surface of the lower source / drain region p_SD and the lower surface of the upper source / drain region p_SD.

[0123] A first work function metal () is formed between the lower channel layer l_ch and the lower gate u_mg, and a second work function metal () is formed between the upper channel layer u_ch and the upper gate u_mg. The first and second work function metals WF1 and WF2 can have the same channel characteristics as the lower gate u_mg and the upper gate u_mg respectively.

[0124] The complementary transistor element 52 can further include an insulator s_de that insulates the lower gate u_mg and the upper gate u_mg between the lower gate u_mg and the upper gate u_mg.

[0125] FIG. 53 shows a flowchart of a manufacturing method of a complementary transistor element according to an embodiment.

[0126] Referring to FIG. 53, in operation 5310, a nanosheet stack ns_s including a lower channel layer l_ch, an upper channel layer u_ch, a first sacrificial layer SiGe1 separating the lower channel layer l_ch and the upper channel layer u_ch, and a plurality of second sacrificial layers SiGe1 can be formed through epitaxial growth. The first and second sacrificial layers SiGe1, 2 can have different Ge contents from each other.

[0127] In operation 5320, a part of each of the first and second sacrificial layers SiGe1, SiGe2 can be removed through an etching process at a rate according to the Ge content. For example, a part of the first and second sacrificial layers SiGe1, SiGe2 can be removed as shown in FIG. 17.

[0128] In operation 5330, an internal spacer is1 can be formed in the space where a part of the first and second sacrificial layers SiGe1, SiGe2 has been removed. For example, the internal spacer is1 can be formed in the space where a part of the first and second sacrificial layers SiGe1, SiGe2 has been removed as shown in FIGS. 18 to 19. In operation 5330, the internal spacer is1 can be formed as sidewalls for the remaining parts of the first and second sacrificial layers SiGe1, SiGe2 above and below the upper channel layer u_ch and the lower channel layer l_ch, respectively.

[0129] In operation 5340, an upper source / drain region n_SD and a lower source / drain region p_SD can be formed. For example, the upper source / drain region n_SD and the lower source / drain region p_SD can be formed as shown in FIGS. 22 to 28.

[0130] In operation 5350, the remaining parts of the first and second sacrificial layers SiGe1, SiGe2 can be removed. For example, the remaining parts of the first and second sacrificial layers SiGe1, SiGe2 can be removed as shown in FIG. 34.

[0131] In operation 5360, a lower metal gate l_mg and an upper metal gate u_mg can be formed in the space where the first and second sacrificial layers SiGe1 and SiGe2 have been removed. The lower gate l_mg can be formed around the lower channel layer l_ch, and the upper gate u_mg can be formed around the upper channel layer u_ch.

[0132] The various embodiments of this document and the terms used herein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or alternatives of the corresponding embodiments. In connection with the description of the drawings, similar or related reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item can include one or more of the said items unless clearly indicated otherwise in the relevant context. In this document, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase of the text, or all possible combinations thereof. Terms such as "first", "second", or "first" or "second" may be used merely to distinguish the corresponding components from other corresponding components and do not limit the corresponding components in other aspects (e.g., importance or order).

[0133] The embodiments described in this specification will be described with reference to cross-sectional views which are ideal schematic diagrams of the present invention. Therefore, the form of the exemplary diagrams may be deformed by manufacturing techniques and / or tolerances, etc. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the forms generated by the manufacturing process.

[0134] Note that in some alternative embodiments, the functions / operations shown in the flowchart blocks of this specification may be performed out of the order shown in the flowchart. For example, two blocks shown consecutively may actually be performed substantially simultaneously. Or the blocks may sometimes be executed in reverse order depending on the related functions / operations. Also, the functions of a given block in the flowchart and / or block diagram may be separated into multiple blocks, and / or the functions of two or more blocks in the flowchart and / or block diagram may be at least partially integrated. Additionally, other blocks may be added / inserted between the illustrated blocks, and / or blocks / operations may be omitted without departing from the scope of the technical idea of the present invention.

[0135] Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries may be understood not to be ideally or overly interpreted unless specifically defined otherwise.

[0136] The terms used herein are for the purpose of describing embodiments and are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated otherwise in the context. In this application, terms such as "including" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should not be construed as precluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0137] When one component is "coupled", "connected", or "responsive" to another component, or is referred to as "on" another component, it can be directly coupled, connected, or responsive to the other component or there can be intervening components between or on the other components. In contrast, when one component is "directly coupled", "directly connected", or "directly responsive" to another component, or is "directly on" another component, there are no intervening components therebetween. As used herein, the term "and / or" includes any one or more, or all combinations of the associated listed items. Further, the symbol " / " (e.g., as used in the term "source / drain") will be understood to have the same meaning as the term "and / or".

[0138] The terms "first", "second", etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a "first component" may be named a "second component".

[0139] Spatially relative terms such as "below", "beneath", "lower", "above", "on", "upper", etc. may be used to facilitate description of the correlation between one element or component and another element or component as illustrated in the drawings. Spatially relative terms are to be understood to include different orientations of the elements relative to each other during use or operation in addition to the orientation shown in the drawings. For example, if an element illustrated in the drawings is turned over, an element described as "below or beneath" another element may be located "above" the other element. Thus, the exemplary term "below" can encompass all directions of up and down. The element may be oriented in other directions (e.g., rotated 90 degrees or otherwise), and in such cases, the spatially relative terms may be interpreted accordingly.

[0140] In this specification, many other embodiments are disclosed in relation to the drawings and the foregoing description. It should be understood that it would be overly repetitive and confusing to fully describe and depict all combinations and subcombinations of such embodiments. Accordingly, the detailed description including the drawings is to be regarded as a complete description of all combinations and subcombinations of the embodiments described herein, and the methods and processes of making and using them, and is to be construed as supporting claims to such combinations or subcombinations.

[0141] Since the previously disclosed inventions are considered as examples, they should not be construed in a limiting sense, and the appended claims are to be understood to include modifications, additions, and other embodiments in accordance with the inventive concept. Therefore, by the broadest interpretation of the following claims and their equivalents, the scope of protection of the invention should be determined to the maximum extent permitted by law and should not be limited by the foregoing detailed description.

Claims

1. In a transistor element, substrate; a lower transistor located over the substrate and including a lower channel layer, a lower gate, and lower source / drain regions; an upper transistor located above the lower transistor and including an upper channel layer, an upper gate, and upper source / drain regions; and an inner spacer located between the lower channel layer and the upper channel layer to insulate the lower transistor from the upper transistor; A transistor element, wherein a sidewall of a portion of the inner spacer is formed to be thicker than sidewalls of the lower gate and the upper gate formed above and below the lower channel layer and the upper channel layer, respectively.

2. The inner spacer is 2. The transistor element according to claim 1, wherein the transistor element is formed by removing a portion of each of a first sacrificial layer and a second sacrificial layer having different Ge contents formed above and below the lower channel layer and the upper channel layer to a depth corresponding to the Ge content, and then depositing an insulating material.

3. the first sacrificial layer is a SiGe layer having a Ge content of 10% to 30%; The transistor device of claim 2 , wherein the second sacrificial layer is a SiGe layer having a Ge content 20% or more higher than that of the first sacrificial layer.

4. The inner spacer is 3. The transistor device of claim 2, wherein the channel layer is formed by etching the second sacrificial layer deeper than the first sacrificial layer through cavity etching at a rate corresponding to a Ge content with a high selectivity, and depositing an insulating material on the outside of the layer remaining after etching.

5. the first sacrificial layer is formed at least on an upper portion and a lower portion of the lower channel layer and the upper channel layer, The transistor element of claim 2 , wherein the second sacrificial layer is formed at least between the first sacrificial layer and the lower channel layer and between the upper channel layer and the lower channel layer.

6. 2. The transistor device of claim 1, further comprising a silicon oxide layer (sl2) between the lower source / drain region and the upper source / drain region, the silicon oxide layer (sl2) being connected to an upper surface of the lower source / drain region and a lower surface of the upper source / drain region to insulate the lower source / drain region from the upper source / drain region.

7. a first work function metal is formed between the lower channel layer and the lower gate; a second work function metal is formed between the upper channel layer and the upper gate; 2. The transistor device of claim 1, wherein said first and second work function metals have the same channel characteristics as said bottom gate and said top gate, respectively.

8. The transistor element of claim 7 , further comprising an insulator (s_de) between the lower gate and the upper gate for insulating the lower gate and the upper gate.

9. the inner spacer is formed adjacent to at least a side surface of a portion of the first and second sacrificial layers between the lower channel layer and the upper channel layer; 3. The transistor element according to claim 2, wherein the lower gate and the upper gate are formed around the lower channel layer and around the upper channel layer in a space remaining after removing the first and second sacrificial layers.

10. forming a nanosheet stack including a lower channel layer, an upper channel layer, a first sacrificial layer separating the lower channel layer and the upper channel layer, and a plurality of second sacrificial layers; the first and second sacrificial layers having different Ge contents from each other; removing a portion of the first sacrificial layer and a portion of the second sacrificial layer through an etching process having a rate according to the Ge content to form an inner spacer in a space; and forming a lower gate around the lower channel layer and an upper gate around the upper channel layer in spaces defined by removing the remainder of the first and second sacrificial layers.

11. The act of forming the inner spacer includes: forming the nanosheet stack such that the plurality of first sacrificial layers are included between the lower channel layer and the upper channel layer and the second sacrificial layer is included between the plurality of first sacrificial layers; etching a portion of each of the first and second sacrificial layers at an etch rate responsive to Ge content, but etching a sidewall of the second sacrificial layer deeper than a sidewall of the plurality of first sacrificial layers; and The method of claim 10, further comprising forming the inner spacers by depositing an insulating material on sidewalls of each of the first and second sacrificial layers.

12. After the step of forming the inner spacer and before the step of forming the gate, The method of claim 10 , further comprising forming lower source / drain regions on sidewalls of the lower channel layer using a substrate below the lower channel layer.

13. removing the dummy source / drain regions while covering the lower source / drain regions with an organic solvent and exposing dummy source / drain regions formed on sidewalls of the upper channel layer together with the lower source / drain regions; and then removing the organic solvent; forming a silicon oxide film on the outer surface of the nanosheet stack from which the organic solvent has been removed; and The method of claim 12 , further comprising the step of forming the upper source / drain regions on sidewalls of the upper channel layer on the silicon oxide film.

14. The act of forming the inner spacer includes:

14. The method of claim 13, further comprising forming the inner spacers to provide insulation between the lower gate and the lower source / drain region and between the upper gate and the upper source / drain region, respectively.

15. forming a dummy gate outside the nanosheet stack; The method further includes depositing a silicon oxide film on a side surface of the dummy gate by a thermal oxidation process to form an outer spacer.

11. The method of claim 10, wherein the outer spacers form sidewalls of the spaces from which the dummy gate, the remainder of the first and second sacrificial layers have been removed.

16. The act of removing the remainder of the first and second sacrificial layers comprises:

16. The method of claim 15, further comprising removing the remainder of the first and second sacrificial layers by an etching process having a high selectivity to the inner spacer, the outer spacer, the upper channel layer, and the lower channel layer.

17. forming a liner layer on the exterior of the nanosheet stack; and The method of claim 15 , further comprising forming the dummy gate layer outside the liner layer.

18. forming a dummy gate cap layer on top of the dummy gate; and 16. The method of claim 15, further comprising the step of etching the dummy gate layer, the upper channel layer and the lower channel layer to a designated channel length using the dummy gate cap layer as a hard mask.

19. 11. The method of claim 10, further comprising forming at least one metal plug outside the space for connecting the lower source / drain region and the upper source / drain region to an external circuit, respectively.

20. In a transistor element, substrate; a lower transistor located over the substrate and including a lower channel layer, a lower gate, and lower source / drain regions; an upper transistor located above the lower transistor and including an upper channel layer, an upper gate, and upper source / drain regions; and an upper end of the lower gate, an insulator (s_de) and a lower end of the upper gate are provided between the lower channel layer and the upper channel layer; a width of at least one of an upper end of the lower gate, the insulator, and a lower end of the upper gate, when viewed from one side of the transistor element, is formed thinner than a remaining width of the lower gate and the upper gate, which are formed below the lower channel layer and above the upper channel layer, respectively.

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