Semiconductor device

Abstract

To reduce an influence of an element isolation region against a main gate electrode of a main transistor.SOLUTION: A semiconductor device 10 constructs a current mirror circuit by a main transistor 11 containing a main gate electrode 31, and a mirror transistor 12 containing a mirror gate electrode 32. The semiconductor device 10 contains: an active region 25 that is surrounded by a frame-like element separation region 24, and contains a first end part 25A and a second end part 25B; a plurality of source regions 41 and a plurality of drain regions 42; and a plurality of gate electrodes 30. The main gate electrode 31 is arranged so as to nip at least one gate electrode 30 to both of the first end part 25A and the second end part 25B. The plurality of gate electrodes 30 contains a first dummy gate electrode 33 and a mirror gate electrode 32. The first dummy gate electrode 33 is adjacently arranged to the main gate electrode 31 while nipping the drain region 42 from a space between the main gate electrode 31 and the first end part 25A.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses an integrated circuit including a current mirror circuit.

Prior Art Document

Patent Document

[0003]

Patent Document 1

[0004] [Summary] In a current mirror circuit, the current mirror ratio of the current flowing through the mirror transistor to the current flowing through the main transistor may deviate from the design value.

[0005] A semiconductor device according to an aspect of the present disclosure is a semiconductor device that forms a current mirror circuit with a main transistor including a main gate electrode and a mirror transistor including a mirror gate electrode, the semiconductor device including: a semiconductor layer including a first surface; a well region formed on the first surface of the semiconductor layer; a frame-shaped element isolation region formed in the well region; an active region surrounded by the element isolation region and including a first end portion in a first direction and a second end portion opposite to the first end portion when viewed from a direction perpendicular to the first surface; a plurality of gate electrodes disposed between the first end portion and the second end portion and extending across the active region in a second direction orthogonal to both the first direction and the direction perpendicular to the first surface; and a plurality of source regions and a plurality of drain regions provided in the active region, sandwiching the plurality of gate electrodes and alternately arranged in the first direction, wherein the plurality of gate electrodes include the main gate electrode disposed so as to sandwich at least one of the gate electrodes with respect to both the first end portion and the second end portion, a first dummy gate electrode disposed between the main gate electrode and the first end portion in the first direction, adjacent to the main gate electrode with the drain region therebetween, and electrically connected to the source region, and at least one of the mirror gate electrodes electrically connected to the main gate electrode.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

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Figure 4

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Figure 10

Figure 11

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Figure 15

[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn at a constant scale. Further, for ease of understanding, the hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is merely for the purpose of explanation and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] As used herein, the expression "at least one" means "one or more" of the desired options. As an example, as used herein, the expression "at least one" means "only one option" or "both of the two options" if the number of options is two. As another example, as used herein, the expression "at least one" means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used herein, "the dimension of A (depth, width, length) is equal to the dimension of B (depth, width, length)" or "the dimension of A (depth, width, length) and the dimension of B (depth, width, length) are equal to each other" includes a relationship where the difference between the dimension of A (depth, width, length) and the dimension of B (depth, width, length) is within 10% of the dimension of A (depth, width, length), for example.

[0011] <First Embodiment> (Schematic Configuration of Semiconductor Device) With reference to FIGS. 1 to 5, the semiconductor device 10 of the first embodiment will be described.

[0012] FIG. 1 schematically shows the planar structure of the semiconductor device 10 of the first embodiment. FIG. 2 schematically shows the cross-sectional structure of the semiconductor device 10 cut along the line F2 - F2 of FIG. 1. FIG. 3 schematically shows the cross-sectional structure of the semiconductor device 10 cut along the line F3 - F3 of FIG. 1. In FIG. 3, the cross-sectional structures at both ends of the semiconductor device 10 are mainly shown, and the cross-sectional structure at the center of the semiconductor device 10 is omitted. FIG. 4 schematically shows the contacts and wirings of the semiconductor device 10 of FIG. 1. In FIG. 4, the first to fourth wirings 61 to 64 are shown by a two-dot chain line. FIG. 5 schematically shows the circuit configuration of the semiconductor device 10.

[0013] As shown in FIG. 1, the semiconductor device 10 includes a main transistor 11 and a mirror transistor 12. The main transistor 11 and the mirror transistor 12 are, for example, MOSFETs (metal-oxide-semiconductor field-effect transistors). The main transistor 11 and the mirror transistor 12 constitute a current mirror circuit CM1 (see FIG. 5). It can be said that the semiconductor device 10 includes the current mirror circuit CM1. The current mirror circuit CM1 may be used for a constant current circuit, a current amplification circuit, a load of a differential amplification circuit, etc. It can be said that the semiconductor device 10 includes a circuit using the current mirror circuit CM1.

[0014] Hereinafter, the detailed configuration of the current mirror circuit CM1 included in the semiconductor device 10 will be described. As shown in FIG. 2, the semiconductor device 10 includes a semiconductor substrate 21 and a semiconductor layer 22.

[0015] The semiconductor substrate 21 is formed in a flat plate shape with the Z direction as the thickness direction. The semiconductor substrate 21 includes a first surface 21S facing the Z direction and a second surface 21R opposite to the first surface 21S. The semiconductor substrate 21 may be a p-type substrate (p-substrate) containing p-type impurities. As the semiconductor substrate 21, a substrate formed of, for example, silicon carbide (SiC) or the like can also be used.

[0016] The semiconductor layer 22 is provided on the first surface 21S of the semiconductor substrate 21. The semiconductor layer 22 includes a first surface 22S facing the same side as the first surface 21S of the semiconductor substrate 21 and a second surface 22R facing the opposite side of the first surface 22S. The second surface 22R of the semiconductor layer 22 is in contact with the first surface 21S of the semiconductor substrate 21. In one example, the semiconductor layer 22 is formed so as to cover the entire first surface 21S of the semiconductor substrate 21.

[0017] Hereinafter, among the directions orthogonal to the Z direction, two mutually orthogonal directions are defined as the X direction and the Y direction. Further, viewing the semiconductor device 10 or the components of the semiconductor device 10 from the Z direction is defined as "plan view". Note that the plan view may be a view from a direction perpendicular to the first surface 22S of the semiconductor layer 22. Here, the X direction is an example of the "first direction", and the Y direction is an example of the "second direction".

[0018] The semiconductor layer 22 is formed of, for example, an epitaxial layer. The semiconductor layer 22 is formed of a material containing Si. An n-type well region 23 is formed on the first surface 22S of the semiconductor layer 22. The well region 23 constitutes a part of the first surface 22S of the semiconductor layer 22. As shown in FIG. 1, the well region 23 is formed in a rectangular shape whose X direction is longer than the Y direction. The broken line shown in FIG. 1 is a boundary defining the outer periphery of the well region 23. The well region 23 includes a first end 23A and a second end 23B in the X direction, and a third end 23C and a fourth end 23D in the Y direction.

[0019] As shown in FIG. 3, an element isolation region 24 is formed on the first surface 22S of the semiconductor layer 22. As shown in FIG. 1, the element isolation region 24 is formed in a frame shape surrounding the well region 23. The element isolation region 24 is in contact with the well region 23. The element isolation region 24 is configured to partition an active region 25 on the surface portion of the well region 23. The element isolation region 24 is formed so as to overlap with the first to fourth ends 23A to 23D of the well region 23. As shown in FIG. 3, the well region 23 is formed deeper than the bottom of the element isolation region 24 from the first surface 22S of the semiconductor layer 22. The well region 23 is formed so as to cover the inner portion of the bottom of the frame-shaped element isolation region 24 from the side of the semiconductor substrate 21.

[0020] As shown in FIG. 1, the active region 25 partitioned by the element isolation region 24 is in contact with the inner end of the element isolation region 24. The active region 25 includes a first end 25A and a second end 25B in contact with the element isolation region 24 in the X direction, and a third end 25C and a fourth end 25D in contact with the element isolation region 24 in the Y direction.

[0021] On the surface portion of the active region 25, a plurality of p-type source regions 41 and a plurality of p-type drain regions 42 are respectively formed. The plurality of source regions 41 and the plurality of drain regions 42 are alternately formed one by one in the X direction. The adjacent source region 41 and drain region 42 in the X direction are formed separately from each other in the X direction. In the example shown in FIG. 1, the drain region 42 is formed at the first end portion 25A of the active region 25, and the source region 41 is formed at the second end portion 25B. These source regions 41 and drain regions 42 have an impurity concentration higher than that of the well region 23. The source regions 41 and drain regions 42 may have an LDD (Lightly Doped Drain) structure as shown in FIGS. 2 and 3. Note that the source regions 41 and drain regions 42 may have a structure other than the LDD structure.

[0022] A plurality of gate electrodes 30 are arranged on the first surface 22S of the semiconductor layer 22. Nine gate electrodes 30 are shown in FIG. 1. Each gate electrode 30 is arranged between the first end portion 25A and the second end portion 25B of the active region 25. The plurality of gate electrodes 30 are arranged separately from each other in the X direction. The plurality of gate electrodes 30 are arranged at the same position as each other in the Y direction. Each gate electrode 30 extends so as to straddle the active region 25 in the Y direction. That is, each gate electrode 30 protrudes in the Y direction from the active region 25 toward the element isolation region 24 in a plan view. In the example shown in FIG. 1, both end portions of each gate electrode 30 in the Y direction are arranged at positions overlapping the element isolation region 24 in a plan view.

[0023] As shown in FIG. 3, each gate electrode 30 is arranged on a gate insulating film 26 formed on the first surface 22S. The gate insulating film 26 is made of an insulating material such as silicon oxide (SiO 2 ), silicon nitride (SiN), etc. Each gate electrode 30 is made of a material containing, for example, conductive polysilicon or the like.

[0024] As shown in FIG. 1, the plurality of gate electrodes 30 includes a main gate electrode 31 which is the gate electrode of the main transistor 11, a mirror gate electrode 32 which is the gate electrode of the mirror transistor 12, and a first dummy gate electrode 33 arranged adjacent to the main gate electrode 31 in the X direction. In the first embodiment, the plurality of gate electrodes 30 includes a first end dummy electrode 34 arranged adjacent to the first end 25A of the active region 25 in the X direction, and a second end dummy electrode 35 arranged adjacent to the second end 25B of the active region 25 in the X direction. Here, the first end dummy electrode 34 is an example of an "end dummy gate electrode".

[0025] The main gate electrode 31 is arranged substantially at the center in the X direction of the active region 25. Source regions 41 and drain regions 42 are formed in a dispersed manner on both sides in the X direction of the main gate electrode 31 in the active region 25. Thereby, the main transistor 11 is formed. The source region 41 of the main transistor 11 is formed at a position adjacent to the main gate electrode 31 closer to the second end 25B of the active region 25 with respect to the main gate electrode 31 in a plan view. The drain region 42 of the main transistor 11 is formed at a position adjacent to the main gate electrode 31 closer to the first end 25A of the active region 25 with respect to the main gate electrode 31 in a plan view.

[0026] The mirror transistor 12 includes a first mirror transistor region 12A and a second mirror transistor region 12B that are formed dispersedly on both sides of the main transistor 11 in the X direction. The first mirror transistor region 12A is arranged closer to the first end 25A of the active region 25 than the main transistor 11 in the X direction. The second mirror transistor region 12B is arranged closer to the second end 25B of the active region 25 than the main gate electrode 31 in the X direction. Corresponding to these first mirror transistor region 12A and second mirror transistor region 12B, the mirror gate electrode 32 includes at least one first mirror gate electrode 32A and at least one second mirror gate electrode 32B. The first mirror transistor region 12A includes at least one first mirror gate electrode 32A. The second mirror transistor region 12B includes at least one second mirror gate electrode 32B.

[0027] In one example, the number of the first mirror gate electrodes 32A and the number of the second mirror gate electrodes 32B may be different. In one example, the number of the second mirror gate electrodes 32B may be less than the number of the first mirror gate electrodes 32A. In the first embodiment, the mirror gate electrode 32 includes two first mirror gate electrodes 32A and three second mirror gate electrodes 32B. The two first mirror gate electrodes 32A are arranged between the main gate electrode 31 and the first end dummy electrode 34 in the X direction. The three second mirror gate electrodes 32B are arranged between the main gate electrode 31 and the second end dummy electrode 35 in the X direction.

[0028] The two first mirror gate electrodes 32A are arranged between the main gate electrode 31 and the first end dummy electrode 34 in the X direction. The two first mirror gate electrodes 32A are arranged adjacent to each other in the X direction. That is, no other gate electrode 30 is arranged between the two first mirror gate electrodes 32A in the X direction. Hereinafter, for convenience, the two first mirror gate electrodes 32A are referred to as "first mirror gate electrodes 32AA, 32AB".

[0029] The first mirror gate electrode 32AA is disposed closer to the main gate electrode 31 than the first mirror gate electrode 32AB. Source regions 41 and drain regions 42 are dispersedly formed on both sides in the X direction of the first mirror gate electrode 32A in the active region 25. The source region 41 is disposed closer to the main gate electrode 31 than the first mirror gate electrode 32A. The drain region 42 is disposed closer to the first mirror gate electrode 32AB than the first mirror gate electrode 32AA. It can be said that the drain region 42 is formed between the first mirror gate electrode 32A and the first mirror gate electrode 32AB in the X direction. A source region 41 is formed on the side opposite to the first mirror gate electrode 32AA with respect to the first mirror gate electrode 32AB in the active region 25.

[0030] Thus, the first mirror transistor region 12A includes the first mirror gate electrodes 32AA and 32AB, and the source regions 41 and drain regions 42 alternately arranged in the X direction. The first mirror gate electrode 32AA, and the source region 41 and drain region 42 sandwiching the first mirror gate electrode 32AA constitute the first mirror transistor 12A1. Similarly, the first mirror gate electrode 32AB, and the source region 41 and drain region 42 sandwiching the first mirror gate electrode 32AB constitute the first mirror transistor 12A2.

[0031] The two first mirror transistors 12A1 and 12A2 include a common drain region 42. Therefore, compared with the case where the first mirror transistors 12A1 and 12A2 are separately formed by an element isolation region, the area for forming the first mirror transistors 12A1 and 12A2 is reduced, so that the semiconductor device 10 can be miniaturized.

[0032] The three second mirror gate electrodes 32B are arranged between the main gate electrode 31 and the second end dummy electrode 35 in the X direction. The three second mirror gate electrodes 32B are arranged adjacent to each other in the X direction. That is, no other gate electrode 30 is arranged between the three second mirror gate electrodes 32B in the X direction. Hereinafter, for convenience, the three second mirror gate electrodes 32B are referred to as "second mirror gate electrodes 32BA, 32BB, 32BC".

[0033] The second mirror gate electrode 32BA is arranged closer to the main gate electrode 31 than the second mirror gate electrodes 32BB and 32BC. The second mirror gate electrode 32BA is arranged adjacent to the main gate electrode 31 with the source region 41 of the main transistor 11 interposed therebetween. The second mirror gate electrode 32BB is arranged closer to the second mirror gate electrode 32BA than the second mirror gate electrode 32BC. That is, the second mirror gate electrode 32BB is arranged between the second mirror gate electrode 32BA and the second mirror gate electrode 32BC in the X direction. A drain region 42 is formed between the second mirror gate electrode 32BA and the second mirror gate electrode 32BB in the X direction within the active region 25. A source region 41 is formed between the second mirror gate electrode 32BB and the second mirror gate electrode 32BC in the X direction within the active region 25. A drain region 42 is formed between the second mirror gate electrode 32BC and the second end dummy electrode 35 in the X direction within the active region 25.

[0034] Thus, the second mirror transistor region 12B includes second mirror gate electrodes 32BA, 32BB, 32BC, and source regions 41 and drain regions 42 that are alternately arranged in the X direction. The second mirror gate electrode 32BA, and the source region 41 and the drain region 42 sandwiching the second mirror gate electrode 32BA constitute the second mirror transistor 12B1. Similarly, the second mirror gate electrodes 32BB, 32BC, and the source regions 41 and the drain regions 42 sandwiching each of the second mirror gate electrodes 32BB, 32BC constitute the second mirror transistors 12B2, 12B3. Therefore, the mirror transistor 12 includes two first mirror transistors 12A1, 12A2 and three second mirror transistors 12B1 to 12B3. It can be said that the semiconductor device 10 includes five mirror transistors.

[0035] The second mirror transistors 12B1, 12B2 include one common drain region 42. The second mirror transistors 12B2, 12B3 include one common source region 41. Therefore, compared with the case where the second mirror transistors 12B1, 12B2, 12B3 are separately formed by an element isolation region, the area for forming the second mirror transistors 12B1 to 12B3 is reduced, so that the semiconductor device 10 can be miniaturized.

[0036] Also, among the second mirror transistors 12B1 to 12B3 in the second mirror transistor region 12B, the second mirror transistor 12B1 close to the main transistor 11 shares the source region 41 with the main transistor 11. That is, the main transistor 11 and the second mirror transistor 12B1 adjacent to the main transistor 11 include a common source region 41. It can be said that the second mirror transistor region 12B and the main transistor 11 are electrically connected via the source region 41. Since the main transistor 11 and the second mirror transistor 12B1 include one source region 41, the semiconductor device 10 can be miniaturized compared with the case where the main transistor 11 and the second mirror transistor 12B1 are separately formed by an element isolation region.

[0037] The semiconductor device 10 includes dummy transistors 13 to 15 corresponding to the first dummy gate electrode 33, the first end dummy electrode 34, and the second end dummy electrode 35. Each of the dummy transistors 13 to 15 is, for example, a MOSFET. The dummy transistor 13 includes the first dummy gate electrode 33. The dummy transistor 14 includes the first end dummy electrode 34. The dummy transistor 15 includes the second end dummy electrode 35.

[0038] The first dummy gate electrode 33 in the dummy transistor 13 is disposed between the main gate electrode 31 and the first end dummy electrode 34 in the X direction. More specifically, the first dummy gate electrode 33 is disposed between the main gate electrode 31 and the first mirror gate electrode 32A in the X direction. In other words, the first mirror gate electrode 32A is disposed between the first end dummy electrode 34 and the first dummy gate electrode 33 in the X direction. In the first embodiment, the first dummy gate electrode 33 is disposed between the main gate electrode 31 and the first mirror gate electrode 32AA closer to the main gate electrode 31 among the two first mirror gate electrodes 32AA and 32AB in the X direction. The first dummy gate electrode 33 is disposed adjacent to the main gate electrode 31 with the drain region 42 of the main transistor 11 therebetween. The first dummy gate electrode 33 is disposed between the drain region 42 of the main transistor 11 and the source region 41 formed at the end closer to the main transistor 11 among the two ends in the X direction of the first mirror transistor region 12A.

[0039] The dummy transistor 13 is composed of a first dummy gate electrode 33, a source region 41 and a drain region 42 sandwiching the first dummy gate electrode 33. The dummy transistor 13 and the main transistor 11 adjacent to the dummy transistor 13 include a common drain region 42. That is, it can be said that the dummy transistor 13 and the main transistor 11 are electrically connected via the drain region 42. Since the dummy transistor 13 and the main transistor 11 include one drain region 42, the semiconductor device 10 can be miniaturized as compared with the case where the dummy transistor 13 and the main transistor 11 are separately formed by an element isolation region.

[0040] The first end dummy electrode 34 in the dummy transistor 14 is arranged adjacent to the first mirror gate electrode 32AB of the first mirror transistor 12A2 on the side opposite to the first mirror gate electrode 32AA in the X direction.

[0041] The dummy transistor 14 is composed of a first end dummy electrode 34, a source region 41 and a drain region 42 sandwiching the first end dummy electrode 34. The dummy transistor 14 and the first mirror transistor 12A2 adjacent to the dummy transistor 14 include a common source region 41. That is, the dummy transistor 14 and the first mirror transistor 12A2 are electrically connected via the source region 41. Since the dummy transistor 14 and the first mirror transistor 12A2 include one source region 41, the semiconductor device 10 can be miniaturized as compared with the case where the dummy transistor 14 and the first mirror transistor 12A2 are separately formed by an element isolation region.

[0042] The second end dummy electrode 35 in the dummy transistor 15 is arranged adjacent to the second mirror gate electrode 32BC of the second mirror transistor 12B3 on the side opposite to the second mirror gate electrode 32BB in the X direction.

[0043] The dummy transistor 15 is composed of a second-end dummy electrode 35, a source region 41 and a drain region 42 sandwiching the second-end dummy electrode 35. The dummy transistor 15 and the second mirror transistor 12B3 adjacent to the dummy transistor 15 include a common drain region 42. That is, the dummy transistor 15 and the second mirror transistor 12B3 are electrically connected via the drain region 42. Since the dummy transistor 15 and the second mirror transistor 12B3 include one drain region 42, the semiconductor device 10 can be miniaturized as compared with the case where the dummy transistor 15 and the second mirror transistor 12B3 are separately formed by an element isolation region.

[0044] (Dimensional relationship of semiconductor device) With reference to FIG. 1, an example of the dimensional relationship of the semiconductor device will be described. The length WS in the X direction of the main gate electrode 31 and the length WM in the X direction of the mirror gate electrode 32 are equal to each other. Therefore, it can be said that the gate lengths of the main transistor 11 including the main gate electrode 31 and the mirror transistor 12 including the mirror gate electrode 32 are equal to each other. The gate length may be, for example, 0.6 μm. In one example, the length WA in the X direction of the first dummy gate electrode 33, the length WB in the X direction of the first-end dummy electrode 34, and the length WC in the X direction of the second-end dummy electrode 35 are equal to the length WS in the X direction of the main gate electrode 31. That is, it can be said that the lengths in the X direction of the plurality of gate electrodes 30 are equal to each other.

[0045] The length LS in the Y direction of the main gate electrode 31 and the length LM in the Y direction of the mirror gate electrode 32 are equal to each other. And the main gate electrode 31 and the mirror gate electrode 32 are formed so as to straddle the rectangular active region 25 in a plan view. Therefore, it can be said that the gate widths of the main transistor 11 including the main gate electrode 31 and the mirror transistor 12 including the mirror gate electrode 32 are equal to each other. The gate width may be, for example, 10 μm. In one example, the length LA in the Y direction of the first dummy gate electrode 33, the length LB in the Y direction of the first end dummy electrode 34, and the length LC in the Y direction of the second end dummy electrode 35 are equal to the length LS in the Y direction of the main gate electrode 31. That is, it can be said that the lengths in the Y direction of the plurality of gate electrodes 30 are equal to each other.

[0046] The distance in the X direction between the main gate electrode 31 and the first dummy gate electrode 33, the distance in the X direction between the main gate electrode 31 and the second mirror gate electrode 32BA, the distance in the X direction between the first dummy gate electrode 33 and the first mirror gate electrode 32AA, the distance in the X direction between the first mirror gate electrode 32AA and the first mirror gate electrode 32AB, the distance in the X direction between the first mirror gate electrode 32AB and the first end dummy electrode 34, the distance in the X direction between the second mirror gate electrode 32BA and the second mirror gate electrode 32BB, the distance in the X direction between the second mirror gate electrode 32BB and the second mirror gate electrode 32BC, and the distance in the X direction between the second mirror gate electrode 32BC and the second end dummy electrode 35 are equal to each other. That is, the lengths RS in the X direction of the respective plurality of source regions 41 are equal to each other. The lengths RD in the X direction of the respective plurality of drain regions 42 are equal to each other. The length RS in the X direction of the source region 41 and the length RD in the X direction of the drain region 42 are equal to each other. Thus, it can be said that the plurality of gate electrodes 30 are arranged at an equal pitch.

[0047] (Electrical connection structure of semiconductor device) As shown in FIG. 4, the main gate electrode 31 is electrically connected to the first wiring 61 by the main gate contact 51. Each of the plurality of mirror gate electrodes 32 is electrically connected to the first wiring 61 by the mirror gate contact 52. Thereby, the main gate electrode 31 and the plurality of mirror gate electrodes 32 are electrically connected to each other.

[0048] The first dummy gate electrode 33 is electrically connected to the second wiring 62 by the dummy gate contact 53. The first end dummy electrode 34 is electrically connected to the second wiring 62 by the dummy gate contact 54. The second end dummy electrode 35 is electrically connected to the second wiring 62 by the dummy gate contact 55. Each source region 41 in the active region 25 is electrically connected to the second wiring 62 by a plurality of source contacts 56. Thereby, the first dummy gate electrode 33, the first end dummy electrode 34, the second end dummy electrode 35, and each source region 41 are electrically connected to each other.

[0049] The drain regions 42 in the first mirror transistor region 12A and the second mirror transistor region 12B are electrically connected to the third wiring 63 by the drain contacts 57. Thereby, the drain regions 42 in the first mirror transistor region 12A and the second mirror transistor region 12B are electrically connected to each other.

[0050] The drain region 42 of the main transistor 11 is electrically connected to the first wiring 61 by the drain contact 57. Therefore, the drain region 42 of the main transistor 11 is electrically connected to each of the main gate electrode 31, the first mirror gate electrode 32A, and the second mirror gate electrode 32B.

[0051] The drain region 42 of the dummy transistor 14 is electrically connected to the fourth wiring 64 by the drain contact 57. The fourth wiring 64 is not electrically connected to the first to third wirings 61 to 63, the main gate electrode 31, the mirror gate electrode 32, the first dummy gate electrode 33, the first end dummy electrode 34, and the second end dummy electrode 35. Also, the fourth wiring 64 is not electrically connected to the source regions 41 and drain regions 42 of the main transistor 11, the mirror transistor 12, and the dummy transistors 13 and 15. Note that the fourth wiring 64 may be electrically connected to the third wiring 63. The fourth wiring 64 may be omitted. The drain contact 57 of the drain region 42 of the dummy transistor 14 may be omitted.

[0052] According to the connection structure of the semiconductor device 10 described above, the circuit configuration shown in FIG. 5 is obtained. That is, the gates of the main transistor 11 and the mirror transistor 12 are connected to each other and are electrically connected to the drain of the main transistor 11. The dummy transistor 13 is connected in parallel with the main transistor 11. The gate of the dummy transistor 13 is connected to the source of the dummy transistor 13. The drain of the dummy transistor 13 is electrically connected to the drain of the main transistor 11.

[0053] The dummy transistor 15 is connected in parallel with the mirror transistor 12. The gate of the dummy transistor 15 is electrically connected to the source of the dummy transistor 15. The source of the dummy transistor 14 is electrically connected to the source of the dummy transistor 15. The gate of the dummy transistor 14 is electrically connected to the source of the dummy transistor 14. The drain of the dummy transistor 14 is open.

[0054] FIG. 5 shows a configuration for checking the current mirror ratio of the current mirror circuit CM1. Note that the configuration shown in FIG. 5 is created, for example, as a simulator model. The constant current source 81 is electrically connected to the drain of the main transistor 11. The ammeter 82 is connected to the drain of the mirror transistor 12. A predetermined current is passed through the main transistor 11 by the constant current source 81. The drain current Ids flowing through the mirror transistor 12 can be confirmed by the ammeter 82. The current mirror ratio between the main transistor 11 and the mirror transistor 12 is confirmed by the current from the constant current source 81 and the current measured by the ammeter 82.

[0055] (Operation of the First Embodiment) With reference to FIGS. 1 and 6 to 9, the operation of the semiconductor device 10 of the first embodiment will be described. FIG. 6 schematically shows the planar structure of the semiconductor device 10X of the first comparative example. FIG. 7 schematically shows the planar structure of the semiconductor device 10Y of the second comparative example. FIG. 8 schematically shows the cross-sectional structure of the semiconductor device 10Y of the second comparative example cut along the line F8 - F8 in FIG. 7. FIG. 9 is a graph showing the relationship between the source-drain voltage Vds and the drain current Ids.

[0056] First, the configuration of the semiconductor device 10X of the first comparative example will be described. As shown in FIG. 6, the semiconductor device 10X includes a main transistor 11X that constitutes a current mirror circuit, and a plurality (four in FIG. 6) of mirror transistors 12XA to 12XD. The main transistor 11X and the mirror transistors 12XA to 12XD are formed in active regions 25X respectively partitioned by the element isolation region 24X. The active regions 25X of the main transistor 11X and the mirror transistors 12XA to 12XD are arranged spaced apart from each other in the X direction. The element isolation region 24X includes a plurality (four in FIG. 6) of intermediate regions 24XA provided between the active regions 25X adjacent to each other in the X direction among the main transistor 11X and the mirror transistors 12XA to 12XD.

[0057] According to the semiconductor device 10X of the first comparative example, an active region 25X is provided for each transistor. Therefore, in a current mirror circuit having a high current mirror ratio, it becomes large in the X direction. In contrast, it is conceivable to share the source region or drain region of two adjacent mirror transistors. That is, as an example of a semiconductor device in which the intermediate region 24XA between the mirror transistor 12XA and the mirror transistor 12XB and the intermediate region 24XA between the mirror transistor 12XC and the mirror transistor 12XD are omitted, the semiconductor device 10Y of the second comparative example is conceivable.

[0058] As shown in FIG. 7, in the semiconductor device 10Y of the second comparative example, the element isolation region 24Y partitions the active region 25X forming the main transistor 11X and the active regions 25Y1 and 25Y2 forming the plurality of mirror transistors 12X1 to 12X3 and 12Y1 to 12Y3. The active regions 25Y1 and 25Y2 are arranged adjacent to the active region 25X of the main transistor 11X with the intermediate regions 24YB and 24YC of the element isolation region 24Y interposed therebetween.

[0059] In the active regions 25Y1 and 25Y2, the mirror gate electrodes 32X of the three mirror transistors 12X1 to 12X3 and 12Y1 to 12Y3 are arranged so as to straddle the active regions 25Y1 and 25Y2. Therefore, the semiconductor device 10Y of the second comparative example includes a current mirror circuit composed of one main transistor 11X and six mirror transistors 12X1 to 12X3 and 12Y1 to 12Y3.

[0060] As shown in FIG. 8, the first intermediate region 24YB separates the drain region 42X of the main transistor 11X and the source region 41X of the mirror transistor 12X1. The second intermediate region 24YC separates the source region 41X of the main transistor 11X and the drain region 42X of the mirror transistor 12Y1.

[0061] As shown in FIG. 7, in the semiconductor device 10Y, the distance GA1 between the main gate electrode 31X and the first intermediate region 24YB in the X direction is equal to the distance GA2 between the main gate electrode 31X and the second intermediate region 24YC in the X direction. The distance GA3 between the mirror gate electrode 32X of the mirror transistor 12X2 and the first intermediate region 24YB in the X direction is equal to the distance GA4 between the mirror gate electrode 32X of the mirror transistor 12X2 and the outer peripheral region 24YA in the X direction. The distance GA5 between the mirror gate electrode 32X of the mirror transistor 12Y2 and the second intermediate region 24YC in the X direction is equal to the distance GA6 between the mirror gate electrode 32X of the mirror transistor 12Y2 and the outer peripheral region 24YA in the X direction. Also, the distances GA5 and GA6 are equal to the distances GA3 and GA4. On the other hand, the distances GA3 to GA6 are longer than the distances GA1 and GA2.

[0062] In a MOSFET, stress from the element isolation region may be applied to the channel region between the source region and the drain region. The stress from the element isolation region may be generated by processes in the step of forming the element isolation region, processes after the element isolation region is formed, etc. in the manufacturing process of the semiconductor device. And the stress applied to the channel region may vary depending on the distance between the channel region and the element isolation region facing the length direction of the channel region. The stress applied to the channel region may affect the saturation drain current of the MOSFET.

[0063] FIG. 9 is a graph showing the relationship between the source-drain voltage Vds and the drain current Ids at the distance GA in the X direction between the gate electrode and the element isolation region. In FIG. 9, graphs for distances G1, G2, G3, G4, G5 (G1 < G2 < G3 < G4 < G5) are shown in ascending order of the distance GA. More specifically, graph Gp1 is the graph corresponding to the distance G1. Here, the distance G1 is equal to the distances GA1 and GA2. Graph Gp2 is the graph when the distance GA is equal to the distance G2. Graph Gp3 is the graph when the distance GA is equal to the distance G3. Graph Gp4 is the graph when the distance GA is equal to the distance G4. Graph Gp5 is the graph when the distance GA is equal to the distance G5. The distance G5 is equal to the distances GA3 to GA6. In one example, G1 = 0.42 μm, G2 = 0.52 μm, G3 = 0.6 μm, G4 = 1.54 μm, and G5 = 2.56 μm.

[0064] In the current mirror circuit, the gates of the main transistor 11X and the mirror transistors 12X1 to 12X3, 12Y1 to 12Y3 are connected to the drain of the main transistor 11X. Therefore, the source-gate voltage Vgs of the main transistor 11X is equal to the source-drain voltage Vds. Also, the source-gate voltage Vgs of the mirror transistors 12X1 to 12X3, 12Y1 to 12Y3 is approximately equal to the source-drain voltage Vds.

[0065] As shown in FIG. 9, as the distance GA increases, the drain current Ids with respect to the source-drain voltage Vds decreases. For example, when the source-drain voltage Vds is a predetermined voltage Vgx (= 0.8 V), in the semiconductor device 10Y of the second comparative example, a drain current Ids1 flows through the main transistor 11X as can be seen from graph Gp1. On the other hand, a drain current Ids5 flows through the mirror transistors 12X2 and 12Y2 as can be seen from graph Gp5. That is, a drain current Ids5 smaller than the drain current Ids1 flowing through the main transistor 11X flows through the mirror transistors 12X2 and 12Y2.

[0066] The difference between the distances GA1 and GA2 and the distances GA3 to GA6 reduces the pairing property between the main transistor 11X and the mirror transistors 12X1 to 12X3 and 12Y1 to 12Y3. More specifically, the difference between the drain current Ids1 corresponding to the predetermined voltage Vgx in the graph Gp1 corresponding to the distances GA1 and GA2 and the drain current Ids5 corresponding to the predetermined voltage Vgx in the graph Gp5 corresponding to the distances GA3 to GA6 is large. As a result, the current mirror ratio decreases. In one example, in the semiconductor device 10Y of the second comparative example shown in FIG. 7, when a current mirror circuit including 100 mirror transistors is provided for one main transistor 11X, the current mirror ratio was "58".

[0067] On the other hand, as shown in FIG. 1, in the semiconductor device 10 of the first embodiment, the shortest distance GAB in the X direction between the mirror gate electrode 32 and the element isolation region 24 in the mirror transistor 12 is increased by the first end dummy electrode 34 and the second end dummy electrode 35. In one example, the shortest distance GAB is equal to the distances GA3 to GA6. The distance GAA in the X direction between the main gate electrode 31 and the element isolation region 24 is longer than the shortest distance GAB. Thus, since both the distance GAA and the shortest distance GAB are increased, the variation in the drain current Ids with respect to the variation in the distance GA is reduced. Therefore, a decrease in the current mirror ratio can be suppressed. In one example, in the semiconductor device 10 of the first embodiment, when a current mirror circuit CM1 including 100 mirror transistors 12 is provided for one main transistor 11, it was confirmed that the current mirror ratio was "100".

[0068] As can be seen from the graphs Gp1 to Gp5 in FIG. 9, the closer the gate electrode 30 is to the element isolation region 24, the more susceptible it is to the influence of the element isolation region 24. When the gate electrode 30 is separated from the element isolation region 24 by a predetermined distance or more, it becomes less susceptible to the influence of the element isolation region 24. As shown in FIG. 1, by providing the first end dummy electrode 34, the first mirror gate electrode 32AB of the first mirror transistor 12A2 is separated from the element isolation region 24. Therefore, the influence of the element isolation region 24 on the first mirror gate electrode 32AB of the first mirror transistor 12A2 can be reduced. Similarly, by providing the second end dummy electrode 35, the influence of the element isolation region 24 on the second mirror gate electrode 32BC of the second mirror transistor 12B3 can be reduced.

[0069] [Effects of the First Embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 forms a current mirror circuit CM1 with a main transistor 11 including a main gate electrode 31 and a mirror transistor 12 including a mirror gate electrode 32. The semiconductor device 10 includes a semiconductor layer 22 including a first surface 22S, a well region 23 formed on the first surface 22S of the semiconductor layer 22, a frame-shaped element isolation region 24 formed in the well region 23, an active region 25 surrounded by the element isolation region 24 and including a first end portion 25A in the X direction in plan view and a second end portion 25B on the side opposite to the first end portion 25A, a plurality of gate electrodes 30 disposed between the first end portion 25A and the second end portion 25B and extending across the active region 25 in the Y direction orthogonal to both the X direction and the Z direction, and a plurality of source regions 41 and a plurality of drain regions 42 provided in the active region 25, sandwiching the plurality of gate electrodes 30 and alternately arranged in the X direction. The plurality of gate electrodes 30 include a main gate electrode 31 arranged so as to sandwich at least one gate electrode 30 with respect to both the first end portion 25A and the second end portion 25B, at least one first dummy gate electrode 33 disposed between the main gate electrode 31 and the first end portion 25A in the X direction, adjacent to the main gate electrode 31 with the drain region 42 therebetween, and electrically connected to the source region 41, and a mirror gate electrode 32 electrically connected to the main gate electrode 31.

[0070] According to this configuration, since at least one gate electrode 30 is disposed on each of both sides in the X direction of the main gate electrode 31 in the active region 25, the distance in the X direction between the main gate electrode 31 and the element isolation region 24 becomes long. Therefore, the influence of the element isolation region 24 on the main gate electrode 31 can be reduced.

[0071] (1-2) The plurality of gate electrodes 30 include a first end dummy electrode 34 as an end dummy gate electrode disposed adjacent to the first end portion 25A and electrically connected to the source region 41. The mirror gate electrode 32 is disposed between the first end dummy electrode 34 and the first dummy gate electrode 33 in the X direction.

[0072] According to this configuration, since the first-end dummy electrode 34 is disposed between the mirror gate electrode 32 and the element isolation region 24 in the X direction in the active region 25, the distance between the mirror gate electrode 32 and the element isolation region 24 in the X direction becomes long. Therefore, the influence of the element isolation region 24 on the mirror gate electrode 32 can be reduced. In addition, since both the distance between the main gate electrode 31 and the element isolation region 24 in the X direction and the distance between the mirror gate electrode 32 and the element isolation region 24 in the X direction become long, the variation between the drain current of the main transistor 11 and the drain current of the mirror transistor 12 becomes small. Therefore, a decrease in the current mirror ratio of the semiconductor device 10 can be suppressed.

[0073] (1-3) The plurality of gate electrodes 30 includes either a first-end dummy electrode 34 disposed adjacent to the first end 25A in the X direction and electrically connected to the source region 41, or a second-end dummy electrode 35 disposed adjacent to the second end 25B in the X direction and electrically connected to the source region 41. The mirror gate electrode 32 is disposed between the first-end dummy electrode 34 and the main gate electrode 31 in the X direction, or between the second-end dummy electrode 35 and the main gate electrode 31 in the X direction.

[0074] According to this configuration, since the first-end dummy electrode 34 or the second-end dummy electrode 35 is disposed between the mirror gate electrode 32 and the element isolation region 24 in the X direction in the active region 25, the distance between the mirror gate electrode 32 and the element isolation region 24 in the X direction becomes long. Therefore, the influence of the element isolation region 24 on the mirror gate electrode 32 can be reduced. In addition, since both the distance between the main gate electrode 31 and the element isolation region 24 in the X direction and the distance between the mirror gate electrode 32 and the element isolation region 24 in the X direction become long, the variation between the drain current of the main transistor 11 and the drain current of the mirror transistor 12 becomes small. Therefore, a decrease in the current mirror ratio of the semiconductor device 10 can be suppressed.

[0075] (1-4) The plurality of gate electrodes 30 are arranged adjacent to the first end portion 25A in the X direction, and include a first end portion dummy electrode 34 electrically connected to the source region 41, and a second end portion dummy electrode 35 arranged adjacent to the second end portion 25B in the X direction and electrically connected to the source region 41. The mirror gate electrode 32 includes at least one first mirror gate electrode 32A arranged between the first end portion dummy electrode 34, the main gate electrode 31, and in the X direction, and at least one second mirror gate electrode 32B arranged between the second end portion dummy electrode 35, the main gate electrode 31, and in the X direction.

[0076] According to this configuration, since the first end portion dummy electrode 34 is arranged between the first mirror gate electrode 32A and the element isolation region 24 in the X direction in the active region 25, the distance between the first mirror gate electrode 32A and the element isolation region 24 in the X direction becomes longer. Since the second end portion dummy electrode 35 is arranged between the second mirror gate electrode 32B and the element isolation region 24 in the X direction in the active region 25, the distance between the second mirror gate electrode 32B and the element isolation region 24 in the X direction becomes longer. Therefore, the influence of the element isolation region 24 on the first mirror gate electrode 32A and the second mirror gate electrode 32B can be reduced. In addition, a first dummy gate electrode 33, a first mirror gate electrode 32A, and a first end portion dummy electrode 34 are arranged between the main gate electrode 31 and the first end portion 25A of the active region 25 in the X direction. For this reason, the distance between the main gate electrode 31 and the element isolation region 24 in the X direction becomes longer. Also, a second mirror gate electrode 32B and a second end portion dummy electrode 35 are arranged between the main gate electrode 31 and the second end portion 25B of the active region 25 in the X direction. For this reason, the distance between the main gate electrode 31 and the element isolation region 24 becomes longer. Thus, since each of the distance between the main gate electrode 31 and the element isolation region 24 in the X direction, the distance between the first mirror gate electrode 32A and the element isolation region 24 in the X direction, and the distance between the second mirror gate electrode 32B and the element isolation region 24 in the X direction becomes longer, the variation between the drain current of the main transistor 11 and the drain current of the mirror transistor 12 becomes smaller. Therefore, a decrease in the current mirror ratio of the semiconductor device 10 can be suppressed.

[0077] (1-5) The first dummy gate electrode 33 is provided between the main gate electrode 31 and the first mirror gate electrode 32A in the X direction. The main gate electrode 31 and the second mirror gate electrode 32B are arranged at positions adjacent to each other via the source region 41 in the X direction.

[0078] According to this configuration, the source region 41 of the main transistor 11 and the source region 41 of the mirror transistor 12 are common. Therefore, the semiconductor device 10 can be miniaturized as compared with a configuration in which the source region 41 of the main transistor 11 and the source region 41 of the mirror transistor 12 are formed individually.

[0079] (1-6) The lengths of the plurality of gate electrodes 30 in the X direction are equal to each other. According to this configuration, the pairing property between the main transistor 11 and the mirror transistor 12 can be improved as compared with the case where the lengths of the plurality of gate electrodes 30 in the X direction are different.

[0080] (1-7) The length RS in the X direction of the plurality of source regions 41 and the length RD in the X direction of the plurality of drain regions 42 are equal to each other. According to this configuration, the pairing property between the main transistor 11 and the mirror transistor 12 can be improved as compared with the case where the length RS in the X direction of the plurality of source regions 41 and the length RD in the X direction of the plurality of drain regions 42 are different from each other.

[0081] <Second Embodiment> With reference to FIGS. 10 and 11, the semiconductor device 10 of the second embodiment will be described. In the semiconductor device 10 of the second embodiment, compared with the semiconductor device 10 of the first embodiment, the main differences are that a second dummy gate electrode 36 is added and the configuration of the second mirror gate electrode 32B. Hereinafter, the same reference numerals are given to the components common to the first embodiment, and the description thereof is omitted.

[0082] FIG. 10 schematically shows the planar structure of the semiconductor device 10 according to the second embodiment. FIG. 11 schematically shows the planar structure in which contacts and first to fourth wirings 61 to 64 are added to the semiconductor device 10 of FIG. 10.

[0083] As shown in FIG. 10, the second mirror gate electrode 32B of the second embodiment includes two second mirror gate electrodes 32B. Hereinafter, for convenience, the two second mirror gate electrodes 32B are referred to as "second mirror gate electrodes 32BA and 32BB". The second mirror gate electrode 32BA is arranged closer to the main gate electrode 31 than the second mirror gate electrode 32BB. Thus, in the second embodiment, the number of the first mirror gate electrodes 32A is equal to the number of the second mirror gate electrodes 32B.

[0084] The second mirror transistor region 12B includes second mirror gate electrodes 32BA and 32BB, one source region 41, and two drain regions 42. Therefore, in the configuration of the second mirror transistor region 12B, the number of the source regions 41 and the number of the drain regions 42 are different from those of the first mirror transistor region 12A.

[0085] The second dummy gate electrode 36 is arranged adjacent to the main gate electrode 31 across the source region 41 of the main transistor 11 on the side opposite to the first dummy gate electrode 33 with respect to the main gate electrode 31 in the X direction. Therefore, the main gate electrode 31 is arranged between the first dummy gate electrode 33 and the second dummy gate electrode 36 in the X direction.

[0086] The second dummy gate electrode 36 is arranged between the main gate electrode 31 and the second mirror gate electrode 32B in the X direction. The second dummy gate electrode 36 is arranged adjacent to the second mirror gate electrode 32BA across the drain region 42 formed at the end closer to the main transistor 11 among the two ends of the second mirror transistor region 12B in the X direction.

[0087] In one example, the length WD in the X direction of the second dummy gate electrode 36 is equal to the length WS in the X direction of the main gate electrode 31. In one example, the length WD in the X direction of the second dummy gate electrode 36 is equal to the length WA in the X direction of the first dummy gate electrode 33. In the second embodiment, the lengths in the X direction of the plurality of gate electrodes 30 are equal to each other.

[0088] In one example, the length LD in the Y direction of the second dummy gate electrode 36 is equal to the length LS in the X direction of the main gate electrode 31. In one example, the length LD in the Y direction of the second dummy gate electrode 36 is equal to the length in the Y direction of the first dummy gate electrode 33. In the second embodiment, the lengths in the Y direction of the plurality of gate electrodes 30 are equal to each other.

[0089] The semiconductor device 10 of the second embodiment includes a dummy transistor 16. The dummy transistor 16 is composed of a second dummy gate electrode 36 and source regions 41 and drain regions 42 that are dispersedly arranged on both sides in the X direction of the second dummy gate electrode 36. The source region 41 of the dummy transistor 16 is common to the source region 41 of the main transistor 11. Therefore, the dummy transistor 16 is electrically connected to the main transistor 11 via the source region 41. The drain region 42 of the dummy transistor 16 is common to the drain region 42 of the second mirror transistor region 12B. Therefore, the dummy transistor 16 is electrically connected to the mirror transistor 12 via the drain region 42.

[0090] As shown in FIG. 11, the second dummy gate electrode 36 is connected to the second wiring 62 by a dummy gate contact 58. Therefore, the second dummy gate electrode 36 is electrically connected to the first dummy gate electrode 33, the first end dummy electrode 34, and the second end dummy electrode 35.

[0091] [Effects of the Second Embodiment] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) The plurality of gate electrodes 30 are arranged adjacent to the main gate electrode 31 with the source region 41 interposed therebetween on the side opposite to the first dummy gate electrode 33 with respect to the main gate electrode 31 in the X direction, and include a second dummy gate electrode 36 electrically connected to the source region 41.

[0092] According to this configuration, the first dummy gate electrode 33 and the second dummy gate electrode 36 are dispersedly arranged on both sides of the main gate electrode 31 in the X direction. Therefore, it is possible to improve the pairing as compared with a configuration in which the dummy gate electrode is arranged only on one side of the main gate electrode 31 in the X direction.

[0093] (2-2) The source region 41 of the dummy transistor 16 is common with the source region 41 of the main transistor 11. According to this configuration, it is possible to reduce the size of the semiconductor device 10 in the X direction as compared with the case where the source regions 41 of the dummy transistor 16 and the main transistor 11 are formed individually.

[0094] (2-3) The drain region 42 of the dummy transistor 16 is common with the drain region 42 of the second mirror transistor region 12B. According to this configuration, it is possible to reduce the size of the semiconductor device 10 in the X direction as compared with the case where the drain regions 42 of the dummy transistor 16 and the second mirror transistor region 12B are formed individually.

[0095] Between the main gate electrode 31 and the first end portion 25A of the active region 25, a first dummy gate electrode 33, two first mirror gate electrodes 32A, and a first end portion dummy electrode 34 are arranged. Between the main gate electrode 31 and the second end portion 25B of the active region 25, a second dummy gate electrode 36, two second mirror gate electrodes 32B, and a second end portion dummy electrode 35 are arranged. That is, the plurality of gate electrodes 30 can be symmetrically arranged around the main gate electrode 31 in the X direction. Therefore, the influence of the element isolation region 24 becomes equal for the gate electrodes 30 arranged between the main gate electrode 31 and the first end portion 25A and the gate electrodes 30 arranged between the main gate electrode 31 and the second end portion 25B. For this reason, symmetry in the arrangement of the plurality of gate electrodes 30 can be ensured, and the influence of the element isolation region 24 can be reduced.

[0096] <Modified Example> Each of the above embodiments can be implemented with the following modifications. Also, the following modified examples can be implemented in combination with each other within a technically non - conflicting range.

[0097] · In each embodiment, the length WA in the X direction of the first dummy gate electrode 33 can be arbitrarily changed. In one example, as shown in FIG. 12, the length WA in the X direction of the first dummy gate electrode 33 is longer than the length WS in the X direction of the main gate electrode 31. According to this configuration, the distance in the X direction between the main gate electrode 31 and the element isolation region 24 can be increased. Therefore, the influence of the element isolation region 24 on the main gate electrode 31 can be reduced.

[0098] In one example, the length WB in the X direction of the first end portion dummy electrode 34 is longer than the length WS in the X direction of the main gate electrode 31. According to this configuration, the distance in the X direction between the main gate electrode 31 and the element isolation region 24 can be increased. Therefore, the influence of the element isolation region 24 on the main gate electrode 31 can be reduced.

[0099] In one example, the length WC in the X direction of the second end dummy electrode 35 is longer than the length WS in the X direction of the main gate electrode 31. According to this configuration, the distance in the X direction between the main gate electrode 31 and the element isolation region 24 can be increased. Therefore, the influence of the element isolation region 24 on the main gate electrode 31 can be reduced.

[0100] In one example, the length WA in the X direction of the first dummy gate electrode 33 is shorter than the length WS in the X direction of the main gate electrode 31. According to this configuration, since the size of the active region 25 in the X direction can be reduced, the semiconductor device 10 can be miniaturized.

[0101] In one example, the length WB in the X direction of the first end dummy electrode 34 is shorter than the length WS in the X direction of the main gate electrode 31. According to this configuration, since the size of the active region 25 in the X direction can be reduced, the semiconductor device 10 can be miniaturized.

[0102] In one example, the length WC in the X direction of the second end dummy electrode 35 is shorter than the length WS in the X direction of the main gate electrode 31. According to this configuration, since the size of the active region 25 in the X direction can be reduced, the semiconductor device 10 can be miniaturized.

[0103] · In the second embodiment, the length WD in the X direction of the second dummy gate electrode 36 can be arbitrarily changed. In one example, the length WD in the X direction of the second dummy gate electrode 36 is longer than the length LS in the X direction of the main gate electrode 31. According to this configuration, the distance in the X direction between the main gate electrode 31 and the element isolation region 24 can be increased. Therefore, the influence of the element isolation region 24 on the main gate electrode 31 can be reduced.

[0104] In one example, the length WD in the X direction of the second dummy gate electrode 36 is shorter than the length LS in the X direction of the main gate electrode 31. According to this configuration, since the size of the active region 25 in the X direction can be reduced, the semiconductor device 10 can be miniaturized.

[0105] · In each embodiment, the length RS in the X direction of the plurality of source regions 41 can be arbitrarily changed. The length RS in the X direction of at least one of the plurality of source regions 41 may be different from the length RS in the X direction of the other source regions 41. In one example, as shown in FIG. 13, the length RS in the X direction of the source region 41 formed at the second end portion 25B of the active region 25 may be longer than the length RS in the X direction of the other source regions 41.

[0106] · In each embodiment, the length RD in the X direction of the plurality of drain regions 42 can be arbitrarily changed. The length RD in the X direction of at least one of the plurality of drain regions 42 may be different from the length RD in the X direction of the other drain regions 42. In one example, as shown in FIG. 13, the length RD in the X direction of the drain region 42 formed at the first end portion 25A of the active region 25 may be longer than the length RD in the X direction of the other drain regions 42.

[0107] · In the first embodiment, the configuration of the plurality of gate electrodes 30 can be arbitrarily changed. In one example, as shown in FIG. 14, the plurality of gate electrodes 30 may be composed of a main gate electrode 31, one mirror gate electrode 32, a first dummy gate electrode 33, and a second end dummy electrode 35. That is, the semiconductor device 10 includes a main transistor 11, a mirror transistor 12, and dummy transistors 13, 15.

[0108] More specifically, the first dummy gate electrode 33 is arranged adjacent to the main gate electrode 31 in the X direction with the drain region 42 interposed therebetween. For this reason, the drain region 42 of the main transistor 11 is common with the drain region 42 of the dummy transistor 13. In other words, the main transistor 11 and the dummy transistor 13 are electrically connected via the drain region 42.

[0109] On the side of the first dummy gate electrode 33 opposite to the drain region 42 in the X direction, a source region 41 is formed. The source region 41 adjacent to the first dummy gate electrode 33 is provided at the first end 25A of the active region 25.

[0110] The mirror gate electrode 32 is arranged adjacent to the main gate electrode 31 in the X direction with the source region 41 interposed therebetween. Therefore, the source region 41 of the main transistor 11 is common with the source region 41 of the mirror transistor 12. In other words, the main transistor 11 and the mirror transistor 12 are electrically connected via the source region 41. Also, a drain region 42 is formed on the side of the mirror gate electrode 32 opposite to the source region 41 in the X direction.

[0111] The second end dummy electrode 35 is arranged on the side opposite to the main gate electrode 31 with respect to the mirror gate electrode 32 in the X direction. The second end dummy electrode 35 is arranged adjacent to the mirror gate electrode 32 in the X direction with the drain region 42 interposed therebetween. Therefore, the mirror transistor 12 and the dummy transistor 15 are electrically connected via the drain region 42. Also, a source region 41 is formed on the side of the second end dummy electrode 35 opposite to the drain region 42 in the X direction. This source region 41 is provided at the second end 25B of the active region 25.

[0112] ·In each embodiment, the length of at least one of the plurality of gate electrodes 30 in the Y direction may be different from the length of the other gate electrodes 30 in the Y direction. ·In each embodiment, at least one of the first end dummy electrode 34 and the second end dummy electrode 35 may be omitted.

[0113] ·In each embodiment, the number of the first mirror gate electrodes 32A can be arbitrarily changed. Also, the number of the second mirror gate electrodes 32B can be arbitrarily changed. ·In each embodiment, one of the first mirror gate electrode 32A and the second mirror gate electrode 32B may be omitted.

[0114] ·In each embodiment, a plurality of first dummy gate electrodes 33 may be provided. The plurality of first dummy gate electrodes 33 are arranged to be spaced apart from each other in the X direction. ·In the second embodiment, a plurality of second dummy gate electrodes 36 may be provided. The plurality of second dummy gate electrodes 36 are arranged to be spaced apart from each other in the X direction.

[0115] ·As shown in FIG. 15, the semiconductor device 10 may include a cascode current mirror circuit CM2. The cascode current mirror circuit CM2 includes first to fourth transistors M1 to M4. For the first to fourth transistors M1 to M4, for example, p-type MOSFETs are used. The gates of the first transistor M1 and the second transistor M2 are connected to each other and connected to the drain of the first transistor M1. The source of the first transistor M1 is connected to the drain of the third transistor M3. The source of the second transistor M2 is connected to the drain of the fourth transistor M4. The gates of the third transistor M3 and the fourth transistor M4 are connected to each other and connected to the drain of the third transistor M3. The sources of the third transistor M3 and the fourth transistor M4 are connected to each other and connected to a power supply wiring.

[0116] The first to fourth transistors M1 to M4 are constituted by the transistors 11 to 15 shown in FIGS. 1 and 4. More specifically, the first transistor M1 and the third transistor M3 are constituted by the main transistor 11 and the dummy transistor 13 shown in FIGS. 1 and 4. The second transistor M2 and the fourth transistor M4 are constituted by the mirror transistor 12 and the dummy transistors 14 and 15 shown in FIGS. 1 and 4.

[0117] The first to fourth transistors M1 to M4 may be constituted by the transistors 11 to 16 shown in FIGS. 10 and 11. The first transistor M1 and the second transistor M2 are constituted by the transistors 11 to 15 shown in FIGS. 1 and 4, and the third transistor M3 and the fourth transistor M4 may be constituted by the transistors 11 to 16 shown in FIGS. 10 and 11. Also, the first transistor M1 and the second transistor M2 may be constituted by the transistors 11 to 16 shown in FIGS. 10 and 11, and the third transistor M3 and the fourth transistor M4 may be constituted by the transistors 11 to 15 shown in FIGS. 1 and 4.

[0118] The cascode current mirror circuit CM2 shown in FIG. 15 shows an example of the connection of the first to fourth transistors M1 to M4. For example, it may be a cascode current mirror circuit in which a bias voltage is supplied to the gates of the first transistor M1 and the second transistor M2, and the gates of the third transistor M3 and the fourth transistor M4 are connected to each other and connected to the drain of the first transistor M1.

[0119] ·In each embodiment, the current mirror circuit CM1 may be constituted by an n-type MOSFET. ·In each embodiment, the semiconductor device 10 may include a current mirror circuit constituted by a p-type MOSFET and a current mirror circuit constituted by an n-type MOSFET.

[0120] ·In each embodiment, a source region 41 may be formed between the first end dummy electrode 34 and the first end 25A of the active region 25 in the X direction. ·In each embodiment, a drain region 42 may be formed between the second end dummy electrode 35 and the second end 25B of the active region 25 in the X direction.

[0121] One or more of the various examples described in this specification can be combined within a technically consistent range. As used herein, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended that in some embodiments, the first element may be in direct contact with the second element and disposed directly on the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. That is, the term "on" does not exclude a structure in which other elements are formed between the first element and the second element.

[0122] The Z direction used in the present disclosure does not necessarily have to be the vertical direction and does not have to be completely consistent with the vertical direction. Therefore, various structures according to the present disclosure are not limited to the "up" and "down" in the Z direction described herein being the "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0123] <Supplementary Note> The technical idea that can be grasped from the present disclosure is described below. For the purpose of assisting understanding rather than limitation, the components described in the supplementary note are assigned the reference numerals of the corresponding components in the above embodiments. The reference numerals are shown as examples for assisting understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0124] [Supplementary Note 1] A semiconductor device (10) that constitutes a current mirror circuit by a main transistor (11) including a main gate electrode (31) and a mirror transistor (12) including a mirror gate electrode (32), A semiconductor layer (22) including a first surface (22S), A well region (23) formed on the first surface (22S) of the semiconductor layer (22), A frame-shaped element isolation region (24) formed in the well region (23), An active region (25) surrounded by the element isolation region (24) and including a first end portion (25A) in a first direction (X) and a second end portion (25B) opposite to the first end portion (25A) when viewed from a direction (Z) perpendicular to the first surface (22S); A plurality of gate electrodes (30) disposed between the first end portion (25A) and the second end portion (25B) and extending across the active region (25) in a second direction (Y) orthogonal to both the first direction (X) and a direction (Z) perpendicular to the first surface (22S); A plurality of source regions (41) and a plurality of drain regions (42) provided in the active region (25), sandwiching the plurality of gate electrodes (30) and alternately arranged in the first direction (X); comprising The plurality of gate electrodes (30) include a main gate electrode (31) disposed so as to sandwich at least one of the gate electrodes (30) with respect to both the first end portion (25A) and the second end portion (25B); A first dummy gate electrode (33) disposed between the main gate electrode (31) and the first end portion (25A) in the first direction (X), disposed adjacent to the main gate electrode (31) with the drain region (42) therebetween, and electrically connected to the source region (41); At least one mirror gate electrode (32) electrically connected to the main gate electrode (31); including a semiconductor device.

[0125] [Appendix 2] The plurality of gate electrodes (30) include an end dummy gate electrode (34) disposed adjacent to the first end portion (25A) in the first direction (X) and electrically connected to the source region (41); The mirror gate electrode (32) is disposed between the end dummy gate electrode (34) and the first dummy gate electrode (33) in the first direction (X). The semiconductor device according to Appendix 1.

[0126] [Appendix 3] The plurality of gate electrodes (30) are arranged adjacent to the first end portion (25A) or the second end portion (25B) in the first direction (X), and include end dummy gate electrodes (34 / 35) electrically connected to the source region (41), The mirror gate electrode (32) is arranged between the end dummy gate electrode (34 / 35) and the main gate electrode (31) in the first direction (X). The semiconductor device according to Appendix 1.

[0127] [Appendix 4] The plurality of gate electrodes (30) are a first end dummy electrode (34) arranged adjacent to the first end portion (25A) in the first direction (X) and electrically connected to the source region (41), a second end dummy electrode (35) arranged adjacent to the second end portion (25B) in the first direction (X) and electrically connected to the source region (41), and include The mirror gate electrode (32) is at least one first mirror gate electrode (32A) arranged between the first end dummy electrode (34) and the main gate electrode (31) in the first direction (X), at least one second mirror gate electrode (32B) arranged between the second end dummy electrode (35) and the main gate electrode (31) in the first direction (X), and include The semiconductor device according to Appendix 1.

[0128] [Appendix 5] The drain region (42) of the main transistor (11) is electrically connected to the main gate electrode (31), the first mirror gate electrode (32A), and the second mirror gate electrode (32B). The semiconductor device according to Appendix 4.

[0129] [Appendix 6] The first dummy gate electrode (34) is provided between the main gate electrode (31) and the first mirror gate electrode (32A) in the first direction (X). The main gate electrode (31) and the second mirror gate electrode (32) are arranged at positions adjacent to each other via the source region (41) in the first direction (X). The semiconductor device according to appended note 4 or 5.

[0130] [Appended note 7] A source region (41) or a drain region (42) is provided between the first end dummy electrode (34) and the first end (25A) in the first direction (X). A source region (41) or a drain region (42) is provided between the second end dummy electrode (35) and the second end (25B) in the first direction (X). The semiconductor device according to any one of appended notes 4 to 6.

[0131] [Appended note 8] The first mirror gate electrode (32A) includes a plurality of first mirror gate electrodes (32AA, 32AB) arranged spaced apart from each other in the first direction (X). The second mirror gate electrode (32B) includes a plurality of second mirror gate electrodes (32BA, 32BB, 32BC) arranged spaced apart from each other in the first direction (X). The semiconductor device according to any one of appended notes 4 to 7.

[0132] [Appended note 9] The number of the first mirror gate electrodes (32A) is different from the number of the second mirror gate electrodes (32B). The semiconductor device according to appended note 8.

[0133] [Appended note 10] The number of the first mirror gate electrodes (32A) is equal to the number of the second mirror gate electrodes (32B). The semiconductor device according to appended note 8.

[0134] [Supplementary Note 11] The plurality of gate electrodes (30) are arranged adjacent to the main gate electrode (31) with the source region (41) therebetween on the side opposite to the first dummy gate electrode (33) with respect to the main gate electrode (31) in the first direction (X), and include a second dummy gate electrode (36) electrically connected to the source region (41). The semiconductor device according to any one of Supplementary Notes 1 to 5.

[0135] [Supplementary Note 12] The lengths of the plurality of gate electrodes (30) in the first direction (X) are equal to each other. The semiconductor device according to any one of Supplementary Notes 1 to 11.

[0136] [Supplementary Note 13] The length (WA) of the first dummy gate electrode (33) in the first direction (X) is greater than the length (WS) of the main gate electrode (31) in the first direction (X). The semiconductor device according to any one of Supplementary Notes 1 to 11.

[0137] [Supplementary Note 14] The lengths (RS, RD) of the plurality of source regions (41) and the plurality of drain regions (42) in the first direction (X) are equal to each other. The semiconductor device according to any one of Supplementary Notes 1 to 13.

[0138] [Supplementary Note 15] The lengths (RS, RD) of the source region (41) or the drain region (42) at the first end portion (25A) or the second end portion (25B) in the first direction (X) are longer than the lengths (RS, RD) of the source region (41) or the drain region (42) between the first end portion (25A) and the second end portion (25B) in the first direction (X). The semiconductor device according to any one of Supplementary Notes 1 to 13.

[0139] [Supplementary Note 16] The plurality of source regions (41) are electrically connected to each other. The semiconductor device according to any one of Supplementary Notes 1 to 15.

[0140] The above description is merely illustrative. Those skilled in the art can recognize that there are more possible combinations and substitutions other than the components and methods (manufacturing processes) enumerated for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to include all alternatives, modifications, and changes within the scope of the present disclosure including the claims.

Description of Reference Numerals

[0141] 10…Semiconductor device 11…Main transistor 12…Mirror transistor 12A…First mirror transistor region 12B…Second mirror transistor region 13 to 16…Dummy transistors 16…Constant current source 17…Dummy transistor 21…Semiconductor substrate 21S…First surface 21R…Second surface 22…Semiconductor layer 22S…First surface 22R…Second surface 23…Well region 23A to 23D…First to fourth ends 24…Element isolation region 25…Active region 25A to 25D…First to fourth ends 26…Gate insulating film 30…Gate electrode 31…Main gate electrode 32…Mirror gate electrode 32A, 32AA, 32AB…First mirror gate electrode 32B, 32BA, 32BB, 32BC…Second mirror gate electrode 33…First dummy gate electrode 34…First end dummy electrode 35…Second end dummy electrode 36…Second dummy gate electrode 41… Source region 42… Drain region 51… Main gate contact 52… Mirror gate contact 53~55…Dummy gate contact 56… Source contact 57… Drain contact 58…Dummy gate contact 61… First wiring 62… Second wiring 63… Third wiring 64… Fourth wiring 81… Constant current source 82… Ammeter CM1,CM2… Current mirror circuit M1~M4… First~Fourth transistor WS… Length of the main gate electrode in the X direction WM… Length of the mirror gate electrode in the X direction WA… Length of the first dummy gate electrode in the X direction WB… Length of the first end dummy electrode in the X direction WC… Length of the second end dummy electrode in the X direction WD… Length of the second dummy gate electrode in the X direction LS… Length of the main gate electrode in the Y direction LM… Length of the mirror gate electrode in the Y direction LA… Length of the first dummy gate electrode in the Y direction LB… Length of the first end dummy electrode in the Y direction LC… Length of the second end dummy electrode in the Y direction LD… Length of the second dummy gate electrode in the Y direction RD… Length of the drain region in the X direction RS… Length of the source region in the X direction GAA… Distance between the main gate electrode and the element isolation region in the X direction GAB… Shortest distance between the mirror gate electrode and the element isolation region in the X direction 10X… Semiconductor device of the first comparative example 10Y… Semiconductor device of the second comparative example 11X… Main transistor 12XA to 12XD, 12X1 to 12X3, 12Y1 to 12Y3... Mirror transistor 23X... Well region 24X... Element isolation region of the first comparative example 24XA... Intermediate region 24Y... Element isolation region of the second comparative example 24YA... Outer peripheral region 24YB... First intermediate region 24YC... Second intermediate region 25X, 25Y1, 25Y2... Active region 31X... Main gate electrode 32X... Mirror gate electrode 41X... Source region 42X... Drain region GA1, GA2... Distance in the X direction between the main gate electrode and the element isolation region of the second comparative example GA3 to GA6... Maximum distance in the X direction between the mirror gate electrode and the element isolation region of the second comparative example

Claims

1. A semiconductor device that forms a current mirror circuit with a main transistor including a main gate electrode and a mirror transistor including a mirror gate electrode, a semiconductor layer including a first surface, a well region formed on the first surface of the semiconductor layer, a frame-shaped element isolation region formed in the well region, an active region surrounded by the element isolation region and including a first end portion in a first direction and a second end portion opposite to the first end portion when viewed from a direction perpendicular to the first surface, a plurality of gate electrodes disposed between the first end portion and the second end portion and extending across the active region in a second direction orthogonal to both the first direction and a direction perpendicular to the first surface, a plurality of source regions and a plurality of drain regions provided in the active region, sandwiching the plurality of gate electrodes and alternately arranged in the first direction, including, the plurality of gate electrodes include, the main gate electrode disposed so as to sandwich at least one of the gate electrodes with respect to both the first end portion and the second end portion, a first dummy gate electrode disposed between the main gate electrode and the first end portion in the first direction, adjacent to the main gate electrode with the drain region therebetween, and electrically connected to the source region, at least one mirror gate electrode electrically connected to the main gate electrode, including a semiconductor device.

2. The plurality of gate electrodes include, an end dummy gate electrode disposed adjacent to the first end portion in the first direction and electrically connected to the source region, the mirror gate electrode is disposed between the end dummy gate electrode and the first dummy gate electrode in the first direction The semiconductor device according to claim 1.

3. The plurality of gate electrodes include, an end dummy gate electrode disposed adjacent to the first end portion or the second end portion in the first direction and electrically connected to the source region, the mirror gate electrode is disposed between the end dummy gate electrode and the main gate electrode in the first direction The semiconductor device according to claim 1.

4. The plurality of gate electrodes include, a first end dummy electrode disposed adjacent to the first end portion in the first direction and electrically connected to the source region, A second-end dummy electrode that is disposed adjacent to the second end in the first direction and is electrically connected to the source region, including the mirror gate electrode is at least one first mirror gate electrode disposed between the first-end dummy electrode, the main gate electrode, and the first direction, at least one second mirror gate electrode disposed between the second-end dummy electrode, the main gate electrode, and the first direction, including The semiconductor device according to claim 1.

5. The drain region of the main transistor is electrically connected to the main gate electrode, the first mirror gate electrode, and the second mirror gate electrode. The semiconductor device according to claim 4.

6. The first dummy gate electrode is provided between the main gate electrode and the first mirror gate electrode in the first direction, The main gate electrode and the second mirror gate electrode are disposed adjacent to each other with the source region therebetween in the first direction. The semiconductor device according to claim 4.

7. A source region or a drain region is provided between the first-end dummy electrode and the first end in the first direction, A source region or a drain region is provided between the second-end dummy electrode and the second end in the first direction. The semiconductor device according to claim 4.

8. The first mirror gate electrode includes a plurality of first mirror gate electrodes arranged spaced apart from each other in the first direction, The second mirror gate electrode includes a plurality of second mirror gate electrodes arranged spaced apart from each other in the first direction. The semiconductor device according to claim 4.

9. The number of the first mirror gate electrodes is different from the number of the second mirror gate electrodes. The semiconductor device according to claim 8.

10. The number of the first mirror gate electrodes is equal to the number of the second mirror gate electrodes. The semiconductor device according to claim 8.

11. The plurality of gate electrodes are disposed adjacent to the main gate electrode across the source region on the side opposite to the first dummy gate electrode with respect to the main gate electrode in the first direction, and include a second dummy gate electrode electrically connected to the source region. The semiconductor device according to claim 1.

12. The lengths of the plurality of gate electrodes in the first direction are equal to each other. The semiconductor device according to claim 1.

13. The length of the first dummy gate electrode in the first direction is greater than the length of the main gate electrode in the first direction The semiconductor device according to claim 1

14. The lengths of the plurality of source regions and the plurality of drain regions in the first direction are equal to each other The semiconductor device according to claim 1

15. The length of the source region or the drain region at the first end or the second end in the first direction is longer than the length of the source region or the drain region between the first end and the second end in the first direction The semiconductor device according to claim 1

16. The plurality of source regions are electrically connected to each other The semiconductor device according to any one of claims 1 to 15

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