Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device that can have excellent ohmic characteristics and also suppress chipping and cracking in dicing, and a method of manufacturing the same.SOLUTION: A semiconductor device 1 has a device region 2 and a dicing line region 3 encircling the device region 2. A surface electrode 5 is provided on a top surface of the semiconductor device 1 in the device region 2. A metallic back electrode 7 is provided on the reverse surface of the semiconductor substrate 1 on the opposite side from the top surface. A first silicide layer 8 is provided between the reverse surface and the back electrode 7 in the device region 2. A second silicide layer 9 is provided between the reverse surface and the back electrode 7 in the dicing region 3. The first silicide layer 8 has less resistance of contact with the semiconductor substrate 1 than the second silicide layer 9.l The second silicide layer 9 has larger hardness than the first silicide layer 8.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A silicide layer is formed to reduce the contact resistance between the back surface of a semiconductor substrate and a back surface electrode. The silicide layer is formed on the entire back surface of a semiconductor substrate in a wafer state including a dicing line region (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is necessary to form a silicide layer having good ohmic characteristics with a semiconductor substrate in order to reduce electrical resistance. However, such a silicide layer has high hardness and is resistant to mechanical stress. For this reason, when mechanical stress is applied to the silicide layer during dicing, the stress propagates to the semiconductor substrate and the back surface electrode in contact with the silicide layer, and chipping or cracking occurs starting from crystal defects or structural stress concentration points, causing problems such as breakdown voltage failure or appearance failure.

[0005] The present disclosure has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device and a method for manufacturing the same that can obtain good ohmic characteristics and suppress the occurrence of chipping and cracking during dicing.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate having a device region and a dicing line region surrounding the device region, a surface electrode provided on the surface of the semiconductor substrate in the device region, a metal back surface electrode provided on the back surface of the semiconductor substrate opposite to the surface, a second silicide layer provided between the back surface and the back surface electrode in the pre-dicing line region, and a first silicide layer provided between the back surface and the back surface electrode in the device region. The first silicide layer has a lower contact resistance with the semiconductor substrate than the second silicide layer, and the second silicide layer has a lower hardness than the first silicide layer.

[0007] The manufacturing method of the semiconductor device according to the present disclosure includes a step of forming a surface electrode on the surface of the semiconductor substrate in the device region of a semiconductor substrate having a device region and a dicing line region surrounding the device region, a step of forming a metal film on the back surface of the semiconductor substrate opposite to the surface, and alloying the semiconductor substrate and the metal film by heat treatment to form a first silicide layer on the back surface in the device region and a second silicide layer on the back surface in the dicing line region. The first silicide layer has a lower contact resistance with the semiconductor substrate than the second silicide layer, and the second silicide layer has a lower hardness than the first silicide layer.

Advantages of the Invention

[0008] In the present disclosure, the first silicide layer in the device region has a low contact resistance with the semiconductor substrate. Thereby, good ohmic characteristics can be obtained between the semiconductor substrate and the back surface electrode in the device region. On the other hand, the second silicide layer in the dicing line region has a low hardness. Thereby, since the mechanical stress when cutting the second silicide layer by dicing can be reduced, the propagation of stress to the semiconductor substrate in contact with the second silicide layer can be suppressed. As a result, the occurrence of chipping and cracks during dicing can be suppressed.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] A semiconductor device and its manufacturing method according to an embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and repeated description may be omitted.

[0011] Embodiment 1. FIG. 1 is a top view showing a semiconductor wafer according to Embodiment 1. A plurality of device regions 2 are regularly arranged in a matrix vertically and horizontally on a semiconductor substrate 1 in a wafer state. Dicing line regions 3 surround the respective device regions 2.

[0012] FIG. 2 is a cross-sectional view showing a semiconductor device according to Embodiment 1. The semiconductor substrate 1 is formed of silicon or silicon carbide. The semiconductor substrate 1 has a high-concentration n-type layer 1a and an n-type drift layer 1b provided thereon. The high-concentration n-type layer 1a has a higher concentration of n-type impurities than the n-type drift layer 1b. Note that the n-type drift layer 1b may be provided on a single-crystal high-concentration p-type layer, or only the single-crystal n-type drift layer 1b may be used.

[0013] In the device region 2 of the semiconductor substrate 1, for example, a vertical MOSFET, a diode, or an IGBT is provided. In this case, unevenness such as a p-type layer, an n-type layer, and a trench is partially or entirely provided on the front surface side or the back surface side of the semiconductor substrate 1. The device region 2 has an active region through which current flows during device operation, a termination region for holding breakdown voltage provided around the active region, a region where a gate pad is formed, and the like. A diffusion layer such as a p-type base layer is formed in the active region. However, in the case of a Schottky barrier diode or when the semiconductor substrate 1 is used as a resistor, a diffusion layer is not necessarily required in the device region 2.

[0014] In the device region 2, an interlayer insulating film 4, a surface electrode 5, and a protective film 6 are provided on the surface of the semiconductor substrate 1. The surface electrode 5 is connected to the surface of the semiconductor substrate 1 through an opening in the interlayer insulating film 4. The protective film 6 covers and protects the outer peripheral portion of the surface electrode 5.

[0015] The surface electrode 5 is composed of one or more types of metal films, and is formed of a metal film containing, for example, titanium (Ti) or aluminum (Al). An electroless plating film or an electrolytic plating film may be formed on the metal film. The protective film 6 is composed of, for example, at least one of silicon nitride (SiN), SInSiN (Semi-Insulating Silicon Nitride), and polyimide.

[0016] In the dicing line region 3, the interlayer insulating film 4, the surface electrode 5, and the protective film 6 are not provided. By removing a substance having a hardness different from that of the semiconductor substrate 1 from the dicing line region 3, mechanical stress in dicing can be reduced.

[0017] A metal back surface electrode 7 is provided on the back surface of the semiconductor substrate 1 opposite to the surface thereof. The back surface electrode 7 is composed of one or more types of metal films, similar to the surface electrode 5, and a plating film may be formed on these metal films. In the device region 2, a first silicide layer 8 is provided between the back surface of the semiconductor substrate 1 and the back surface electrode 7. In the dicing line region 3, a second silicide layer 9 is provided between the back surface of the semiconductor substrate 1 and the back surface electrode 7. The first silicide layer 8 and the second silicide layer 9 are in contact with the back surface of the semiconductor substrate 1.

[0018] FIG. 3 is a bottom view showing the silicide layer on the back surface of the semiconductor wafer according to the first embodiment. A first silicide layer 8 is provided in the device region 2. A second silicide layer 9 is provided in a region other than the device region 2, such as the dicing line region 3.

[0019] The first silicide layer 8 and the second silicide layer 9 are metal compounds containing silicon (Si), such as titanium silicide film (Ti 5 Si 3 , TiSi, TiSi 2 ), titanium silicon carbide film (Ti 3 SiC 2 ), nickel silicide film (Ni 2 Si, NiSi, NiSi 2) molybdenum silicide film (Mo 3 Si, Mo 5 Si 3 , MoSi 2 ), aluminum silicide film (Al - Si), tungsten silicide film (W 5 Si 3 , WSi 2 ). The first silicide layer 8 and the second silicide layer 9 may be a combination of compounds of different metal elements, or a combination of compounds of the same metal element with different composition ratios.

[0020] The first silicide layer 8 has a lower contact resistance with the semiconductor substrate 1 than the second silicide layer 9. Therefore, good ohmic characteristics can be obtained for the first silicide layer 8. On the other hand, although the second silicide layer 9 has a high contact resistance with the semiconductor substrate 1, since it is formed in the dicing line region 3, it does not affect the electrical characteristics of the semiconductor device. Also, a metal compound with a high contact resistance tends to have a low hardness. The second silicide layer 9 in the dicing line region 3 has a lower hardness and a thinner film thickness than the first silicide layer 8. Therefore, the mechanical stress when cutting the second silicide layer 9 during dicing can be reduced.

[0021] FIG. 4 is a cross - sectional view showing a semiconductor device according to Embodiment 1 fragmented by dicing. FIG. 5 is a top view showing the fragmented semiconductor device according to Embodiment 1. FIG. 6 is a bottom view showing the fragmented semiconductor device according to Embodiment 1. Note that the wafer - shaped semiconductor substrate 1 is adhered to a dicing sheet (not shown) during dicing.

[0022] The dicing line region 3 is divided by dicing into an invalid region 3a and a dicing cutting region 3b. The invalid region 3a is adjacent to the device region 2. The fragmented semiconductor device includes at least a part of the invalid region 3a. The second silicide layer 9 is provided on the back surface of the semiconductor substrate 1 in the invalid region 3a.

[0023] Since the cutting width of dicing by the blade is about 30 μm, it is preferable to add the positional accuracy α of the blade to the dicing line region 3 and secure 30 + α μm. That is, it is preferable that the width of the dicing line region 3 is 30 μm or more. Thereby, the second silicide layer can be formed in all the passing regions of the dicing blade.

[0024] Figs. 7 to 10 are cross-sectional views showing a method of manufacturing a semiconductor device according to Embodiment 1. First, as shown in Fig. 7, an n-type drift layer 1b is epitaxially grown on a single-crystalline high-concentration n-type layer 1a to form a semiconductor substrate 1.

[0025] Next, as shown in Fig. 8, an interlayer insulating film 4, a surface electrode 5, and a protective film 6 are partially formed on the surface of the semiconductor substrate 1 by a mask process. Note that unevenness such as a p-type layer, an n-type layer, and a trench may be partially or entirely formed on the front surface side or the back surface side of the semiconductor substrate 1 by ion implantation or etching. The thickness of the semiconductor substrate 1 may be thinned.

[0026] Next, as shown in Fig. 9, a metal film 10 is formed on the back surface of the semiconductor substrate 1 by sputtering or vapor deposition. Heat treatment is applied to the metal film 10. Thereby, the silicon of the semiconductor substrate 1 and the metal atoms of the metal film 10 diffuse mutually to form a second silicide layer 9. The heat treatment method is sintering, RTA (Rapid Thermal Anneal), FLA (Flash Lamp Anneal), or laser annealing, etc. The heat treatment temperature is set to a slightly low temperature of about 300 to 800°C. Thereby, a second silicide layer 9 having a high contact resistance with the semiconductor substrate 1 is formed, and the film thickness of the second silicide layer 9 becomes thin.

[0027] Further, the second silicide layer 9 may be formed by the energy at which metal ions are deposited in the sputtering process, and the alloying may be accelerated by adjusting the sputtering process temperature. Further, during the sputtering process, by etching the back surface of the semiconductor substrate 1 (sputter etch), strain in the crystal of the semiconductor substrate 1 is formed, making it easier to generate the second silicide layer 9 with high contact resistance. By forming the second silicide layer 9 by adjusting these sputtering process conditions, the heat treatment process can be reduced.

[0028] Next, as shown in FIG. 10, a laser is irradiated onto the back surface of the semiconductor substrate 1 only in the device region 2. The thermal reaction of the silicide in the device region 2 is promoted to form the first silicide layer 8. The heat treatment temperature is higher than the temperature at the time of forming the second silicide layer 9, for example, 800° C. or higher. As a result, the first silicide layer 8 has a thicker film thickness and a higher silicon composition ratio with respect to the metal element than the second silicide layer 9.

[0029] Thereafter, a back surface electrode 7 is formed on the back surface of the semiconductor substrate 1 by sputtering, vapor deposition, electroless plating, electroplating, or the like. Note that all of the metal film 10 may be alloyed as the silicide layer, or the remainder of the metal film 10 may be used as the back surface electrode 7. The semiconductor device according to the present embodiment is manufactured by the above steps.

[0030] As described above, in the present embodiment, the first silicide layer 8 in the device region 2 has a low contact resistance with the semiconductor substrate 1. Thereby, good ohmic characteristics can be obtained between the semiconductor substrate 1 and the back surface electrode 7 in the device region 2. On the other hand, the second silicide layer 9 in the dicing line region 3 has a low hardness. Thereby, since the mechanical stress when cutting the second silicide layer 9 by dicing can be reduced, the propagation of stress to the semiconductor substrate 1 in contact with the second silicide layer 9 can be suppressed. As a result, the occurrence of chipping and cracking during dicing can be suppressed.

[0031] Also, the second silicide layer is thinner in film thickness than the first silicide layer 8. As a result, the mechanical stress when cutting the second silicide layer 9 during dicing can be further reduced.

[0032] Also, the composition ratio of silicon to the metal element in the first silicide layer 8 in the device region 2 is higher than that in the second silicide layer 9 in the dicing line region 3. As a result, good ohmic characteristics with the semiconductor substrate 1 can be obtained. For example, when the first silicide layer 8 is TiSi 2 and the second silicide layer 9 is Ti 5 Si 3 . Therefore, since the first silicide layer 8 has a higher composition ratio of silicon, it has a low contact resistance with the semiconductor substrate 1 and good ohmic characteristics can be obtained. On the other hand, since the second silicide layer 9 has a higher composition ratio of metal elements, its contact resistance with the semiconductor substrate 1 is high, but its crystal lattice is sparse, so its hardness is low. As a result, the propagation of stress to the semiconductor substrate 1 during cutting of the second silicide layer 9 in dicing can be suppressed.

[0033] Also, the first silicide layer 8 and the second silicide layer 9 may be silicide layers having different crystal structures from each other. However, the first silicide layer 8 in the device region 2 has a crystal structure with a lower resistivity than the second silicide layer 9. Therefore, the on-voltage can be reduced. For example, the first silicide layer is titanium silicide (TiSi 2 ) having a C54 structure (face-centered orthorhombic system), and the second silicide layer is TiSi 2 having a C49 structure (body-centered orthorhombic system). The silicide with the C54 structure has a dense atomic arrangement, so it has good ohmic properties and high hardness. The resistivity of titanium silicide with the C49 structure is about 60 μΩ·cm, and the resistivity of titanium silicide with the C54 structure is about 15 - 20 μΩ·cm. Therefore, good electrical resistance can be obtained in the device region 2. Since the C49 structure is formed at a low temperature of about 400°C and the C54 structure is formed at a high temperature of about 800°C, the first silicide layer 8 and the second silicide layer 9 can be differentiated according to the heat treatment conditions during silicide formation.

[0034] Also, the first silicide layer 8 and the second silicide layer 9 may be silicide layers with different crystallinities from each other. For example, the second silicide layer 9 may be in a quasi-crystalline state or an amorphous state (non-crystalline). Since amorphous titanium silicide has a lower hardness than crystalline titanium silicide, it is possible to suppress the propagation of stress to the semiconductor substrate 1 during dicing of the second silicide layer 9. On the other hand, the first silicide layer 8 is a metal compound containing silicon in a crystalline state in order to obtain good ohmic characteristics. Since the silicide in the crystalline state has a dense atomic arrangement, it has good ohmic properties and high hardness. When the semiconductor substrate 1 is sputtered or etched (sputter etch) on the surface of the semiconductor substrate 1, crystal distortion occurs, and when a metal film is formed thereafter, metal elements enter the crystal gaps and a layer in a quasi-crystalline state or an amorphous state is formed. Thereafter, by performing heat treatment only on the device region 2, a crystalline state is obtained and the first silicide layer 8 is formed. The dicing line region 3 without heat treatment becomes the second silicide layer 9 in a quasi-crystalline state or an amorphous state.

[0035] Embodiment 2. FIGS. 11 to 14 are cross-sectional views showing a method of manufacturing a semiconductor device according to Embodiment 2. First, as in Embodiment 1, a semiconductor substrate 1 is formed, and an interlayer insulating film 4, a surface electrode 5, and a protective film 6 are partially formed on the surface of the semiconductor substrate 1.

[0036] Next, as shown in FIG. 11, a first metal film 10a is formed on the back surface of the semiconductor substrate 1 by sputtering or vapor deposition. At this time, an arbitrary silicide layer may be formed between the semiconductor substrate 1 and the first metal film 10a.

[0037] Next, as shown in FIG. 12, a resist 11 is formed on the back surface side of the semiconductor substrate 1 in the device region 2. Using the resist 11 as a mask, the first metal film 10a in the dicing line region 3 is removed by etching. Also, when an arbitrary silicide layer is formed on the back surface side of the semiconductor substrate 1 in the dicing line region 3, it is removed simultaneously. Thereafter, the resist 11 is removed.

[0038] Next, as shown in FIG. 13, a second metal film 10b is formed on the back surface of the exposed semiconductor substrate 1 by sputtering or vapor deposition. At this time, an arbitrary silicide layer may be formed between the semiconductor substrate 1 and the second metal film 10b. Note that the first metal film 10a and the second metal film 10b may be made of the same type of metal or different types of metals.

[0039] Next, as shown in FIG. 14, the entire back surface of the semiconductor substrate 1 is irradiated with a laser to perform laser annealing. As a result, the semiconductor substrate 1 and the first metal film 10a undergo a thermal reaction to form a second silicide layer 9, and the semiconductor substrate 1 and the second metal film 10b undergo a thermal reaction to form a first silicide layer 8.

[0040] Select a metal type with excellent ohmic properties as the first metal film 10a. For example, titanium is selected as the first metal film 10a for an n-type semiconductor substrate 1. On the other hand, aluminum is selected as the second metal film 10b.

[0041] Also, the thicker the film thickness of the metal film, the thicker the thickness of the silicide formed by heat treatment. Therefore, the film thickness of the first metal film 10a is made thicker than that of the second metal film 10b. As a result, the thickness of the first silicide layer 8 in the device region 2 becomes thicker.

[0042] Adjust the conditions of the laser annealing so as to perform sufficient heat treatment with respect to the film thickness of the first metal film 10a. As a result, the film thickness of the first silicide layer 8 can be made thicker than that of the second silicide layer 9, and good ohmic characteristics with the semiconductor substrate 1 can be obtained. Note that if the heat treatment is insufficient, it is difficult to make the difference in thickness between the first silicide layer 8 and the second silicide layer 9.

[0043] In this embodiment, a second silicide layer 9 and a first silicide layer 8 of different metal elements can be formed. Further, the first silicide layer 8 and the second silicide layer 9 can be formed collectively by irradiating the entire surface with a laser without performing pattern irradiation of laser annealing. Other configurations and effects are the same as those in Embodiment 1.

[0044] As described above, the preferred embodiments have been described in detail. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims. Hereinafter, aspects of the present disclosure will be summarized as appendices. (Appendix 1) A semiconductor substrate having a device region and a dicing line region surrounding the device region, A surface electrode provided on the surface of the semiconductor substrate in the device region, A metal back surface electrode provided on the back surface of the semiconductor substrate opposite to the surface, A first silicide layer provided between the back surface and the back surface electrode in the device region, A second silicide layer provided between the back surface and the back surface electrode in the dicing line region, The first silicide layer has a lower contact resistance with the semiconductor substrate than the second silicide layer, A semiconductor device, wherein the second silicide layer has a lower hardness than the first silicide layer. (Appendix 2) The semiconductor device according to Appendix 1, wherein the second silicide layer is thinner than the first silicide layer. (Appendix 3) The semiconductor device according to Appendix 1 or 2, wherein the composition ratio of silicon to the metal element in the first silicide layer is larger than that in the second silicide layer. (Appendix 4) The semiconductor device according to Appendix 1 or 2, wherein the first silicide layer has a crystal structure with a lower resistivity than the second silicide layer. (Appendix 5) The first silicide layer is in a crystalline state, The semiconductor device according to appendix 1 or 2, characterized in that the second silicide layer is in a quasi-crystalline state or an amorphous state. (Appendix 6) The semiconductor device according to any one of appendices 1 to 5, characterized in that a plurality of the device regions are provided in a matrix on the semiconductor substrate in a wafer state. (Appendix 7) The semiconductor device according to any one of appendices 1 to 6, characterized in that the surface electrode is not provided on the surface in the dicing line region. (Appendix 8) The semiconductor device according to any one of appendices 1 to 7, characterized in that the width of the dicing line region is 30 μm or more. (Appendix 9) The semiconductor device according to any one of appendices 1 to 8, characterized in that the semiconductor substrate is formed of silicon or silicon carbide. (Appendix 10) A step of forming a surface electrode on the surface of the semiconductor substrate in the device region of the semiconductor substrate having a device region and a dicing line region surrounding the device region; A step of forming a metal film on the back surface opposite to the surface of the semiconductor substrate; A step of alloying the semiconductor substrate and the metal film by heat treatment to form a first silicide layer on the back surface in the device region and a second silicide layer on the back surface in the dicing line region; The first silicide layer has a lower contact resistance with the semiconductor substrate than the second silicide layer, The manufacturing method of a semiconductor device, characterized in that the second silicide layer has a lower hardness than the first silicide layer. (Appendix 11) The manufacturing method of the semiconductor device according to appendix 10, characterized in that the temperature of the heat treatment for the device region is higher than the temperature of the heat treatment for the dicing line region. (Appendix 12) The manufacturing method of the semiconductor device according to appended claim 10 or 11, characterized in that as the metal film, a first metal film is formed in the device region, and a second metal film different from the first metal film is formed in the dicing line region. (Appended claim 13) The manufacturing method of the semiconductor device according to appended claim 12, characterized in that laser annealing is performed on the entire back surface of the semiconductor substrate to alloy the semiconductor substrate and the first metal film to form the first silicide layer, and the semiconductor substrate and the second metal film are alloyed to form the second silicide layer.

Explanation of reference numerals

[0045] 1 Semiconductor substrate, 2 Device region, 3 Dicing line region, 5 Surface electrode, 7 Back surface electrode, 8 First silicide layer, 9 Second silicide layer, 10 Metal film, 10a First metal film, 10b Second metal film

Claims

1. A semiconductor substrate having a device region and a dicing line region surrounding the device region, A surface electrode provided on the surface of the semiconductor substrate in the device region, A metal back electrode provided on the back surface of the semiconductor substrate opposite to the surface, A first silicide layer provided between the back surface and the back electrode in the device region, A second silicide layer provided between the back surface and the back electrode in the dicing line region, and The first silicide layer has a lower contact resistance with the semiconductor substrate than the second silicide layer, A semiconductor device, wherein the second silicide layer has a lower hardness than the first silicide layer.

2. The semiconductor device according to claim 1, wherein the second silicide layer has a thinner film thickness than the first silicide layer.

3. The semiconductor device according to claim 1 or 2, wherein the composition ratio of silicon to the metal element in the first silicide layer is higher than that in the second silicide layer.

4. The semiconductor device according to claim 1 or 2, wherein the first silicide layer has a crystal structure with a lower resistivity than the second silicide layer.

5. The first silicide layer is in a crystalline state, The semiconductor device according to claim 1 or 2, wherein the second silicide layer is in a quasi-crystalline state or an amorphous state.

6. The semiconductor device according to claim 1 or 2, wherein a plurality of the device regions are provided in a matrix on the semiconductor substrate in a wafer state.

7. The semiconductor device according to claim 1 or 2, wherein the surface electrode is not provided on the surface in the dicing line region.

8. The semiconductor device according to claim 1 or 2, wherein the width of the dicing line region is 30 μm or more.

9. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is formed of silicon or silicon carbide.

10. A step of forming a surface electrode on the surface of the semiconductor substrate in the device region of a semiconductor substrate having a device region and a dicing line region surrounding the device region, A step of forming a metal film on the back surface of the semiconductor substrate opposite to the surface, A step of alloying the semiconductor substrate and the metal film by heat treatment to form a first silicide layer on the back surface in the device region and a second silicide layer on the back surface in the dicing line region is provided. The contact resistance of the first silicide layer with the semiconductor substrate is lower than that of the second silicide layer. A method of manufacturing a semiconductor device, characterized in that the second silicide layer has a lower hardness than the first silicide layer.

11. The method of manufacturing a semiconductor device according to claim 10, characterized in that the temperature of the heat treatment for the device region is higher than the temperature of the heat treatment for the dicing line region.

12. The method of manufacturing a semiconductor device according to claim 10 or 11, characterized in that as the metal film, a first metal film is formed in the device region and a second metal film different from the first metal film is formed in the dicing line region.

13. The method of manufacturing a semiconductor device according to claim 12, characterized in that laser annealing is performed on the entire back surface of the semiconductor substrate to alloy the semiconductor substrate and the first metal film to form the first silicide layer, and alloy the semiconductor substrate and the second metal film to form the second silicide layer.

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