Semiconductor device and electronic apparatus

Abstract

To provide a semiconductor device that is fine, consumes less power, has high reliability, and has a small off-state current.SOLUTION: A manufacturing method of a semiconductor device, includes steps of: forming a second insulation body 302 onto a first insulation body 301; forming a third insulation body 303 onto the second insulation body; forming an open part reached to the second insulation body on the third insulation body and forming a first conductor 310 in the open part and onto the third insulation body; removing a second conductor 311 and the first conductor that are positioned at a position higher than an upper surface of the third insulation body by performing a grinding processing after the second conductor onto the first conductor is formed; and further forming a third conductor 312 onto the second conductor. An end part of the first conductor is the same of or lower than a height of the end part of the open part at the end part of the open part. The height of the upper surface of the second conductor is the same of or higher than the end part of the first conductor. A wiring layer prevents an oxidation of the second conductor by having the first and third conductors that surround and cover a bottom surface, a side surface, and the upper surface of the second conductor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine , a manufacture, or a composition of matter. In particular , one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a storage device , a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to an acid semiconductor device, a display device, or a light-emitting device having an oxide semiconductor.

[0002] Note that, in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may have a semiconductor device.

Background Art

[0003] Silicon used for the semiconductor of a transistor is properly selected between amorphous silicon and polycrystalline silicon depending on the application. For example, for a transistor constituting a large display device, it is suitable to use amorphous silicon for which a film formation technique on a large-area substrate has been established. On the other hand, for a transistor constituting a high-functional display device in which a driving circuit and a pixel portion are integrally formed, it is suitable to use polycrystalline silicon capable of fabricating a transistor having a high field-effect mobility. Polycrystalline silicon is formed by performing heat treatment or laser light treatment on amorphous silicon at a high temperature. A method of forming is known.

[0004] In recent years, the development of transistors using an oxide semiconductor (typically In-Ga-Zn oxide) has been active. A transistor using an oxide semiconductor has higher performance than a transistor using amorphous silicon. performance than a transistor using amorphous silicon. The transistor has characteristics different from those of transistors using polycrystalline silicon. For example a display device to which a transistor using an oxide semiconductor is applied is known to have low power consumption.

[0005] Also, a transistor using an oxide semiconductor is known to have an extremely small leakage current in the non-conducting state. For example, a low-power CPU that applies the characteristic of low leakage current of a transistor using an oxide semiconductor is disclosed (see Patent Document 1).

[0006] In order to reduce power consumption by power gating, it is preferable that a transistor using an oxide semiconductor has normally-off electrical characteristics. As one method of controlling the threshold voltage of a transistor using an oxide semiconductor to have normally-off electrical characteristics, a method of disposing a floating gate in a region overlapping with the oxide semiconductor and injecting negative fixed charges into the floating gate is disclosed (see Patent Document 2).

[0007] Since an oxide semiconductor can be formed into a film by a sputtering method or the like, it can be used for transistors constituting a large display device. Also, since a transistor using an oxide semiconductor has a high field-effect mobility, a high-performance display device in which a driving circuit and a pixel portion are integrally formed can be realized. Also, since it is possible to improve and use a part of the production equipment of a transistor using amorphous silicon or a transistor using polycrystalline silicon, there is also an advantage of suppressing capital investment.

[0008] The history of oxide semiconductors is long. In 1985, the synthesis of crystalline In-Ga-Zn oxide was reported (see Non-Patent Document 1). Also, in 1995, it was reported that In-Ga-Zn oxide has a homologous structure and is described by the composition formula InGaO 3 (ZnO) m (where m is a natural number) (see Non-Patent Document 2). Also, in 1995, a transistor using an oxide semiconductor was invented, and its electrical

[0009] characteristics were disclosed (see Patent Document 3). Also, in 2014, a transistor using a crystalline oxide semiconductor was reported

[0010] (see Non-Patent Documents 3 and 4). Here, a transistor using CAAC-OS (C-Axis Aligned C rystalline Oxide Semiconductor), which enables mass production and has excellent electrical characteristics and reliability, was reported. rystalline Oxide Semiconductor) was reported. With the miniaturization of integrated circuits, the resistance of wiring layers has been reduced and multi-layered, and planarization of the wiring layers has become

[0011] indispensable. To solve these problems, the damascene method of embedding wiring layers in interlayer insulating films is widely used (see Non-Patent Document 5).

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Literature

[0013]

Non-Patent Literature 1

Non-Patent Literature 2

Non-Patent Literature 3

Non-Patent Literature 4

Non-Patent Literature 5

Summary of the Invention

Problems to be Solved by the Invention

[0014] One aspect of the present invention aims to provide a fine semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with a small off-current. Or, one aspect of the present invention aims to provide a semiconductor device capable of holding data over a long period. Or, one aspect of the present invention aims to provide a novel semiconductor device. Or, one aspect of the present invention aims to provide an eye-friendly display device. Or, one aspect of the present invention aims to provide a semiconductor device having a transparent semiconductor. It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc. One aspect of the present invention aims to provide a fine semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with a small off-current. Or, one aspect of the present invention aims to provide a semiconductor device capable of holding data over a long period. Or, one aspect of the present invention aims to provide a novel semiconductor device. Or, one aspect of the present invention aims to provide an eye-friendly display device. Or, one aspect of the present invention aims to provide a semiconductor device having a transparent semiconductor. It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc. One aspect of the present invention aims to provide a fine semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with a small off-current. Or, one aspect of the present invention aims to provide a semiconductor device capable of holding data over a long period. Or, one aspect of the present invention aims to provide a novel semiconductor device. Or, one aspect of the present invention aims to provide an eye-friendly display device. Or, one aspect of the present invention aims to provide a semiconductor device having a transparent semiconductor. It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc. One aspect of the present invention aims to provide a fine semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with a small off-current. Or, one aspect of the present invention aims to provide a semiconductor device capable of holding data over a long period. Or, one aspect of the present invention aims to provide a novel semiconductor device. Or, one aspect of the present invention aims to provide an eye-friendly display device. Or, one aspect of the present invention aims to provide a semiconductor device having a transparent semiconductor. It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc.

[0015] It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc. It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc. It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc. It should be noted that the description of these problems does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. It should be noted that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problem

[0016] (1) One aspect of the present invention is to form a second insulator on a first insulator, form a third insulator on the second insulator, form an opening reaching the second insulator in the third insulator, form a first conductor on the third insulator and in the opening, form a second conductor on the first conductor, and then perform a polishing process to remove the second conductor and the first conductor that are at positions higher than the upper surface of the third insulator. The end of the first conductor is at the same height or lower than the end of the opening at the end of the opening, and the height of the upper surface of the second conductor is at the same height or lower than the height of the end of the first conductor. This is a method for manufacturing a wiring layer. (2) Alternatively, one aspect of the present invention is to form a second insulator on a first insulator, form a third insulator on the second insulator, form an opening reaching the second insulator in the third insulator, form a first conductor on the third insulator and in the opening, form a second conductor on the first conductor, and then perform a polishing process to remove the second conductor and the first conductor that are at positions higher than the upper surface of the third insulator. Then, form a third conductor on the second conductor and on the third insulator, perform a polishing process until the third conductor reaches the third insulator, and the end of the first conductor is at the same height or lower than the end of the opening at the end of the opening, the height of the upper surface of the second conductor is at the same height or lower than the height of the end of the first conductor, the third conductor is in contact with the upper surface of the second conductor, and is in contact with the end of the first conductor at the end of the opening. This is a method for manufacturing a wiring layer. (3) Alternatively, one aspect of the present invention has a second insulator on a first insulator, and a third insulator on the second insulator. The third insulator has an opening reaching the second insulator. The opening has a first conductor in contact with the side surface and the bottom surface of the opening, and a second conductor on the first conductor. The end of the first conductor is at the end of the opening and is at the same height as or lower than the height of the end of the opening. The height of the upper surface of the second conductor is at the same height as or lower than the height of the end of the first conductor. It is a wiring layer characterized by this. (4) Alternatively, one aspect of the present invention has a second insulator on a first insulator, and a third insulator on the second insulator. The third insulator has an opening reaching the second insulator. The opening has a first conductor in contact with the side surface and the bottom surface of the opening, a second conductor on the first conductor, and a third conductor on the second conductor. The end of the first conductor is at the end of the opening and is at the same height as or lower than the height of the end of the opening. The height of the upper surface of the second conductor is at the same height as or lower than the height of the end of the first conductor. The third conductor is in contact with the upper surface of the second conductor and is in contact with the end of the first conductor at the end of the opening. It is a wiring layer characterized by this. (5) Alternatively, one aspect of the present invention is that the first conductor is more difficult to permeate oxygen than the second conductor. It is the wiring layer described in (3) characterized by this. (6) Alternatively, one aspect of the present invention is that the first conductor and the third conductor are more difficult to permeate oxygen than the second conductor. It is the wiring layer described in (4) characterized by this.

Effect of the Invention

[0017] It is possible. Or, a highly reliable semiconductor device can be provided. Or, a semiconductor device with a small OFF current can be provided. Or, a semiconductor device that can hold data over a long period can be provided. Or, a novel semiconductor device can be provided. Or, an eye-friendly display device can be provided. Or, a semiconductor device having a transparent semiconductor

[0018] can be provided. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the

[0019]

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Mode for Carrying Out the Invention

[0020] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, those skilled in the art can easily understand that its form and details can be variously changed. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. It will be readily understood by those skilled in the art. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0021] In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and repeated description thereof may be omitted. Also, when referring to similar functions, the hatching patterns are the same, and there are cases where no particular reference numerals are given.

[0022] Note that the functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are employed or when the direction of current changes in a circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0023] It should be noted that ordinal numbers such as "first" and "second" in this specification and the like are added to avoid confusion of components and are not intended to be numerically limiting.

[0024] In each of the figures described in this specification, the size, thickness of layers, or areas of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0025] A transistor is a type of semiconductor device and can realize operations such as amplification of current or voltage and switching operations for controlling conduction or non - conduction. The transistors in this specification ​​​​​​​​​​IGFET (Insulated Gate Field Effect Transi stor) and thin film transistors (TFTs: Thin Film Transistors) are included.

[0026] Note that the terms "film" and "layer" can, in some cases or depending on the situation, be interchangeable with each other. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0027] Also, in this specification, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state is, unless otherwise specified, for an n-channel transistor, the state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth, and for a p-channel transistor, the state where the voltage Vgs between the gate and the source is higher than the threshold voltage Vth. For example, the off-current of an n-channel transistor may refer to the drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth .

[0028] The off-current of a transistor may depend on Vgs. Therefore, when it is said that the off-current of a transistor is I or less, it may mean that there exists a value of Vgs for which the off-current of the transistor becomes I or less . The off-current of a transistor may refer to the off-current in the off state at a given Vgs, the off state at Vgs within a given range, or the off state at a Vgs where a sufficiently reduced off-current is obtained , etc. ​

[0029] As an example, the threshold voltage Vth is 0.5 V, and the drain current when Vgs is 0.5 V is 1×10 -9 A, and the drain current when Vgs is 0.1 V is 1×10 -13 A, and the drain current when Vgs is -0.5 V is 1×10 -19 A, and when Vgs is -0.8 V, the drain current is 1×10 -22 A. Assume an n-channel transistor. The drain current of the transistor is, when Vgs is -0.5 V, or, when Vgs is in the range of -0.5 V to -0.8 V, 1×10 A or less -19 because, in this case, the off-current of the transistor may be 1×10 A or less. Since there exists a Vgs for which the drain current of the transistor becomes 1×10 -19 A or less . In this case, the off-current of the transistor may be 1×10 -22 A or less. In this specification, the off-current of a transistor having a channel width W may be represented by the current value flowing per channel width W. Also, it may be represented by the current value flowing per a predetermined channel width (for example, 1 μm). In the latter case, the unit of the off-current may be represented by a unit having the dimension of current / length -22 (for example, A / μm).

[0030] The off-current of a transistor may depend on temperature. In this specification, the off-current represents, unless otherwise specified, the off-current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Or, the reliability of a semiconductor device or the like including the transistor is guaranteed when the off-current is represented as such. The off-current of a transistor may depend on temperature. In this specification, the off-current represents, unless otherwise specified, the off-current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Or, the reliability of a semiconductor device or the like including the transistor is guaranteed (for example, A / μm).

[0031] The off-current of a transistor may depend on temperature. In this specification, the off-current represents, unless otherwise specified, the off-current at room temperature, 60 °C, 85 °C, 95 °C, or 125 °C. Or, the reliability of a semiconductor device or the like including the transistor is guaranteed when the off-current is represented as such. when the off-current is represented as such. Or, the reliability of a semiconductor device or the like including the transistor is guaranteed The temperature at which it is used, or the temperature at which a semiconductor device including the transistor is used (for example, either one of the temperatures from 5°C to 35°C), may represent the off-current. When it is said that the off-current of the transistor is I or less, it means that at room temperature, 60°C, 85°C, 95°C, 125°C, the temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the temperature at which the semiconductor device including the transistor is used (for example, either one of the temperatures from 5°C to 35°C), there exists a value of Vgs such that the off-current of the transistor is I or less. The off-current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-current may represent the off-current at Vds of 0.1V, 0.8V, 1 V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Or, it may represent the off-current at Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or the off-current at Vds used in the semiconductor device including the transistor. When it is said that the off-current of the transistor is I or less, it means that at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2

[0032]

[0033] .5V, 3V, 3.3V, 10V, 12V, 16V, 20V, Vds at which the reliability of the semiconductor device including the transistor is guaranteed, or Vds used in the semiconductor device including the transistor, there exists a value of Vgs such that the off-current of the transistor is I or less. In this specification, in the same meaning as the off-current, it may be described as the leakage current.

[0033] ​​​

[0034] In this specification, the off-current may refer to, for example, the current flowing between the source and the drain when the transistor is in the off state. and the drain.

[0035] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Furthermore, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Furthermore, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Furthermore, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. Furthermore, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0036] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is expressed as a hexagonal system. .

[0037] (Embodiment 1) In this embodiment, a method for manufacturing a wiring layer will be described with reference to FIGS. 2(A), (B), and (C). .

[0038] First, an insulator 302 is formed on an insulator 301, and an insulator 303 is formed on the insulator 302 (see FIG. 2(A)). Next, a groove reaching the insulator 302 is formed in the insulator 303. (See FIG. 2(B)). The groove includes, for example, holes and openings. The groove may be formed using wet etching, but dry etching is more preferable for microfabrication. The groove includes, for example, holes and openings. The groove may be formed using wet etching, but dry etching is more preferable for microfabrication. Also, it is preferable to select the insulator 302 as an insulating layer that functions as an etching stopper when etching the insulator 303 to form the groove. For example, the insulator 3 that forms the groove is selected as the insulating layer that functions as an etching stopper when etching the insulator 303 to form the groove. For example, the insulator 3 When a silicon oxide film is used in 03, the insulator 302 may be a silicon nitride film or an aluminum oxide film. It is preferable to use.

[0039] In this embodiment, the insulator 302 is used, but depending on the application, a conductor or a semiconductor may be used instead of the insulator 302. It is also possible.

[0040] After the formation of the groove, the conductor 310 is formed. The conductor 310 desirably has a function of being difficult to permeate oxygen. Or, it is desirable that it has a function of being more difficult to permeate oxygen than the conductor 311. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. The conductor 310 can be formed using a sputtering method, a CVD method, an ALD method, etc. Next, the conductor 311 is formed on the conductor 310 (see Fig. 2(C)). The conductor 311 desirably has a low resistivity. For example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, etc. can be used. The film formation method of the conductor 311 can use the same method as the conductor 310. It is desirable. It is possible. It is possible. Next, the conductor 311 is formed on the conductor 310 (see Fig. 2(C)). 1 desirably has a low resistivity. For example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, etc. can be used. It is possible. The film formation method of the conductor 311 can use the same method as the conductor 310.

[0041] Next, by performing Chemical Mechanical Polishing (CMP), the conductor 311 and the conductor 310 on the insulator 303 are removed. As a result, only in the groove portion, the conductor 311 and the conductor 310 remain, and the wiring layer shown in Fig. 1(A) can be formed. As a result, only in the groove portion, the conductor 311 and the conductor 310 remain, and the wiring layer shown in Fig. 1(A) can be formed. It is possible to form.

[0042] The end portion of the conductor 310 is at the same or lower position as the height of the groove at the end of the groove, but the upper surface of the conductor 311 is at the same or lower position than the height of the end portion of the conductor 310. This is because the conductor The upper surface of 311 is at the same or lower position than the height of the end of conductor 310. This is because the conductor It is formed due to the difference in the polishing rates between the conductor 310 and the conductor 311. That is, in the present embodiment in the example, the conductor 311 has a higher polishing rate than the conductor 310.

[0043] When using the conductor as a wiring layer or an electrode layer, attention must be paid to the oxidation of the conductor caused by oxygen contained in the surrounding oxide film, for example, a silicon oxide film. If the conductor is oxidized there is a possibility that the function as a wiring layer or an electrode layer may deteriorate due to an increase in resistivity. Or, it may cause film peeling or cracking of the conductor itself due to volume increase, or film peeling or cracking around the conductor, and it is important to prevent this.

[0044] According to the present invention, as shown in FIG. 1(A), the conductor 310 has a structure that covers the bottom surface and the side surface of the conductor 311 and does not directly contact the oxide film. As a result, the intrusion of oxygen into the conductor 311 can be suppressed, so that serious problems such as film peeling due to volume increase associated with the oxidation of the conductor 311 can be prevented.

[0045] In the present embodiment, although the substrate is not shown, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be used. Or, an insulator substrate such as quartz or glass can also be used, and the wiring layer fabricated in the present embodiment can be used above it. Or, the above-described substrate having elements such as transistors and capacitors can be used.

[0046] This embodiment can be appropriately combined with at least a part of other embodiments described in this specification ​​​​​​​​​​They can be implemented together.

[0047] (Embodiment 2) In this embodiment, a method for manufacturing a wiring layer as shown in FIG. 1(B) will be described.

[0048] In Embodiment 1, CMP was performed to form a structure in which the bottom surface and the side surface of the conductor 311 were covered with a conductor. However, in this embodiment, a conductor 312 is further formed on the conductor 311. The conductor 312 desirably has a function of being difficult to permeate oxygen, similar to the conductor 310. Also, it desirably has a function of being more difficult to permeate oxygen than the conductor 311. The conductor 312 can be, for example, tantalum nitride, tungsten nitride, titanium nitride, etc. Or, the same conductor as the conductor 310 may be used.

[0049] Next, CMP is performed until the conductor 312 reaches the insulator 303, and a wiring layer having a structure in which the conductor 310, the conductor 311, and the conductor 312 are embedded in the groove, as shown in FIG. 1(B), can be formed.

[0050] The wiring layer shown in FIG. 1(B) has a structure in which the conductor 310 and the conductor 312 surround and cover the bottom surface, the side surface, and the top surface of the conductor 311, and can prevent the oxidation of the conductor 311. Furthermore, in this embodiment, compared with Embodiment 1, one more CMP is performed. Therefore, the upper surface of the wiring layer is further planarized, and the coverage of the film on the upper layer of the wiring layer is more favorable, which is preferable.

[0051] In this embodiment, as in Embodiment 1, the substrate is not shown, but for example, a single semiconductor substrate such as silicon, germanium, or silicon carbide, silicon germanium, or Compound semiconductors made of materials such as gallium arsenide, indium phosphide, zinc oxide, and gallium oxide Substrates and the like can be used. Alternatively, insulator substrates such as quartz and glass can also be used and the wiring layer fabricated in this embodiment can be used thereon. Alternatively, the above-described substrate having elements such as transistors, capacitors, etc. can be used

[0052] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification

[0053] (Embodiment 3) In this embodiment, an example of using the wiring layer described in Embodiment 1 for a transistor is shown FIG. 3(A) is a top view of the transistor according to the present invention. The cross-section along the dashed line X1-X2 shown in FIG. 3(A) is shown in FIG. 3(B) and is a cross-sectional view of the transistor in the channel length direction, and the cross-sectional view along the dashed line Y1-Y2 is shown in FIG. 3(C) and corresponds to the cross-sectional view of the transistor in the channel width direction

[0054] The substrate 300 can be, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of materials such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Alternatively, insulator substrates such as quartz and glass can also be used

[0055] An insulator 301 is formed on the substrate 300. As the insulator 301, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, a hafnium oxide film, etc. can be used. The film formation method is a thermal oxidation method, a CVD method, etc ​​​​​​​Methods such as the CVD method, sputtering method, ALD method, plasma oxidation method, and plasma nitridation method can be used. It is possible.

[0056] Next, an insulator 302 is formed on the insulator 301. Next, in the same manner as in Embodiment 1, a wiring layer that covers the bottom surface and the side surface of the conductor 3 10 is formed. In this transistor, a wiring layer composed of the conductor 310 and the conductor 311 is used as a gate electrode.

[0057] An insulator 304 is formed on the conductor 311 and on the insulator 303. The insulator 304 can use a film similar to the above-described insulator 301, and the same film formation method can be used. Preferably, an insulator having a function of being difficult to permeate oxygen may be used. For example, an aluminum oxide film or an aluminum nitride film can be used. As a result, the bottom surface and the side surface of the conductor 3 11 are wrapped by the conductor 310, and the upper surface is covered by the insulator 304. This prevents oxidation of the conductor 311 and can prevent the occurrence of serious problems such as film lifting or film peeling of the surrounding films due to the volume increase accompanying oxidation.

[0058] An insulator 305 is formed on the insulator 304. Note that the insulator 305 is preferably an insulator containing excess oxygen.

[0059] For example, an insulator containing excess oxygen is an insulator having a function of releasing oxygen by heat treatment. For example, a silicon oxide film containing excess oxygen is a silicon oxide film that can release oxygen by heat treatment or the like. Therefore, the insulator 305 is an insulator in which oxygen can move through the film. That is, the insulator 305 may be an insulator having oxygen permeability. For example, In that case, the insulator 305 may be an insulator having a higher oxygen permeability than the semiconductor 320.

[0060] An insulator containing excess oxygen may have a function of reducing oxygen vacancies in the semiconductor 320. In the semiconductor 320, oxygen vacancies become hole traps and the like. Also, hydrogen may enter the oxygen vacancy sites to generate electrons as carriers. Therefore, by reducing the oxygen vacancies in the semiconductor 320, stable electrical characteristics can be imparted to the transistor.

[0061] Here, an insulator that releases oxygen by heat treatment releases 1 × 10 or more, 1 × 10 18 atoms / cm 3 or more, or 1 × 10 19 atoms / cm 3 or more of oxygen (in terms of the number of oxygen atoms) in the range of the surface temperature of 100°C or higher and 700°C or lower or 100°C or higher and 500°C or lower in TDS analysis. 20 atoms / cm 3

[0062] Here, the method for measuring the amount of oxygen released using TDS analysis will be described below.

[0063] When the measurement sample is subjected to TDS analysis, the total amount of gas released is proportional to the integral value of the ionic strength of the released gas. And by comparison with a standard sample, the total amount of gas released can be calculated.

[0064] For example, from the TDS analysis results of a silicon substrate containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the measurement sample, the amount of oxygen molecules released from the measurement sample (N ) can be obtained by the following formula. Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis O2 ​​​​​​​Assume that all of them are derived from oxygen molecules. CH 3 The mass-to-charge ratio of CH OH is 32, but it is not considered here as the probability of its existence is low. Also, for oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18, which are isotopes of oxygen atoms, they are not considered because their abundance ratios in nature are extremely low.

[0065] N O2 =N H2 / S H2 ×S O2 ×α, it becomes.

[0066] N H2 is the value obtained by converting the hydrogen molecules desorbed from the standard sample into density. S H2 is the integrated value of the ionic strength when the standard sample is analyzed by TDS. Here, let the reference value of the standard sample be N H2 / S H2 . S O2 is the integrated value of the ionic strength when the measurement sample is analyzed by TDS is. α is a coefficient that affects the ionic strength in TDS analysis. For the details of the formula shown above, refer to Japanese Patent Laid-Open No. 6-275697. The amount of oxygen released above was measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electron Science Co., Ltd., and using, as a standard sample, for example, a silicon substrate containing 1×10 atoms / cm 16 of hydrogen atoms 2 . .

[0067] Also, in TDS analysis, a part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the amount of oxygen molecules released, the amount of oxygen atoms released can also be estimated. .

[0068] Note that N O2 is the amount of oxygen molecules released. The amount released in terms of oxygen atoms is twice the amount of oxygen molecules released.

[0069] Alternatively, an insulator that releases oxygen by heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 or more. Note that an insulator containing peroxide radicals may have an asymmetric signal with a g-value in the vicinity of 2. 01.

[0070] Alternatively, an insulator containing excess oxygen may be oxygen-rich silicon oxide (SiO X (X>2)) or the like. Oxygen-rich silicon oxide (SiO X (X>2)) contains more oxygen atoms per unit volume than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering spectrometry (RBS). per unit volume. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering spectrometry (RBS: Rutherford Backscattering Spectrometry).

[0071] Insulator 305 functions as a gate insulator of a transistor. Insulator 305 can use the same film and the same film formation method as the above-described insulator 301. In FIGS. 3(B) , (C), insulator 305 is a single layer, but a multilayer film may also be used. For example, a three-layer structure in which a hafnium oxide film is formed on a silicon oxide film and a silicon oxide film is further formed on the hafnium oxide film can also be used. Using the hafnium oxide film as an electron capture layer, a hafnium oxide film is formed on a silicon oxide film, and then a silicon oxide film is formed on the hafnium oxide film to form a three-layer structure. a hafnium oxide film is formed on a silicon oxide film, and then a silicon oxide film is formed on the hafnium oxide film to form a three-layer structure. The threshold voltage of the transistor may be controlled. Or, it may be further made into multiple layers. The combinations of the films can be arbitrarily combined from the same ones as the above-described insulator 301.

[0072] After forming the semiconductor 320 on the insulator 305 and forming a conductor on the semiconductor 320, the conductor in the channel formation region portion is etched to form the channel formation region. Next, the conductor and the semiconductor 320 are etched to form a stacked island-shaped region composed of a pair of source electrodes or drain electrodes 312a, 312b, and the semiconductor 320.

[0073] Or, before forming the channel formation region, the conductor and the semiconductor 320 are etched to form a stacked island-shaped region composed of the conductor and the semiconductor 320, and then the conductor in the channel formation region portion is etched to form the channel formation region, a pair of source electrodes or drain electrodes 312a, 312b.

[0074] The source electrode or drain electrode 312a and the source electrode or drain electrode 312b can be made of tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, tungsten nitride, titanium nitride, tantalum nitride, etc. Or, it can also be made into a multilayer structure. As the film formation method, a sputtering method, a CVD method, an ALD method, etc. can be used.

[0075] Next, an insulator 306 is formed so as to cover the source electrode or drain electrode 312a, the source electrode or drain electrode 312b, and the channel formation region. The insulator 306 is a transistor ​​​​​​​​​​functions as the second gate insulator of the transistor. Insulator 306 refers to the description of insulator 305 for reference. For reference.

[0076] By arranging semiconductors above and below semiconductor 320, the electrical characteristics of the transistor may be improved. In the following, semiconductor 320 and the semiconductors arranged above and below it will be described in detail with reference to FIGS. 4(A) and 4(B). For reference. For reference.

[0077] FIG. 4(A) is an enlarged cross-sectional view of the vicinity of semiconductor 320 in the channel length direction of the transistor shown in FIG. 3(B). FIG. 4(B) is an enlarged cross-sectional view of the vicinity of semiconductor 320 in the channel width direction of the transistor shown in FIG. 3(C). For reference. For reference.

[0078] In the transistor structure shown in FIGS. 4(A) and 4(B), semiconductor 320a is disposed between insulator 305 and semiconductor 320. Further, semiconductor 320c is disposed between insulator 306 and 312a and 312b, which are the drain electrode or the source electrode. For reference. For reference.

[0079] Semiconductor 320 is, for example, an oxide semiconductor containing indium. When semiconductor 320 contains indium, for example, the carrier mobility (electron mobility) becomes high. Further, semiconductor 320 preferably contains element M. Element M is preferably aluminum, gallium, yttrium or tin, etc. Applicable elements for other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, etc. However, element M may be a combination of a plurality of the aforementioned elements in some cases. Element M is, for example, an acid For reference. For reference. For reference. For reference. For reference. For reference. It is an element with a high binding energy with other elements. For example, it is an element with a higher binding energy with oxygen than indium is. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of an oxide semiconductor. Further, the semiconductor 320 preferably contains zinc. The oxide semiconductor may be more likely to crystallize when it contains zinc.

[0080] However, the semiconductor 320 is not limited to an indium-containing oxide semiconductor. The semiconductor 320 may be, for example, an oxide semiconductor that does not contain indium and contains zinc, such as zinc tin oxide or gallium tin oxide, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, etc. is also acceptable.

[0081] For the semiconductor 320, for example, an oxide having a large energy gap is used. The energy gap of the semiconductor 320 is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less.

[0082] For example, the semiconductor 320a and the semiconductor 320c are oxide semiconductors composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 320. Since the semiconductor 320a and the semiconductor 320c are composed of one or more, or two or more, elements other than oxygen that constitute the semiconductor 320, defect levels are less likely to be formed at the interface between the semiconductor 320a and the semiconductor 320, and at the interface between the semiconductor 320 and the semiconductor 320c.

[0083] It is preferable that the semiconductor 320a, the semiconductor 320, and the semiconductor 320c contain at least indium. When the semiconductor 320a is an In-M-Zn oxide, the sum of In and M is 1 is. When it is 00atomic%, preferably In is less than 50atomic%, M is higher than 50a tomic%, more preferably In is less than 25atomic%, and M is higher than 75at omic%. Further, when the semiconductor 320 is an In-M-Zn oxide, when the sum of In and M is 100atomic%, preferably In is higher than 25atomic%, M is less than 75atomic%, more preferably In is higher than 34atomic%, and M is less than 66atomic%. Further, when the semiconductor 320c is an In-M-Zn oxide, when the sum of In and M is 100atomic%, preferably In is less than 50 atomic%, M is higher than 50atomic%, more preferably In is less than 25a tomic%, and M is higher than 75atomic%. Note that the semiconductor 320c may use the same type of oxide as the semiconductor 320a. However, there may be cases where the semiconductor 320a or / and the semiconductor 320c do not contain indium. For example, the semiconductor 32 0a or / and the semiconductor 320c may be gallium oxide. Note that the atomic numbers of the respective elements contained in the semiconductor 320a, the semiconductor 320, and the semiconductor 320c do not have to be in a simple integer ratio.

[0084] The semiconductor 320 uses an oxide with a higher electron affinity than the semiconductor 320a and the semiconductor 320c. For example, as the semiconductor 320, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less higher, more preferably 0.15 eV or more and 0.4 eV or less than that of the semiconductor 320a and the semiconductor 320c is used. Note that the electron affinity is the difference between the vacuum level

[0085] Indium gallium oxide has a small electron affinity and high oxygen-blocking properties. . Therefore, it is preferable that the semiconductor 320c contains indium gallium oxide. The gallium atom ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

[0086] At this time, when a gate voltage is applied, a channel is formed in the semiconductor 320 having a large electron affinity among the semiconductors 320a, 320, and 320c. Among the semiconductors 320a, 320, and 320c, a channel is formed in the semiconductor 320 having a large electron affinity.

[0087] Here, there may be a mixed region between the semiconductor 320a and the semiconductor 320. Also, there may be a mixed region between the semiconductor 320 and the semiconductor 320c. The mixed region has a low defect level density. Therefore, the laminate of the semiconductors 320a, 320, and 320c becomes a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface (see Fig. 4(C)). Note that the interfaces of the semiconductors 320a, 320, and 320c may not be clearly distinguishable from each other. There may be a mixed region between the semiconductor 320a and the semiconductor 320. Also, there may be a mixed region between the semiconductor 320 and the semiconductor 320c. The mixed region has a low defect level density. Therefore, the laminate of the semiconductors 320a, 320, and 320c becomes a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface (see Fig. 4(C)). Note that the interfaces of the semiconductors 320a, 320, and 320c may not be clearly distinguishable from each other. 320 and the semiconductor 320c. The mixed region has a low defect level density. Therefore, the laminate of the semiconductors 320a, 320, and 320c becomes a band diagram in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface (see Fig. 4(C)). Note that the interfaces of the semiconductors 320a, 320, and 320c may not be clearly distinguishable from each other. becomes lower. Therefore, the laminate of the semiconductors 320a, 320, and 320c has energy that changes continuously (also referred to as a continuous junction) in the vicinity of each interface. (See Fig. 4(C)). Note that the interfaces of the semiconductors 320a, 320, and 320c may not be clearly distinguishable from each other.

[0088] At this time, electrons mainly move not in the semiconductor 320a and the semiconductor 320c but in the semiconductor 320. As described above, by reducing the defect level density at the interface between the semiconductor 320a and the semiconductor 320 and the defect level density at the interface between the semiconductor 320 and the semiconductor 320c, the movement of electrons in the semiconductor 320 is less inhibited, and the on-current of the transistor can be increased.

[0089] ​​​​​ The on-current of the transistor can be increased as the factors that inhibit the movement of electrons are reduced. For example, when there are no factors that inhibit the movement of electrons, it is presumed that electrons move efficiently. The movement of electrons is inhibited, for example, even when the physical unevenness of the channel formation region is large.

[0090] To increase the on-current of the transistor, for example, the root mean square (RMS) roughness in the range of 1 μm × 1 μm on the upper surface or the lower surface (the surface to be formed, here semiconductor 320a) of the semiconductor 320 is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. (RMS:Root Mean Square) Also, the average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Further, the maximum height difference (also referred to as P-V) in the range of 1 μm × 1 μm may be less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and P-V can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nanotechnology Inc. or the like.

[0091] Alternatively, for example, even when the density of defect levels in the region where the channel is formed is high, the movement of electrons is inhibited.

[0092] For example, when the semiconductor 320 has oxygen vacancies (also denoted as V O ), hydrogen may enter the sites of the oxygen vacancies to form donor levels. Hereinafter, water at the sites of the oxygen vacancies ​ The state in which the element has entered is denoted as V O and H in some cases. V O and H scatter electrons, which becomes a factor reducing the on-current of the transistor. Note that at the oxygen-deficient sites, oxygen enters more stably than hydrogen. Therefore, by reducing the oxygen deficiency in the semiconductor 320, the on-current of the transistor may be increased in some cases. In addition, if the density of defect levels in the region where the channel is formed is high, the electrical characteristics of the transistor may fluctuate. For example, when the defect levels serve as carrier generation sources, the threshold voltage of the transistor may

[0093] fluctuate. To reduce the oxygen deficiency in the semiconductor 320, for example, there is a method of moving the excess oxygen contained in the insulator 305 to the semiconductor 320 through the semiconductor 320a. In this case, the semiconductor 320a is preferably a layer having oxygen permeability (a layer that allows oxygen to pass through or permeate).

[0094]

[0095] Preferably. In addition, to increase the on-current of the transistor, the smaller the thickness of the semiconductor 320c, the more preferable. For example, a semiconductor 320c having a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less may be used. On the other hand, the semiconductor 320c has a function of blocking elements other than oxygen (such as hydrogen and silicon) that constitute the adjacent insulator from entering the semiconductor 320 where the channel is formed. Therefore, the semiconductor 320c preferably has a certain thickness. For example, a semiconductor 320c having a region with a thickness of 0.3 nm or more, preferably 1 nm or more, and even more preferably 2 nm or more may be used. Also, the half The conductor 320c preferably has the property of blocking oxygen in order to suppress the outward diffusion of oxygen released from the insulator 305 or the like. It is preferable that it has the property of blocking oxygen.

[0096] Also, in order to improve reliability, it is preferable that the semiconductor 320a is thick and the semiconductor 320c is thin. For example, the semiconductor 320a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and even more preferably 60 nm or more. By increasing the thickness of the semiconductor 320a, the distance from the interface between the adjacent insulator and the semiconductor 320a to the semiconductor 320 where the channel is formed can be increased. However, since the productivity of the semiconductor device may decrease, for example, the semiconductor 320a may have a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. For example, the semiconductor 320a may have a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less.

[0097] For example, between the semiconductor 320 and the semiconductor 320a, in, for example, secondary ion mass spectrometry (SI MS: Secondary Ion Mass Spectrometry), 1×10 16 atoms / cm 3 or more and 1×10 19 atoms / cm 3 or less, preferably 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, and more preferably 1×10 16 atoms / cm 3 or more and 2×10 18 atoms / cm 3 or less, and has a region with a silicon concentration. Also, between the semiconductor 320 and the semiconductor 320c, in SIMS it has a region with a silicon concentration of 1×10 16atoms / cm 3 1×10 or more 19 atoms / cm 3 and below, preferably 1×10 16 atoms / cm 3 1×10 or more and 5×10 18 atoms / cm 3 and below, more preferably 1×10 16 atoms / cm 3 1×10 or more and 2×10 18 atoms / cm 3 and have a region with a silicon concentration below this.

[0098] Also, in order to reduce the hydrogen concentration of semiconductor 320, it is preferable to reduce the hydrogen concentration of semiconductor 320a and semiconductor 320c. Semiconductor 320a and semiconductor 320c have, in SIMS, 1×10 16 atoms / cm 3 or more and 2×10 20 atoms / cm 3 and below, preferably 1×10 16 atoms / cm 3 or more and 5×10 19 atoms / cm 3 and below, more preferably 1×10 16 atoms / cm 3 or more and 1×10 19 atoms / cm 3 and below and even more preferably 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 and have a region with a hydrogen concentration below this. Also, in order to reduce the nitrogen concentration of semiconductor 320 it is preferable to reduce the nitrogen concentration of semiconductor 320a and semiconductor 320c. Semiconductor 320a and semiconductor 320c have, in SIMS, 1×10 15 atoms / cm 3Over 5 ×10 19 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 Over 5 ×10 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 Below Top 1×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / c m 3 5×10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0099] The three-layer structure described above is an example. For example, a two-layer structure without semiconductor 320a or semiconductor 320c Alternatively, the semiconductor 320a may be disposed above or below the semiconductor 320c. Above and below, the semiconductors exemplified as semiconductor 320a, semiconductor 320, and semiconductor 320c are Alternatively, a four-layer structure may be used in which the semiconductor 320a is on the upper side of the semiconductor 320b and the semiconductor 320c is on the lower side of the semiconductor 320a. At least two of the following locations are located below the conductor 320a, above the semiconductor 320c, and below the semiconductor 320c: Any one of the semiconductors exemplified as the semiconductor 320a, the semiconductor 320, and the semiconductor 320c. Alternatively, the layer may have an n-layer structure (n is an integer of 5 or more).

[0100] The structure of an oxide semiconductor will be described below.

[0101] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, amorphous oxide semiconductor, and the like. There are polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, and the like.

[0102] From another perspective, oxide semiconductors can be divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystalline oxide semiconductors, CAAC-OS CAAC-O S, polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and the like.

[0103] First, CAAC-OS will be described. Note that CAAC-OS can also be called an oxide semiconductor having CANC (C-A xis Aligned nanocrystals). It can also be called an oxide semiconductor having CANC (C-Axis Aligned nanocrystals).

[0104] CAAC-OS is one type of oxide semiconductor having a plurality of c-axis oriented crystal parts (also referred to as pellets). It is one type of oxide semiconductor having a plurality of c-axis oriented crystal parts (also referred to as pellets).

[0105] When a composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and diffraction pattern of CAAC-OS is observed by a transmission electron microscope (TEM: Transmission Electron Micro scope), a plurality of pellets can be confirmed. On the other hand In a high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries. In a high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries. In a high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries), cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries. Therefore, it can be said that CAAC-OS is less likely to cause a decrease in electron mobility due to grain boundaries.

[0106] Hereinafter, CAAC-OS observed by TEM will be described. FIG. 5(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. High resolution Hereinafter, CAAC-OS observed by TEM will be described. FIG. 5(A) shows a high-resolution TEM image of a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface. High resolution For the observation of the TEM image of the solution energy, a spherical aberration corrector function was used. The high-resolution TEM image obtained using the spherical aberration corrector function is specifically referred to as the Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed, for example, using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. in Japan and the like .

[0107] The Cs-corrected high-resolution TEM image obtained by magnifying the region (1) in Fig. 5(A) is shown in Fig. 5(B). From Fig. 5 (B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film and is parallel to the surface to be formed or the upper surface of the CAAC-OS .

[0108] As shown in Fig. 5(B), CAAC-OS has a characteristic atomic arrangement. Fig. 5(C) shows the characteristic atomic arrangement indicated by auxiliary lines. From Fig. 5(B) and Fig. 5(C), the size of one pellet is about 1 nm or more and 3 nm or less, and the size of the gap generated due to the inclination between pellets is about 0.8 nm. Therefore, the pellet can also be called a nanocrystal (nc: nanocrystal).

[0109] Here, when the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown based on the Cs-corrected high-resolution TEM image, it has a structure like bricks or blocks stacked (see Fig. 5(D)). The location where the inclination occurs between the pellets observed in Fig. 5(C) corresponds to the region 5161 shown in Fig. 5(D).

[0110] ​​​​​​Further, FIG. 6(A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in FIG. 6(A) are shown in FIGS. 6(B), 6(C), and 6(D), respectively. From FIGS. 6(B), 6(C), and 6(D), it can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of the metal atoms between different pellets. Next, CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, when performing a structural analysis of CAAC-OS having a crystal of InGaZnO by the out-of-plane method, as shown in FIG. 7(A), a peak may appear in the vicinity of a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO crystal, it can be confirmed that the crystal of CAAC-OS has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak in the vicinity of 2θ of 31°, a peak may also appear in the vicinity of 2θ of 36°. The peak in the vicinity of 2θ of 36° indicates that a part of CAAC-OS contains crystals having no c-axis orientation. A more preferable CAAC-OS shows a peak at around 2θ of 31° and does not show a peak at around 2θ of 36° in the structural analysis by the out-of-plane method.

[0111] 4 4

[0112]

[0113] ​​​​​​​​​​​​​​​​On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In GaZnO 4 In the case of CAAC-OS, the 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. , InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed at around 56° and φ is When the ion beam was scanned, a peak was observed that was assigned to a crystal plane equivalent to the (110) plane, as shown in FIG. Therefore, the structure analysis using XRD shows that CAAC-OS has a-axis It can be seen that the orientation of the b axis is irregular.

[0114] Next, we will explain the CAAC-OS analyzed by electron diffraction. nO 4 For CAAC-OS with a crystal of 100 nm, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction pattern) like that shown in Figure 8(A) is generated. This diffraction pattern may show a pattern of InGaZnO 4 The result The spots due to the (009) plane of the crystal are included. Therefore, the electron diffraction also shows that The pellets contained in the AAC-OS have a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the film is formed or the upper surface. On the other hand, for the same sample, the probe diameter is perpendicular to the sample surface. The diffraction pattern when an electron beam of 300 nm is incident is shown in FIG. 8(B). A ring-shaped diffraction pattern is observed. Therefore, CAA is also confirmed by electron diffraction. It can be seen that the a-axis and b-axis of the pellets contained in C-OS have no orientation. Note that the first ring in Fig. 8(B) is considered to be due to the (010) plane and (10 4 0) plane, etc. of the crystal of InGaZnO. Also, the second ring in Fig. 8(B) is considered to be due to the (110) plane, etc.

[0115] In addition, CAAC-OS is an oxide semiconductor with a low density of defect levels. Defects in the oxide semiconductor include, for example, defects caused by impurities and oxygen deficiencies. Therefore, CAAC -OS can also be said to be an oxide semiconductor with a low impurity concentration. Also, CAAC-OS can also be said to be an oxide semiconductor with few oxygen deficiencies.

[0116] Impurities contained in the oxide semiconductor may act as carrier traps or carrier generation sources. Also, oxygen deficiencies in the oxide semiconductor may act as carrier traps or may become carrier generation sources by capturing hydrogen.

[0117] Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, elements with a stronger binding force to oxygen than the metal elements constituting the oxide semiconductor, such as silicon, take oxygen from the oxide semiconductor and disrupt the atomic arrangement of the oxide semiconductor, becoming a factor in reducing the crystallinity. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), so they disrupt the atomic arrangement of the oxide semiconductor and become a factor in reducing the crystallinity.

[0118] In addition, an oxide semiconductor with a low density of defect levels (few oxygen deficiencies) has a low carrier density​​​​​ It is possible. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect levels. That is, it is likely to become a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Therefore, a transistor using CAAC -OS has electrical characteristics (also called normally-on) in which the threshold voltage is rarely negative. In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few carrier traps. Charges trapped in the carrier traps of the oxide semiconductor take a long time to be released and behave like fixed charges. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics. On the other hand, a transistor using CAAC-OS has small fluctuations in electrical characteristics and is a highly reliable transistor.

[0119] Also, since CAAC-OS has a low density of defect levels, carriers generated by light irradiation or the like are rarely trapped in defect levels. Therefore, a transistor using CAAC -OS has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0120] Next, the microcrystalline oxide semiconductor will be described.

[0121] The microcrystalline oxide semiconductor has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. The crystal parts contained in the microcrystalline oxide semiconductor are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less ​ An oxide semiconductor having nanocrystals, which is called nc-OS (nanocrystalline Oxide Semiconductor). In an nc-OS, for example, in a high-resolution TEM image, grain boundaries may not be clearly confirmed. Note that the nanocrystals may have the same origin as the pellets in CAAC- OS. Therefore, hereinafter, the crystal part of nc- OS may be referred to as a pellet.

[0122] An nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, in an nc-OS, no regularity is observed in the crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, an nc- OS may not be distinguishable from an amorphous oxide semiconductor. For example, when performing structural analysis on an nc-OS using an XRD apparatus that uses X-rays with a diameter larger than that of a pellet, in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected. Also, when performing electron diffraction (also referred to as limited-field electron diffraction) on an nc-OS using an electron beam with a probe diameter larger than that of a pellet (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on an nc-OS using an electron beam with a probe diameter close to the size of a pellet or smaller than that of a pellet, spots are observed. Also, when performing nano-beam electron diffraction on an nc-OS, a region with high brightness may be observed so as to draw a circle (ring-shaped). Furthermore, a plurality of spots may be observed within the ring-shaped region.

[0123] Thus, since the crystal orientations among the pellets (nanocrystals) have no regularity, nc- OS is also called an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide semiconductor having NANC (Non-Aligned nanocrystals ).

[0124] nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore, nc-OS has a lower density of defect levels than an amorphous oxide semiconductor. However, nc-OS shows no regularity in crystal orientation among different pellets. Therefore, nc-OS has a higher density of defect levels than CAAC-OS.

[0125] Next, the amorphous oxide semiconductor will be described.

[0126] An amorphous oxide semiconductor is an oxide semiconductor in which the atomic arrangement in the film is irregular and has no crystalline part. An example is an oxide semiconductor having an amorphous state like quartz.

[0127] In a high-resolution TEM image, no crystalline part can be confirmed for an amorphous oxide semiconductor.

[0128] When performing structural analysis on an amorphous oxide semiconductor using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of-pl ane method analysis. Also, when performing electron diffraction on an amorphous oxide semiconductor, a halo pattern is observed. Also, when performing nano-beam electron diffraction on an amorphous oxide semiconductor, no spot is observed, and only a halo pattern is observed.

[0129] Regarding the amorphous structure, various views have been presented. For example, the atomic arrangement has no order at all​ A structure that is not crystalline may be referred to as a completely amorphous structure. Also, a structure that has no long-range order but may have order within the range from a certain atom to its nearest neighbor atom or second-nearest neighbor atom may be called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even the slightest order in its atomic arrangement cannot be called an amorphous oxide semiconductor. Also, at least an oxide semiconductor that has long-range order cannot be called an amorphous oxide semiconductor. Thus, since it has a crystalline portion, for example, CAAC-OS and nc-OS cannot be called amorphous oxide semiconductors or completely amorphous oxide semiconductors. Note that an oxide semiconductor may have a structure between nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semiconductor). a-like OS may have voids observed in a high-resolution TEM image. Also, in a high-resolution TEM image, it has regions where a crystalline portion can be clearly confirmed and regions where a crystalline portion cannot be confirmed. Because it has voids, a-like OS has an unstable structure. Hereinafter, to show that a-like OS has a more unstable structure than CAAC-OS and nc-OS, the change in structure due to electron irradiation is shown.

[0130]

[0131]

[0132]

[0133] ​​​​​​​​​​​​​​As samples for electron irradiation, a-like OS (referred to as Sample A), nc-OS ( referred to as Sample B), and CAAC-OS (referred to as Sample C) are prepared. All of these samples are In-Ga-Zn oxides.

[0134] First, high-resolution cross-sectional TEM images of each sample are obtained. From the high-resolution cross-sectional TEM images, it can be seen that all samples have crystal parts.

[0135] Note that the determination of which part is regarded as one crystal part can be carried out as follows. For example, InGaZnO 4 The unit cell of the crystal has three In-O layers and six Ga-Zn-O layers, and it is known to have a structure in which a total of nine layers are stacked in the c-axis direction in a layered manner. The distance between these adjacent layers is about the same as the lattice plane spacing of the (009) plane (also referred to as the d value), and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, the part where the lattice fringe spacing is between 0.28 nm and 0.30 nm can be regarded as the crystal part of InGaZnO 4 . Note that the lattice fringes correspond to the a-b plane of the InGaZnO 4 crystal.

[0136] Fig. 9 is an example of investigating the average size of the crystal parts (from 22 to 45 parts) of each sample. However, the length of the above-mentioned lattice fringes is regarded as the size of the crystal part. From Fig. 9, it can be seen that the crystal part of a-like OS increases with the cumulative electron irradiation dose. Specifically, , as shown by (1) in Fig. 9, the crystal part (also referred to as the initial nucleus) with a size of about 1.2 nm at the initial stage of observation by TEM becomes when the cumulative irradiation dose is 4.2×10 8 e - / nm 2 at It can be seen that it has grown to a size of about 2.6 nm. On the other hand, nc-OS and CAAC-OS show no change in the size of the crystalline part within the range where the cumulative electron irradiation dose is from the start of electron irradiation to 4.2×10 8 e - / nm 2 up to. Specifically, as shown in (2) and (3) in Fig. 9, regardless of the cumulative electron irradiation dose, the sizes of the crystalline parts of nc-OS and CAA C-OS are about 1.4 nm and about 2.1 nm, respectively, as can be seen. It can be seen that.

[0137] Thus, a-like OS may show growth of the crystalline part due to electron irradiation. On the other hand, it can be seen that nc-OS and CAAC-OS hardly show growth of the crystalline part due to electron irradiation. That is, it can be seen that a-like OS has an unstable structure compared to nc-OS and CAAC-O S.

[0138] Also, because it has looseness, a-like OS has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. Also, the density of nc-OS and CAAC -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself. For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO having a rhombohedral crystal structure is 6.357 g / cm

[0139] with. Therefore, 4 3 ​​​​​​​​That is, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio] , the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also , for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0140] Note that there may be no single crystal of the same composition. In that case, by combining single crystals with different compositions in an arbitrary ratio, the density corresponding to the single crystal in the desired composition can be estimated . The density corresponding to the single crystal of the desired composition may be estimated using the weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible .

[0141] As described above, the oxide semiconductor has various structures, each having various characteristics. In addition , the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS

[0142] A conductor is formed on the insulator 306, unnecessary portions of the conductor are etched, and the second gate electrode 331 is formed. The second gate electrode can be made of tantalum, tungsten, titanium, molybdenum dibdenum, aluminum, copper, a molybdenum-tungsten alloy, tungsten nitride, titanium nitride tantalum, etc. Alternatively, a multilayer structure can also be used. The film formation ​As the film formation method, a sputtering method, a CVD method, an ALD method, etc. can be used.

[0143] Next, an insulator 307 is formed so as to cover the insulator 306 and the second gate electrode 331. The insulator 307 can use the same film as the above-described insulator 305, and the same film formation method can be used. Preferably, an insulator having a function of being difficult to permeate oxygen may be used. For example, an aluminum oxide film may be used.

[0144] An insulator 308 is formed on the insulator 307. The insulator 308 can use the same film as the above-described insulator 301, and the same film formation method can be used. After forming the insulator 308, CMP is performed to planarize the insulator 308.

[0145] Next, contact holes reaching the upper surfaces of 312a and 312b, which are the source electrode or the drain electrode and have the insulator 308, the insulator 307, and the insulator 306, are formed.

[0146] Next, a conductor 314 is formed, and a conductor 315 is formed on the conductor 314. The conductor 314 and the conductor 315 can use tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum tungsten alloy, tungsten nitride, titanium nitride, tantalum nitride, etc. As the film formation method, a sputtering method, a CVD method, an ALD method, etc. can be used.

[0147] Next, CMP is performed until reaching the upper surface of the insulator 308 to form a plug formed from the conductor 314 and the conductor 315.

[0148] Next, a conductor 316 is formed on the conductor 315 and on the insulator 308. The conductor 316 include tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloys, tungsten nitride, titanium nitride, tantalum nitride, etc. can be used. Or, it can be made into a multilayer film. As the film formation method, a sputtering method, a CVD method, an AL D method, etc. can be used. Next, the unnecessary part of the conductor 316 is etched to form an electrode made of the conductor 316.

[0149] Through the above steps, a semiconductor device having a transistor according to one aspect of the present invention can be manufactured. can.

[0150] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. combined and implemented.

[0151] (Embodiment 4) In this embodiment, an example of a semiconductor device using a transistor having an oxidation-prevented back gate electrode and wiring layer described in Embodiment 3 will be described.

[0152] FIG. 10(A) shows an example of a circuit of a memory device, and FIG. 10(B) shows a cross-sectional view.

[0153] The substrate 350 can be a single crystal semiconductor substrate made of silicon, silicon carbide, etc., a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, etc., an SOI (Silic on On Insulator) substrate, etc.

[0154] A transistor 100 is formed on the substrate 350. The transistor 100 can be a planar type transistor having a sidewall 355 as shown in FIG. 10. like. The transistor formed element isolation by forming (Shallow Trench Isolation) STI351 Also, the transistor 100 may use a Fin-shaped transistor as shown in FIG. 11 Further, the transistor 100 may use a p-channel transistor or an n-channel transistor. Or both may be used as well

[0155] In this embodiment, the transistor 100 uses a single crystal silicon in the channel formation region However, an oxide semiconductor, for example, may be used in the channel formation region, and it is not limited to a single crystal silicon As the insulator 354 having the function as a gate insulator, for example, silicon oxide obtained by thermally oxidizing single crystal silicon may be used. In addition, silicon oxide film , silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film , aluminum nitride film, hafnium oxide film, etc. can be used. As the film formation method , thermal oxidation method, CVD method, sputtering method, ALD method, plasma oxidation method, plasma nitridation method, etc. can be used Or, appropriately select from the above-mentioned films to form a laminated film is also possible

[0156] An insulator 360 is formed on the transistor 100, on the STI351, and on the diffusion layer 353, and CMP is performed to planarize the surface of the insulator 360. As the insulator 360, a silicon oxide film , silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, aluminum nitride film , hafnium oxide film, etc. can be used. As the film formation method, the thermal oxidation method , CVD method, sputtering method, ALD method, plasma oxidation method, plasma nitridation method, etc. can be used ​can be achieved. Planarization may use other processes. Or, CMP may be combined with etching (dry etching, wet etching) or plasma processing, etc. Etching, wet etching) or plasma processing may be combined.

[0157] A contact hole reaching the upper surface of the gate electrode 330 of the transistor 100 and a contact hole reaching the upper surface of the diffusion layer 353 are formed in the insulator 360, and a conductor is embedded in the contact hole, and CMP is performed until the upper surface of the insulator 360 is exposed to form plugs 370, plugs 371, and plugs 372. The plugs 370, plugs 371, and plugs 372 can be made of, for example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum tungsten alloy, etc. Or, a plurality may be appropriately selected from the above to form a laminated film. The film formation method can use, for example, sputtering, CVD, ALD, plating, etc. The film formation of the laminated film may use a plurality of formation methods from the above. Next, a conductor is formed on the insulator 360 to form wiring layers 373, 374, and 375. The wiring layers 373, 374, and 375 can use the same film and film formation method as the above-described plugs 370, plugs 371, and plugs 372. An insulator 361 is formed on the insulator 360 and on the wiring layers 373, 374, and 375, and CMP is performed to planarize the surface of the insulator 361. The insulator 361 can use the same film and film formation method as the above-described insulator 360. A contact hole reaching the upper surface of each of the wiring layers 373, 374, and 375 is formed in the insulator 361. The film formation method can use, for example, sputtering, CVD, ALD, plating, etc. The film formation of the laminated film may use a plurality of formation methods from the above.

[0158] Next, a conductor is formed on the insulator 360 to form wiring layers 373, 374, and 375. The wiring layers 373, 374, and 375 can use the same film and film formation method as the above-described plugs 370, plugs 371, and plugs 372.

[0159] An insulator 361 is formed on the insulator 360 and on the wiring layers 373, 374, and 375, and CMP is performed to planarize the surface of the insulator 361. The insulator 361 can use the same film and film formation method as the above-described insulator 360. A contact hole reaching the upper surface of each of the wiring layers 373, 374, and 375 is formed in the insulator 361.

[0160] In the insulator 361, contact holes reaching the upper surfaces of the wiring layers 373, 374, and 375 respectively Form a contact hole and a groove, and embed a conductor into the contact hole and the groove. Next Perform CMP until the upper surface of the insulator 361 is exposed, and form a wiring layer 376, a wiring layer 377, and a wiring layer 378 that also serve as a plug. The wiring layer 376, the wiring layer 377, and the wiring layer 378 can be formed of the same film and by the same film formation method as the plugs 370, 371, and 372 described above. The wiring layer 376, the wiring layer 377, and the wiring layer 378 can be formed of the same film and by the same film formation method as the plugs 370, 371, and 372 described above. can be used.

[0161] Next, form an insulator 362 on the insulator 361 and on the wiring layer 376, the wiring layer 377, and the wiring layer 378, and form a wiring layer 379, a wiring layer 380, and a wiring layer 381 that also serve as a plug in the same manner as the insulator 361 described above. The insulator 362 can be formed of the same film and by the same film formation method as the insulator 360 described above. The wiring layer 379, the wiring layer 380, and the wiring layer 38 1 can be formed of the same film and by the same film formation method as the plugs 370, 371, and 372 described above. The formation of this wiring layer that also serves as a plug can be repeatedly formed by the above-described method as necessary, so that a semiconductor device with a high degree of integration can be manufactured. 1 can be formed of the same film and by the same film formation method as the plugs 370, 371, and 372 described above. The formation of this wiring layer that also serves as a plug can be repeatedly formed by the above-described method as necessary, so that a semiconductor device with a high degree of integration can be manufactured. 1 can be formed of the same film and by the same film formation method as the plugs 370, 371, and 372 described above. The formation of this wiring layer that also serves as a plug can be repeatedly formed by the above-described method as necessary, so that a semiconductor device with a high degree of integration can be manufactured. can be used. The formation of this wiring layer that also serves as a plug can be repeatedly formed by the above-described method as necessary, so that a semiconductor device with a high degree of integration can be manufactured. Since the formation of this wiring layer that also serves as a plug can be repeatedly formed by the above-described method as necessary, a semiconductor device with a high degree of integration can be manufactured. .

[0162] Next, form an insulator 363 on the insulator 362 and on the wiring layer 379, the wiring layer 380, and the wiring layer 381. The insulator 363 can be formed of the same film and by the same film formation method as the insulator 360 described above. The insulator 363 preferably has a function of being less permeable to hydrogen. Also The insulator 363 may not be formed. The insulator 363 may not be formed.

[0163] Form an insulator 302 on the insulator 363, and form the transistor 1 10 by the method described in Embodiment 3.

[0164] Next, an insulator 308 is formed, and a plug 382, ​​a plug 383, and a plug 384 are formed. A wiring layer 385 is formed on the plug 382, ​​the plug 383, and the plug 384, respectively. The wiring layer 386 and the wiring layer 387 are formed.

[0165] Next, an insulating layer is formed on the insulator 308, the wiring layer 385, the wiring layer 386, and the wiring layer 387. The insulator 364 is formed, and the surface of the insulator 364 is planarized by CMP. The same film and film formation method as those for the insulator 360 described above can be used.

[0166] Contact holes are formed in the insulator 364, reaching the upper surfaces of the wiring layers 386 and 387. Then, the conductor is embedded in the contact hole, and CMP is performed until the top surface of the insulator 364 is exposed. The plugs 388 and 389 are formed by: The same films and film formation methods as those for the plugs 370, 371, and 372 described above are used. This can be done.

[0167] Next, a conductor is formed on the insulator 364, and one electrode 341 of the capacitor element 130 and a wiring layer The electrode 341 and the wiring layer 390 are connected to the plug 370 and the plug 3 The same film and film formation method as those for the plug 372 can be used. The other electrode 342 is formed so as to overlap the electrode 341 via an insulator. Then, an insulator 365 is formed, and the surface of the insulator 365 is planarized by CMP. For the insulator 5, the same film and film formation method as those for the insulator 360 described above can be used.

[0168] A contact hole is formed in the insulator 365 so as to reach the top surface of the other electrode 342 of the capacitor element 130. Then, on the other hand, contact holes reaching the upper surface of the wiring layer 390 are formed, and conductors are embedded in the contact holes, and CMP is performed until the upper surface of the insulator 365 is exposed, and plugs 391 and plugs 392 are formed. The plugs 391 and 392 can use the same films and film formation methods as those of the above-described plugs 370, 371, and 372. Next, conductors are formed on the insulator 365 to form a wiring layer 393 and a wiring layer 394. The wiring layer 393 and the wiring layer 394 can use the same films and film formation methods as those of the above-described plugs 370, 371, and 372. Also, a planar capacitor element 130 shown in FIG. 10 may be formed like a cylindrical capacitor element 140 shown in FIG. 12. The cylindrical capacitor element 140 is more preferable because a capacitor element can be manufactured with a smaller area than the planar capacitor element 130. Through the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0169] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. (Embodiment 5) <Imaging device>

[0170] Hereinafter, an imaging device according to one aspect of the present invention will be described. FIG. 13(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 includes a pixel portion 210, a peripheral circuit 260 for driving the pixel portion 210, and a peripheral circuit...

[0171]

[0172]

[0173]

[0174] ​​​​​​​​​It has a path 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel section 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (where p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. In this specification and the like, all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as "peripheral circuit" or "driving circuit". For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit.

[0175] Also, the imaging device 200 preferably has a light source 291. The light source 291 can emit detection light P1.

[0176] Also, the peripheral circuit has at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Also, the peripheral circuit may be fabricated on the substrate forming the pixel section 210. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that the peripheral circuit may omit any one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290.

[0177] Also, as shown in FIG. 13(B), in the pixel section 210 of the imaging device 200, the pixels 211 may be arranged obliquely. By arranging the pixels 211 obliquely, the pixel intervals (pitches) in the row direction and the column direction can be shortened. Thereby, the imaging quality of the imaging device 200 can be further improved.

[0178] <Example configuration of pixel 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and a filter (color filter) that transmits light in a specific wavelength band is combined with each sub- pixel 212, so that information for realizing color image display can be obtained.

[0179] FIG. 14(A) is a plan view showing an example of the pixel 211 for obtaining a color image. The pixel 211 shown in FIG. 14(A) is provided with a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength band, and transmits light in the green (G) wavelength band. The provided sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G"), and a sub-pixel 212 (hereinafter also referred to as "sub- pixel 212B") provided with a color filter that transmits light in the blue (B) wavelength band. The sub-pixel 212 can function as a photosensor.

[0180] The sub-pixels 212 (sub-pixel 212R, sub-pixel 212G, and sub-pixel 212B) are electrically connected to wiring 23 1, wiring 247, wiring 248, wiring 249, and wiring 250. Also, the sub- pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected to an independent wiring 25 3. Also, in this specification and the like, for example, the wiring 248 and wiring 249 connected to the pixel 211 in the nth row are respectively denoted as wiring 248[n] and wiring 249[n]. Also, for example, the wiring 253 connected to the pixel 211 in the mth column is denoted as wiring 253[m]. Note that in FIG. 14(A), the wiring 253 connected to the sub-pixel 212R included in the pixel 211 in the mth column is denoted as wiring 253[m]R, and the wiring 253 connected to the sub-pixel 212G is denoted as wiring 253[m]. The wiring 253[m]G and the wiring 253 connected to the sub-pixel 212B are the wiring 253[m]B and is described. The sub-pixel 212 is electrically connected to the peripheral circuit via the above wiring.

[0181] In addition, the imaging device 200 has a configuration in which sub-pixels 212 provided with color filters that transmit the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. FIG. 14(B) shows a connection example of the sub-pixels 212 included in the pixels 211 arranged in n rows (n is an integer of 1 or more and p or less) and m columns (m is an integer of 1 or more and q or less), and the sub-pixels 212 included in the pixels 211 arranged in the (n + 1)th row and m columns adjacent to the pixel 211. In FIG. 14(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column are connected via a switch 14(B) shows a connection example of the sub-pixels 212 included in the pixels 211 arranged in n rows (n is an integer of 1 or more and p or less) and m columns (m is an integer of 1 or more and q or less), and the sub-pixels 212 included in the pixels 211 arranged in the (n + 1)th row and m columns adjacent to the pixel 211. In FIG. 14(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column are connected via a switch 14(B) shows a connection example of the sub-pixels 212 included in the pixels 211 arranged in n rows (n is an integer of 1 or more and p or less) and m columns (m is an integer of 1 or more and q or less), and the sub-pixels 212 included in the pixels 211 arranged in the (n + 1)th row and m columns adjacent to the pixel 211. In FIG. 14(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column are connected via a switch 14(B) shows a connection example of the sub-pixels 212 included in the pixels 211 arranged in n rows (n is an integer of 1 or more and p or less) and m columns (m is an integer of 1 or more and q or less), and the sub-pixels 212 included in the pixels 211 arranged in the (n + 1)th row and m columns adjacent to the pixel 211. In FIG. 14(B), the sub-pixel 212R arranged in the nth row and mth column and the sub-pixel 212R arranged in the (n + 1)th row and mth column are connected via a switch 201. Also, the sub-pixel 212G arranged in the nth row and mth column and the sub-pixel 212G arranged in the (n + 1)th row and mth column are connected via a switch 202. Further, the sub-pixel 212B arranged in the nth row and mth column and the sub-pixel 212B arranged in the (n + 1)th row and mth column are connected via a switch 201. Also, the sub-pixel 212G arranged in the nth row and mth column and the sub-pixel 212G arranged in the (n + 1)th row and mth column are connected via a switch 202. Further, the sub-pixel 212B arranged in the nth row and mth column and the sub-pixel 212B arranged in the (n + 1)th row and mth column are connected via a switch 202. Also, the sub-pixel 212B arranged in the nth row and mth column and the sub-pixel 212B arranged in the (n + 1)th row and mth column are connected via a switch 203.

[0182] Note that the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and color filters that transmit cyan (C), yellow (Y), and magenta (M) light, respectively, may be used. By providing the sub-pixel 212 that detects light of three different wavelength bands in one pixel 211, a full-color image can be obtained.

[0183] Alternatively, in addition to the sub-pixels 212 provided with color filters that transmit red (R), green (G), and blue (B) light, respectively, sub-pixels provided with a color filter that transmits yellow (Y) light are provided ​​​​​The pixel 211 having the pixel 212 may be used. Alternatively, in addition to the sub-pixel 212 provided with color filters that transmit light of cyan (C), yellow (Y ), and magenta (M), a pixel 21 1 having a sub-pixel 212 provided with a color filter that transmits blue (B) light may be used. By providing four sub-pixels 2 12 for detecting light in four different wavelength bands in one pixel 211, the color reproducibility of the acquired image can be further enhanced.

[0184] Also, for example, in FIG. 14(A), the pixel number ratio ( or the light receiving area ratio) of the sub-pixel 212 for detecting the red wavelength band, the sub-pixel 212 for detecting the green wavelength band, and the sub-pixel 212 for detecting the blue wavelength band does not have to be 1:1:1. For example, it may be a Bayer array with a pixel number ratio (light receiving area ratio ) of red:green:blue = 1:2:1. Alternatively, the pixel number ratio (light receiving area ratio) may be red:green:blue = 1:6:1.

[0185] Note that the number of sub-pixels 212 provided in the pixel 211 may be one, but two or more are preferable. For example , by providing two or more sub-pixels 212 for detecting the same wavelength band, redundancy can be increased and the reliability of the imaging device 200 can be enhanced.

[0186] Also, an imaging device 200 for detecting infrared light can be realized by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light.

[0187] Also, by using an ND (ND: Neutral Density) filter (attenuating filter), the output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element) can be prevented. ​​It can be prevented. By combining and using ND filters with different light reduction amounts, the dynamic range of the imaging device can be increased. The dynamic range of the imaging device can be increased.

[0188] In addition to the filters described above, a lens may be provided on the pixel 211. Here, with reference to the cross-sectional view of FIG. 15, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 15(A), the light 256 can be made to enter the photoelectric conversion element 220 through the lens 255 formed on the pixel 211, the filter 254 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 230, etc. However, as shown in the region surrounded by the dashed-dotted line, a part of the light 256 indicated by the arrow may be blocked by a part of the wiring 257. Therefore, as shown in FIG. 15(B), it is preferable to arrange the lens 255 and the filter 254 on the side of the photoelectric conversion element 220 so that the photoelectric conversion element 220 can efficiently receive the light 256. By making the light 256 enter the photoelectric conversion element 220 from the side of the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity can be provided. The photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 15(A), the light 256 can be made to enter the photoelectric conversion element 220 through the lens 255 formed on the pixel 211, the filter 254 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 230, etc. Specifically, as shown in FIG. 15(A), the light 256 can be made to enter the photoelectric conversion element 220 through the lens 255 formed on the pixel 211, the filter 254 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 230, etc. 4 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 230, etc. The light 256 can be made to enter the photoelectric conversion element 220 through the lens 255 formed on the pixel 211, the filter 254 (filter 254R, filter 254G, and filter 254B), and the pixel circuit 230, etc.

[0189] However, as shown in the region surrounded by the dashed-dotted line, a part of the light 256 indicated by the arrow may be blocked by a part of the wiring 257. Therefore, as shown in FIG. 15(B), it is preferable to arrange the lens 255 and the filter 254 on the side of the photoelectric conversion element 220 so that the photoelectric conversion element 220 can efficiently receive the light 256. The photoelectric conversion element 220 can efficiently receive the light 256. The photoelectric conversion element 220 can efficiently receive the light 256. By making the light 256 enter the photoelectric conversion element 220 from the side of the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity can be provided. The imaging device 200 with high detection sensitivity can be provided.

[0190] As the photoelectric conversion element 220 shown in FIG. 15, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used. A photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.

[0191] In addition, the photoelectric conversion element 220 may be formed using a substance having a function of absorbing radiation and generating charges. As the substance having a function of absorbing radiation and generating charges, Lead, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0192] For example, when selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, a photoelectric conversion element 2 20 having a light absorption coefficient over a wide wavelength band such as X-rays and gamma rays can be realized.

[0193] Here, one pixel 211 included in the imaging device 200 may have a sub-pixel 212 having a first filter in addition to the sub-pixel 212 shown in FIG. 14.

[0194] <Configuration Example 2 of Pixel> Hereinafter, an example of configuring a pixel using a transistor using silicon and a transistor using an oxide semiconductor will be described.

[0195] FIGS. 16(A) and 16(B) are cross-sectional views of elements constituting an imaging device. The imaging device shown in FIG. 16(A) includes a transistor 55 1 using silicon provided on a silicon substrate 500, a transistor 55 2 using an oxide semiconductor stacked and arranged on the transistor 551, a transistor 55 3, and a photodiode 560 provided on the silicon substrate 500. Each transistor and the photodiode 560 have electrical connections with various plugs 570 and wirings 571. Further, an anode 5 61 of the photodiode 560 has an electrical connection with the plug 570 via a low resistance region 563.

[0196] The imaging device also includes a layer 510 having a transistor 551 and a photodiode 560 provided on the silicon substrate 500, and a layer 5 provided in contact with the layer 510 and having a wiring 571. 20 and is provided in contact with layer 520 and has transistors 552 and 553 layer 530 provided in contact with layer 530 and having wirings 572 and 573, and layer 5 40.

[0197] In an example of the cross-sectional view of FIG. 16(A), on the silicon substrate 500, a configuration is adopted in which the light-receiving surface of the photodiode 560 is provided on the surface opposite to the surface on which the transistor 55 1 is formed. By adopting this configuration, an optical path can be secured without being affected by various transistors, wirings, etc. Therefore, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode 560 can also be the same as the surface on which the transistor 551 is formed.

[0198] Note that when forming a pixel using a transistor using an oxide semiconductor, layer 530 may be a layer having transistors. Alternatively, layer 510 may be omitted and a pixel may be formed only with transistors using an oxide semiconductor.

[0199] Note that when forming a pixel using a transistor using silicon, layer 530 may be omitted. An example of a cross-sectional view in which layer 530 is omitted is shown in FIG. 16(B).

[0200] Note that the silicon substrate 500 may be a SOI substrate. Further, instead of the silicon substrate 500, a substrate having germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be used.

[0201] Here, layer 510 having transistors 551 and photodiode 560, and the transistor An insulator 580 is provided between a layer 530 having a resistor 552 and a transistor 553. However, the position of the insulator 580 is not limited. Hydrogen in the insulator provided near the channel formation region of the transistor 551 terminates the dangling bond of silicon and has the effect of improving the reliability of the transistor 551. On the other hand,

[0202] hydrogen in the insulator provided near the transistor 552 and the transistor 553 etc. becomes one of the factors for generating carriers in the oxide semiconductor. Therefore, it may be a factor for reducing the reliability of the transistor 552 and the transistor 553 etc. Therefore, when a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. Hydrogen in the insulator provided near the channel formation region of the transistor 551 terminates the dangling bond of silicon and has the effect of improving the reliability of the transistor 551. On the other hand, hydrogen in the insulator provided near the transistor 552 and the transistor 553 etc. becomes one of the factors for generating carriers in the oxide semiconductor. Therefore, it may be a factor for reducing the reliability of the transistor 552 and the transistor 553 etc. Therefore, when a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. Hydrogen in the insulator provided near the channel formation region of the transistor 551 terminates the dangling bond of silicon and has the effect of improving the reliability of the transistor 551. On the other hand, hydrogen in the insulator provided near the transistor 552 and the transistor 553 etc. becomes one of the factors for generating carriers in the oxide semiconductor. Therefore, it may be a factor for reducing the reliability of the transistor 552 and the transistor 553 etc. Therefore, when a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. When a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. When a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. When a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. When a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. When a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved. When a transistor using an oxide semiconductor is laminated and provided on the upper layer of a transistor using a silicon-based semiconductor, it is preferable to provide an insulator 580 having a function of blocking hydrogen between them. By confining hydrogen in the lower layer than the insulator 580, the reliability of the transistor 551 can be improved. Further, since hydrogen diffusion from the lower layer than the insulator 580 to the upper layer than the insulator 580 can be suppressed, the reliability of the transistor 552 and the transistor 553 etc. can be improved.

[0203] As the insulator 580, for example, refer to the description of the insulator 363.

[0204] In addition, in the cross-sectional view of Fig. 16(A), the photodiode 560 provided in the layer 510 and the transistor provided in the layer 530 can be formed so as to overlap. Then, the integration degree of the pixel can be increased. That is, the resolution of the imaging device can be increased. In addition, in the cross-sectional view of Fig. 16(A), the photodiode 560 provided in the layer 510 and the transistor provided in the layer 530 can be formed so as to overlap. Then, the integration degree of the pixel can be increased. That is, the resolution of the imaging device can be increased. In addition, in the cross-sectional view of Fig. 16(A), the photodiode 560 provided in the layer 510 and the transistor provided in the layer 530 can be formed so as to overlap. Then, the integration degree of the pixel can be increased. That is, the resolution of the imaging device can be increased.

[0205] Also, as shown in FIGS. 17(A1) and 17(B1), part or all of the imaging device may be curved. FIG. 17(A1) shows the state where the imaging device is curved in the direction of the dashed-dotted line X1-X2 in the figure. FIG. 17(A2) is a cross-sectional view of the part indicated by the dashed-dotted line X1-X 2 in FIG. 17(A1). FIG. 17(A3) is a cross-sectional view of the part indicated by the dashed-dotted line Y1- Y2 in FIG. 17(A1).

[0206] FIG. 17(B1) shows the state where the imaging device is curved in the direction of the dashed-dotted line X3-X4 in the figure and is also curved in the direction of the dashed-dotted line Y3-Y4 in the figure. FIG. 17(B2) is a cross-sectional view of the part indicated by the dashed-dotted line X3-X4 in FIG. 17(B1). FIG. 17(B3) is a cross-sectional view of the part indicated by the dashed-dotted line Y3-Y4 in FIG. 17(B1).

[0207] By curving the imaging device, field curvature and spherical aberration can be reduced. Therefore, the optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lens elements for aberration correction can be reduced, miniaturization and weight reduction of an electronic device or the like using the imaging device can be achieved. Also, the quality of the captured image can be improved. .

[0208] (Embodiment 6) In this embodiment, the RF tag including the transistor or the memory device exemplified in the above embodiment will be described with reference to FIG. 18.

[0209] The RF tag in this embodiment has a memory circuit inside, stores the necessary information in the memory circuit, and performs information transfer with the outside using non-contact means, for example, wireless communication. ​From these features, the RF tag can be used in an individual authentication system or the like to identify an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. For use in these applications, extremely high reliability is required.

[0210] The configuration of the RF tag will be described with reference to FIG. 18. FIG. 18 is a block diagram showing a configuration example of the RF tag.

[0211] As shown in FIG. 18, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing the reverse current in a transistor showing a rectifying action included in the demodulation circuit 807, for example, an oxide semiconductor, may be used. Thus, a decrease in the rectifying action due to the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. Note that the data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in the present embodiment can be used in any of these methods. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 8

[0212] The antenna 804 is for transmitting and receiving the radio signal 803 between the antenna 802 connected to the communicator 801. Also, the rectifier circuit 8 is for rectifying the received radio signal 803. 05 rectifies the input AC signal generated by receiving a wireless signal with the antenna 804 , for example, performs half-wave voltage doubler rectification, and smooths the rectified signal with a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit that controls so that when the amplitude of the input AC signal is large and the internally generated voltage is large, power exceeding a certain level is not input to the subsequent circuit .

[0213] The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside . The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 80 9 by utilizing the rise of the stable power supply voltage.

[0214] The demodulation circuit 807 demodulates by envelope detection of the input AC signal to generate a demodulated signal. Also, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804 .

[0215] The logic circuit 809 analyzes the demodulated signal and is a circuit for performing processing. The storage circuit 810 is a circuit for holding the input information, and has a row decoder, a column decoder, a storage area, etc. . Also, the ROM 811 is a circuit for storing a unique number (ID), etc., and outputting according to the processing .

[0216] Note that each of the above circuits can be appropriately selected and discarded as necessary.

[0217] Here, the memory circuit described in the previous embodiment can be used as the memory circuit 810. Since the memory circuit according to an aspect of the present invention can retain information even when the power supply is cut off, it can be suitably used for an RF tag. Further, since the power (voltage) required for writing data in the memory circuit according to an aspect of the present invention is significantly smaller than that of a conventional non-volatile memory, it is also possible not to cause a difference in the maximum communication distance between the time of reading data and the time of writing data. Furthermore, it is possible to suppress malfunction or miswriting due to insufficient power during data writing.

[0218] In addition, since the memory circuit according to an aspect of the present invention can be used as a non-volatile memory, it can also be applied to the ROM 811. In that case, it is preferable to separately prepare a command for the producer to write data into the ROM 811 and prevent the user from freely rewriting it. After the producer writes a unique number before shipping the product, it is possible to assign unique numbers only to the non-defective products to be shipped, rather than to all the manufactured RF tags, so that the unique numbers of the products after shipping are not discontinuous and customer management corresponding to the products after shipping becomes easy.

[0219] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0220] (Embodiment 7) In this embodiment, at least the transistor described in the embodiment can be used, and a CPU including the memory device described in the previous embodiment will be described.

[0221] FIG. 19 shows a configuration example of a CPU that uses at least a part of the transistors described in the previous embodiment. It is a block diagram showing the configuration of an example.

[0222] The CPU shown in FIG. 19 has, on a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1 198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate , a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 19 is only an example showing a simplified configuration thereof, and an actual CPU has various configurations depending on its application. For example, a configuration including the CPU or the arithmetic circuit shown in FIG. 19 may be used as one core, and a plurality of such cores may be included, and each core may operate in parallel. Also, the number of bits that the CPU can handle with its internal arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0223] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the inter rupt controller 1194, the register controller 1197, and the timing controller 1195.

[0224] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during program execution of the CPU, based on their priorities and mask states. The register

[0225] controller 1197 generates addresses for the register 1196 and performs read and write operations to the register 1196 according to the state of the CPU. Also, the timing controller 1195 generates signals for controlling the operation timing of the ALU 1191, ALU controller 119 2, instruction decoder 1193, interrupt controller 1194, and register

[0226] controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal

[0227] to the various circuits mentioned above. In the CPU shown in FIG. 19, the register 1196 is provided with memory cells. As the memory cells of the register 1196, the transistors Select whether to hold data by an element. When data holding by a flip-flop is selected, a power supply voltage is supplied to the memory cells in register 1196 . When data holding in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cells in register 1196 can be stopped.

[0228] FIG. 20 is an example of a circuit diagram of a memory circuit that can be used as register 1196. The memory circuit 1200 includes a circuit 1201 in which stored data is volatile when the power supply is cut off, a circuit 1202 in which stored data is non-volatile when the power supply is cut off, a switch 1203, a switch 1204, a logic element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. Circuit 1202 includes a capacitive element 1208, a transistor 1209, and a transistor 1210. Note that the memory circuit 1200 may further include

[0229] other elements such as diodes, resistive elements, and inductors as necessary. When the supply of the power supply voltage to the memory circuit 1200 is stopped, a ground potential (0 V) or a potential at which transistor 1209 is turned off is continuously input to the gate of transistor 1209 in circuit 1202. For example, the gate of transistor 1209 is grounded through a load such as a resistor.

[0230] Switch 1203 is configured using a transistor 1213 of one conductivity type (e.g., n-channel type), and switch 1204 is of a conductivity type opposite to that of the An example configured using the transistor 1214 is shown. Here, the first end of the switch 1203 corresponds to one of the source and drain of the transistor 1213, and the second terminal of the switch 1203 corresponds to the other of the source and drain of the transistor 1213. The switch 1203 is controlled by the control signal RD input to the gate of the transistor 1213 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 1213 ). The first terminal of the switch 1204 corresponds to one of the source and drain of the transistor 1214, and the second terminal of the switch 1204 corresponds to the other of the source and drain of the transistor 1214. The switch 1204 is controlled by the control signal RD input to the gate of the transistor 1214 to select conduction or non-conduction between the first terminal and the second terminal (that is, the on state or off state of the transistor 1214). One of the source and drain of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitive element 1208 and the gate of the transistor 1210. Here, the connection part is designated as the node M2. One of the source and drain of the transistor 1210 is electrically connected to a wiring (for example, a GND line) capable of supplying a low power supply potential, and the other is electrically connected to the first terminal (one of the source and drain of the transistor 1213) of the switch 1203.

[0231] The second terminal (the other of the source and drain of the transistor 1213) of the switch 1203 is electrically connected to the first terminal (one of the source and drain of the transistor 1214) of the switch 1204. The second terminal (the source of the transistor 1214 and the other of the drain) of the switch 1204 is electrically connected to the first terminal (one of the source and drain of the transistor 1214) of the switch 1204. is electrically connected. The second terminal (the other of the source and drain of the transistor 1214) of the switch 1204 is electrically connected to the first terminal (one of the source and drain of the transistor 1214 and the other of the drain) of the switch 1204. The second terminal (the source of the transistor 1214 and the other of the drain) of the switch 1204 is electrically connected to the first terminal (one of the source and drain of the transistor 1213) of the switch 1203. is electrically connected. The second terminal (the other of the source and drain of the transistor 1213) of the switch 1203 is electrically connected to the first terminal (one of the source and drain of the transistor 1214 and the other of the drain) of the switch 1204. The first terminal (one of the source and drain of the transistor 1214 ) of the switch 1204 is electrically connected to the second terminal (the other of the source and drain of the transistor 1214) of the switch 1204. The other of the switch and the drain is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (one of the source and the drain of the transistor 1214), the input terminal of the logic element 1206, and one of the pair of electrodes of the capacitor element 1207. Here, the connection part is defined as the node M1. The other of the pair of electrodes of the capacitor element 1207 can be configured to receive a constant potential. For example, it can be configured to receive a low power supply potential (such as GND) or a high power supply potential (such as VDD). The other of the pair of electrodes of the capacitor element 1207 is electrically connected to a wiring capable of supplying a low power supply potential (for example, a GND line). The other of the pair of electrodes of the capacitor element 1208 can be configured to receive a constant potential. For example, it can be configured to receive a low power supply potential (such as GND) or a high power supply potential (such as VDD). The other of the pair of electrodes of the capacitor element 1208 is electrically connected to a wiring capable of supplying a low power supply potential (for example, a GND line ).

[0232] Note that the capacitor elements 1207 and 1208 can also be omitted by positively utilizing the parasitic capacitances of transistors and wirings, etc.

[0233] The control signal WE is input to the first gate (the first gate electrode) of the transistor 1209. The switches 1203 and 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE, and one of the switches When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

[0234] On the other side of the source and drain of the transistor 1209, a signal corresponding to the data held in the circuit 1201 is input. In FIG. 20, an example is shown in which the signal output from the circuit 1201 is input to the other side of the source and drain of the transistor 1209. The signal output from the second terminal of the switch 1203 (the other side of the source and drain of the transistor 1213) becomes an inverted signal whose logical value is inverted by the logic element 1206, and is input to the circuit 1201 via the circuit 1220.

[0235] Note that in FIG. 20, an example is shown in which the signal output from the second terminal of the switch 1203 (the other side of the source and drain of the transistor 1213) is input to the circuit 1201 via the logic element 1206 and the circuit 1220, but it is not limited to this. The signal output from the second terminal of the switch 1203 (the other side of the source and drain of the transistor 1213) may be input to the circuit 1201 without inverting its logical value. For example, if there is a node in the circuit 1201 that holds a signal whose logical value is inverted from the signal input from the input terminal, the signal output from the second terminal of the switch 1203 (the other side of the source and drain of the transistor 1213) can be input to the node.

[0236] Also, in FIG. 20, among the transistors used in the memory circuit 1200, the transistors other than the transistor 1209 are layers or substrates 119 made of semiconductors other than oxide semiconductors. ​A transistor in which a channel is formed at 0 can be used. For example, a silicon film or A transistor in which a channel is formed on a silicon substrate can be used. Also, all the transistors used in the memory circuit 1200 can also be transistors in which a channel is formed of an oxide semiconductor. Or, the memory circuit 1200 may further include, in addition to the transistor 1209, transistors in which a channel is formed of an oxide semiconductor, and the remaining transistors can also be transistors in which a channel is formed on a layer or substrate 1190 made of a semiconductor other than the oxide semiconductor.

[0237] For the circuit 1201 in FIG. 20, for example, a flip-flop circuit can be used. Also, as the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

[0238] In the semiconductor device according to one aspect of the present invention, while the power supply voltage is not supplied to the memory circuit 1200, the data stored in the circuit 1201 can be held by the capacitor element 120 8 provided in the circuit 1202.

[0239] Also, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-current. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using such a transistor as the transistor 1209, the signal held in the capacitor element 1208 can be maintained for a long period even while the power supply voltage is not supplied to the memory circuit 120 0. Thus, the memory circuit 1200 can retain the stored content (data) even while the supply of the power supply voltage is stopped. ​​​​​ is capable of holding

[0240] Also, by providing switches 1203 and 1204, a precharge operation is performed, and since it is a memory circuit characterized by this, after the power supply voltage supply resumes, the time until circuit 1201 retains the original data can be shortened.

[0241] Also, in circuit 1202, the signal held by capacitor element 1208 is input to the gate of transistor 1210. Therefore, after the supply of the power supply voltage to memory circuit 1200 resumes, the signal held by capacitor element 1208 can be converted into the state of transistor 1210 (on state or off state) and read out from circuit 1202. Therefore, even if the potential corresponding to the signal held by capacitor element 1208 fluctuates somewhat, the original signal can be accurately read out. Therefore, even if the potential corresponding to the signal held by capacitor element 1208 fluctuates somewhat, the original signal can be accurately read out.

[0242] By using such a memory circuit 1200 in a memory device such as a register or cache memory that a processor has, it is possible to prevent the loss of data in the memory device due to the suspension of the power supply voltage supply . Also, after the supply of the power supply voltage resumes, it is possible to return to the state before the power supply suspension in a short time . Therefore, in the entire processor, or in one or a plurality of logic circuits that make up the processor, it is possible to perform a power-off even for a short time, so the power consumption can be suppressed. can be suppressed.

[0243] In this embodiment, an example in which memory circuit 1200 is used for a CPU has been described, but memory circuit 1 200 is a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Device), R It can also be applied to F tags (Radio Frequency Identification). It is possible.

[0244] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification. It can be implemented in combination.

[0245] (Embodiment 8)

[0246] Hereinafter, a display device according to an aspect of the present invention will be described with reference to FIGS. 21 and 22. It will be described.

[0247] As the display element used in the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element (also referred to as a light emitting display element), etc. can be used. The light emitting element includes an element whose luminance is controlled by current or voltage in its category, specifically including inorganic EL (Elect roluminescence), organic EL, etc. Hereinafter, as an example of the display device A display device using an EL element (EL display device) and a display device using a liquid crystal element (liquid crystal display device) will be described. It will be described.

[0248] Note that the display device shown below includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. It includes.

[0249] In addition, the display device shown below refers to an image display device or a light source (including a lighting device). Also, a module to which a connector, for example, an FPC or a TCP is attached, a module having a printed wiring board at the tip of the TCP, or an IC (integrated circuit) is directly connected to the display element by the COG method. A module or display element having a printed wiring board at the tip of the TCP or an IC (integrated circuit) directly connected to the display element by the COG method. A module having a printed wiring board at the tip of the TCP or an IC (integrated circuit) directly connected to the display element by the COG method. All the modules connected and implemented shall also be included in the display device.

[0250] FIG. 21 shows an example of an EL display device according to an aspect of the present invention. FIG. 21(A) shows a circuit diagram of a pixel of the EL display device. FIG. 21(B) is a top view showing the entire EL display device. Also, FIG. 21(C) is an M-N cross-section corresponding to a part of the dashed line M-N in FIG. 21(B). .

[0251] FIG. 21(A) is an example of a circuit diagram of a pixel used in an EL display device.

[0252] In the present specification and the like, for all terminals of active elements (such as transistors and diodes), passive elements ( capacitive elements, resistive elements, etc.), even if the connection destination is not specified, a person skilled in the art may be able to configure an aspect of the invention. That is, even if the connection destination is not specified, it can be said that an aspect of the invention is clear. And when the content of the specified connection destination is described in the present specification and the like, there may be a case where it is possible to determine that an aspect of the invention without specifying the connection destination is described in the present specification and the like. In particular, when multiple locations are assumed as the connection destination of a terminal, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, for some terminals of active elements (such as transistors and diodes), passive elements (capacitive elements, resistive elements, etc.), etc., by specifying the connection destination, it may be possible to configure an aspect of the invention.

[0253] In the present specification and the like, for a certain circuit, if at least the connection destination is specified, a person skilled in the art may be able to specify the invention. Or, for a certain circuit, if at least If the function is specified, a person skilled in the art may be able to identify the invention. Thus, if the function is specified, it can be said that one aspect of the invention is clear. And in some cases, it may be possible to determine that one aspect of the invention whose function has been specified is described in this specification or the like. Therefore, for a certain circuit, even if the function is not specified, if the connection destination is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Or, for a certain circuit, even if the connection destination is not specified, if the function is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Thus, if the function is specified, it can be said that one aspect of the invention is clear. And in some cases, it may be possible to determine that one aspect of the invention whose function has been specified is described in this specification or the like. Therefore, for a certain circuit, even if the function is not specified, if the connection destination is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Or, for a certain circuit, even if the connection destination is not specified, if the function is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Thus, if the function is specified, it can be said that one aspect of the invention is clear. And in some cases, it may be possible to determine that one aspect of the invention whose function has been specified is described in this specification or the like.

[0254] The EL display device shown in Fig. 21(A) includes a switch element 743, a transistor 741, a capacitor element 742, and a light-emitting element 719. Note that Fig. 21(A) and the like are examples of circuit configurations. Therefore, it is further possible to add a transistor. Conversely, it is also possible not to add a transistor, a switch, a passive element, or the like at each node in Fig. 21(A).

[0255] Note that Fig. 21(A) and the like are examples of circuit configurations. Therefore, it is further possible to add a transistor. Conversely, it is also possible not to add a transistor, a switch, a passive element, or the like at each node in Fig. 21(A). The gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor element 742 and electrically connected to one electrode of the light-emitting element 719. The drain of the transistor 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is electrically connected to the signal line 744. The other electrode of the light-emitting element 719 is supplied with a fixed potential. Note that the fixed potential is set to the ground potential GND or a potential lower than that. The gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor element 742 and electrically connected to one electrode of the light-emitting element 719. The drain of the transistor 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is electrically connected to the signal line 744. The other electrode of the light-emitting element 719 is supplied with a fixed potential. Note that the fixed potential is set to the ground potential GND or a potential lower than that.

[0256] The gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor element 742 and electrically connected to one electrode of the light-emitting element 719. The drain of the transistor 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is electrically connected to the signal line 744. The other electrode of the light-emitting element 719 is supplied with a fixed potential. Note that the fixed potential is set to the ground potential GND or a potential lower than that.

[0257] As the switching element 743, it is preferable to use a transistor. Using a transistor makes it possible to reduce the area of the pixel and achieve a high-resolution EL display device. Also , as the switching element 743, using a transistor fabricated through the same process as the transistor 741 can improve the productivity of the EL display device. Note that as the transistor 74 1 or / and the switching element 743, for example, the above-described transistor can be applied .

[0258] Fig. 21(B) is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 7 50, a sealing material 734, a drive circuit 735, a drive circuit 736, a pixel 737, and an FP C732. The sealing material 734 is disposed between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. Note that the drive circuit 735 or / and the drive circuit 736 may be disposed outside the sealing material 734.

[0259] Fig. 21(C) is a cross-sectional view of the EL display device corresponding to a part of the dashed line M-N in Fig. 21(B) .

[0260] In Fig. 21(C), as the transistor 741, an insulator 708 on the substrate 700 and a conductor 704a embedded in the insulator 708 are provided. An insulator 712a on the insulator 708 and the conductor 704a , an insulator 712b on the insulator 712a, a semiconductor 706 on the insulator 712b and overlapping the conductor 704a , conductors 716a and conductors 716b in contact with the semiconductor 706, and an insulator 7 on the semiconductor 706, the conductor 716a, and the conductor 716b are shown. 18a, insulator 718b on insulator 718a, and insulator 718c on insulator 718b , and a structure having a conductor 714a that is on insulator 718c and overlaps semiconductor 706 is shown . Note that the structure of transistor 741 is an example and may be different from the structure shown in Fig. 21(C). Conductor 704a may be a wiring layer formed by the method described in Embodiment 1. It may be used.

[0261] Therefore, in transistor 741 shown in Fig. 21(C), conductor 704a has the function of a gate electrode, and insulators 712a and 712b have the function of a gate insulator, conductor 716a has the function of a source electrode, conductor 716b has the function of a drain electrode, insulators 718a, 718b, and 718c have the function of a gate insulator, and conductor 714a has the function of a gate electrode. Also, semiconductor 706 may have its electrical characteristics fluctuate when light hits it. Therefore, it is preferable that one or more of conductor 704a, conductor 716a, conductor 716b, and conductor 714a have light-shielding properties.

[0262] Note that the interface between insulator 718a and insulator 718b is represented by a dashed line, which indicates that the boundary between the two may not be clear. For example, when using the same type of insulator for insulator 718a and insulator 718b, there may be cases where they cannot be distinguished depending on the observation method.

[0263] In Fig. 21(C), as capacitor element 742, insulator 708 on the substrate, conductor 704b embedded in insulator 708, insulator 712a on insulator 708 and on conductor 704b are shown ​​​​​​​​​​, an insulator 712b on the insulator 712a, and a conductor 704b on the insulator 712b. A conductor 716a is connected to the insulator 718a. An insulator 718a is connected to the insulator 718a. 718b, an insulator 718c on the insulator 718b, and a conductor 71 6a and conductor 714b overlapping each other, and the overlapping portion of conductor 716a and conductor 714b In the region, a portion of the insulator 718a and the insulator 718b are removed. The conductor 704b may be a wiring layer formed by the method described in the first embodiment.

[0264] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. The conductor 716a serves as the other electrode.

[0265] Therefore, the capacitor 742 can be formed using a film common to the transistor 741. In addition, it is preferable that the conductor 704a and the conductor 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b can be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. .

[0266] A capacitor 742 shown in FIG. 21C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 21C has high display quality. The illustrated capacitive element 742 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulator 718a and the insulator 718b are partially removed. The capacitive element according to one aspect is not limited to this. For example, in order to thin the overlapping region of the conductor 716a and the conductor 714b, a structure in which a part of the insulator 718c is removed may be had.

[0267] An insulator 720 is disposed on the transistor 741 and the capacitive element 742. Here, the insulator 720 may have an opening that reaches the conductor 716a that functions as the source electrode of the transistor 741. A conductor 781 is disposed on the insulator 720. The conductor 78 1 may be electrically connected to the transistor 741 through the opening of the insulator 720.

[0268] A partition wall 784 having an opening reaching the conductor 781 is disposed on the conductor 781. The partition wall 784 has a light-emitting layer 782 in contact with the conductor 781 at the opening of the partition wall 784. The light-emitting layer 782 is disposed on the light-emitting layer 782. The conductor 781, the light-emitting layer 782, and the overlapping region of the conductor 783 becomes the light-emitting element 719.

[0269] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. Next, an example of a liquid crystal display device will be described.

[0270] FIG. 22(A) is a circuit diagram showing a configuration example of a pixel of a liquid crystal display device. The pixel shown in FIG. 22 includes a transistor 751, a capacitive element 752, and an element (liquid crystal element) 753 filled with liquid crystal between a pair of electrodes. The transistor 751 has one of the source and drain electrically connected to the signal line 755,

[0271] and the gate is electrically connected to the scanning line 754. The gate is electrically connected to the scanning line 754.

[0272] In the capacitor element 752, one electrode is electrically connected to the other of the source and drain of the transistor 751, and the other electrode is electrically connected to the wiring that supplies the common potential. The other electrode is electrically connected to the wiring that supplies the common potential.

[0273] In the liquid crystal element 753, one electrode is electrically connected to the other of the source and drain of the transistor 751, and the other electrode is electrically connected to the wiring that supplies the common potential. Note that The other electrode is electrically connected to the wiring that supplies the common potential. Note that The common potential applied to the wiring to which the other electrode of the capacitor element 752 described above is electrically connected and The common potential applied to the other electrode of the liquid crystal element 753 may be different potentials.

[0274] Note that the liquid crystal display device will also be described in the same manner as the EL display device for the top view. A cross-sectional view of the liquid crystal display device corresponding to the dashed line M-N in FIG. 21(B) is shown in FIG. 22(B). In FIG. 22(B), The FPC 732 is connected to the wiring 733a via the terminal 731. Note that the wiring 73 3a may be made of the same kind of conductor or semiconductor as either the conductor or semiconductor constituting the transistor 751. 3a may be made of the same kind of conductor or semiconductor as either the conductor or semiconductor constituting the transistor 751. Or a semiconductor may be used.

[0275] For the transistor 751, refer to the description of the transistor 741. Also, for the capacitor element 752, refer to the description of the capacitor element 742. Note that FIG. 22(B) shows the structure of the capacitor element 752 corresponding to the capacitor element 742 in FIG. 21 (C), but it is not limited to this. It is not limited to this.

[0276] Note that when an oxide semiconductor is used for the semiconductor of the transistor 751, a transistor with an extremely small off-current can be obtained. Therefore, the charge held in the capacitor element 752 is less likely to leak, and the voltage applied to the liquid crystal element 753 can be maintained over a long period. Therefore, the charge held in the capacitor element 752 is less likely to leak, and the voltage applied to the liquid crystal element 753 can be maintained over a long period. And the voltage applied to the liquid crystal element 753 can be maintained over a long period. Therefore, when displaying a video with little movement or a still image, turning off the transistor 751 eliminates the need for power for the operation of the transistor 751, enabling a liquid crystal display device with low power consumption. Also, since the occupied area of the capacitive element 752 can be reduced, a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device can be provided. An insulator 721 is disposed over the transistor 751 and the capacitive element 752. Here, the insulator 721 has an opening reaching the transistor 751. A conductor 791 is disposed over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 721. A conductor 791 is disposed over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 721.

[0277] An insulator 792 that functions as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed over the insulator 792. An insulator 794 that functions as an alignment film is disposed over the liquid crystal layer 793. A spacer 795 is disposed over the insulator 794. A conductor 796 is disposed over the spacer 795 and the insulator 794. A substrate 797 is disposed over the conductor 796. By having the above-described structure, a display device having a capacitive element with a small occupied area can be provided, or a display device with high display quality can be provided. Or, a high-definition display device can be provided. For example, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or various An insulator 792 that functions as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed over the insulator 792. An insulator 794 that functions as an alignment film is disposed over the liquid crystal layer 793. A spacer 795 is disposed over the insulator 794. A conductor 796 is disposed over the spacer 795 and the insulator 794. A substrate 797 is disposed over the conductor 796.

[0278] An insulator 792 that functions as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed over the insulator 792. An insulator 794 that functions as an alignment film is disposed over the liquid crystal layer 793. A spacer 795 is disposed over the insulator 794. A conductor 796 is disposed over the spacer 795 and the insulator 794. A substrate 797 is disposed over the conductor 796. An insulator 792 that functions as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed over the insulator 792. An insulator 794 that functions as an alignment film is disposed over the liquid crystal layer 793. A spacer 795 is disposed over the insulator 794. A conductor 796 is disposed over the spacer 795 and the insulator 794. A substrate 797 is disposed over the conductor 796. An insulator 792 that functions as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed over the insulator 792. An insulator 794 that functions as an alignment film is disposed over the liquid crystal layer 793. A spacer 795 is disposed over the insulator 794. A conductor 796 is disposed over the spacer 795 and the insulator 794. A substrate 797 is disposed over the conductor 796. An insulator 792 that functions as an alignment film is disposed over the conductor 791. A liquid crystal layer 793 is disposed over the insulator 792. An insulator 794 that functions as an alignment film is disposed over the liquid crystal layer 793. A spacer 795 is disposed over the insulator 794. A conductor 796 is disposed over the spacer 795 and the insulator 794. A substrate 797 is disposed over the conductor 796. By having the above-described structure, a display device having a capacitive element with a small occupied area can be provided, or a display device with high display quality can be provided. Or, a high-definition display device can be provided.

[0279] By having the above-described structure, a display device having a capacitive element with a small occupied area can be provided, or a display device with high display quality can be provided. Or, a high-definition display device can be provided. For example, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or various For example, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or various

[0280] For example, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or various For example, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or various It can have various elements. The display element, display device, light-emitting element, or light-emitting device can be, for example, an EL element (including an EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element), an LE D (such as a white LED, a red LED, a green LED, a blue LED, etc.), a transistor (a transistor that emits light in response to current), an electron-emitting element, a liquid crystal element, electronic ink, an electrophoretic element, a gr rating light valve (GLV), a plasma display (PDP), a display element using MEMS (ma icro - electro - mechanical system), a digital micromirror device (DMD), a DMS (digital microshutter), an IMOD (inter ference modulation) element, a shutter - type MEMS display element, a light interference type MEMS display element, an electro - wetting element, a piezoelectric ceramic display having at least one of, for example, a display element using carbon nanotubes. Among these, it may also have a display medium whose contrast, brightness, reflectance, transmittance, etc. change due to an electrical or magnetic action.

[0281] As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron - emitting element, there is a field emission display (FED) or an SED - type flat - panel display (SED: Surface - conduction E lectron - emitter Display), etc. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct - view liquid crystal display, a projection liquid crystal display) etc. As an example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element, ​ As an example, there is electronic paper. In the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have the function of a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, etc. Further, in that case, it is possible to provide any storage circuit such as SRAM under the reflective electrode. This can further reduce power consumption. When using an LED, graphene or graphite may be disposed under the electrode of the LED or the nitride semiconductor. Graphene or graphite may be stacked in a plurality of layers to form a multilayer film. By providing graphene or graphite in this way, it is possible to easily form a film of a nitride semiconductor, for example, an n-type GaN semiconductor having a crystal, on it. Furthermore, by providing a p-type GaN semiconductor having a crystal or the like on it, an LED can be formed. An AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal.

[0282] The GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can also be formed by a sputtering method. (Embodiment 9) A semiconductor device according to an aspect of the present invention includes a display device, a personal computer, and an image playback device having a recording medium (typically a device having a display capable of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying the image). It can be used for the above.

[0283] ​​​​​​​​​can be achieved. Additionally, an electronic device that can use the semiconductor device according to one aspect of the present invention and include mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays ), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 23 .

[0284] FIG. 23(A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908 , etc. Note that the portable game machine shown in FIG. 23(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this .

[0285] FIG. 23(B) is a portable data terminal, which has a first housing 911, a second housing 912, a first display unit 9 13, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 913 is provided on the first housing 911, and the second display unit 914 is provided on the second housing 912 . The first housing 911 and the second housing 912 are connected by a connection unit 915 , and the angle between the first housing 911 and the second housing 912 can be changed by the connection unit 915 . The video on the first display unit 913 may be configured to be switched according to the angle between the first housing 911 and the second housing 9 12 at the connection unit 915. Also, the first display unit 913 and A display device with a function as a position input device added to at least one of the second display units 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel portion of the display device.

[0286] FIG. 23(C) shows a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard 923, a pointing device 924, etc.

[0287] FIG. 23(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a freezer door 933, etc.

[0288] FIG. 23(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, operation keys 944, a lens 945, a connection portion 946, etc. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display unit 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by the connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. The video image on the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 at the connection portion 946.

[0289] FIG. 23(F) shows an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, etc.

[0290] This embodiment may be appropriately combined with at least some of the other embodiments described in this specification.​​​​​​​​​​​ They can be implemented together.

[0291] (Embodiment 10) In this embodiment, a usage example of an RF tag according to one aspect of the present invention will be described with reference to FIG. 24. The applications of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, certificates (see FIG. 24(A) such as driver's licenses and residence certificates), recording media (DVDs, video tapes, etc., see FIG. 24(B)), packaging containers (wrapping paper, bottles, etc., see FIG. 24(C) ), vehicles (bicycles, etc., see FIG. 24(D)), personal belongings (bags, glasses, etc.), food products, plants animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), etc., or labels (see FIGS. 24(E) and 24(F)) attached to each article can be provided and used.

[0292] The RF tag 4000 according to one aspect of the present invention is fixed to an article by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin, it is embedded inside the organic resin and fixed to each article. The RF tag 4000 according to one aspect of the present invention realizes small size, thin thickness, and light weight, so that the designability of the article itself is not impaired even after being fixed to the article. In addition, by providing the RF tag 4000 according to one aspect of the present invention on banknotes, coins, securities, bearer bonds, or certificates etc., an authentication function can be provided, and by utilizing this authentication function, forgery can be prevented. Also, for packaging containers recording media, personal belongings, food products, clothing, daily necessities, or electronic devices, etc., one aspect of the present invention can be provided. recording media, personal belongings, food products, clothing, daily necessities, or electronic devices, etc., one ​By attaching the RF tag according to the aspect, the efficiency of a system such as an inspection system can be improved. Also, even for vehicles, attaching the RF tag according to one aspect of the present invention can enhance the security against theft and the like.

[0293] As described above, by using the RF tag according to one aspect of the present invention for each of the applications exemplified in this embodiment it is possible to reduce the operating power including information writing and reading, so that the maximum communication distance can be extended. Also, since information can be held for an extremely long period even in a state where the power is cut off it can be suitably used for applications where the frequency of writing and reading is low.

[0294] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

Example

[0295] In this Example 1, the wiring layer of Embodiment 1 was fabricated, and cross-sectional observation was performed using a scanning transmission electron microscope (STEM). ing Transmission Electron Microscope: STEM

[0296] A thermal oxide film was formed on a silicon single crystal wafer with a film thickness of 400 nm. Next, a silicon nitride film was formed by plasma CVD with a film thickness of 50 nm. Next, a silicon oxynitride film was formed by plasma CVD with a film thickness of 150 nm.

[0297] Next, in order to form a groove in the silicon oxynitride film, resist patterning was performed by electron beam lithography. Using this resist pattern as a mask, dry etching was used. , grooves were formed in the silicon oxynitride film.

[0298] After removing the resist, a conductor was formed by metal CVD method. First, titanium nitride was formed with a film thickness of 5 nm, and then tungsten was continuously formed with a film thickness of 200 nm.

[0299] Next, CMP was performed using a slurry containing silica to remove tungsten and titanium nitride on the silicon oxynitride film.

[0300] Cleaning was performed to remove the slurry and particles remaining on the substrate after CMP. The cleaning conditions were immersion in ozone water, followed by brush cleaning, then cleaning with diluted hydrofluoric acid, and finally pure water cleaning and drying. The sample was prepared as described above.

[0301] Cross-sectional observation of this sample was performed in two orthogonal directions using STEM. Figures 25(A), 25( B) and 25(C) are cross-sectional STEM photographs in two orthogonal directions.

[0302] As a result of the observation, as in Embodiment 1, the end of titanium nitride, which is the first conductor, is at the same level or lower than the height of the groove at the end of the groove, and the upper surface of W, which is the second conductor, is at the same level or lower than the height of the end of titanium nitride. It was also confirmed that problems such as oxidation of tungsten and film peeling associated therewith were suppressed.

Example

[0303] In this example, a transistor having the wiring layer of Example 1 shown in FIG. 3 as the first gate electrode was fabricated, and transistor characteristics were measured.

[0304] ​​​​​The channel length L of the fabricated transistor was 59 nm, and the channel width W was 67 nm. First, the initial characteristics of the transistor were measured.

[0305] The measurement conditions for the initial characteristics were as follows: at room temperature, the source was grounded, the drain voltage (Vd) was fixed at 0.1 V, the second gate voltage (Vg) was varied from -3.0 V to +3.0 V at 0.1 V intervals, the drain current (Id) was measured, and its variation curve was recorded. Next, with the drain voltage fixed at 1.8 V, the variation curve of the drain current was similarly recorded. At this time, the first gate electrode, which was the back gate, was grounded. The results are shown in Fig. 26(A), and excellent transistor characteristics in terms of on / off characteristics were obtained.

[0306] Next, using the same transistor as above, a voltage was applied to the first gate electrode, which was the back gate, to measure the transistor characteristics. The potential of the first gate electrode (Vbg), which was the back gate, was varied at 2 V intervals as -4 V, -2 V, 0 V, +2 V, and +4 V, and the variation curve of the drain current was recorded under the same measurement conditions as the above-mentioned initial characteristics. In Fig. 26(B), the variation curve of the drain current when the potential of the first gate electrode, which was the back gate, was varied as -4 V, -2 V, 0 V, + 2 V, and +4 V at a drain voltage of +0.1 V is shown. In Fig. 26(C), the variation curve of the drain current when the potential of the first gate electrode, which was the back gate, was varied as -4 V, -2 V, 0 V +2 V, and +4 V at a drain voltage of +1.8 V is shown. When the voltage of the first gate electrode, which was the back gate, was changed in the negative direction, the variation curve of the drain current shifted in the positive direction. When the voltage of the first gate electrode was changed in the positive direction, the drain

[0307] current variation curve shifted in the positive direction. When the first gate voltage was changed in the positive direction, the drain It was confirmed that the change curve of the in-current shifted in the negative direction. As a result, it was confirmed that the first gate electrode functions as a back gate and the threshold voltage can be controlled normally.

Explanation of Signs

[0308] 100 Transistor 110 Transistor 130 Capacitor 140 Capacitor 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 Pixel 212 Sub-pixel 212B Sub-pixel 212G Sub-pixel 212R Sub-pixel 220 Photoelectric conversion element 230 Pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 Light 257 Wiring 260 Peripheral circuit 270 Peripheral circuit 280 Peripheral circuit 290 Peripheral circuit 291 Light source 300 Substrate 301 Insulator 302 Insulator 303 Insulator 304 Insulator 305 Insulator 306 Insulator 307 Insulator 308 Insulator 310 Conductor 311 Conductor 312 Conductor 312a Source electrode or drain electrode 312b Source electrode or drain electrode 314 Conductor 315 Conductor 316 Conductor 320 Semiconductor 320a Semiconductor 320c Semiconductor 330 Gate electrode 331 Gate electrode 341 Electrode 342 Electrode 350 Substrate 351 STI 353 Diffusion layer 354 Insulator 355 Sidewall 360 Insulator 361 Insulator 362 Insulator 363 Insulator 364 Insulator 365 Insulator 370 Plug 371 Plug 372 Plug 373 Wiring layer 374 Wiring layer 375 Wiring layer 376 Wiring layer 377 Wiring layer 378 Wiring layer 379 Wiring layer 380 Wiring layer 381 Wiring layer 382 Plug 383 Plug 384 Plug 385 Wiring layer 386 Wiring layer 387 Wiring layer 388 Plug 389 Plug 390 Wiring layer 391 Plug 392 Plug 393 Wiring Layer 394 Wiring Layer 500 Silicon Substrate 510 Layer 520 Layer 530 Layer 540 Layer 551 Transistor 552 Transistor 553 Transistor 560 Photodiode 561 Anode 563 Low-Resistance Region 570 Plug 571 Wiring 572 Wiring 573 Wiring 580 Insulator 700 Substrate 704a Conductor 704b Conductor 706 Semiconductor 708 Insulator 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c Insulator 719 Light-Emitting Element 720 Insulator 721 Insulator 731 Terminal 732 FPC 733a Wiring 734 Sealing Material 735 Driving Circuit 736 Driving Circuit 737 Pixel 741 Transistor 742 Capacitor Element 743 Switching Element 744 Signal Line 750 Substrate 751 Transistor 752 Capacitor element 753 Liquid crystal element 754 Scanning line 755 Signal line 781 Conductor 782 Light-emitting layer 783 Conductor 784 Partition wall 791 Conductor 792 Insulator 793 Liquid crystal layer 794 Insulator 795 Spacer 796 Conductor 797 Substrate 800 RF tag 801 Communicator 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Memory circuit 811 ROM 901 Housing 902 Housing 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display unit 914 Display unit 915 Connection part 916 Operation key 921 Housing 922 Display unit 923 Keyboard 924 Pointing device 931 Housing 932 Door for refrigerator compartment Door for the 933 Freezer Housing 941 Housing 942 Display Unit 943 Operation Key 944 Lens 945 Connection Part 946 Vehicle Body 951 Wheel 952 Dashboard 953 Light 954 1189 ROM Interface Substrate 1190 ALU 1191 ALU Controller 1192 Instruction Decoder 1193 Interrupt Controller 1194 Timing Controller 1195 Register 1196 Register Controller 1197 Bus Interface 1198 ROM 1199 Memory Circuit 1200 Circuit 1201 Circuit 1202 Switch 1203 Switch 1204 Logic Element 1206 Capacitive Element 1207 Capacitive Element 1208 Transistor 1209 Transistor 1210 Transistor 1213 Transistor 1214 Circuit 1220 4000 RF Tag 5100 Pellet Substrate 5120 Region 5161

Claims

1. A semiconductor device having a plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor, the insulating films each have a first opening; the second conductor is provided below the plurality of insulating films; the first conductor has a region in contact with the second conductor at a bottom of the first opening, the third conductor is provided in the plurality of insulating films; the fourth conductor is provided above the plurality of insulating films; the first conductor has a region in contact with a side surface of the third conductor; the first conductor has a region in contact with the fourth conductor, the first conductor does not have a region in contact with the fifth conductor; the plurality of insulating films include at least a first insulating film, a second insulating film, and a third insulating film; the first insulating film has a region in contact with a bottom surface of the fifth conductor and a region in contact with a side surface of the first conductor; the second insulating film has a region in contact with an upper surface of the first insulating film, a region in contact with a first side surface of the fifth conductor, and a region in contact with a side surface of the first conductor; a third insulating film having a region in contact with an upper surface of the second insulating film, a region in contact with a second side surface of the fifth conductor, a region in contact with an upper surface of the fifth conductor, and a region in contact with a side surface of the first conductor.

2. A semiconductor device having a silicon substrate, a plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor, the silicon substrate is provided with a channel formation region of a transistor; the insulating films are provided above the silicon substrate, the insulating films each have a first opening; the second conductor is provided above the silicon substrate and below the insulating films; the first conductor has a region in contact with the second conductor at a bottom of the first opening, the third conductor is provided in the plurality of insulating films; the fourth conductor is provided above the plurality of insulating films; the first conductor has a region in contact with a side surface of the third conductor; the first conductor has a region in contact with the fourth conductor, the first conductor does not have a region in contact with the fifth conductor; the plurality of insulating films include at least a first insulating film, a second insulating film, and a third insulating film; the first insulating film has a region in contact with a bottom surface of the fifth conductor and a region in contact with a side surface of the first conductor; the second insulating film has a region in contact with an upper surface of the first insulating film, a region in contact with a first side surface of the fifth conductor, and a region in contact with a side surface of the first conductor; a third insulating film having a region in contact with an upper surface of the second insulating film, a region in contact with a second side surface of the fifth conductor, a region in contact with an upper surface of the fifth conductor, and a region in contact with a side surface of the first conductor.

3. 3. An electronic device comprising the semiconductor device according to claim 1.

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