Semiconductor device

Abstract

To provide a semiconductor device in which ringing is suppressed and simplification of a snubber circuit and improvement of reliability are performed.SOLUTION: A semiconductor device A1 comprises: at least one semiconductor element 10 that has a switching function; a first power lead 31 and a second power lead 32 that are current paths switched by the semiconductor element, and are conductive members made of a first material (Cu etc.); and a coating layer 90 that covers at least a portion of the conductive member and is made of a second material. The second material satisfies at least one requirement of the following three requirements. (1) Permeability is higher than that of the first material. (2) Electrical resistivity is higher than that of the first material. (3) Dielectric tangent is larger than 0.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a semiconductor element.

Background Art

[0002] Patent Document 1 discloses a conventional semiconductor device. The semiconductor device described in Patent Document 1 includes a semiconductor element, an island, leads, a plurality of bonding materials, a connection plate, and a sealing resin. In this semiconductor device, the semiconductor element is, for example, a transistor such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the semiconductor device is energized, the main circuit current switched by the semiconductor element flows through the island and leads as a path. The faster the switching speed, the more likely ringing occurs in the main circuit current, and this ringing can cause electromagnetic interference noise that affects the operation of surrounding devices, for example.

[0005] In view of the above problems, one object of the present disclosure is to provide a semiconductor device capable of suppressing ringing.

Means for Solving the Problems

[0006] The semiconductor device provided by the present disclosure includes at least one semiconductor element having a switching function, a conduction member made of a first material that forms a current path switched by the semiconductor element, and a coating layer made of a second material that covers at least a part of the conduction member. Further, the second material satisfies at least one of the following three requirements: (a) having a higher magnetic permeability than the first material, (b) having a higher electrical resistivity than the first material, and (c) having a dielectric tangent greater than 0.

[0007] Preferably, the second material is a magnetic conductor having a higher magnetic permeability than the first material and a higher electrical resistivity than the first material.

[0008] Preferably, the second material has a dielectric tangent greater than 0.

[0009] Preferably, the second material has a higher magnetic permeability than the first material and a dielectric tangent greater than 0.

[0010] Preferably, the second material has a higher electrical resistivity than the first material and a dielectric tangent greater than 0.

[0011] Preferably, the thickness of the coating layer is 1 μm to 5 μm.

[0012] Preferably, the relative magnetic permeability of the second material is 10 or more.

[0013] Preferably, the electrical resistivity of the second material is at least twice that of the first material.

[0014] Preferably, the dielectric tangent of the second material is 0.01 or more.

[0015] Preferably, the semiconductor device according to the present disclosure further includes a capacitor having a first terminal and a second terminal for electrical connection. Further, the at least one semiconductor element is a plurality of semiconductor elements that constitute a half bridge including at least one set of upper and lower arms, and the plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm. The conductive member includes a first metal layer connected to the drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to the source electrode of the second semiconductor element. The first terminal of the capacitor is connected to the first power lead, and the second terminal of the capacitor is connected to the second power lead. The coating layer includes a first portion covering the first power lead and a second portion covering the second power lead.

[0016] Preferably, the first power lead includes a portion that constitutes a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered by the first portion.

[0017] Preferably, the second power lead includes a portion that constitutes a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered by the second portion.

[0018] Preferably, the coating layer includes a third portion that covers the first metal layer.

[0019] Preferably, the conductive member includes a second metal layer connected to the drain electrode of the second semiconductor element and a third power lead connected to the second metal layer, and the second metal layer and the third power lead are not covered by the coating layer.

[0020] Preferably, the conductive member includes an intermediate lead connected to the source electrode of the first semiconductor element and the second metal layer, and the intermediate lead is not covered by the coating layer.

[0021] Preferably, the conductive member includes a first spacer interposed between the first metal layer and the first power lead, and the coating layer includes a fourth portion covering the first spacer.

[0022] Preferably, the conductive member includes a conductor interposed between the source electrode of the second semiconductor element and the second power lead.

[0023] Preferably, the semiconductor element is any one of a SiC MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT, and a GaN HEMT.

Advantages of the Invention

[0024] According to the present disclosure, in a semiconductor device, ringing can be suppressed, and the snubber circuit can be simplified and the reliability can be improved.

Brief Description of the Drawings

[0025]

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Embodiments for Carrying Out the Invention

[0026] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings.

[0027] FIGS. 1 to 11 show a semiconductor device according to the first embodiment. The semiconductor device A1 of the first embodiment includes a plurality of semiconductor elements 10, a support substrate 20, a plurality of leads, a plurality of intermediate leads 40, a plurality of wire members 50, a plurality of conductive blocks 60, a sealing resin 70, a capacitor 81, and a coating layer 90. The plurality of leads includes a first power lead 31, a second power lead 32, a third power lead 33, a pair of gate leads 34A, 34B, a pair of driver source leads 35A, 35B, and a plurality of dummy leads 36. The plurality of conductive blocks 60 includes a plurality of first blocks 61 and a plurality of second blocks 62.

[0028] FIG. 1 is a perspective view showing a semiconductor device A1. FIG. 2 is a view of the perspective view of FIG. 1 with the encapsulating resin 70 omitted. In FIG. 2, a plurality of wire members 50 are omitted. FIG. 3 is a plan view showing the semiconductor device A1. FIG. 4 is a view of the plan view of FIG. 3 with the encapsulating resin 70 indicated by an imaginary line (two-dot chain line). FIG. 5 is a partially enlarged view of a part of FIG. 4. FIG. 6 is a front view showing the semiconductor device A1. FIG. 7 is a bottom view showing the semiconductor device A1. FIG. 8 is a left side view showing the semiconductor device A1. FIG. 9 is a right side view showing the semiconductor device A1. FIG. 10 is a cross-sectional view taken along the line X-X of FIG. 4. FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 10. In FIGS. 1 to 8, for convenience of understanding, a plurality of discrete points are drawn on the coating layer 90.

[0029] In the following description, three mutually orthogonal directions (x direction, y direction, z direction) are referred to as appropriate. The z direction corresponds to the thickness direction of the semiconductor device A1. The x direction corresponds to the left-right direction in the plan view of the semiconductor device A1 (see FIGS. 3 and 4). The y direction corresponds to the up-down direction in the plan view of the semiconductor device A1 (see FIGS. 3 and 4). If necessary, one of the x directions is the x1 direction and the other of the x directions is the x2 direction. Similarly, one of the y directions is the y1 direction, the other of the y directions is the y2 direction, one of the z directions is the z1 direction, and the other of the z directions is the z2 direction.

[0030] Each of the plurality of semiconductor elements 10 has a function of switching the main circuit current, and its specific configuration is not particularly limited. Specific examples of the semiconductor element 10 include, for example, SiC (silicon carbide) MOSET, SiC IGBT, Si MOSFET, Si IGBT (Insulated Gate Bipolar Transistor), and GaN (gallium nitride) HEMT (High Electron Mobility Transistor). Each semiconductor element 10 is rectangular when viewed in the z direction (also referred to as "plan view"), but the present disclosure is not limited thereto.

[0031] As shown in FIGS. 5 and 10, each of the plurality of semiconductor elements 10 has a device main surface 101 and a device back surface 102. In each semiconductor element 10, the device main surface 101 and the device back surface 102 are spaced apart in the z direction and face opposite sides. In the present embodiment, the device main surface 101 faces the z2 direction, and the device back surface 102 faces the z1 direction.

[0032] As shown in FIGS. 5 and 10, each of the plurality of semiconductor elements 10 has a main surface electrode 11, a back surface electrode 12, and an insulating film 13.

[0033] As shown in FIG. 5, the main surface electrode 11 is provided on the device main surface 101. The main surface electrode 11 includes a source electrode 111, a gate electrode 112, and a driver source electrode 113 as shown in FIG. 5. In the present embodiment, the source electrode 111 is an electrode through which a source current flows. In the present embodiment, a gate voltage for driving each semiconductor element 10 is applied to the gate electrode 112. The driver source electrode 113 is an electrode that serves as a reference potential for the gate voltage. The source electrode 111 is larger than the gate electrode 112 and the driver source electrode 113. The gate electrode 112 and the driver source electrode 113 are substantially the same size. In the present embodiment, the source electrode 111 is shown as being composed of one region, but it may be divided into a plurality of regions.

[0034] As shown in FIG. 10, the back surface electrode 12 is provided on the device back surface 102. The back surface electrode 12 is formed over the entire device back surface 102. In the present embodiment, the back surface electrode 12 is an electrode through which a drain current flows, and will also be referred to as the drain electrode 12 in the following description.

[0035] As shown in FIG. 5, the insulating film 13 is provided on the device main surface 101. The insulating film 13 has electrical insulation properties. The insulating film 13 surrounds the main surface electrode 11 in plan view. The insulating film 13 insulates the source electrode 111 and the gate electrode 112. The insulating film 13 is, for example, a SiO 2 (silicon dioxide) layer, Si 3 N 4(Silicon nitride) layer and polybenzoxazole layer are laminated in this order on the main element surface 101, and the polybenzoxazole layer is the surface layer. In the insulating film 13, a polyimide layer may be used instead of the polybenzoxazole layer. The configuration of the insulating film 13 is not limited to the above-described one.

[0036] The plurality of semiconductor elements 10 include a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. In the present embodiment, the semiconductor device A1 constitutes a half-bridge type switching circuit. The plurality of first semiconductor elements 10A constitute the upper arm circuit in this switching circuit, and the plurality of second semiconductor elements 10B constitute the lower arm circuit in this switching circuit. As shown in FIG. 4, the semiconductor device A1 includes four first semiconductor elements 10A and four second semiconductor elements 10B. The number of the semiconductor elements 10 is not limited to this configuration and can be freely set according to the performance required for the semiconductor device A1.

[0037] As shown in FIGS. 2, 4, 5, and 10, each of the plurality of first semiconductor elements 10A is mounted on a support substrate 20 (conductive substrate 22A). In the present embodiment, the plurality of first semiconductor elements 10A are arranged side by side in the y direction and are spaced apart from each other. When each first semiconductor element 10A is mounted on the conductive substrate 22A, the back surface 102 of the element faces the conductive substrate 22A. Each first semiconductor element 10A is conductively joined to the support substrate 20 (conductive substrate 22A) through, for example, an element bonding material having conductivity (not shown). Examples of the element bonding material include solder, sintered silver, silver paste, and the like.

[0038] As shown in FIGS. 2, 4, 5, and 10, each of the plurality of second semiconductor elements 10B is mounted on a support substrate 20 (conductive substrate 22B). In the present embodiment, the plurality of second semiconductor elements 10B are arranged side by side in the y direction and are spaced apart from each other. When each second semiconductor element 10B is mounted on the conductive substrate 22B, the back surface 102 of the element faces the conductive substrate 22B. Each second semiconductor element 10B is conductively joined to the support substrate 20 (conductive substrate 22B) via, for example, an element bonding material (not shown) having conductivity. In the present embodiment, when viewed in the x direction, the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap. Alternatively, the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B may not overlap when viewed in the x direction.

[0039] The support substrate 20 is a support member that supports the plurality of semiconductor elements 10. The support substrate 20 includes an insulating substrate 21, two conductive substrates 22A and 22B, a pair of insulating layers 23A and 23B, a pair of gate layers 24A and 24B, a pair of driver source layers 25A and 25B, a first spacer 26A, and a second spacer 26B.

[0040] The insulating substrate 21 is a plate-like member having electrical insulation. The insulating substrate 21 supports the two conductive substrates 22A and 22B. In the present embodiment, the insulating substrate 21 is composed of two flat insulating substrates 21A and 21B. The configuration of the insulating substrate 21 is not limited to that described above. For example, it may not be divided into two insulating substrates 21A and 21B and may be a single flat plate. Each constituent material of the insulating substrates 21A and 21B is, for example, a ceramic having excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), Al 2 O 3 (aluminum oxide), and the like.

[0041] The insulating substrates 21A and 21B are each rectangular in plan view. The insulating substrate 21A supports the conductive substrate 22A, and the insulating substrate 21B supports the conductive substrate 22B. The insulating substrates 21A and 21B are spaced apart from each other. In the present embodiment, as shown in FIGS. 2, 4, and 10, the insulating substrate 21A and the insulating substrate 21B are spaced apart in the x direction and are arranged side by side.

[0042] As shown in FIG. 10, the insulating substrate 21A has a front surface 211A and a back surface 212A. The front surface 211A and the back surface 212A are spaced apart in the z direction and face opposite sides of each other. The front surface 211A faces the z2 direction, and the back surface 212A faces the z1 direction. The front surface 211A faces the conductive substrate 22A, and the back surface 212A is exposed from the encapsulating resin 70. Different from the illustrated example, another conductive substrate may be joined to the back surface 212A of the insulating substrate 21A. In this case, the back surface of the conductive substrate is exposed from the encapsulating resin 70.

[0043] As shown in FIG. 10, the insulating substrate 21B has a front surface 211B and a back surface 212B. The front surface 211B and the back surface 212B are spaced apart in the z direction and face opposite sides of each other. The front surface 211B faces the z2 direction, and the back surface 212B faces the z1 direction. The front surface 211B faces the conductive substrate 22B, and the back surface 212B is exposed from the encapsulating resin 70. Different from the illustrated example, another conductive substrate may be joined to the back surface 212B of the insulating substrate 21B. In this case, the back surface of the conductive substrate is exposed from the encapsulating resin 70.

[0044] The conductive substrates 22A and 22B are each plate-like members having conductivity. In the present embodiment, as shown in FIG. 10, each of the conductive substrates 22A and 22B is a composite substrate including a graphite substrate 220m and copper films 220n formed on both surfaces of the graphite substrate 220m in the z direction. The constituent materials of the conductive substrates 22A and 22B are not limited to this, and may be Cu or a Cu alloy. Each surface of the conductive substrates 22A and 22B may be covered with silver plating. The conductive substrates 22A and 22B, together with a plurality of leads (the first power lead 31, the second power lead 32, the third power lead 33, a pair of gate leads 34A and 34B, a pair of driver source leads 35A and 35B, and a plurality of dummy leads 36), constitute conduction paths to a plurality of semiconductor elements 10. The conductive substrates 22A and 22B are spaced apart from each other. As shown in FIGS. 4 and 10, the conductive substrate 22A and the conductive substrate 22B are spaced apart in the x direction and are arranged side by side. As shown in FIG. 4, the conductive substrates 22A and 22B are rectangular in plan view. The dimension of the conductive substrates 22A and 22B in the z direction is about 1.0 to 3.5 mm. In the present embodiment, the dimension of the graphite substrate 220m in the z direction is about 0.5 to 2.5 mm, and the dimension of each of the pair of copper films 220n in the z direction is about 0.25 to 0.5 mm. These dimensions in the z direction are not limited to those described above. The upper copper film 220n in the drawing of FIG. 10 of the conductive substrate 22A is an example of the "first metal layer", and the upper copper film 220n in the drawing of FIG. 10 of the conductive substrate 22B is an example of the "second metal layer". The upper copper film 220n in the drawing of FIG. 10 of the conductive substrate 22A and the upper copper film 220n in the drawing of FIG. 10 of the conductive substrate 22B are examples of the "conductive member". The material constituting the upper copper film 220n in the drawing of FIG. 10 of the conductive substrate 22A and the upper copper film 220n in the drawing of FIG. 10 of the conductive substrate 22B is an example of the "first material".

[0045] As shown in FIG. 10, the conductive substrate 22A is joined to the insulating substrate 21A via a substrate joining material 220A. The substrate joining material 220A may be a conductive joining material such as, for example, silver paste, solder, or sintered metal, or may be an insulating joining material. As shown in FIGS. 4 and 10, the conductive substrate 22A is positioned in the x1 direction with respect to the conductive substrate 22B. When viewed in the x direction, the entire conductive substrate 22A overlaps the conductive substrate 22B.

[0046] As shown in FIG. 10, the conductive substrate 22A has a front surface 221A and a back surface 222A. The front surface 221A and the back surface 222A are spaced apart in the z direction and face opposite sides. The front surface 221A faces the z2 direction, and the back surface 222A faces the z1 direction. A plurality of first semiconductor elements 10A are mounted on the front surface 221A. An insulating layer 23A is joined to the front surface 221A.

[0047] As shown in FIG. 10, the conductive substrate 22B is joined to the insulating substrate 21B via a substrate joining material 220B. The substrate joining material 220B may be a conductive joining material such as, for example, silver paste, solder, or sintered metal, or may be an insulating joining material.

[0048] As shown in FIG. 10, the conductive substrate 22B has a front surface 221B and a back surface 222B. The front surface 221B and the back surface 222B are spaced apart in the z direction and face opposite sides. The front surface 221B faces the z2 direction, and the back surface 222B faces the z1 direction. A plurality of second semiconductor elements 10B are mounted on the front surface 221B. One end of an insulating layer 23B and a plurality of intermediate leads 40 are respectively joined to the front surface 221B.

[0049] The pair of insulating layers 23A and 23B have electrical insulation properties, and their constituent materials are, for example, glass epoxy resin or ceramics. As shown in FIG. 4, the pair of insulating layers 23A and 23B are each strip-shaped and extend in the y direction. As shown in FIGS. 4 and 10, the insulating layer 23A is joined to the main surface 221A of the conductive substrate 22A. The insulating layer 23A is located in the x1 direction relative to the plurality of first semiconductor elements 10A. Alternatively, the insulating layer 23A may be arranged on the x2 direction side of the plurality of first semiconductor elements 10A. As shown in FIGS. 4 and 10, the insulating layer 23B is joined to the main surface 221B of the conductive substrate 22B. The insulating layer 23B is located in the x2 direction relative to the plurality of second semiconductor elements 10B. Alternatively, the insulating layer 23B may be arranged on the x1 direction side of the plurality of second semiconductor elements 10B.

[0050] The pair of gate layers 24A and 24B have conductivity, and their constituent materials are, for example, Cu or a Cu alloy. As shown in FIG. 4 and the like, the pair of gate layers 24A and 24B include a strip-shaped portion extending in the y direction and a hook-shaped portion protruding from this strip-shaped portion. The shape of the pair of gate layers 24A and 24B is not limited to that shown in FIG. 4. For example, it may be composed only of the strip-shaped portion without the hook-shaped portion. As shown in FIGS. 4 and 10, the gate layer 24A is arranged on the insulating layer 23A. The gate layer 24A is electrically connected to the gate electrode 112 of each first semiconductor element 10A via a wire member 50 (gate wire 51 described later). As shown in FIGS. 4 and 10, the gate layer 24B is arranged on the insulating layer 23B. The gate layer 24B is electrically connected to the gate electrode 112 of each second semiconductor element 10B via a wire member 50 (gate wire 51 described later).

[0051] The pair of driver source layers 25A and 25B are conductive, and their constituent materials are, for example, Cu or a Cu alloy. As shown in FIG. 4 and the like, the pair of driver source layers 25A and 25B includes a strip-shaped portion extending in the y direction and a hook-shaped portion protruding from this strip-shaped portion. The shape of the pair of driver source layers 25A and 25B is not limited to that shown in FIG. 4. For example, it may be composed only of the strip-shaped portion without the hook-shaped portion. As shown in FIGS. 4 and 10, the driver source layer 25A is disposed on the insulating layer 23A together with the gate layer 24A. In a plan view, the driver source layer 25A is located adjacent to the gate layer 24A and separated from the gate layer 24A on the insulating layer 23A. In the present embodiment, the driver source layer 25A is disposed closer to a plurality of first semiconductor elements 10A than the gate layer 24A in the x direction. Therefore, the driver source layer 25A is located on the x2 direction side of the gate layer 24A. The arrangement of the gate layer 24A and the driver source layer 25A in the x direction may be the opposite of the above. The driver source layer 25A is electrically connected to the driver source electrodes 113 of the respective first semiconductor elements 10A via wire members 50 (driver source wires 52). As shown in FIGS. 4 and 10, the driver source layer 25B is disposed on the insulating layer 23B together with the gate layer 24B. In a plan view, the driver source layer 25B is located adjacent to the gate layer 24B and separated from the gate layer 24B on the insulating layer 23B. In the present embodiment, the driver source layer 25B is disposed closer to a plurality of second semiconductor elements 10B than the gate layer 24B. Therefore, the driver source layer 25B is located on the x1 direction side of the gate layer 24B. The arrangement of the gate layer 24B and the driver source layer 25B in the x direction may be the opposite of the above. The driver source layer 25B is electrically connected to the driver source electrodes 113 of the respective second semiconductor elements 10B via wire members 50 (driver source wires 52).

[0052] The first spacer 26A and the second spacer 26B are conductive, and the constituent material thereof is, for example, Cu or a Cu alloy. The constituent material of each of the first spacer 26A and the second spacer 26B is not limited to those described above, and may be, for example, a composite material of CuMo (copper molybdenum), a composite material of CIC (Copper-Inver-Copper), or the like. The constituent materials of the first spacer 26A and the second spacer 26B may be made different from each other. The first spacer 26A and the second spacer 26B are an example of a "conductive member", and the material constituting the first spacer 26A and the second spacer 26B is an example of a "first material".

[0053] As shown in FIG. 10, the first spacer 26A is interposed between the conductive substrate 22A and the first power lead 31. As shown in FIG. 4, the first spacer 26A is rectangular in shape extending in the y direction in plan view. The first spacer 26A is conductively joined to the conductive substrate 22A. The first spacer 26A is located near the edge in the x1 direction of the conductive substrate 22A in plan view. The first spacer 26A is provided to position the first power lead 31 substantially at the same position as the second power lead 32 in the z direction. Alternatively, the first spacer 26A may be absent and the first power lead 31 may be directly joined to the conductive substrate 22A. The shape of the first spacer 26A is not particularly limited.

[0054] As shown in FIG. 10, the second spacer 26B is interposed between the conductive substrate 22B and the third power lead 33. As shown in FIG. 4, the second spacer 26B is rectangular in shape extending in the y direction in plan view. The second spacer 26B is conductively joined to the conductive substrate 22B. The second spacer 26B is located near the edge in the x2 direction of the conductive substrate 22B in plan view. The second spacer 26B is provided to position the third power lead 33 substantially at the same position as the second power lead 32 in the z direction. Alternatively, the second spacer 26B may be absent and the third power lead 33 may be directly joined to the conductive substrate 22B. The shape of the second spacer 26B is not particularly limited.

[0055] Each of the plurality of leads (the first power lead 31, the second power lead 32, the third power lead 33, the pair of gate leads 34A, 34B, the pair of driver source leads 35A, 35B, and the plurality of dummy leads 36) includes a portion located inside the encapsulating resin 70 and a portion located outside the encapsulating resin 70. That is, each lead includes a portion covered by the encapsulating resin 70 and a portion exposed from the encapsulating resin 70. Each lead is used when mounting the semiconductor device A1 on a circuit board such as an electronic device.

[0056] The first power lead 31 and the second power lead 32 are each a metal plate. The constituent material of the metal plate is Cu or a Cu alloy. The constituent materials of the first power lead 31 and the second power lead 32 are not limited to this, and may be, for example, aluminum. In the present embodiment, both the first power lead 31 and the second power lead 32 have a dimension in the z direction of about 0.8 mm, but the present disclosure is not limited to this. As shown in FIGS. 1 to 4 and 7, both the first power lead 31 and the second power lead 32 are located closer to the x1 direction in the semiconductor device A1. A power supply voltage is applied, for example, between the first power lead 31 and the second power lead 32. The first power lead 31 is the positive electrode (P terminal), and the second power lead 32 is the negative electrode (N terminal). The first power lead 31 and the second power lead 32 are spaced apart from each other. The second power lead 32 is spaced apart from the conductive substrate 22A. The first power lead 31 and the second power lead 32 are an example of a "conductive member", and the material constituting the first power lead 31 and the second power lead 32 is an example of a "first material".

[0057] As shown in FIG. 4, the first power lead 31 has a pad portion 311 and a terminal portion 312.

[0058] The pad portion 311 is the portion of the first power lead 31 covered by the encapsulating resin 70. The pad portion 311 is electrically connected to the conductive substrate 22A via the first spacer 26A. As shown in FIGS. 2, 4, and 10, the pad portion 311 is electrically joined to the first spacer 26A. The method of electrical joining is not limited in any way and may be, for example, laser joining, joining with an electrically conductive joining material, or the like.

[0059] The terminal portion 312 is the portion of the first power lead 31 exposed from the encapsulating resin 70. As shown in FIGS. 3, 4, 6, 7, and 10, the terminal portion 312 extends in the x1 direction from the encapsulating resin 70.

[0060] As shown in FIG. 4, the second power lead 32 has a pad portion 321 and a terminal portion 322.

[0061] The pad portion 321 is the portion of the second power lead 32 covered by the encapsulating resin 70. The pad portion 321 includes a connecting portion 321a, a plurality of extending portions 321b, and a connecting portion 321c.

[0062] The connecting portion 321a is strip-shaped and extends in the y direction. The connecting portion 321a connects the plurality of extending portions 321b.

[0063] The plurality of extending portions 321b are each strip-shaped and extend from the connecting portion 321a in the x2 direction. In the present embodiment, each extending portion 321b extends in the x direction from the connecting portion 321a until it overlaps each second semiconductor element 10B in a plan view. Each extending portion 321b extends across the conductive substrate 22A to the conductive substrate 22B in a plan view. The tip portion of each extending portion 321b overlaps the second block 62 in a plan view. The plurality of extending portions 321b are arranged side by side in the y direction and are spaced apart from each other in a plan view. Each extending portion 321b is electrically connected to the source electrode 111 (source electrode) of the second semiconductor element 10B via a plurality of conductive blocks 60. As shown in FIGS. 4 and 10, the tip portion of each extending portion 321b is conductively joined to the second block 62. The method of conductive joining is not limited at all, and may be, for example, laser joining, joining with a conductive joining material, or the like.

[0064] The connecting portion 321c is a portion that connects the connecting portion 321a and the terminal portion 322. In the present embodiment, as shown in FIG. 4, the connecting portion 321c extends in the x1 direction from the edge on the y2 direction side and the x1 direction side of the connecting portion 321a in a plan view.

[0065] The terminal portion 322 is a portion of the second power lead 32 that is exposed from the encapsulating resin 70. The terminal portion 322 extends in the x1 direction from the encapsulating resin 70 as shown in FIGS. 1, 3, 4, and 7. The terminal portion 322 has a rectangular shape in a plan view. The terminal portion 322 is located on the y2 direction side of the terminal portion 312 of the first power lead 31 in a plan view as shown in FIGS. 3, 4, and 7. In the present embodiment, the shape of the terminal portion 322 is the same as the shape of the terminal portion 312, but the present disclosure is not limited thereto.

[0066] The third power lead 33 is a metal plate. The constituent material of the metal plate is, for example, Cu or a Cu alloy. Note that the constituent material of the third power lead 33 is not limited to this, and for example, it may be aluminum. As shown in FIGS. 1 to 4, 6, 7, and 10, the third power lead 33 is located closer to the x2 direction in the semiconductor device A1. The AC power (voltage) power-converted by the plurality of semiconductor elements 10 is output from this third power lead 33.

[0067] As shown in FIGS. 4 and 10, the third power lead 33 includes a pad portion 331 and a terminal portion 332.

[0068] The pad portion 331 is the portion of the third power lead 33 covered by the encapsulating resin 70. The pad portion 331 is electrically connected to the conductive substrate 22B via the second spacer 26B. As shown in FIGS. 2, 4, and 10, the pad portion 331 is conductively joined to the second spacer 26B. The method of conductive joining is not limited at all, and for example, it may be laser joining, joining with a conductive joining material, etc.

[0069] The terminal portion 332 is the portion of the third power lead 33 exposed from the encapsulating resin 70. As shown in FIGS. 3, 4, 6, 7, and 10, the terminal portion 332 extends in the x2 direction from the encapsulating resin 70.

[0070] As shown in FIGS. 1 to 7, the pair of gate leads 34A and 34B are located adjacent to the respective conductive substrates 22A and 22B in the y direction. A gate voltage for driving the plurality of first semiconductor elements 10A is applied to the gate lead 34A. A gate voltage for driving the plurality of second semiconductor elements 10B is applied to the gate lead 34B.

[0071] The pair of gate leads 34A and 34B both have a pad portion 341 and a terminal portion 342 as shown in FIG. 5. In each of the gate leads 34A and 34B, the pad portion 341 is covered with the encapsulating resin 70. Each of the gate leads 34A and 34B is supported by the encapsulating resin 70. The terminal portion 342 is connected to the pad portion 341 and exposed from the encapsulating resin 70. The terminal portion 342 forms an L shape when viewed in the x direction. In the present embodiment, the terminal portion 342 protrudes from the surface facing the y1 direction of the encapsulating resin 70 (resin side surface 733).

[0072] As shown in FIGS. 1 to 7, the pair of driver source leads 35A and 35B are located adjacent to the pair of gate leads 34A and 34B in the x direction. The driver source lead 35A is a lead that serves as a reference potential for the gate voltage for driving the plurality of first semiconductor elements 10A. The driver source lead 35B is a lead that serves as a reference potential for the gate voltage for driving the plurality of second semiconductor elements 10B.

[0073] The pair of driver source leads 35A and 35B both have a pad portion 351 and a terminal portion 352 as shown in FIG. 5. In each of the driver source leads 35A and 35B, the pad portion 351 is covered with the encapsulating resin 70. Each of the driver source leads 35A and 35B is supported by the encapsulating resin 70. The terminal portion 352 is connected to the pad portion 351 and exposed from the encapsulating resin 70. The terminal portion 352 forms an L shape when viewed in the x direction. In the present embodiment, the terminal portion 352 protrudes from the surface facing the y1 direction of the encapsulating resin 70 (resin side surface 733).

[0074] As shown in FIGS. 1 to 7, the plurality of dummy leads 36 are located on the side opposite to the pair of driver source leads 35A and 35B with respect to the pair of gate leads 34A and 34B in the x direction. In this embodiment, the number of dummy leads 36 is four. Two of these dummy leads 36 are located on one side (x2 direction) in the x direction. The remaining two dummy leads 36 are located on the other side (x1 direction) in the x direction. The plurality of dummy leads 36 are not limited to the above-described configuration. A configuration without the plurality of dummy leads 36 may also be used.

[0075] As shown in FIG. 5, each of the plurality of dummy leads 36 has a pad portion 361 and a terminal portion 362. In each dummy lead 36, the pad portion 361 is covered with the encapsulating resin 70. The plurality of dummy leads 36 are supported by the encapsulating resin 70. The terminal portion 362 is connected to the pad portion 361 and exposed from the encapsulating resin 70. The terminal portion 362 has an L shape when viewed in the x direction. In this embodiment, the terminal portion 362 protrudes from the surface (resin side surface 733) facing the y1 direction of the encapsulating resin 70.

[0076] In this embodiment, each of the gate leads 34A and 34B, each of the driver source leads 35A and 35B, and each of the dummy leads 36 have substantially the same shape. And, as shown in FIGS. 1 to 7, they are arranged along the x direction. In the semiconductor device A1, each lead (the first power lead 31, the second power lead 32, the third power lead 33, the pair of gate leads 34A and 34B, the pair of driver source leads 35A and 35B, and the plurality of dummy leads 36) is formed from the same lead frame.

[0077] The plurality of intermediate leads 40 connect each first semiconductor element 10A and the conductive substrate 22B. The constituent material of each intermediate lead 40 is, for example, Cu or a Cu alloy. The constituent material of each intermediate lead 40 is not limited to this, and may be a clad material such as CIC, aluminum, or the like. Each intermediate lead 40 is a flat plate-shaped connecting member. As shown in FIG. 4, each intermediate lead 40 is rectangular in shape extending in the x direction in a plan view. Each intermediate lead 40 overlaps each extending portion 321b of the second power lead 32 in a plan view. The intermediate lead 40 is an example of a "conductive member", and the material constituting the intermediate lead 40 is an example of a "first material".

[0078] As shown in FIG. 10, each intermediate lead 40 includes a first joint portion 41, a second joint portion 42, and a connecting portion 43.

[0079] As shown in FIG. 10, the first joint portion 41 is a portion joined to the first block 61. In the present embodiment, the first joint portion 41 and the first block 61 are conductively joined. The method of conductive joining is not particularly limited, and may be, for example, laser joining, joining with a conductive joining material, or the like.

[0080] As shown in FIG. 10, the second joint portion 42 is a portion joined to the conductive substrate 22B. In the present embodiment, the second joint portion 42 and the conductive substrate 22B are conductively joined. The method of conductive joining is not particularly limited, and may be, for example, laser joining, joining with a conductive joining material, or the like.

[0081] The connecting portion 43 is a portion connecting the first joint portion 41 and the second joint portion 42. The dimension of the connecting portion 43 in the z direction is the same as that of the first joint portion 41 and the second joint portion 42. In the present embodiment, a part of the connecting portion 43 is bent in the z direction. By the connecting portion 43 being bent, the first joint portion 41 and the second joint portion 42 having different positions in the z direction are connected.

[0082] Each of the plurality of wire members 50 is a wire (bonding wire). Each wire member 50 has conductivity, and its constituent material is, for example, any one of aluminum, gold, and Cu. In the present embodiment, as shown in FIGS. 4 and 5, the plurality of wire members 50 includes a plurality of gate wires 51, a plurality of driver source wires 52, a pair of first connection wires 53, and a pair of second connection wires 54.

[0083] As shown in FIG. 5, one end (first end) of each of the plurality of gate wires 51 is joined to the gate electrode 112 of each semiconductor element 10, and the other end (second end) is joined to either one of the pair of gate layers 24A and 24B. Among the plurality of gate wires 51, there are those that conduct between the gate electrode 112 of each first semiconductor element 10A and the gate layer 24A, and those that conduct between the gate electrode 112 of each second semiconductor element 10B and the gate layer 24B.

[0084] As shown in FIG. 5, one end of each of the plurality of driver source wires 52 is joined to the driver source electrode 113 of each semiconductor element 10, and the other end is joined to either one of the pair of driver source layers 25A and 25B. Among the plurality of driver source wires 52, there are those that conduct between the driver source electrode 113 of each first semiconductor element 10A and the driver source layer 25A, and those that conduct between the driver source electrode 113 of each second semiconductor element 10B and the driver source layer 25B.

[0085] As shown in FIG. 5, one of the pair of first connection wires 53 connects the gate layer 24A and the gate lead 34A, and the other connects the gate layer 24B and the gate lead 34B. One of the first connection wires 53 has one end joined to the gate layer 24A and the other end joined to the pad portion 341 of the gate lead 34A. The other first connection wire 53 has one end joined to the gate layer 24B and the other end joined to the pad portion 341 of the gate lead 34B.

[0086] As shown in FIG. 5, one of a pair of second connection wires 54 connects the driver source layer 25A and the driver source lead 35A, and the other connects the driver source layer 25B and the driver source lead 35B. One of the second connection wires 54 has one end joined to the driver source layer 25A and the other end joined to the pad portion 351 of the driver source lead 35A. The other second connection wire 54 has one end joined to the driver source layer 25B and the other end joined to the pad portion 351 of the driver source lead 35B.

[0087] The plurality of conductive blocks 60 have conductivity. Each of the plurality of conductive blocks 60 is joined on a corresponding one of the semiconductor elements 10. Each conductive block 60 has a z-direction dimension of about 0.1 to 2.0 mm, but the present disclosure is not limited thereto. The plurality of conductive blocks 60 include a plurality of first blocks 61 and a plurality of second blocks 62.

[0088] Each of the plurality of first blocks 61 is joined one by one on any one of the plurality of first semiconductor elements 10A. Each first block 61 is conductively joined to each first semiconductor element 10A by solder or the like. Each first block 61 faces the element main surface 101 of each first semiconductor element 10A. In the present embodiment, as shown in FIG. 4, each first block 61 is a columnar body and has a rectangular shape in plan view. The plan-view shape of each first block 61 is not limited thereto, and may be circular, elliptical, or polygonal. The first block 61 is made of, for example, Cu or a Cu alloy.

[0089] A plurality of second blocks 62 are each joined one by one on any one of a plurality of second semiconductor elements 10B. Each second block 62 is conductively joined to each second semiconductor element 10B by solder or the like. Each second block 62 faces the element main surface 101 of each second semiconductor element 10B. The z-direction dimension of each second block 62 is not particularly limited, but in this embodiment, it is about 1.83 mm, for example. In this embodiment, each second block 62 is a columnar body and has a rectangular shape in plan view, as shown in FIGS. 4 and 10. The shape of each second block 62 in plan view is not limited to this, and may be circular, elliptical, or polygonal. The second block 62 is made of, for example, Cu or a Cu alloy.

[0090] The z-direction dimension of each first block 61 is smaller than the z-direction dimension of each second block 62. In this embodiment, since the z-direction dimension of each second block 62 is about 1.83 mm as described above, the z-direction dimension of each first block 61 is smaller than this value. Thereby, each extension portion 321b of the second power lead 32 can be disposed above each intermediate lead 40.

[0091] The capacitor 81 is of a chip type having a first end and a second end. The first end is placed on the pad portion 311 of the first power lead 31, and the second end is placed on the connection portion 321a of the second power lead 32. The joining of the capacitor 81 to each of the power leads 31 and 32 can be performed by, for example, a conductive joining material. By electrically connecting the capacitor 81 between the first power lead 31 and the second power lead 32, it is possible to stabilize the power supply voltage (input voltage) applied between the first power lead 31 and the second power lead 32. The capacitor 81 may be referred to as a DC link capacitor. Different from this embodiment, a configuration without the capacitor 81 may also be possible.

[0092] As shown in FIGS. 4 and 10, the encapsulating resin 70 covers a plurality of semiconductor elements 10, a part of the support substrate 20, and parts of a plurality of leads (the first power lead 31, the second power lead 32, the third power lead 33, a pair of gate leads 34A, 34B, a pair of driver source leads 35A, 35B, and a plurality of dummy leads 36), a plurality of intermediate leads 40, a plurality of wire members 50, and a plurality of conductive blocks 60. The constituent material of the encapsulating resin 70 is, for example, an epoxy resin. As shown in FIGS. 1, 3, and 6 to 10, the encapsulating resin 70 has a resin front surface 71, a resin back surface 72, and a plurality of resin side surfaces 731 to 734.

[0093] As shown in FIGS. 6 and 8 to 10, the resin front surface 71 and the resin back surface 72 are spaced apart in the z direction and face opposite sides. The resin front surface 71 faces the z2 direction, and the resin back surface 72 faces the z1 direction. As shown in FIG. 7, the resin back surface 72 is in a frame shape surrounding the back surface 212A of the insulating substrate 21A and the back surface 212B of the insulating substrate 21B in a plan view. Each of the back surfaces 212A, 212B is exposed from the resin back surface 72. As shown in FIGS. 3 and 6 to 10, each of the plurality of resin side surfaces 731 to 734 is connected to both the resin front surface 71 and the resin back surface 72 and is sandwiched between them in the z direction. In the present embodiment, the resin side surfaces 731, 732 are spaced apart in the x direction and face opposite sides. The resin side surface 731 faces the x1 direction, and the resin side surface 732 faces the x2 direction. The resin side surfaces 733, 734 are spaced apart in the y direction and face opposite sides. The resin side surface 733 faces the y1 direction, and the resin side surface 734 faces the y2 direction.

[0094] The coating layer 90 is a layer that covers at least a part of the "conductive member" and is made of a second material. This second material satisfies at least one of the following three requirements: (1) It has a higher magnetic permeability than the first material that constitutes the "conductive member". (2) It has a higher electrical resistivity than the first material. (3) Its dielectric tangent is greater than 0 (greater than that of an ideal dielectric). Regarding these, for example, assume that the first material is Cu. In this case, examples of the second material with a higher magnetic permeability than the first material include magnetic metals such as Ni, Co, and Fe. Examples of the second material with a higher electrical resistivity than the first material include metals such as Ni, W, and Mo, conductive polymers, and transparent conductive films. Examples of the second material with a dielectric tangent greater than 0 include dielectrics. Also, when making the magnetic permeability of the second material higher than that of the first material, the relative magnetic permeability of the second material is preferably, for example, 10 or more. When making the electrical resistivity of the second material higher than that of the first material, the electrical resistivity of the second material is preferably, for example, twice or more that of the first material. Regarding the above requirement (3), the dielectric tangent of the second material is preferably 0.01 or more. The thickness of the coating layer 90 is not particularly limited and is, for example, 1 μm to 5 μm. When the coating layer 90 is made of a metal, the coating layer 90 is formed, for example, by plating such as magnetic body plating.

[0095] The coating layer 90 may be a magnetic metal in which the magnetic permeability of the second material is higher than that of the first material and the electrical resistivity of the second material is higher than that of the first material. The coating layer 90 may have a configuration in which the magnetic permeability of the second material is higher than that of the first material and the dielectric tangent of the second material is greater than 0. The coating layer 90 may have a configuration in which the electrical resistivity of the second material is higher than that of the first material and the dielectric tangent of the second material is greater than 0. The coating layer 90 may have a configuration in which the magnetic permeability of the second material is higher than that of the first material, the electrical resistivity of the second material is higher than that of the first material, and the dielectric tangent of the second material is greater than 0.

[0096] As shown in FIGS. 1 to 11, in the present embodiment, the coating layer 90 has a first portion 91 and a second portion 92. The first portion 91 covers at least a part of the first power lead 31. In the present embodiment, the first portion 91 covers all of the first power lead 31. As shown in FIG. 11, when the first power lead 31 functions as a path of the main circuit current, the entire circumference of the cross section of the first power lead 31 is covered by the first portion 91. The second portion 92 covers at least a part of the second power lead 32. In the present embodiment, the second portion 92 covers all of the second power lead 32. Similar to the first portion 91, when the second power lead 32 functions as a path of the main circuit current, the entire circumference of the cross section of the second power lead 32 is covered by the second portion 92.

[0097] Next, the operation and effect of the semiconductor device A1 described above will be described.

[0098] Generally, when an alternating current flows through a conductor, the current density becomes higher near the surface of the conductor (this is called the skin effect). The skin effect becomes more prominent as the frequency of the alternating current is higher. In the present embodiment, a coating layer 90 is provided on the conductive member that forms the path of the main circuit current in the semiconductor device A1. More specifically, the coating layer 90 is provided at a portion where the density of the alternating current becomes high due to the skin effect. When the magnetic permeability of the second material constituting the coating layer 90 is higher than the magnetic permeability of the first material (such as Cu) constituting the conductive member (the first power lead 31, the second power lead 32, etc.), the influence of the skin effect becomes more prominent, and the alternating current resistance of the current path becomes high. Thereby, it is possible to attenuate the alternating current flowing through the coating layer 90 and suppress ringing. On the other hand, regarding the low-frequency component of the current, the skin effect is relatively unlikely to occur. Therefore, the low-frequency component of the current is not unduly attenuated by the coating layer 90. Further, since ringing can be suppressed, the snubber circuit provided in the semiconductor device A1 can be simplified, and the reliability of the semiconductor device A1 itself can be improved.

[0099] Also, even when the electrical resistivity of the second material constituting the coating layer 90 is higher than the electrical resistivity of the first material (such as Cu) constituting the conduction members (such as the first power lead 31 and the second power lead 32), it is possible to attenuate the alternating current flowing through the coating layer 90 and suppress ringing. As described above, the low-frequency component of the current is not unduly attenuated by the coating layer 90.

[0100] Also, even when the dielectric loss tangent of the second material constituting the coating layer 90 is greater than 0 (greater than the dielectric loss tangent of an ideal dielectric), it is possible to consume the energy of the alternating current flowing through the coating layer 90 as dielectric loss and suppress ringing.

[0101] The respective effects obtained by the requirements regarding the magnetic permeability, electrical resistivity, and dielectric loss tangent of the second material described above can be exerted independently of each other. For this reason, not only a configuration in which only any one of the requirements regarding the magnetic permeability, electrical resistivity, and dielectric loss tangent of the second material is satisfied, but also a configuration in which any two of them are satisfied, and further a configuration in which all three are satisfied can more effectively suppress ringing.

[0102] Figs. 12 to 21 show modified examples and other embodiments according to the present disclosure. In these figures, the same or similar elements as those in the above-described embodiment are denoted by the same reference numerals.

[0103] Fig. 12 shows a first modified example of the semiconductor device A1. In the semiconductor device A11 of this modified example, the configuration of the coating layer 90 is different from the example described above. Taking the first part 91, which is a part of the coating layer 90, as an example, in this modified example, in the cross-section through which the main circuit current flows, the first part 91 does not cover the entire circumference of the cross-section of the first power lead 31, but only covers a part thereof. More specifically, the first part 91 covers only three sides (the upper side and two side sides) of the rectangular cross-section of the first power lead 31, and does not cover the remaining one side (the bottom side) (that is, the bottom side is exposed from the first part 91). Note that each of the above three sides (the upper side and two side sides) is completely covered by the first part 91.

[0104] FIG. 13 shows a second modification of the semiconductor device A1. Taking the first part 91 which is a part of the coating layer 90 as an example, in this modification, in the cross-section through which the main circuit current flows, the first part 91 is formed over the entire circumference of the cross-section of the first power lead 31, but any side (the upper side, the two side edges, and the bottom edge) is partially exposed from the first part 91 (in other words, is partially covered by the first part 91). In the example shown in the figure, the first part 91 has a plurality of voids spaced apart from each other along the entire circumference of the rectangular cross-section. Also, the plurality of voids includes one or more voids corresponding to each side of the cross-section. Such a first part 91 (coating layer 90) can be configured, for example, to have a plurality of small holes or slits formed therein. Alternatively, the first part 91 (coating layer 90) can be configured as an aggregate of a plurality of small regions spaced apart from each other.

[0105] The semiconductor devices A11 and A12 can also suppress ringing. As can be understood from these modifications, the specific configuration of the coating layer 90 is not particularly limited. Even when the coating layer 90 is configured to cover a part of the conductive member (FIGS. 12 and 13), an effect of suppressing ringing can be expected depending on the position, size, etc. of the region where the coating layer 90 is provided.

[0106] FIGS. 14 to 16 show a semiconductor device according to the second embodiment of the present disclosure. In the semiconductor device A2 of the present embodiment, the configuration of the coating layer 90 is different from that of the coating layer 90 of the semiconductor device A1 described above.

[0107] In the second embodiment, the first part 91 covers a part of the first power lead 31, and the second part 92 covers a part of the second power lead 32. More specifically, the first part 91 does not cover the part of the first power lead 31 that constitutes the path between the first semiconductor element 10A and the capacitor 81. That is, the first part 91 covers the terminal part 312 of the first power lead 31 while not covering the pad part 311.

[0108] Further, the second portion 92 does not cover the portion of the second power lead 32 that constitutes the path between the second semiconductor element 10B and the capacitor 81. That is, the second portion 92 covers the terminal portion 322 of the second power lead 32 and the connection portion 321c of the pad portion 321, but does not cover the connection portion 321a and the plurality of extension portions 321b.

[0109] Also according to the second embodiment, ringing can be suppressed. Among the first power lead 31 and the second power lead 32, the portion that constitutes the path through which only the charging and discharging current of the capacitor 81 flows has a resistance equivalent to the ESR of the capacitor 81. That is, since this path is a path through which a steep charging and discharging current flows to the capacitor 81, it is not preferable that the AC resistance is too high. In this regard, as described above, it is preferable that the first portion 91 and the second portion 92 do not cover a part of the first power lead 31 and the second power lead 32, respectively, for performing a steep charge and discharge to the capacitor 81.

[0110] FIGS. 17 to 19 show a semiconductor device according to the third embodiment of the present disclosure. In the semiconductor device A3 of the present embodiment, the configuration of the coating layer 90 is different from the coating layer 90 of the semiconductor devices A1 and A2 described above.

[0111] In the third embodiment, the coating layer 90 includes a first portion 91, a second portion 92, a third portion 93, a fourth portion 94, a fifth portion 95, and a sixth portion 96. The first portion 91 and the second portion 92 have the same configuration as the first portion 91 and the second portion 92 in the semiconductor device A1.

[0112] The third portion 93 covers the copper film 220n of the conductive substrate 22A as the first metal layer. The fourth portion 94 covers the first spacer 26A. The fifth portion 95 covers the copper film 220n of the conductive substrate 22B as the second metal layer. The sixth portion 96 covers the plurality of intermediate leads 40. In the illustrated example, the third portion 93 covers the portion of the copper film 220n excluding the joint surface with the graphite substrate 220m. The fifth portion 95 covers the portion of the copper film 220n excluding the joint surface with the graphite substrate 220m.

[0113] Also according to the third embodiment, ringing can be suppressed. Further, as understood from this embodiment, the coating layer 90 can change the location where it is appropriately provided according to the required degree of ringing suppression and the configuration of the semiconductor device.

[0114] FIGS. 20 and 21 show a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A4 of this embodiment, the configurations of the first power lead 31 and the second power lead 32 are different from those of the above-described embodiments.

[0115] In the fourth embodiment, the terminal portion 312 of the first power lead 31 and the terminal portion 322 of the second power lead 32 overlap each other when viewed along the z direction. The terminal portion 312 is covered by the first portion 91, and the terminal portion 322 is covered by the second portion 92. An insulator 89 is provided between the terminal portion 312 and the terminal portion 322. The insulator 89 is for insulating each other when an assumed voltage is applied between the terminal portion 312 and the terminal portion 322.

[0116] In the fourth embodiment, the second material constituting the coating layer 90 is made of at least a material having a dielectric loss tangent greater than 0 (greater than the dielectric loss tangent of an ideal dielectric), for example, the dielectric loss tangent is 0.01 or more. When the coating layer 90 having such a configuration is adopted, a site having a capacitance, that is, a site having an electrical configuration similar to a capacitor is realized by the terminal portion 312, the terminal portion 322, the coating layer 90 interposed therebetween, and the insulator 89.

[0117] Also according to the fourth embodiment, ringing can be suppressed. Further, the capacitance formed by the terminal portion 312, the terminal portion 322, the coating layer 90 interposed therebetween, and the insulator 89 is expected to exhibit a synergistic effect with the capacitor 81, and the stabilization effect of the power supply voltage (input voltage) applied between the first power lead 31 and the second power lead 32 can be further enhanced.

[0118] The semiconductor device according to the present disclosure is not limited to the above-described embodiments and modifications. The specific configuration of each part of the semiconductor device of the present disclosure can be freely designed in various ways.

[0119] The semiconductor device according to the present disclosure includes the embodiments described in the following supplementary notes. Supplementary Note 1. At least one semiconductor element having a switching function, A conductive member made of a first material that forms a path for the current switched by the semiconductor element, A coating layer made of a second material that covers at least a part of the conductive member, and The second material satisfies at least one of the following three requirements: (a) It has a higher magnetic permeability than the first material, (b) It has a higher electrical resistivity than the first material, and (c) Its dielectric loss tangent is greater than 0. A semiconductor device. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the second material is a magnetically conductive material having a higher magnetic permeability than the first material and a higher electrical resistivity than the first material. Supplementary Note 3. The semiconductor device according to Supplementary Note 2, wherein the second material has a dielectric loss tangent greater than 0. Supplementary Note 4. The semiconductor device according to Supplementary Note 1, wherein the second material has a higher magnetic permeability than the first material and a dielectric loss tangent greater than 0. Supplementary Note 5. The semiconductor device according to Supplementary Note 1, wherein the second material has a higher electrical resistivity than the first material and a dielectric loss tangent greater than 0. Supplementary Note 6. The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the thickness of the coating layer is 1 μm to 5 μm. Supplementary Note 7. The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the relative magnetic permeability of the second material is 10 or more. Supplementary Note 8. The semiconductor device according to any one of Appendices 1 to 7, wherein the resistivity of the second material is two times or more that of the first material. Appendix 9. The semiconductor device according to any one of Appendices 1 to 8, wherein the dielectric loss tangent of the second material is 0.01 or more. Appendix 10. The semiconductor device further includes a capacitor having a first end and a second end for electrical connection, The at least one semiconductor element is a plurality of semiconductor elements that constitute a half bridge including at least one set of upper and lower arms, The plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm, The conduction member includes a first metal layer connected to the drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to the source electrode of the second semiconductor element, The first end of the capacitor is connected to the first power lead, and the second end of the capacitor is connected to the second power lead, The semiconductor device according to any one of Appendices 1 to 9, wherein the coating layer includes a first portion covering the first power lead and a second portion covering the second power lead. Appendix 11. The semiconductor device according to Appendix 10, wherein the first power lead includes a portion that constitutes a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered by the first portion. Appendix 12. The semiconductor device according to Appendix 10 or 11, wherein the second power lead includes a portion that constitutes a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered by the second portion. Appendix 13. The semiconductor device according to any one of Appendices 10 to 12, wherein the coating layer includes a third portion covering the first metal layer. Appendix 14. The conduction member includes a second metal layer connected to the drain electrode of the second semiconductor element and a third power lead connected to the second metal layer. The second metal layer and the third power lead are not covered by the coating layer, and the semiconductor device according to any one of Appendices 10 to 13. Appendix 15. The conduction member includes an intermediate lead connected to the source electrode of the first semiconductor element and the second metal layer, and the intermediate lead is not covered by the coating layer, and the semiconductor device according to Appendix 14. Appendix 16. The conduction member includes a first spacer interposed between the first metal layer and the first power lead. The coating layer includes a fourth portion covering the first spacer, and the semiconductor device according to any one of Appendices 10 to 15. Appendix 17. The conduction member includes a conductor interposed between the source electrode of the second semiconductor element and the second power lead, and the semiconductor device according to any one of Appendices 10 to 16. Appendix 18. The semiconductor element is any one of SiC MOSET, SiC IGBT, Si MOSFET, Si IGBT, and GaN HEMT, and the semiconductor device according to any one of Appendices 1 to 17.

Explanation of Signs

[0120] A1, A11, A12, A2, A3, A4: Semiconductor device 10: Semiconductor element 10A: First semiconductor element 10B: Second semiconductor element 11: Main surface electrode 12: Drain electrode (back surface electrode) 13: Insulating film 20: Support substrate 21, 21A, 21B: Insulating substrate 22A, 22B: Conductive substrate 23A, 23B: Insulating layer 24A, 24B: Gate layer 25A, 25B: Driver source layer 26A: First spacer 31: First power lead 32: Second power lead 33: Third power lead 34A, 34B: Gate lead 35A, 35B: Driver source lead 36: Dummy lead 40: Intermediate lead 41: First joint 42: Second joint 43: Connection part 50: Wire member 51: Gate wire 52: Driver source wire 53: First connection wire 54: Second connection wire 60: Conductive block 61: First block 62: Second block 70: Encapsulating resin 71: Main resin surface 72: Back resin surface 81: Capacitor 89: Insulator 90: Coating layer 91: First part 92: Second part 93: Third part 94: Fourth part 95: Fifth part 96: Sixth part 101: Main element surface 102: Back element surface 111: Source electrode 112: Gate electrode 113: Driver source electrode 211A, 211B: Main surface 212A, 212B: Back surface 220A, 220B: Substrate bonding material 220m: Graphite substrate 220n: Copper film 221A, 221B: Main surface 222A, 222B: Back side 260A: Spacer bonding material 260B: Spacer bonding material 311, 321, 331, 341, 351, 361: Pad portion 312, 322, 332, 342, 352, 362: Terminal portion 321a: Connecting portion 321b: Extending portion 321c: Connection portion 731, 732, 733, 734: Resin side surface

Claims

1. At least one semiconductor element having a switching function; a conductive member that serves as a path for a current switched by the semiconductor element and is made of a first material; a covering layer covering at least a portion of the conductive member and made of a second material; Equipped with The second material has the following three requirements: (a) having a higher magnetic permeability than the first material; (b) a higher electrical resistivity than the first material; and (c) a dielectric tangent greater than 0; A semiconductor device that satisfies at least one of the requirements.

2. 2. The semiconductor device according to claim 1, wherein the second material is a magnetic conductor having a higher magnetic permeability than the first material and a higher electrical resistivity than the first material.

3. The semiconductor device according to claim 2 , wherein the second material has a dielectric loss tangent greater than zero.

4. The semiconductor device according to claim 1 , wherein the second material has a higher magnetic permeability and a dielectric loss tangent greater than 0 than the first material.

5. The semiconductor device according to claim 1 , wherein the second material has a higher electrical resistivity and a dielectric loss tangent greater than 0 than the first material.

6. 6. The semiconductor device according to claim 1, wherein the coating layer has a thickness of 1 μm to 5 μm.

7. 7. The semiconductor device according to claim 1, wherein the second material has a relative magnetic permeability of 10 or more.

8. 8. The semiconductor device according to claim 1, wherein the electrical resistivity of the second material is at least twice as high as the electrical resistivity of the first material.

9. 9. The semiconductor device according to claim 1, wherein the second material has a dielectric loss tangent of 0.01 or more.

10. a capacitor having a first end and a second end for electrical connection; the at least one semiconductor element is a plurality of semiconductor elements constituting a half bridge including at least one pair of upper and lower arms, the plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm, the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element, the first end of the capacitor is connected to the first power lead and the second end of the capacitor is connected to the second power lead; 10. The semiconductor device according to claim 1, wherein said covering layer includes a first portion covering said first power lead and a second portion covering said second power lead.

11. 11. The semiconductor device according to claim 10, wherein the first power lead includes a portion that constitutes a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered by the first portion.

12. 12. The semiconductor device according to claim 10, wherein the second power lead includes a portion that constitutes a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered by the second portion.

13. The semiconductor device according to claim 10 , wherein the covering layer includes a third portion covering the first metal layer.

14. the conductive member includes a second metal layer connected to a drain electrode of the second semiconductor element and a third power lead connected to the second metal layer; 14. The semiconductor device according to claim 10, wherein said second metal layer and said third power lead are not covered by said covering layer.

15. 15 . The semiconductor device according to claim 14 , wherein the conductive member includes an intermediate lead connected to a source electrode of the first semiconductor element and the second metal layer, the intermediate lead being not covered by the covering layer.

16. the conductive member includes a first spacer interposed between the first metal layer and the first power lead; The semiconductor device according to claim 10 , wherein the covering layer includes a fourth portion covering the first spacer.

17. 17. The semiconductor device according to claim 10, wherein the conductive member includes a conductor interposed between a source electrode of the second semiconductor element and the second power lead.

18. 18. The semiconductor device according to claim 1, wherein the semiconductor element is any one of a SiC MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT, and a GaN HEMT.

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