Semiconductor device and method for manufacturing the same

Abstract

To prevent electric field concentration at a shoulder of a trench in a gate pull-up portion in a silicon carbide semiconductor device.SOLUTION: A semiconductor device (100) includes a gate pull-up portion (103) which is a region where a portion of a gate wiring (10) is pulled up from a trench (8) to the upper surface of a semiconductor substrate (1). The sidewall of the trench (8) of the gate pull-up portion (103) includes a vertical portion (8a) perpendicular to the upper surface of the semiconductor substrate (1), a horizontal portion (8a) parallel to the upper surface of the semiconductor substrate (1), and an inclined portion (8b) provided between the vertical portion (8a) and the horizontal portion (8a). The inclined portion (8b) is inclined such that the width of the trench (8) increases upward, and is linear in cross-sectional view. In cross-sectional view, the corner formed by the vertical portion (8a) and the inclined portion (8b) does not protrude into the inside of the trench (8) from a region sandwiched between a tangent (L1) of the vertical portion (8a) and a tangent (L2) of the inclined portion (8b).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] In a semiconductor device having a trench-gate semiconductor element, a "gate pull-up portion" is provided, which is a region for pulling up a part of the gate wiring above the substrate in order to electrically connect the gate wiring embedded in the trench to the gate pad. In the gate pull-up portion, it is desirable to make the shape of the upper end of the trench, i.e., the corner between the surface of the substrate and the side of the trench, gentle in order to prevent dielectric breakdown of the gate insulating film. Hereinafter, the upper end of the trench is referred to as the "trench shoulder."

[0003] For example, Patent Document 1 below discloses a technique for rounding the shoulder of a trench in which the gate wiring of a trench-gate MOSFET is embedded to suppress a decrease in gate breakdown voltage and an increase in channel resistance. Patent Document 2 below discloses a technique for combining multiple etching processes to give a slope only to the shoulder of a trench. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-164865 A [Patent Document 2] JP 2016-048747 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology of Patent Document 1, a thermal process is used to make the shoulder of the trench round. This causes problems such as a longer tact time for manufacturing the semiconductor device, and a current leak in the channel part due to diffusion and rearrangement of atoms on the trench sidewall, which changes the channel region to n-type or i-type. In particular, when an impurity layer is formed on the trench sidewall, problems occur such as uneven loss of the impurities implanted on the trench sidewall, and local accelerated oxidation occurs in the part of the trench sidewall where the impurities are implanted, making it difficult to obtain a uniform slope on the trench sidewall, which tends to make the characteristics of the semiconductor device unstable.

[0006] On the other hand, in the technology of Patent Document 2, since only the shape of the shoulder of the trench is processed, the characteristics of the semiconductor device tend to be stable even when an impurity layer is formed on the side wall of the trench. However, when the sloped portion is formed on the shoulder of the trench by the dry etching process, the corner formed by the sloped portion and the vertical portion of the trench protrudes into the inside of the trench, and the reliability of the gate insulating film decreases at the protruding portion.

[0007] In particular, in a silicon carbide (SiC) semiconductor device, if the corner formed by the inclined and vertical portions of the trench in the gate pull-up portion protrudes, when a voltage is generated between the semiconductor substrate and the gate wiring, a high voltage is applied to the gate of the semiconductor element, causing an electric field to concentrate at the corner and destroying the gate oxide film; or, when a negative bias is applied to the gate while a voltage is applied between the drain and source to expand the depletion layer, an electric field concentrates at the corner and destroys the gate oxide film. This destruction mode is unique to SiC semiconductor devices, and has been confirmed by the inventors of the technology disclosed herein.

[0008] The present disclosure has been made to solve the above-mentioned problems, and has an object to prevent electric field concentration at the shoulder of the trench in the gate pull-up portion in a trench-gate type silicon carbide semiconductor device. [Means for solving the problem]

[0009] A semiconductor device according to the present disclosure comprises a semiconductor substrate made of silicon carbide, a trench formed on an upper surface of the semiconductor substrate, a gate insulating film formed on an inner surface of the trench, a gate wiring formed on the gate insulating film and embedded in the trench, and a gate pull-up portion which is a region where a part of the gate wiring is pulled up from the trench to the upper surface of the semiconductor substrate, wherein a sidewall of the trench in the gate pull-up portion comprises a vertical portion perpendicular to the upper surface of the semiconductor substrate, a horizontal portion located at an upper portion of the trench and parallel to the upper surface of the semiconductor substrate, and an inclined portion located at a shoulder of the trench and provided between the vertical portion and the horizontal portion, wherein the inclined portion is inclined such that a width of the trench widens upward and is linear in a cross-sectional view, and wherein a corner formed by the vertical portion and the inclined portion does not protrude into the inside of the trench from a region sandwiched between a tangent to the vertical portion and a tangent to the inclined portion in the cross-sectional view. Effect of the Invention

[0010] According to the present disclosure, electric field concentration at the shoulder of the trench in the gate pull-up portion is suppressed, thereby preventing breakdown of the gate oxide film and improving the reliability of the semiconductor device. [Brief description of the drawings]

[0011] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Diagram 3] 3 is an enlarged view of a shoulder portion of a trench in the semiconductor device according to the first embodiment. FIG. [Figure 4] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Diagram 5] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 6] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 7] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 8]1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 9] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 10] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 11] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 12] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 13] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 14] 1 is a manufacturing process diagram of the semiconductor device according to the first embodiment; [Figure 15] FIG. 13 is a diagram showing the relationship between the amount of wet etching in a hard mask reduction step, the amount of dry etching in a first etching step, and the shape of a trench shoulder portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In the following embodiments, the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. The impurity concentration of each region is determined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0013] <Embodiment 1> Fig. 1 is a plan view showing a configuration of a semiconductor device 100 according to a first embodiment. Fig. 2 is a cross-sectional view of a main part of the semiconductor device 100. Here, the semiconductor element included in the semiconductor device 100 will be described as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the semiconductor element may be any type of trench gate type semiconductor element, such as an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting IGBT).

[0014] As shown in FIG. 1, a semiconductor device 100 includes a cell section 101, a gate lead-out section 102, and a gate pull-up section 103. The cell section 101 is a cell region.

[0015] The cell section 101 is a region where the cells of a semiconductor element (MOSFET) are formed.

[0016] The gate routing section 102 is a region where a gate routing line made of, for example, aluminum is arranged to connect the gate pad and the gate wiring of the semiconductor element. Therefore, the gate routing section 102 includes a gate pad region 102a where the gate pad is arranged.

[0017] The gate pull-up portion 103 is a region for pulling up a part of the gate wiring onto the semiconductor substrate in order to connect the gate wiring of the semiconductor element to the gate lead-out wiring. Therefore, the gate pull-up portion 103 is provided at the boundary between the cell portion 101 and the gate lead-out portion 102.

[0018] FIG. 2 is a cross-sectional view of the cell portion 101 and the gate pull-up portion 103 of the semiconductor device 100 according to the first embodiment.

[0019] The semiconductor device 100 is formed using an N-type semiconductor substrate 1 made of a silicon carbide semiconductor. In the cell section 101, a P-type channel doped layer 2 is formed in a surface layer of the semiconductor substrate 1. In addition, an N-type source layer 3 and a P-type contact layer 4 having a higher impurity concentration than the channel doped layer 2 are selectively formed in a surface layer of the channel doped layer 2.

[0020] A trench 8 is formed on the upper surface of the semiconductor substrate 1 so as to penetrate the source layer 3 and the channel dope layer 2. A gate insulating film 9 made of, for example, a silicon oxide film is formed on the inner surface of the trench 8. A gate wiring 10 made of, for example, polysilicon is formed on the gate insulating film 9 so as to be embedded in the trench 8. The semiconductor substrate 1, the channel dope layer 2, the source layer 3, the gate insulating film 9, and the gate wiring 10 form the basic structure of a MOSFET. The N-type region below the source layer 3 in the semiconductor substrate 1 becomes a so-called drift layer, and the trench 8 reaches the drift layer.

[0021] In this embodiment, in addition to the above basic structure, a P-type electric field relaxation layer 5 formed at the bottom of the trench 8, and a trench sidewall P-type layer 6 and a trench sidewall N-type layer 7 formed on the sidewall of the trench 8 are provided. The electric field relaxation layer 5 relaxes the electric field generated at the bottom of the trench 8. The trench sidewall P-type layer 6 applies a source potential to the electric field relaxation layer 5 by connecting between the electric field relaxation layer 5 and the channel doped layer 2. The trench sidewall N-type layer 7 prevents the current path between the trenches 8 from being narrowed by the electric field relaxation layer 5, and contributes to reducing the on-resistance of the MOSFET.

[0022] An interlayer insulating film 11 is formed on the semiconductor substrate 1 so as to cover the gate wiring 10. In addition, a metal electrode 12 serving as a source electrode is formed on the interlayer insulating film 11. The metal electrode 12 is electrically connected to the source layer 3 and the contact layer 4 through contact holes formed in the interlayer insulating film 11. Although not shown in the figure, a drain electrode of the MOSFET is provided on the lower surface of the semiconductor substrate 1.

[0023] In the gate pull-up portion 103 , the gate insulating film 9 and the gate wiring 10 extend from inside the trench 8 to the upper surface of the semiconductor substrate 1 , so that the gate wiring 10 is pulled up onto the semiconductor substrate 1 .

[0024] In the gate pull-up portion 103, the gate insulating film 9 and the gate wiring 10 are provided so as to straddle the multiple trenches 8, and the interlayer insulating film 11 is formed so as to cover the gate wiring 10 extending on the upper surface of the semiconductor substrate 1, so that the interlayer insulating film 11 is not provided with a contact hole for connecting the metal electrode 12 to the source layer 3. Therefore, it is not necessary to provide the contact layer 4 in the gate pull-up portion 103. In addition, since the gate pull-up portion 103 does not become a current path, it is not necessary to provide the trench sidewall N-type layer 7. However, as described later, in order to suppress leakage current occurring in the gate pull-up portion 103, at least a portion of the source layer 3 of the gate pull-up portion 103 adjacent to the inclined portion 8b of the trench 8 may be changed to a P-type semiconductor layer similar to the contact layer 4.

[0025] Here, the shape of the trench 8 will be described. As shown in FIG. 2, the sidewall of the trench 8 includes a vertical portion 8a perpendicular to the upper surface of the semiconductor substrate 1, a horizontal portion 8c located at the upper portion of the trench 8 and parallel to the upper surface of the semiconductor substrate 1, and an inclined portion 8b located at the shoulder of the trench 8 and provided between the vertical portion 8a and the horizontal portion 8c. The inclined portion 8b is inclined so that the width of the trench 8 widens toward the top. In addition, the inclined portion 8b is not rounded but linear in cross section. Note that the terms "vertical", "parallel" and "linear" do not mean strictly vertical, parallel and linear, respectively, but may mean substantially vertical, parallel and linear.

[0026] The gate insulating film 9 formed on the sidewall of the trench 8 is formed uniformly over the vertical portion 8a, the inclined portion 8b, and the horizontal portion 8c. The gate wiring 10 of the cell portion 101 is located below the corner formed by the inclined portion 8b and the vertical portion 8a of the trench 8. The gate wiring 10 of the gate pull-up portion 103 is formed so as to cover the vertical portion 8a, the inclined portion 8b, and the horizontal portion 8c of the trench 8.

[0027] Fig. 3 is an enlarged view of a shoulder of the trench 8. In Fig. 3, the gate wiring 10 is omitted. As shown in Fig. 3, in a cross-sectional view, a corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 does not protrude into the inside of the trench 8 from a region sandwiched between a tangent L1 of the vertical portion 8a and a tangent L2 of the inclined portion 8b. In other words, the corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 does not protrude into the inside of the trench 8 beyond the tangent L1 of the vertical portion 8a, and does not protrude upward beyond the tangent L2 of the inclined portion 8b.

[0028] In particular, in the gate pull-up portion 103, since the shoulder of the trench 8 is covered with the gate wiring 10, if the corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 protrudes, an electric field is likely to concentrate at that portion. As in the present embodiment, the corner formed by the vertical portion 8a and the inclined portion 8b of the trench 8 does not protrude into the inside of the trench 8 from the region sandwiched between the tangent L1 of the vertical portion 8a of the trench 8 and the tangent L2 of the inclined portion 8b of the trench 8, so that the electric field is prevented from concentrating at the shoulder of the trench 8 covered with the gate wiring 10. As a result, the gate insulating film 9 can be prevented from being destroyed, and the reliability of the semiconductor device is improved.

[0029] A method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to the process diagrams of FIGS.

[0030] First, a semiconductor substrate 1 made of N-type silicon carbide is prepared. The semiconductor substrate 1 is formed by forming an epitaxial layer made of silicon carbide on a substrate made of silicon carbide.

[0031] Next, impurities are ion-implanted into the surface layer (epitaxial layer) of the semiconductor substrate 1 to form a P-type channel dope layer 2 and an N-type source layer 3. As the impurity for forming the P-type semiconductor layer, for example, Al (aluminum) is used. As the impurity for forming the N-type semiconductor layer, for example, N (nitrogen) is used.

[0032] Next, an oxide film is deposited on the semiconductor substrate 1, a resist having an opening in the pattern of the trench 8 is formed thereon, and the oxide film is etched using the resist as a mask. As a result, a hard mask 20 made of an oxide film having an opening in the formation region of the trench 8 is formed on the semiconductor substrate 1, as shown in FIG.

[0033] Next, the semiconductor substrate 1 is etched using the hard mask 20 as a mask to form trenches 8 as shown in Fig. 5. This etching forms vertical portions 8a of the trenches 8, and at this time, eaves-shaped protrusions A are formed at the interface with the hard mask 20 on the shoulders (upper ends of the vertical portions 8a) of the trenches 8.

[0034] Thereafter, the size of the hard mask 20 is reduced by a certain dimension by, for example, wet etching the hard mask 20, and the shoulder portion of the trench 8 is exposed from the hard mask 20 as shown in FIG.

[0035] Then, using the reduced hard mask 20 as a mask, anisotropic dry etching such as reactive ion etching is performed on the shoulder portion of the trench 8. As a result, a sloped portion 8b is formed on the shoulder portion of the trench 8 as shown in FIG. 7. Hereinafter, this process is referred to as the "first etching process."

[0036] By performing the first etching step by anisotropic etching, the shoulder of the trench 8 can be selectively processed. Specifically, by applying etching using an etchant such as Freon, which has a large molecular diameter and a short mean free path (compared to hydrogen processing), to the first etching step, the etching rate near the shoulder of the trench 8 can be suitably increased. In addition, the etching rate is high at the shoulder of the trench 8 because the reaction proceeds from both the top and side surfaces, while the etching rate is low at the bottom of the trench 8 because only the surface reaction occurs, which also contributes to selective etching of the shoulder of the trench 8. Due to these effects, the shape change of the bottom of the trench 8 in the first etching step is suppressed, which contributes to improving the reliability of the semiconductor device 100.

[0037] When the inclined portion 8b is formed in the first etching step, at least the upper portion of the protrusion A is removed. However, if the protrusion A has a large vertical width, even after the first etching step, a protrusion B, which is a remainder of the protrusion A, may protrude into the trench 8 from a region between the tangent line L1 of the vertical portion 8a and the tangent line L2 of the inclined portion 8b, as shown in FIG.

[0038] Therefore, after the first etching step, isotropic dry etching is performed using the hard mask 20 as a mask to remove the protrusions B. As a result, as shown in Fig. 8, the corner formed by the vertical portion 8a and the inclined portion 8b becomes an inflection point C that falls within the region between the tangent line L1 of the vertical portion 8a and the tangent line L2 of the inclined portion 8b. Hereinafter, this step is referred to as the "second etching step."

[0039] In this way, the first etching step and the second etching step for forming the inclined portion 8b on the shoulder of the trench 8 are a self-alignment process using the hard mask 20 used in the trench formation step as a mask. Therefore, the inclined portion 8b can be formed with high positional accuracy without increasing the number of photolithography steps.

[0040] 15 shows the relationship between the amount of wet etching in the reduction step of the hard mask 20, the amount of dry etching in the first etching step, and the shape of the shoulder of the trench 8. As shown in FIG. 15, when the amount of etching in the reduction step of the hard mask 20 is reduced and the amount of etching in the first etching step is increased, the shape of the shoulder of the trench 8 is improved (protrusion A becomes smaller). It is preferable to reduce the amount of etching in the reduction step of the hard mask 20 compared to the amount of etching in the first etching step. By doing so, the protrusion B remaining after the first etching step can be made smaller, and the protrusion B can be easily removed in the second etching step.

[0041] After the second etching step, the hard mask 20 is removed. Then, by selective ion implantation, the electric field relaxation layer 5, the trench sidewall P-type layer 6, and the trench sidewall N-type layer 7 are formed as shown in FIG. 9. The electric field relaxation layer 5 may be formed between the step of forming the trench 8 (FIG. 5) and the step of reducing the hard mask 20 (FIG. 6). In this case, the electric field relaxation layer 5 can be formed by vertical ion implantation using the hard mask 20 before being reduced as a mask, and it is possible to suppress the implantation of impurities into the sidewall of the trench 8 during the formation of the electric field relaxation layer 5, thereby improving the reliability of the semiconductor device 100.

[0042] Furthermore, a P-type contact layer 4 is formed by selective ion implantation, as shown in Fig. 10. At this time, P-type impurities may also be implanted into the gate pull-up portion 103 to change at least a portion of the N-type source layer 3 formed in the gate pull-up portion 103 adjacent to the vertical portion 8a of the trench 8 into a P-type semiconductor layer. This is because the source layer 3 of the gate pull-up portion 103 is surrounded by the gate wiring 10, which may cause an increase in leakage current. It is presumed that the reason leakage current is high in N-type semiconductors is that there is an excess of highly mobile electrons, which makes it easy to increase leakage current.

[0043] After all the impurity implantation steps are performed, a heat treatment is performed to activate the implanted impurities. Then, as shown in Fig. 11, a gate insulating film 9 is formed on the upper surface of the semiconductor substrate 1 including the inside of the trench 8. In addition, as shown in Fig. 12, a conductive film such as polysilicon is deposited on the gate insulating film 9 to form a gate wiring 10.

[0044] Then, the gate wiring 10 is patterned by selective etching, as shown in Fig. 13. In this patterning process of the gate wiring 10, an etch-back is performed on the gate wiring 10 in the cell portion 101, and the gate wiring 10 is removed from the upper surface of the semiconductor substrate 1 in the cell portion 101 while leaving the gate wiring 10 in the trench 8 in the cell portion 101. At that time, the etching is performed until the upper surface of the gate wiring 10 remaining in the trench 8 is located below the inflection point C of the shoulder portion of the trench 8.

[0045] Then, an interlayer insulating film 11 is formed on the semiconductor substrate 1. After forming contact holes in the interlayer insulating film 11, a metal electrode 12 and a gate pad (not shown) are formed on the interlayer insulating film 11 as shown in Fig. 14. If necessary, a protective film such as a passivation film is formed on the metal electrode 12 and the gate pad, and the protective film is opened so that a part of the metal electrode 12 and the gate pad are exposed.

[0046] Furthermore, after the back surface of the semiconductor substrate 1 is ground to thin the semiconductor substrate 1, a drain electrode made of metal is formed on the back surface of the semiconductor substrate 1, and the semiconductor device 100 is completed.

[0047] This is followed by a dicing process for dividing the semiconductor device 100 into individual pieces, and a test process for the semiconductor device 100. The semiconductor device 100 is modularized, and ultimately forms an inverter circuit or the like.

[0048] The above-described embodiment can be modified or omitted as appropriate.

[0049] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0050] (Appendix 1) a semiconductor substrate made of silicon carbide; a trench formed in an upper surface of the semiconductor substrate; a gate insulating film formed on an inner surface of the trench; a gate wiring formed on the gate insulating film and embedded in the trench; a gate lift-up portion, which is a region where a portion of the gate wiring is lifted up from the trench to the upper surface of the semiconductor substrate; Equipped with The sidewall of the trench of the gate pull-up portion is a vertical portion perpendicular to the top surface of the semiconductor substrate; a horizontal portion located at an upper portion of the trench and parallel to the top surface of the semiconductor substrate; a sloped portion located at a shoulder of the trench and disposed between the vertical portion and the horizontal portion; Equipped with The inclined portion is inclined so that the width of the trench increases upward and is linear in cross-sectional view; In a cross-sectional view, a corner portion formed by the vertical portion and the inclined portion does not protrude into the trench from a region between a tangent line of the vertical portion and a tangent line of the inclined portion. Semiconductor device.

[0051] (Appendix 2) The trench reaches a drift layer of a first conductivity type, A second conductivity type electric field relaxation layer is formed at the bottom of the trench. 2. The semiconductor device according to claim 1.

[0052] (Appendix 3) the second conductive type impurity layer connected to the electric field relaxation layer is formed on a part of the side wall of the trench; 3. The semiconductor device according to claim 2.

[0053] (Appendix 4) In the gate pull-up portion, at least a portion of the semiconductor substrate adjacent to the vertical portion of the trench is a P-type semiconductor layer. 4. The semiconductor device according to claim 1,

[0054] (Appendix 5) forming a mask on an upper surface of a semiconductor substrate; forming a trench having a vertical portion perpendicular to the upper surface of the semiconductor substrate by etching using the mask; shrinking the mask; a first etching step of forming a slope at a shoulder of the trench by etching using the reduced mask; a second etching step of etching a corner portion formed by the vertical portion and the inclined portion by etching using the reduced mask after the first etching step; A method for manufacturing a semiconductor device comprising the steps of:

[0055] (Appendix 6) the etching of the first etching step is anisotropic etching; The etching of the second etching step is an isotropic etching. A method for manufacturing the semiconductor device according to claim 5.

[0056] (Appendix 7) an etching amount in the step of reducing the mask is smaller than an etching amount in the first etching step; 7. A method for manufacturing the semiconductor device according to claim 5 or 6. [Explanation of symbols]

[0057] 100 semiconductor device, 101 cell portion, 102 gate routing portion, 102a gate pad region, 103 gate pull-up portion, 1 semiconductor substrate, 2 channel doped layer, 3 source layer, 4 contact layer, 5 electric field relaxation layer, 6 trench sidewall P-type layer, 7 trench sidewall N-type layer, 8 trench, 8a vertical portion, 8b inclined portion, 8c horizontal portion, 9 gate insulating film, 10 gate wiring, 11 interlayer insulating film, 12 metal electrode, 20 hard mask.

Claims

1. a semiconductor substrate made of silicon carbide; a trench formed in an upper surface of the semiconductor substrate; a gate insulating film formed on an inner surface of the trench; a gate wiring formed on the gate insulating film and embedded in the trench; a gate lift-up portion, which is a region where a portion of the gate wiring is lifted up from the trench to the upper surface of the semiconductor substrate; Equipped with The sidewall of the trench of the gate pull-up portion is a vertical portion perpendicular to the top surface of the semiconductor substrate; a horizontal portion located at an upper portion of the trench and parallel to the top surface of the semiconductor substrate; a sloped portion located at a shoulder of the trench and disposed between the vertical portion and the horizontal portion; Equipped with The inclined portion is inclined so that the width of the trench increases upward and is linear in cross-sectional view; In a cross-sectional view, a corner portion formed by the vertical portion and the inclined portion does not protrude into the trench from a region between a tangent line of the vertical portion and a tangent line of the inclined portion. Semiconductor device.

2. The trench reaches a drift layer of a first conductivity type, An electric field relaxation layer of a second conductivity type is formed at the bottom of the trench. The semiconductor device according to claim 1 .

3. the second conductivity type impurity layer connected to the electric field relaxation layer is formed on a part of the side wall of the trench; The semiconductor device according to claim 2 .

4. In the gate pull-up portion, at least a portion of the semiconductor substrate adjacent to the vertical portion of the trench is a P-type semiconductor layer. The semiconductor device according to claim 1 .

5. forming a mask on an upper surface of a semiconductor substrate; forming a trench having a vertical portion perpendicular to the upper surface of the semiconductor substrate by etching using the mask; shrinking the mask; a first etching step of forming a slope at a shoulder of the trench by etching using the reduced mask; a second etching step of etching a corner portion formed by the vertical portion and the inclined portion by etching using the reduced mask after the first etching step; A method for manufacturing a semiconductor device comprising the steps of:

6. the etching in the first etching step is anisotropic etching; The etching of the second etching step is an isotropic etching. The method for manufacturing a semiconductor device according to claim 5 .

7. an etching amount in the step of reducing the mask is smaller than an etching amount in the first etching step; The method for manufacturing a semiconductor device according to claim 5 or 6.

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