Amplifier circuit and doherty amplifier circuit

Abstract

To provide an amplifier circuit capable of improving characteristics.SOLUTION: An amplifier circuit includes a transistor Q1 having an input terminal to which a high-frequency signal is input and an output terminal to which an amplified high-frequency signal is output, an inductor L connected in parallel with the transistor between the input terminal and the output terminal, and a capacitor C connected in parallel with the transistor between the input terminal and the output terminal and connected in series to the inductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an amplifier circuit and a Doherty amplifier circuit. [Background technology]

[0002] As an amplifier circuit, an N-way (N is 3 or more) Doherty amplifier circuit using a main amplifier and two or more peak amplifiers is known (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 8,022,760 [Patent Document 2] U.S. Pat. No. 10,601,375 Summary of the Invention [Problem to be solved by the invention]

[0004] The maximum gain of an amplifier circuit such as a Doherty amplifier circuit can be improved by suppressing the feedback capacitance of a transistor.

[0005] The present disclosure aims to improve properties. [Means for solving the problem]

[0006] One embodiment of the present disclosure is an amplifier circuit comprising: a transistor having an input terminal to which a high-frequency signal is input and an output terminal to which an amplified high-frequency signal is output; an inductor connected in parallel to the transistor between the input terminal and the output terminal; and a capacitor connected in parallel to the transistor between the input terminal and the output terminal and connected in series to the inductor. Effect of the Invention

[0007] According to the present disclosure, characteristics can be improved. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of an amplifier circuit according to a first embodiment. [Diagram 2] FIG. 2 is a circuit diagram of circuit A. [Diagram 3] FIG. 3 is a circuit diagram of the circuit B. [Figure 4] FIG. 4 is a circuit diagram of the circuit C. [Diagram 5] FIG. 5 is a diagram showing the maximum gain gmax versus frequency in the circuit C. [Figure 6] FIG. 6 is a diagram showing the maximum gain gmax versus frequency in the circuit C. [Figure 7] FIG. 7 is a circuit diagram of circuit D. [Figure 8] FIG. 8 is a diagram showing the maximum gain gmax versus frequency in circuit D. [Figure 9] FIG. 11 is a block diagram of a Doherty amplifier circuit according to a second embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is an amplifier circuit including a transistor having an input terminal to which a high-frequency signal is input and an output terminal to which an amplified high-frequency signal is output, an inductor connected in parallel with the transistor between the input terminal and the output terminal, and a capacitor connected in parallel with the transistor between the input terminal and the output terminal and connected in series with the inductor. This allows the inductor to compensate for the feedback capacitance of the transistor. This improves the gain of the amplifier circuit and improves its characteristics. (2) In the above (1), when the feedback capacitance of the transistor is Cgd, the inductance of the inductor is L, the capacitance of the capacitor is C, and the center frequency of the operating band is f0, 1 / ((2π×f0) 2 ×Cgd) + 1 / ((2π×f0) 2 ×C)≦L≦10 / ((2π×f0) 2 ×Cgd) + 10 / ((2π×f0) 2 × C). This allows the inductor to compensate for the feedback capacitance, thereby improving the characteristics. (3) In the above (2), 1 / (2π×f0×C)<2π×f0×L may be used. This allows the series circuit of the inductor and capacitor to be inductive. (4) In the above (3), C>Cgd may be satisfied, so that the capacitor can be used as a DC cutoff. (5) In any one of the above (1) to (4), a maximum gain at a center frequency of an operating band between the input terminal and the output terminal may be greater than a maximum gain at the center frequency between the input terminal and the output terminal when the inductor and the capacitor are not provided, thereby improving gain. (6) In any one of the above (1) to (5), the transistor may be a FET, the input terminal may be a gate, and the output terminal may be a drain. This makes it possible to improve the characteristics of the FET. (7) A Doherty amplifier circuit may include a main amplifier having the amplifier circuit of any one of (1) to (6) above, and a peak amplifier, thereby improving the characteristics of the Doherty amplifier circuit. (8) In the above (7), the peak amplifier may not include an inductor and a capacitor connected in parallel to the transistor between the input terminal and the output terminal of the transistor, thereby making it possible to reduce the size of the peak amplifier.

[0010] [Details of the embodiment of the present disclosure] Specific examples of an amplifier circuit and a Doherty amplifier circuit according to the embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] 1 is a block diagram of an amplifier circuit according to a first embodiment. The frequency of a high-frequency signal amplified by the amplifier circuit 100 is, for example, 0.5 GHz or more and 100 GHz or less. When the amplifier circuit 100 is used as a high-output high-frequency amplifier circuit for use in a mobile communication base station, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less.

[0012] As shown in Fig. 1, in the amplifier circuit 100 of the first embodiment, an amplifier 11 is connected between an input terminal Tin and an output terminal Tout. The amplifier 11 includes a transistor Q1. The transistor Q1 is, for example, a FET (Field Effect Transistor). A source S, a gate G, and a drain D of the transistor Q1 are electrically connected to a reference potential such as ground, the input terminal Tin, and the output terminal Tout, respectively. The amplifier 11 amplifies a high-frequency signal input to the input terminal Tin, and outputs the amplified harmonic signal to the output terminal Tout.

[0013] The transistor Q1 is, for example, a field effect transistor (FET), such as a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0014] A capacitor C and an inductor L, which are connected in series, are connected in parallel to the amplifier 11 between the input terminal Tin and the output terminal Tout. The inductor L compensates for the feedback capacitance (for example, the gate drain capacitance Cgd) of the transistor Q1. The capacitor C is a DC blocking capacitor.

[0015] [simulation] In order to explain the operation of the first embodiment, simulations of several circuits A to D will be described below.

[0016] [Circuit A] FIG. 2 is a circuit diagram of circuit A. As shown in FIG. 2, an inductor L1 is connected in parallel to the gate-drain capacitance Cgd between the input terminal Tin and the output terminal Tout. At the resonant frequency of the parallel resonant circuit of the gate-drain capacitance Cgd and the inductor L1, the impedance between the input terminal Tin and the output terminal Tout becomes high. This makes it possible to compensate for the gate-drain capacitance Cgd. If the center frequency of the operating band is f0, the inductance of the inductor L1 is L1, and the gate-drain capacitance Cgd is Cgd, then the inductance L1 when the parallel resonant circuit resonates at the center frequency f0 is given by Equation 1. L1=1 / ((2π×f0) 2 ×Cgd) (Formula 1) When f0=2.1GHz and Cgd=0.246pF, L1=23.1nH.

[0017] [Circuit B] FIG. 3 is a circuit diagram of circuit B. As shown in FIG. 3, a capacitor C2 is connected in parallel to the gate-drain capacitance Cgd and in series to the inductor L2 between the input terminal Tin and the output terminal Tout. In circuit A, a direct current flows in parallel to the gate-drain capacitance Cgd via the inductor L1. Therefore, the capacitor C2 is provided to cut the direct current. In circuit B, the inductance L2 of the inductor L2, which corresponds to the capacitor C2, is made larger than the inductance L1 of the inductor L1. The relationship between L1, L2, and C2 is expressed by Equation 2. 2π×f0×L1=2π×f0×L2-1 / (2π×f0×C2) (Formula 2) From equation 2, the inductance of inductor L2 is given by equation 3. L2=1 / ((2π×f0) 2 ×Cgd) + 1 / ((2π×f0) 2 ×C2) (Formula 3) When f0=2.1GHz, Cgd=0.246pF and C2=0.5pF, L2=34.7nH.

[0018] [Circuit C] 4 is a circuit diagram of the circuit C. In the circuit C, an inductor L3 and a capacitor C3 are connected in parallel to a gate-drain capacitance Cgd in an equivalent circuit 52 of a transistor. The equivalent circuit 52 is an equivalent circuit of a FET.

[0019] In the equivalent circuit 52, the drain-source current is represented by a current source Id. A current source Id and a drain-source capacitance Cds are connected in parallel between nodes N1 and N2. The node N1 is connected to a source S via a source resistance Rs and a source inductance Ls. The node N2 is connected to a drain D via a drain resistance Rd and a drain inductance Ld. The node N3 is connected to a gate G via a gate resistance Rg and a gate inductance Lg. A gate-drain capacitance Cgd is connected between nodes N2 and N3. A gate-source capacitance Cgs and a channel resistance Ri are connected in series between nodes N3 and N1.

[0020] In the circuit C, an inductor L3 and a capacitor C3 are connected in parallel to the gate-drain capacitance Cgd between nodes N2 and N3.

[0021] The simulation was performed using the values ​​of inductor L2 and capacitor C2 in circuit B as inductor L3 and capacitor C3. The equivalent circuit 52 used was the equivalent circuit of a GaN HEMT. Cds=0.246.

[0022] Fig. 5 is a diagram showing the maximum gain gmax versus frequency in circuit C. Circuit C is a simulation result of circuit C, and without L3 and C3 is a simulation result of a circuit without inductor L3 and capacitor C3. As shown in Fig. 5, in circuit C, the maximum gain is maximized near 4.7 GHz, but the maximum gain at center frequency f0 = 2.1 GHz is lower than that of the circuit without L3 and C3.

[0023] Therefore, the values ​​of inductor L3 and capacitor C3 were optimized. Figure 6 is a diagram showing the maximum gain gmax versus frequency in circuit C. The inductor L3 has an inductance of 91 nH, and the capacitor C3 has a capacitance of 1 pF. As shown in Figure 6, the frequency at which the maximum gain is maximized in circuit C is lower, at about 2.7 GHz, than in Figure 5. Accordingly, the maximum gain at the center frequency f0=2.1 GHz is about 2 dB higher than in a circuit without L3 and C3.

[0024] [Circuit D] In an actual amplifier circuit, the inductor L and the capacitor C are connected in parallel to the transistor Q1 between the gate G and the drain D. Fig. 7 is a circuit diagram of the circuit D. In the circuit D, the inductor L and the capacitor C are connected in parallel to the equivalent circuit 52 between a node N4 between the gate G and the input terminal Tin, and a node N5 between the drain D and the output terminal Tout.

[0025] FIG. 8 is a diagram showing the maximum gain gmax versus frequency in circuit D. Without L and C is the simulation result of a circuit without inductor L and capacitor C. The inductor L has an inductance of 91 nH, and the capacitor C has a capacitance of 1 pF. As shown in FIG. 8, the frequency at which the maximum gain in circuit D is maximized is approximately 2.7 GHz, which is approximately the same as that of circuit C in FIG. 6. The maximum gain at the center frequency f0=2.1 GHz is approximately 2 dB higher than that of a circuit without L and C.

[0026] When f0=2.1 GHz, Cgd=0.246 pF, and C2=1 pF, L2 calculated from equation 3 is 28.8 nH. In circuits C and D, it is considered that L and L3 will be larger than L2 calculated from equation 3 due to the influence of other elements of equivalent circuit 52.

[0027] 1 and 7, the inductor L is connected in parallel with the transistor Q1 between the gate G (input terminal) and drain D (output terminal) of the transistor Q1. The capacitor C is connected in parallel with the transistor Q1 between the gate G and drain D, and is also connected in series with the inductor L. This allows the inductor L to compensate for the feedback capacitance (gate drain capacitance Cgd) of the transistor Q1. This makes it possible to improve the gain of the amplifier circuit 100 having the transistor Q1, thereby improving the characteristics.

[0028] The inductance L of the inductor L is a value calculated by the formula 3 if the influence of elements other than the gate-drain capacitance Cgd of the equivalent circuit 52 is small. If the influence of elements other than the gate-drain capacitance Cgd of the equivalent circuit 52 is large, the inductance L of the inductor L is larger than the value calculated by the formula 3. Therefore, 1 / ((2π×f0) 2 ×Cgd) + 1 / ((2π×f0) 2 ×C)≦L As a result, the inductor L compensates for the gate-drain capacitance Cgd, thereby improving the characteristics.

[0029] When the influence of factors other than the gate-drain capacitance Cgd of the equivalent circuit 52 is large, 1 / ((2π×f0) 2 ×Cgd) + 1 / ((2π×f0) 2 ×C) <L It may be said that 2 / ((2π×f0) 2 ×Cgd) + 2 / ((2π×f0) 2 ×C)≦L It is also possible to use the following.

[0030] If the inductance L is large, the resonance frequency with Cgs becomes lower than the center frequency f0. This causes the gain to decrease. From this viewpoint, L≦10 / ((2π×f0) 2 ×Cgd) + 10 / ((2π×f0) 2 ×C) It may be said that L≦8 / ((2π×f0)2×Cgd)+8 / ((2π×f0)2×C) It may be said that L≦6 / ((2π×f0) 2 ×Cgd) + 6 / ((2π×f0) 2 ×C) It is also possible to use the following.

[0031] To make the series circuit of capacitor C and inductor L inductive, 1 / (2π×f0×C)<2π×f0×L It can be said that: 1 / (2π×f0×C)≦π×f0×L / 2 It may be said that 1 / (2π×f0×C)≦π×f0×L / 4 It is also possible to use the following. 1 / (2π×f0×C)≧2π×f0×L / 20 It is also possible to use the following.

[0032] The capacitance C is relatively large because the capacitor C is used as a DC cutoff. For example, C>Cgd It can be said that: C ≥ 1.5 × Cgd It may be said that C ≥ 2 × Cgd It may be said that C≦10×Cgd It is also possible to use the following.

[0033] 8, the maximum gain gmax at the center frequency f0 between the gate G and the drain D is larger than the maximum gain gmax0 at the center frequency f0 when the inductor L and the capacitor C are not provided. This makes it possible to improve the gain.

[0034] The maximum gain gmax can be set to 0.5 dB or more, and can be set to 1 dB or more, higher than gmax0.

[0035] The transistor Q1 does not have to be a FET. An inductor L and a capacitor C may be connected in parallel to the feedback capacitance of the transistor Q1. When the transistor Q1 is a FET and the amplifier is a common-source amplifier, the equivalent circuit of the transistor Q1 is the equivalent circuit 52 in FIG. 7. In this case, the provision of the inductor L and the capacitor C can improve the gain in particular.

[0036] [Example 2] A second embodiment is an example in which the amplifier circuit of the first embodiment is used as a Doherty amplifier circuit. Fig. 9 is a block diagram of a Doherty amplifier circuit according to the second embodiment.

[0037] 9, in the Doherty amplifier circuit 102, a main amplifier 10 and peak amplifiers 12 and 14 are connected in parallel between a distributor 16 and a combiner 18. In this manner, the Doherty amplifier circuit 102 is a 3-way amplifier circuit. The Doherty amplifier circuit may be an N-way Doherty amplifier circuit having one or three or more peak amplifiers.

[0038] A high frequency signal is input as an input signal Sin to an input terminal Tin. A distributor 16 distributes the input signal Sin input to the input terminal Tin into signals S1, S2, and S3. The distributor 16 is, for example, a Wilkison type distributor.

[0039] The path to which the signal S1 is input includes a matching circuit 30, a bias circuit 36, a main amplifier 10, a bias circuit 39, and a matching circuit 33. The path to which the signal S2 is input includes a matching circuit 31, a bias circuit 37, a peak amplifier 12, and a matching circuit 34. The path to which the signal S3 is input includes a matching circuit 32, a bias circuit 38, a peak amplifier 14, and a matching circuit 35.

[0040] The matching circuits 30 to 32 match the impedance seen from the distributor 16 at the matching circuits 30 to 32, respectively, to the impedance seen from the matching circuits 30 to 32 at the main amplifier 10, the peak amplifiers 12 and 14, respectively. The bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of the main amplifier 10, the peak amplifiers 12 and 14, respectively, and suppress leakage of the signals S1 to S3 to the bias terminals.

[0041] The main amplifier 10 and the peak amplifiers 12 and 14 amplify the signals S1, S2 and S3, respectively, and output the amplified signals S4, S5 and S6, respectively. The bias circuit 39 supplies a drain bias voltage VD to the drains D of the main amplifier 10 and the peak amplifiers 12 and 14, and suppresses the signal S4 from leaking to the bias terminal. The matching circuits 33 to 35 match the impedances seen from the main amplifier 10 and the peak amplifiers 12 and 14 to the matching circuits 33 to 35, respectively, to the impedances seen from the matching circuits 33 to 35 to the combiner 18, respectively. The combiner 18 combines the signals S4 to S6, and outputs the combined signal to the output terminal Tout as the output signal Sout.

[0042] The main amplifier 10 operates in class A or class AB, and the peak amplifiers 12 and 14 operate in class C. When the input power of the input signal Sin is small, the main amplifier 10 operates, and the peak amplifiers 12 and 14 do not operate. When the input power increases, the main amplifier 10 and the peak amplifier 12 operate, and the peak amplifier 14 does not operate. Furthermore, when the input power increases, the main amplifier 10, the peak amplifiers 12 and 14 all operate.

[0043] Fig. 10 is a plan view of a semiconductor device in Example 2. The lid of package 50 is not shown in Fig. 10. The thickness direction of base 51 of package 50 is the Z direction, the direction from leads 27a to 27c to leads 28a to 28c is the X direction, and the direction perpendicular to the X direction and Z direction is the Y direction.

[0044] 10, in the semiconductor device 104, a package 50 has a base 51 having at least a conductive upper surface. The base 51 is a conductive substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the base 51. The semiconductor chips 20a to 20c, the capacitive components 24a to 24c, and the passive chip 40 are mounted on the base 51.

[0045] Leads 27a to 27c are provided on the negative side of base 51 in the X direction with an insulating layer (not shown) sandwiched therebetween. Leads 28a to 28c are provided on the positive side of base 51 in the X direction with an insulating layer (not shown) sandwiched therebetween. Leads 27a to 27c and 28a to 28c are, for example, metal layers or metal plates such as copper. Signals S1 to S3 are input to leads 27a to 27c, respectively, and signals S4 to S6 are output from leads 28a to 28c, respectively.

[0046] The semiconductor chip 20a includes a substrate 21a, a transistor Q1, pads 22a and 23a provided on the upper surface of the substrate 21a, and an electrode (not shown) provided on the lower surface of the substrate 21a. The pads 22a and 23a and the electrode on the lower surface are electrically connected to the gate G, drain D, and source S of the transistor Q1, respectively. The semiconductor chip 20b includes a substrate 21b, a transistor Q2, pads 22b and 23b provided on the upper surface of the substrate 21b, and an electrode provided on the lower surface of the substrate 21b. The pads 22b and 23b and the electrode on the lower surface are electrically connected to the gate G, drain D, and source S of the transistor Q2, respectively. The semiconductor chip 20c includes a substrate 21c, a transistor Q3, pads 22c and 23c provided on the upper surface of the substrate 21c, and an electrode provided on the lower surface of the substrate 21c. The pads 22c, 23c and the bottom electrode are electrically connected to the gate G, drain D and source S of the transistor Q3, respectively.

[0047] The substrates 21a to 21c are semiconductor substrates. When the transistors Q1 to Q3 are GaN HEMTs, the substrates 21a to 21c are, for example, silicon carbide (SiC) substrates, sapphire substrates, or gallium nitride (GaN) substrates. When the transistors Q1 to Q3 are LDMOSs, the substrates 21a to 21c are, for example, silicon (Si) substrates. The pads 22a to 22c, 23a to 23c, and the bottom electrodes are, for example, metal layers such as gold layers.

[0048] The capacitive components 24a to 24c each include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode provided on the lower surface of the dielectric substrate 25. The electrode 26 and the electrode on the lower surface sandwiching the dielectric substrate 25 form a capacitor. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is, for example, a metal layer such as a gold layer.

[0049] The bonding wires 46 electrically connect the leads 27a to 27c to the electrodes 26 of the capacitive components 24a to 24c, respectively. The bonding wires 47 electrically connect the electrodes 26 of the capacitive components 24a to 24c to the pads 22a to 22c, respectively. The bonding wires 48 electrically connect the pads 23a to 23c to the leads 28a to 28c, respectively. The bonding wires 46 to 48 are metal wires such as gold wires or aluminum wires.

[0050] The bond wires 46 and 47 function as inductors, and the capacitive components 24a to 24c function as capacitors. The bond wires 46, 47 and the capacitive components 24a to 24c correspond to the matching circuits 30 to 32 of the T-type LCL circuit.

[0051] A passive chip 40 is provided in the positive direction of the Y direction of the semiconductor chip 20a. The passive chip 40 includes a substrate 41 and pads 42 and 44 provided on the upper surface of the substrate 41. A capacitor C and an inductor L are connected in series between the pads 42 and 44. A bonding wire 49a electrically connects the pad 22a to the pad 42. A bonding wire 49b electrically connects the pad 23a to the pad 44. This allows the inductor L and the capacitor C to be connected in parallel to the transistor Q1.

[0052] As in the second embodiment, an inductor L and a capacitor C may be connected in parallel to at least one of the main amplifier 10 and the peak amplifiers 12 and 14 of the Doherty amplifier circuit 102. In particular, the main amplifier 10 mainly amplifies the input signal Sin. Therefore, the inductor L and the capacitor C are connected in parallel to the main amplifier 10. This can improve the characteristics of the Doherty amplifier circuit 102, such as the gain.

[0053] The peak amplifiers 12 and 14 do not include an inductor and a capacitor connected in parallel to the transistors Q2 and Q3 between the gate G and the drain D of the transistors Q2 and Q3. The peak amplifiers 12 and 14 operate only when the input power is large. Therefore, the peak amplifiers 12 and 14 do not need to include the inductor L and the capacitor C. This allows for miniaturization.

[0054] Although a 3-way Doherty amplifier circuit has been described as an example, a 2-way Doherty amplifier circuit not including the peak amplifier 14 may be used. Also, an N-way Doherty amplifier circuit, where N is 4 or more, may be used. In this case, it is sufficient to provide N-1 peak amplifiers.

[0055] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0056] 10 Main Amplifier 11 Amplifier 12, 14 Peak amplifier 16 Distributor 18 Synthesizer 20a, 20b, 20c Semiconductor chip 21a, 21b, 21c Substrate 22a, 22b, 22c, 23a, 23b, 23c, 42, 44 Pads 24a, 24b, 24c Capacitive components 25 Dielectric Substrate 26 electrodes 27a, 27b, 27c, 28a, 28b, 28c Lead 30, 31, 32, 33, 34, 35 matching circuit 36, 37, 38, 39 Bias circuit 40 Passive Chips 41 Substrate 46, 47, 48, 49a, 49b Bonding wire 50 packages 51 Base 52 Equivalent Circuit 100 Amplification circuit 102 Doherty amplifier C, C2, C3 Capacitor, Capacitance Cgd Gate drain capacitance (feedback capacitance) L, L1, L2, L3 inductor, inductance Q1, Q2, Q3 transistors Sin input signal Sout Output signal Tin Input terminal Tout output terminal

Claims

1. a transistor having an input terminal for receiving a high frequency signal and an output terminal for outputting an amplified high frequency signal; an inductor connected in parallel with the transistor between the input terminal and the output terminal; a capacitor connected in parallel with the transistor between the input terminal and the output terminal and connected in series with the inductor; An amplifier circuit comprising:

2. When the feedback capacitance of the transistor is Cgd, the inductance of the inductor is L, the capacitance of the capacitor is C, and the center frequency of the operating band is f0, 1 / ((2π×f0) ２ ×Cgd)+1 / ((2π×f0) ２ ×C)≦L≦10 / ((2π×f0) ２ ×Cgd)+10 / ((2π×f0) ２ ×C) 2. The amplifier circuit according to claim 1,

3. 1 / (2π×f0×C)<2π×f0×L 3. The amplifier circuit according to claim 2, wherein:

4. C>Cgd 4. The amplifier circuit according to claim 3, wherein:

5. 5. The amplifier circuit according to claim 1, wherein a maximum gain at a center frequency of an operating band between the input terminal and the output terminal is greater than a maximum gain at the center frequency between the input terminal and the output terminal when the inductor and the capacitor are not provided.

6. the transistor is a FET, 5. The amplifier circuit according to claim 1, wherein the input terminal is a gate and the output terminal is a drain.

7. A main amplifier including the amplifier circuit according to any one of claims 1 to 4; A peak amplifier and A Doherty amplifier circuit comprising:

8. The Doherty amplifier circuit according to claim 7 , wherein the peak amplifier does not include an inductor and a capacitor connected in parallel to the transistor between the input terminal and the output terminal of the transistor.

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