Display device

Abstract

To provide a display device with the improved resolution characteristics.SOLUTION: A display device in an example includes a base layer, a driving element layer including a transistor, an insulating layer, and a driving connection part electrically coupled to the transistor, a light-emitting element layer including a pixel defining film where a light-emitting opening part and a penetration hole not overlapping with the light-emitting opening part are defined (sectioned and formed), a light-emitting element disposed in the light-emitting opening part, and a separator disposed on the pixel defining film, and a conductive pattern including a contact part disposed below the separator and filling the penetration hole and an extension part coupled to the contact part and disposed on an upper surface of the pixel defining film. The light-emitting element includes an anode disposed on the driving element layer, an intermediate layer disposed over the anode, and a cathode disposed over the intermediate layer. The contact part is electrically coupled to the driving connection part. The extension part is connected to the cathode on an upper surface of the pixel defining film.SELECTED DRAWING: Figure 5a

Description

[Technical field]

[0001] The present invention relates to displays, and more particularly to displays with improved resolution. [Background technology]

[0002] 2. Description of the Related Art Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation systems, game consoles, and the like, include a display device for displaying images.

[0003] A display device includes a light emitting element and a circuit for driving the light emitting element. The light emitting element included in the display device emits light by a voltage applied from the circuit to generate an image. Research on the connection between the light emitting element and the circuit has been ongoing in order to improve the reliability of the display device. Also, in order to improve the resolution of the display device, the arrangement of a contact part for connecting the light emitting element to the circuit should be considered. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication 2022-084143 (JP2022-084143A; US2022-0165818A) Summary of the Invention [Problem to be solved by the invention]

[0005] It is an object of the present invention to provide a display device with improved resolution characteristics. [Means for solving the problem]

[0006] One embodiment provides a display device including: a base layer; a driving element layer disposed on the base layer, the driving element layer including a transistor, a plurality of insulating layers disposed on the transistor, and a driving connection portion electrically connected to the transistor; a light emitting element layer disposed on the driving element layer, the light emitting element layer including a pixel defining film having a light emitting opening and a through hole that does not overlap with the light emitting opening, a light emitting element disposed in the light emitting opening, and a separator disposed on the pixel defining film; and a conductive pattern including a contact portion disposed under the separator and filling the through hole, and an extension portion connected to the contact portion and disposed on an upper surface of the pixel defining film, wherein the light emitting element includes an anode disposed on the driving element layer, an intermediate layer disposed above the anode, and a cathode disposed above the intermediate layer, the contact portion being electrically connected to the driving connection portion, and the extension portion connecting to the cathode on the upper surface of the pixel defining film.

[0007] In a plan view, the through-hole may be spaced from an edge of the separator and overlap the separator.

[0008] A side of the extension adjacent to the light emitting opening on the pixel defining film may extend from the separator, and the cathode may be connected to the exposed side of the extension.

[0009] The cathode and the intermediate layer may be disconnected by the separator, and a first end of the disconnected intermediate layer may be connected to the one side surface above the first pixel defining film, and a first end of the disconnected cathode may be connected to the one side surface above the intermediate layer.

[0010] The first end of the intermediate layer and the first end of the cathode may not overlap the separator in a planar manner.

[0011] The first end of the intermediate layer and the first end of the cathode may overlap the separator in a plane.

[0012] A second end of the disconnected intermediate layer may be disposed on the separator and a second end of the disconnected cathode may be disposed on the separator and on the intermediate layer.

[0013] The extension may have a thickness of 1000 to 5000 Å.

[0014] One side end of the extension adjacent to the light emitting opening on the pixel defining film may be exposed from the separator, and the cathode may be connected to the exposed upper surface of the one side end of the extension.

[0015] The cathode and the intermediate layer may be disconnected by the separator, a first end of the disconnected intermediate layer may be disposed directly on the upper surface, and a first end of the disconnected cathode may be connected to the exposed upper surface while covering the intermediate layer on the exposed upper surface.

[0016] The first end of the intermediate layer and the first end of the cathode may overlap the separator in a plane.

[0017] The first end of the intermediate layer and the first end of the cathode may not overlap the separator in a planar manner.

[0018] A second end of the disconnected intermediate layer may be disposed on the separator and a second end of the disconnected cathode may be disposed on the separator and on the intermediate layer.

[0019] The extension may have a thickness of 500 Å or less.

[0020] The separator may include a lower pattern adjacent to the pixel defining film and an upper pattern disposed continuously on the lower pattern and having a width greater than a width of the lower pattern on a cross section, and on the cross section, a side of the separator may include an inflection portion between the lower pattern and the upper pattern.

[0021] The conductive pattern may include a transparent conductive metal material.

[0022] The drive connection portion may include, stacked in sequence, a first layer including titanium, a second layer including aluminum disposed above the first layer, and a third layer including titanium disposed above the second layer.

[0023] The transistor may include a semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region, and the conductive pattern may be electrically coupled to the drain region via the drive connection portion.

[0024] The transistor may be an N-type transistor.

[0025] According to one embodiment, a semiconductor device includes a base layer, a transistor disposed on the base layer, a lower insulating layer disposed on the transistor and defining a lower hole, a driving connection portion disposed on the lower insulating layer by filling the lower hole and electrically connecting with the transistor, an upper insulating layer covering the driving connection portion on the lower insulating layer, a pixel defining film disposed on the upper insulating layer and defining a light emitting opening, a separator disposed on the pixel defining film without overlapping with the light emitting opening, and a separator penetrating the upper insulating layer and the pixel defining film, a light-emitting element including a conductive pattern arranged to fill a through hole defined so as to overlap a pixel electrode, a light-emitting layer arranged on the upper insulating layer and arranged in the light-emitting opening, a first electrode arranged below the light-emitting layer, a second electrode arranged above the light-emitting layer, and a functional layer arranged at least one of between the first electrode and the light-emitting layer and between the light-emitting layer and the second electrode, wherein one end of the conductive pattern is connected to the driving connection portion, and the other end of the conductive pattern is connected to the second electrode on the pixel definition film.

[0026] The conductive pattern may include a contact portion filled in the through hole and including the one end, and an extension portion connected to the contact portion, including the other end, and disposed on an upper surface of the pixel defining layer.

[0027] The second electrode and the functional layer extending from the light emitting opening toward the separator are disconnected by the separator, and a first portion of the disconnected second electrode and one side end of the functional layer is connected to the other end of the conductive pattern, and a second portion of the disconnected second electrode and the other side end of the functional layer is disposed on the separator.

[0028] In each of the first and second portions, the second electrode may be disposed on the functional layer.

[0029] The first portion may be disposed directly on a side surface or an upper surface of the other end of the conductive pattern.

[0030] The first portion includes the functional layer disposed directly on the upper surface of the conductive pattern and a second electrode disposed directly on the functional layer, and an edge of the second electrode may be positioned closer to the through hole in a plane than an edge of the functional layer.

[0031] The transistor may include a semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region, and the conductive pattern may electrically connect the drain region and the second electrode via the drive connection portion.

[0032] In one embodiment, a display device is provided that includes a plurality of light emitting portions that emit light of different wavelengths, a separator that separates the light emitting portions, a pixel definition film disposed below the separator and defining light emitting openings in which each of the light emitting portions is disposed and through holes that do not overlap with the light emitting openings, light emitting elements disposed corresponding to each of the light emitting portions and including an anode, an intermediate layer disposed above the anode, and a cathode disposed above the intermediate layer, a driving element layer disposed below the pixel definition film and including a transistor, and a conductive pattern disposed below the separator, filling the through holes and electrically connecting the cathode and the transistor.

[0033] On a plan view, the through hole may entirely overlap the separator.

[0034] On a plane, the conductive pattern may be in the form of a closed line surrounding each of the light emitting portions along the shape of the separator.

[0035] The light emitting portion may include a first light emitting portion, a second light emitting portion, and a third light emitting portion spaced apart from each other on a plane, and the conductive pattern may include a first conductive pattern surrounding the first light emitting portion, a second conductive pattern surrounding the second light emitting portion, and a third conductive pattern surrounding the third light emitting portion, and each of the first conductive pattern, the second conductive pattern, and the third conductive pattern may have a closed line shape on a plane.

[0036] The conductive pattern may include a contact portion filling the through hole, and an extension portion connected to the contact portion and disposed between the pixel defining layer and the separator, and the extension portion may be connected to the cathode.

[0037] The cathode may be disposed directly on the side or top surface of the extension.

[0038] The greater the spacing between adjacent light emitting portions, the thinner the intermediate layer adjacent to the conductive pattern may be.

[0039] The cathode is connected to an upper surface of the conductive pattern exposed below the separator, and the contact area of ​​the cathode with the upper surface of the conductive pattern may increase as the spacing between adjacent light emitting units increases. Effect of the Invention

[0040] In one embodiment, the display device may exhibit improved resolution characteristics by arranging a conductive pattern connecting a pixel circuit unit and a light-emitting element under a separator, thereby minimizing the space required to arrange a separate contact structure for connecting the light-emitting element and the pixel circuit unit. [Brief description of the drawings]

[0041] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 2a] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment. [Figure 2b] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment. [Figure 3a] FIG. 2 is a plan view of a display panel according to an embodiment. [Figure 3b] FIG. 2 is a plan view of a display panel according to an embodiment. [Figure 4a] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment; FIG. [Figure 4b] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment; FIG. [Figure 4c] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment; FIG. [Figure 5a] 1 is a cross-sectional view of a display panel according to an embodiment. [Figure 5b] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 5c] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 6a] 1 is a cross-sectional view of a display panel according to an embodiment. [Figure 6b]2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 7a] FIG. 2 is a cross-sectional view of a display panel according to an embodiment. [Figure 7b] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 7c] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 8a] 1 is a cross-sectional view of a display panel according to an embodiment. [Figure 8b] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 9] 2 is an enlarged plan view showing a partial area of ​​a display panel according to an embodiment; FIG. [Figure 10a] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 10b] 2 is an enlarged cross-sectional view showing a partial area of ​​a display panel according to an embodiment; [Figure 11] 2 is an enlarged plan view showing a partial area of ​​a display panel according to an embodiment; FIG. [Figure 12] 2 is an enlarged plan view showing a partial area of ​​a display panel according to an embodiment; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Since the present invention can be modified in various ways and can have various forms, specific embodiments are shown in the drawings and described in detail in the text, but it is not intended to limit the present invention to the specific disclosed forms, but it should be understood that the present invention includes all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

[0043] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on" or "coupled" to another component, it means that it may be directly disposed, coupled, or connected to the other component, or that a third component may be disposed therebetween.

[0044] On the other hand, in this application, "directly disposed" may mean that there is no additional layer, film, region, plate, etc. between one layer, film, region, plate, etc. and another portion. For example, "directly disposed" may mean disposed between two layers or two members without the use of an additional member, such as an adhesive member, between the two layers or two members.

[0045] The same reference numerals refer to the same components. Also, in the drawings, thicknesses, ratios, and dimensions of the components are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all combinations of one or more defined by the related configuration.

[0046] Terms such as "first" and "second" are used to describe various components, but the components are not limited to these terms. The terms are used only to distinguish one component from another. For example, the first component may be named the second component without departing from the scope of the present invention, and similarly, the second component may be named the first component. A singular surface includes a plural expression unless the context clearly indicates otherwise.

[0047] In addition, terms such as "under," "below," "on," and "above" are used to explain the relationship of components shown in the drawings. The terms are relative concepts and are explained based on the directions shown in the drawings. In this specification, "disposed on" refers to being disposed not only above but also below any one component.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms that are commonly used and defined in dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless expressly defined herein.

[0049] It should be understood that the terms "comprise" or "have" specify the presence of any feature, numeral, step, operation, component, part, or combination thereof described hereinabove in the specification, but do not preclude the presence or additional possibility of one or more other features, numerals, steps, operations, components, parts, or combinations thereof.

[0050] Hereinafter, a display device according to an embodiment will be described with reference to the drawings.

[0051] FIG. 1 is a block diagram of a display device DD according to an embodiment. Referring to FIG. 1, the display device DD may include a display panel DP, a panel driver SDC, EDC, DDC, a power supply unit PWS, and a timing controller TC. In an embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In the following embodiment, an organic light-emitting display panel will be taken as an example for detailed description. The panel driver SDC, EDC, DDC may include a scan driver SDC, an emission driver EDC, and a data driver DDC.

[0052] The display panel DP may include scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm. The display panel DP may include a plurality of pixels connected to the scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm (where m and n are integers greater than 1). For example, a pixel PXij (where i and j are integers greater than 1) located on the ith horizontal line (or the ith row) and the jth vertical line (or the jth pixel column) may be connected to the ith first scan line (or write scan line) GWLi, the ith second scan line (or compensation scan line) GCLi, the ith third scan line (or the first initialization scan line) GILi, the ith fourth scan line (or the second initialization scan line) GBLi, the ith fifth scan line (or reset scan line) GRLi, the jth data line DLj, and the ith emission line ESLi.

[0053] The pixel PXij may include a plurality of light emitting elements, a plurality of transistors, and a plurality of capacitors. The pixel PXij may be supplied with a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (or reference voltage) VREF, a fourth power supply voltage (or first initialization voltage) VINT1, a fifth power supply voltage (or second initialization voltage) VINT2, and a sixth power supply voltage (or compensation voltage) VCOMP via a power supply unit PWS.

[0054] The first and second power supply voltages VDD and VSS are set to a voltage value such that a current flows through the light emitting device to emit light, For example, the first power supply voltage VDD may be set to a voltage higher than the second power supply voltage VSS.

[0055] The third power supply voltage VREF may be a voltage for initializing a gate of a driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to realize a predetermined gray scale by using a voltage difference with the data signal. To this end, the third power supply voltage VREF may be set to a predetermined voltage within the voltage range of the data signal.

[0056] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage higher than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the present invention is not limited thereto.

[0057] The fifth power supply voltage VINT2 may be a voltage for initializing the cathode of the light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or may be set to a voltage similar to or the same as the third power supply voltage VREF, but is not limited thereto. The fifth power supply voltage VINT2 may be set to a voltage similar to or the same as the first power supply voltage VDD.

[0058] The sixth power supply voltage VCOMP may provide a predetermined current to the drive transistor in compensating for the threshold voltage of the drive transistor.

[0059] 1, the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, and VCOMP are all supplied from the power supply unit PWS, but the present invention is not limited thereto. For example, the first power supply voltage VDD and the second power supply voltage VSS are all supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied in accordance with the structure of the pixel PXij.

[0060] In the embodiment of the present invention, the signal lines connected to the pixels PXij can be variously set in accordance with the circuit structure of the pixels PXij.

[0061] The scan driver SDC receives a first control signal SCS from the timing controller TC, and can supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0062] The scan signal may be set to a voltage at which the transistor to which the scan signal is supplied is turned on. For example, the scan signal supplied to a P-type transistor may be set to a logic low level, and the scan signal supplied to an N-type transistor may be set to a logic high level. Hereinafter, the meaning of "a scan signal is supplied" may be interpreted as the scan signal being supplied to a logic level that turns on the transistor controlled by the scan signal.

[0063] 1, for convenience of explanation, the scan driver SDC is shown as a single configuration, but the present invention is not limited thereto. According to an embodiment, a plurality of scan drivers may be included for supplying scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn, respectively.

[0064] The light emitting driver EDC may provide light emitting signals to the light emitting lines ESL1 to ESLn in response to the second control signal ECS. For example, the light emitting signals may be sequentially provided to the light emitting lines ESL1 to ESLn.

[0065] In the present invention, the transistors connected to the light emitting lines ESL1 to ESLn may be N-type transistors. In this case, the light emitting signals provided to the light emitting lines ESL1 to ESLn may be set to a gate open voltage. The transistors receiving the light emitting signals may be turned off when the light emitting signals are provided, and may be turned on otherwise.

[0066] The second control signal ECS includes a light emission start signal and a clock signal, and the light emission driver EDC may be implemented as a shift register that sequentially shifts the pulse-shaped light emission start signal using the clock signal to sequentially generate and output the pulse-shaped light emission signals.

[0067] The data driver DDC may receive a third control signal DCS and image data RGB from the timing controller TC. The data driver DDC may convert the digital image data RGB into an analog data signal (i.e., data voltage). The data driver DDC may provide data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0068] The third control signal DCS may include a data enable signal instructing output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register for shifting the horizontal start signal in synchronization with the data clock signal to generate a sampling signal, a latch for latching image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) for converting the latched image data (e.g., data in a digital form) into an analog data signal, and a buffer (or amplifier) ​​for outputting the data signal to the data lines DL1 to DLm.

[0069] The power supply unit PWS may supply a first power supply voltage VDD, a second power supply voltage VSS, and a third power supply voltage VREF to the display panel DP for driving the pixels PXij, and may also supply at least one of a fourth power supply voltage VINT1, a fifth power supply voltage VINT2, and a sixth power supply voltage VCOMP to the display panel DP.

[0070] As an example, the power supply unit PWS may supply the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP via a first power supply line VDL (see FIG. 2a), a second power supply line VSL (see FIG. 2a), a third power supply line VRL (or a reference voltage line, see FIG. 2a), a fourth power supply line VIL1 (or a first initialization voltage line, see FIG. 2a), a fifth power supply line VIL2 (or a second initialization voltage line, see FIG. 2a), and a sixth power supply line VCL (or a compensation voltage line, see FIG. 2a), which are not shown in the figure.

[0071] The power supply unit PWS may be implemented as, but is not limited to, a power management integrated circuit.

[0072] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal, etc. The first control signal SCS may be supplied to the scan driver SDC, the second control signal ECS may be supplied to the emission driver EDC, the third control signal DCS may be supplied to the data driver DDC, and the fourth control signal PCS may be supplied to the power driver PDC. The timing controller TC may realign the input image data IRGB in response to an arrangement of the pixels PXij in the display panel DP to generate image data RGB (or frame data).

[0073] Meanwhile, the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply PWS, and / or the timing controller TC may be directly formed on the display panel DP or may be provided in the form of a separate driver chip and connected to the display panel DP. Also, at least two of the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply PWS, and the timing controller TC may be provided as one driver chip. For example, the data driver DDC and the timing controller TC may be provided as one driver chip.

[0074] Although the display device DD according to an embodiment has been described with reference to FIG. 1, the display device of the present invention is not limited thereto. Signal lines may be added or omitted depending on the pixel configuration. Also, the connection relationship between one pixel and the signal lines may be changed. If any one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0075] 2a and 2b are equivalent circuit diagrams of pixels according to an embodiment of the present invention, which exemplarily show equivalent circuit diagrams of pixels PXij and PXij-1 connected to an i-th first scan line GWLi (hereinafter, first scan line) and a j-th data in DLj (hereinafter, data line).

[0076] As shown in Fig. 2a, the pixel PXij may include a light emitting element LD and a pixel driving circuit PDC. The light emitting element LD is connected between the first power line VDL and the pixel driving circuit PDC.

[0077] The pixel driving unit PDC may be connected to a plurality of scan lines GWLi, GCLi, GILi, GBLi, GRLi, data lines DLj, light emitting lines ESLi, and a plurality of power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, VCL. The pixel driving unit PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8, a first capacitor C1, and a second capacitor C2. Hereinafter, the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8 are all N-type transistors. However, the present invention is not limited thereto, and some of the first to eighth transistors T1 to T8 may be N-type transistors and the rest may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be P-type transistors, and is not limited to any one of the embodiments.

[0078] The gate of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL through the light emitting element LD to the second power line VSL in response to the voltage of the first node N1. In this case, the first power supply voltage VDD may be set to a voltage having a higher potential than the second power supply voltage VSS.

[0079] In this specification, "electrically connected between a transistor and a signal line or between transistors" means "the source, drain, and gate of a transistor are integral with the signal line or are connected via a connecting electrode."

[0080] The second transistor T2 may include a gate coupled to the write scan line GWLi, a first electrode coupled to the data line DLj, and a second electrode coupled to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 may be turned on when the write scan signal GW is supplied to the write scan line GWLi to electrically connect the data line DLj to the first node N1.

[0081] The third transistor T3 may be coupled between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be coupled to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through an i-th fifth scan line GRLi (hereinafter, a reset scan line). When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to provide the reference voltage VREF to the first node N1.

[0082] The fourth transistor T4 may be coupled between the third node N3 and the first initialization voltage line VIL1. A first electrode of the fourth transistor T4 may be coupled to the third node N3, and a second electrode of the fourth transistor T4 may be coupled to the first initialization voltage line VIL1 providing the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. A gate of the fourth transistor T4 may receive a first initialization scan signal GI via an i-th third scan line GILi (hereinafter, a first initialization scan line). The fourth transistor T4 may be turned on when the first initialization scan signal GI is provided to the first initialization scan line GILi, and may provide the first initialization voltage VINT1 to the third node N3.

[0083] The fifth transistor T5 may be connected between the compensation power line VCL and the second node N2. A first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP through the compensation voltage line VCL, and a second electrode of the fifth transistor T5 may be connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 may receive a compensation scan signal GC through an i-th second scan line GCLi (hereinafter, a compensation scan line). If the compensation scan signal GC is supplied to the compensation scan line CGLi, the fifth transistor T5 may be turned on to provide the compensation voltage VCOMP to the second node N2, and the threshold voltage of the first transistor T1 may be compensated during the compensation period.

[0084] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. More specifically, a gate of the sixth transistor T6 may receive an emission signal EM through an i-th emission line ESLi (hereinafter, emission line). A first electrode of the sixth transistor T6 may be connected to a cathode of the light emitting element LD by a fourth node N4, and a second electrode of the sixth transistor T6 may be connected to a first electrode of the first transistor T1 by a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. When an emission signal EM is provided to the emission line ESLi, the sixth transistor T6 may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0085] The seventh transistor T7 may be coupled between the second power line VSL and the third node N3. A first electrode of the seventh transistor T7 may be coupled to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the seventh transistor T7 may receive the second power voltage VSS through the second power line VSL. A gate of the seventh transistor T7 may be electrically coupled to the light emitting line ESLi. The seventh transistor T7 may be referred to as a second light emitting control transistor. When the light emitting signal EM is provided to the light emitting line ESLi, the seventh transistor T7 is turned on to electrically couple the second electrode of the first transistor T1 to the second power line VSL.

[0086] Meanwhile, in the present embodiment, the sixth transistor T6 and the seventh transistor T7 are connected to the same emission line ESLi and turned on by the same emission signal EM, but this is merely an example, and the sixth transistor T6 and the seventh transistor T7 may be turned on independently by different signals that are distinct from each other. Also, in the pixel driving unit PDC according to an embodiment of the present invention, one of the sixth transistor T6 and the seventh transistor T7 may be omitted.

[0087] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter, the second initialization scan line), a first power supply connected to the second initialization voltage node VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply a second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to a second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0088] Meanwhile, in this embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be simultaneously turned on by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be simultaneously turned on by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be simultaneously operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be simultaneously turned on / off by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be provided as a substantially single scan line. Thereby, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 may be performed at the same timing. However, this is merely an example and is not limited to any one embodiment.

[0089] In addition, according to the present invention, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 can be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be provided as a substantially single power supply voltage line. In this case, the cathode initialization operation and the compensation operation of the driving transistor can be performed with one power supply voltage, so that the design of the driving unit can be simplified. However, this is shown by way of example, and the embodiment of the present invention is not limited to any one specific embodiment.

[0090] The first capacitor C1 may be disposed between the first node N1 and the second node N2. The first capacitor C1 may store a difference voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0091] The second capacitor C2 may be disposed between the third node N3 and the second power supply VSL. That is, one electrode of the second capacitor C2 may be coupled to the first power supply line VSL to which the first power supply VSS is supplied, and the other electrode of the second capacitor C2 may be coupled to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power supply voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor. The second capacitor C2 may have a higher storage capacitance than the first capacitor C1. Thus, the second capacitor C2 may minimize a voltage change at the third node N3 in response to a voltage change at the first node N1.

[0092] In this embodiment, the light emitting element LD may be connected to the pixel driving part PDC through a fourth node N4. The light emitting element LD may include a first electrode (anode) connected to the first power line VDL and a second electrode (cathode) facing the first electrode (anode). In this embodiment, the light emitting element LD may be connected to the pixel driving part PDC through the cathode. That is, in the pixel PXij according to the present invention, the connection node where the light emitting element LD and the pixel driving part PDC are connected may be the fourth node N4, and the fourth node N4 may correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Thus, the potential of the fourth node N4 may substantially correspond to the cathode potential of the light emitting element LD.

[0093] In detail, the anode of the light emitting element LD may be connected to the first power line VDL and may be applied with the first power supply voltage VDD, which is a static voltage, and the cathode may be connected to the first transistor T1 through the sixth transistor T6. That is, in this embodiment in which the first to eighth transistors T1 to T8 are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if the light emitting element LD is deteriorated, the influence on the transistors constituting the pixel driving unit PDC, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. That is, the amount of change in the driving current due to deterioration of the light emitting element LD may be reduced, and the lifespan may be improved by reducing the afterimage defect of the display panel due to the increase in the usage time.

[0094] Alternatively, as shown in Fig. 2b, the pixel PXij-1 may include a pixel driver PDC-1 including two transistors T1, T2 and one capacitor C1. The pixel driver PDC-1 is connected to the light emitting element LD, the write scan line GWLi, the data line DLj, and the second power line VSL. The pixel driver PDC-1 shown in Fig. 2b may correspond to the pixel driver PDC shown in Fig. 2a with the third to eighth transistors T3 to T8 and the second capacitor C2 omitted.

[0095] Each of the first and second transistors T1 and T2 may be an N-type or P-type transistor. In this embodiment, the first and second transistors T1 and T2 are exemplarily described as N-type transistors.

[0096] The first transistor T1 may include a gate coupled to a first node N1, a first electrode coupled to a second node N2, and a second electrode coupled to a third node N3. The second node N2 may be a node coupled to a first power line VDL, and the third node N3 may be a node coupled to a second power line VSL. The first transistor T1 may be coupled to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0097] The second transistor T2 may include a gate receiving a write scan signal GW via a write scan line GWLi, a first electrode coupled to the data line DLj, and a second electrode coupled to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted via the write scan line GWLi.

[0098] The capacitor C1 may include an electrode coupled to the first node N1 and an electrode coupled to the third node N3, and stores a data signal DATA transmitted to the first node N1.

[0099] The light emitting element LD may include an anode (or a first electrode) and a cathode (or a second electrode). In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving part PDC-1 via the second node N2. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving part PDC-1.

[0100] In this embodiment where the first and second transistors T1 and T2 are N-type transistors, the second node N2 to which the cathode of the light emitting element LD and the pixel driving part PDC-1 are connected may correspond to the drain of the first transistor T1. That is, the gate-source voltage Vgs of the first transistor T1 due to the light emitting element LD may be prevented. As a result, the amount of change in driving current due to deterioration of the light emitting element LD may be reduced, and image retention defects of the display panel due to the increase in usage time may be reduced, thereby improving the lifespan.

[0101] Meanwhile, Figures 2a and 2b show circuits for pixel driving units PDC and PDC-2 according to an embodiment of the present invention, and the display panel according to an embodiment of the present invention is not limited to any one embodiment, and the number and arrangement of transistors and the number and arrangement of capacitors can be designed in various ways as long as the circuit is connected to the cathode of the light emitting element LD.

[0102] 3a and 3b are plan views showing a display panel according to an embodiment of the present invention. Some components are omitted in each of Figs. 3a and 3b. Hereinafter, a description will be given with reference to Figs. 3a and 3b. Referring to Fig. 3a, the display panel DP according to the embodiment is divided into a display area DA and a peripheral area (or non-display area) NDA. The display area DA may include a plurality of light emitting units EP.

[0103] The light emitting portion EP may be an area that is emitted by each pixel PXij (FIG. 1). In detail, each light emitting portion EP may be a portion that corresponds to a light emitting aperture portion OP-PDL (FIG. 5a) described later.

[0104] The peripheral area NDA may be disposed adjacent to the display area DA. In this embodiment, the peripheral area NDA is illustrated as surrounding the edge of the display area DA. However, this is merely an example, and the peripheral area NDA may be disposed on one side of the display area DA or may be omitted.

[0105] In one embodiment, the scan driver SDC and the data driver DDC may be implemented in a display panel DP. In one embodiment, the scan driver SDC may be disposed in a display area DA, and the data driver DDC may be disposed in a peripheral area NDA. The scan driver SDC may overlap at least a part of the light emitting unit EP disposed in the display area DA in a plan view. By disposing the scan driver SDC in the display area DA, the area of ​​the peripheral area NDA may be reduced compared to a conventional display panel in which a scan driver is disposed in the peripheral area, and a display device with a thin bezel may be easily implemented.

[0106] Meanwhile, unlike the illustration of Fig. 3a, the scan driver SDC may be provided in two parts separated from each other. The two scan drivers SDC may be arranged spaced apart on the left and right sides of the center of the display area DA. Alternatively, the scan driver SDC may be provided in a greater number than two, and the present invention is not limited to any one embodiment.

[0107] 3A shows an example of a display panel, and the data driver DDC may be disposed in the display area DA. In this case, a part of the light emitting unit EP disposed in the display area DA may overlap the data driver DDC on a plane.

[0108] In one embodiment, the data driver DDC may be provided in the form of a separate driver independent of the display panel DP and connected to the display panel DP, but this is merely an example, and the data driver DDC may be formed in the same process as the scan driver SDC to configure the display panel DP, and is not limited to any one embodiment.

[0109] As shown in Fig. 3b, the display panel DP may have a length in a first direction DR1 that is longer than a length in a second direction DR2. A plurality of pixels PX11 to PXnm arranged in n-type m columns are exemplarily illustrated in the display area DA. In one embodiment, the display panel DP may include a plurality of pixel driving sections SDC1 and SDC2. The scan driving sections SDC1 and SDC2 are exemplarily illustrated as including a first scan driving section SDC1 and a second scan driving section SDC2 that are spaced apart from each other in the first direction.

[0110] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to other parts of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines of the scan lines GL1 to GLn.

[0111] For ease of explanation, pads PD of the data lines DL1 to DLm are shown in Fig. 3b. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to the data driver DDC (Fig. 3a) via the pads PD.

[0112] According to the present invention, the pads PD may be divided and arranged in the peripheral area NDA at positions spaced apart from each other across the display area DA. For example, some of the pads DP may be arranged on the upper side, i.e., adjacent to the first scan line GL1 of the scan lines GL1 to GLn, and other parts of the pads DP may be arranged on the lower side, i.e., adjacent to the last scan line GLn of the scan lines GL1 to GLn. In this embodiment, the pads PD connected to odd-numbered data lines of the data lines DL1 to DLm may be arranged on the upper side, and the pads PD connected to even-numbered data lines of the data lines DL1 to DLm may be arranged on the lower side.

[0113] Although not shown, the display panel DP may include a plurality of upper data drivers connected to the pads PD arranged on the upper side and / or a plurality of lower data drivers connected to the pads PD arranged on the lower side. However, this is an exemplary description, and the display panel DP may include one upper data driver connected to the pads PD arranged on the upper side and / or one lower data driver connected to the pads PD arranged on the lower side. The pads PD according to an embodiment of the present invention may be arranged on only one side of the display panel DP and connected to a single data driver, and is not limited to any one embodiment.

[0114] Furthermore, as described in FIG. 3a, the display panel DP in FIG. 3b may also have a scan driver and / or a data driver arranged in the display area DA, and accordingly, some of the light emitting units arranged in the display area DA may overlap with the scan driver and / or the data driver in a plane.

[0115] Figures 4a to 4c are plan views showing an enlarged partial area of ​​a display panel according to an embodiment. Figure 4a shows an area in which a total of four light emitting units UT are arranged in two rows and two columns, and Figure 4b shows an enlarged partial area shown in Figure 4a. Figure 4c shows some of the components shown in Figure 4a with some omitted or emphasized parts. Hereinafter, the present invention will be described with reference to Figures 4a and 4c.

[0116] FIG. 4a shows two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. The first row Rk light emitting unit includes light emitting units constituting the first row, first column light emitting unit UT11 and the first row, second column light emitting unit UT12, and the second row Rk+1 light emitting unit includes light emitting units constituting the second row, first column light emitting unit UT21 and the second row, second column light emitting unit UT22. FIG. 4a shows the first row Rk light emitting unit. FIG. 4a to FIG. 4c show a separator SPR, a plurality of light emitting units EP1, EP2, and EP3 arranged in the area partitioned by the separator SPR, driving connection units CD1, CD2, and CD3, through holes TH1, TH2, and TH3, conductive patterns CP1, CP2, and CP3, a first electrode EL1, and a second electrode EL2_1, EL2_2, and EL2_3, among the configurations of a plurality of display panels.

[0117] As described above, each of the light-emitting portions EP1, EP2, and EP3 may correspond to a light-emitting opening OP-PDL described later. That is, each of the light-emitting portions EP1, EP2, and EP3 may be an area in which light is emitted by the light-emitting elements described above, and may correspond to a unit constituting an area displayed on the display panel DP (FIG. 1). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by a light-emitting opening OP-PDL (FIG. 5a) described later, in particular, an area defined by a bottom surface (lower surface) of the light-emitting opening OP-PDL.

[0118] The light emitting units EP1, EP2, and EP3 may include a first light emitting unit EP1, a second light emitting unit EP2, and a third light emitting unit EP3. The first light emitting unit EP1, the second light emitting unit EP2, and the third light emitting unit EP3 may emit light of different colors. For example, the first light emitting unit EP1 may emit red light, the second light emitting unit EP2 may emit green light, and the third light emitting unit EP3 may emit blue light, but the color combination is not limited to this. In addition, at least two or more of the light emitting units EP1, EP2, and EP3 may emit light of the same color. For example, the first to third light emitting units EP1, EP2, and EP3 may all emit blue light or all emit white light.

[0119] Meanwhile, among the light emitting units EP1, EP2, and EP3, the third light emitting unit EP3 displaying light emitted by a third light emitting element may include two sub-light emitting units EP31, EP32 spaced apart from each other in the second direction DR2. However, this is merely an example, and the third light emitting unit EP3 may be provided in a single pattern having an integral shape like the other light emitting units EP1, EP2, or any one of the other light emitting units EP1, EP2 may have a spaced apart sub-light emitting unit, and the embodiment is not limited to any one of the embodiments.

[0120] The first row Rk light-emitting section may include light-emitting sections EP1, EP2, and EP3 constituting the first row, first column light-emitting unit UT11 and the first row, second column light-emitting unit UT12, and the second row Rk+1 light-emitting section may include light-emitting sections EP1, EP2, and EP3 constituting the second row, first column light-emitting unit UT21 and the second row, second column light-emitting unit UT22. A part of the first row Rk light-emitting section and a part of the second row RK+1 light-emitting section may have a symmetrical shape. For example, the first light emitting unit EP1 and the second light emitting unit EP2 of the second row, first column light emitting unit UT21 and the first light emitting unit EP1 and the second light emitting unit EP2 of the first row, first column light emitting unit UT11 may have shapes and arrangements that are line symmetrical with respect to an axis along the second direction DR2, and the third light emitting unit EP3 of the second row, first column light emitting unit UT21 and the third light emitting unit EP3 of the first row, first column light emitting unit UT11 may have shapes and arrangements that are line symmetrical with respect to an axis along the first direction DR1, however, this is merely an example and is not limited to this.

[0121] The first row, first column light emitting unit UT11 will be described below. For ease of explanation, FIG. 4b shows a plurality of second electrodes EL2_1, EL2_2, EL2_3, a plurality of circuit driving parts PDC1, PDC2, PDC3, a plurality of driving connection parts CD1, CD2, CD3, a plurality of through holes TH1, TH2, TH3, and a plurality of conductive patterns CP1, CP2, CP3. The second electrodes EL2_1, EL2_2, EL2_3 can be electrically disconnected by being separated from each other by a separator SPR. In this embodiment, one light emitting unit UT may include three light emitting parts EP1, EP2, EP3. Accordingly, the light emitting unit UT may include three electrodes EL2_1, EL2_2, EL2_3 (hereinafter, first to third cathodes) and three pixel driving parts PDC1, PDC2, PDC3. In addition, in one embodiment, one light emitting unit UT may include three conductive patterns CP1, CP2, CP3 for electrically connecting pixel driving units PDC1, PDC2, PDC3 corresponding to the first to third cathodes EL2_1, EL2_2, EL2_3, respectively, and three through holes TH1, TH2, TH3 disposed in the conductive patterns CP1, CP2, CP3, respectively. However, this is an exemplary illustration, and the number and arrangement of the light emitting units UT may be variously designed and are not limited to any one embodiment. Furthermore, the arrangement of the conductive patterns CP1, CP2, CP3 and the positions and number of the conductive through holes TH1, TH2, TH3 may also be variously designed.

[0122] The first to third pixel driving units PDC1, PDC2, and PDC3 are electrically connected to the light emitting elements constituting the first to third light emitting units EP1, EP2, and EP3, respectively. In this specification, "connected" includes not only a case where they are connected by direct physical contact, but also a case where they are electrically connected.

[0123] Also, as shown in FIG. 4b, each area in which the pixel driving units PDC1, PDC2, and PDC3 are defined on a plane may correspond to a unit in which transistor and capacitor elements that constitute the circuit PDC (FIG. 2a) for driving the light-emitting element of the pixel are repeatedly arranged.

[0124] The first, second, and third pixel driving units PDC1, PDC2, and PDC3 may be sequentially arranged along a first direction DR1. Meanwhile, the arrangement positions of the first, second, and third pixel driving units PDC1, PDC2, and PDC3 may be designed independently of the positions and shapes of the first, second, and third light emitting units EP1, EP2, and EP3.

[0125] For example, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged at positions different from the positions where the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged, or may be designed to have a shape and area different from the shapes of the first to third cathodes EL2_1, EL2_2, and EL2_3, or may be arranged to overlap the positions where the first to third light emitting units EP1, EP2, and EP3 are present, and may be designed to have a shape having an area similar to the area defined by the separator SPR, for example, the first to third cathodes EL2_1, EL2_2, and EL2_3.

[0126] In this embodiment, the first to third pixel driving units PDC1, PDC2, and PDC3 are each shown in a rectangular shape, the first to third light emitting units EP1, EP2, and EP3 are each arranged in a different shape with a smaller area than the rectangular shape, and the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3, but are shown in an irregular shape.

[0127] 4b, the first pixel driver PDC1 may be disposed at a position where it partially overlaps with the first light emitter EP1, the second light emitter EP2, and other adjacent light emitters. The second pixel driver PDC2 may be disposed at a position where it overlaps with the first light emitter EP1, the second light emitter EP2, and the third light emitter EP3. The third pixel driver PDC3 may be disposed at a position where it overlaps with the third light emitter EP3. However, this is merely an example, and the positions of the first to third pixel driver PDC1, PDC2, and PDC3 may be designed in various shapes and arrangements independent of the light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0128] The display device according to an embodiment includes a conductive pattern CP. The conductive pattern CP may be provided in a plurality of patterns.

[0129] In one embodiment, the conductive patterns CP may be provided to correspond to the light emitting units EP1, EP2, and EP3. The conductive patterns CP may be arranged on the lower side of the separator SPR along the shape of the separator SPR. The conductive patterns CP may include a first conductive pattern CP1 arranged adjacent to the first light emitting unit EP1, a second conductive pattern CP2 arranged adjacent to the second light emitting unit EP2, and a third conductive pattern CP1 arranged adjacent to the third light emitting unit EP3. For example, the first to third conductive patterns CP1, CP2, and CP3 may be arranged to surround the corresponding first to third light emitting units EP1, EP2, and EP3, respectively. When viewed from above, the first to third conductive patterns CP1, CP2, and CP3 may have a closed line shape arranged to surround the corresponding first to third light emitting units EP1, EP2, and EP3, respectively.

[0130] However, the embodiment is not limited thereto. In one embodiment, the conductive pattern CP may be disposed under the separator SPR and may be disposed so as to overlap only a part of the separator SPR. In one embodiment, the conductive pattern CP may overlap only a part of the separator SPR on a plane. The shape of the conductive pattern CP may be different from that shown in the figure and may not surround EP1, EP2, and EP3, but may be disposed adjacent to at least one side of the light emitting portions EP1, EP2, and EP3. In other words, each of the conductive patterns CP may be disposed only on one side of each of the light emitting portions EP1, EP2, and EP3, or may be disposed so as to surround only a part of each of the light emitting portions EP1, EP2, and EP3. For example, on a plane, the conductive pattern CP may be linear or have a curved portion.

[0131] Meanwhile, in this specification, "on a plane" or "when viewed from a plane" can mean on a plane parallel to the plane defined by the first direction axis DR1 and the second direction axis DR2.

[0132] The conductive patterns CP may be disposed so as to overlap with the separator SPR on a plane. Each of the conductive patterns CP may be entirely overlapped with the separator SPR, or at least a portion of each of the conductive patterns CP may overlap with the separator SPR on a plane. Meanwhile, in one embodiment, a portion of the conductive pattern CP may be disposed under the separator SPR so as to protrude from an edge of the separator SPR it overlaps. However, the embodiment is not limited thereto, and one edge of the conductive pattern CP may overlap with one edge of the separator SPR it overlaps, or one edge of the conductive pattern CP may be separated from the light emitting unit EP and overlap inside the separator SPR on a plane.

[0133] In one embodiment, two conductive patterns corresponding to each of the two light emitting units may be arranged under the separator SPR that divides the adjacent light emitting units EP1, EP2, and EP3 and is arranged between the two light emitting units. For example, the first conductive pattern CP1 and the second conductive pattern CP2 may be arranged under the separator SPR that divides the first light emitting unit EP1 and the second light emitting unit EP2, the first conductive pattern CP1 and the third conductive pattern CP3 may be arranged under the separator SPR that divides the first light emitting unit EP1 and the third light emitting unit EP3, and the second conductive pattern CP2 and the third conductive pattern CP3 may be arranged under the separator SPR that divides the second light emitting unit EP2 and the third light emitting unit EP3. However, the embodiment is not limited thereto, and when the conductive patterns CP1, CP2, and CP3 are provided so as to be adjacent to only a part of the surfaces of the light emitting units EP1, EP2, and EP3, only one conductive pattern may be arranged under the separator SPR that is arranged between the two light emitting units.

[0134] One conductive pattern CP may electrically connect one of the pixel driving units PDC1, PDC2, and PDC3 to a corresponding light emitting element. In particular, the conductive pattern CP may correspond to a node (the fourth node N4 in FIG. 2a or the second node N2 in FIG. 2b) at which the light emitting element LD (FIG. 2a) is connected to the pixel driving unit (PDC in FIG. 2a or PDC-1 in FIG. 2b).

[0135] The conductive patterns CP1, CP2, and CP3 may be electrically connected to one electrode of a transistor constituting the pixel driving unit PDC. Also, the conductive patterns CP1, CP2, and CP3 may be connected to a second electrode (or cathode EL2, FIG. 5a) of the light emitting element. For example, the contact portion CP-H (FIG. 5b) of the conductive patterns CP1, CP2, and CP3 described below may be connected to the transistor via the driving connection portion CD1, CD2, and CD3, and the extension portion CP-F (FIG. 5b) of the conductive patterns CP1, CP2, and CP3 may be connected to the cathode EL2 (FIG. 5a). In the conductive patterns CP1, CP2, and CP3, the contact portion CP-H (FIG. 5c) may be a portion disposed by filling the through hole TH, and the extension portion CP-F (FIG. 5b) may be a portion connected to the contact portion CP-H (FIG. 5c).

[0136] The first conductive pattern CP1 may connect the light-emitting elements forming the first light-emitting portion EP1 to the first pixel driving unit PDC1, the second conductive pattern CP2 may connect the light-emitting elements forming the second light-emitting portion EP2 to the second pixel driving unit PDC2, and the third conductive pattern CP3 may connect the light-emitting elements forming the third light-emitting portion EP3 to the third pixel driving unit PDC3.

[0137] In detail, the first to third conductive patterns CP1, CP2, and CP3 may connect the first to third cathodes EL2_1, EL2_2, and EL2_3 to the first to third pixel driving units PDC1, PDC2, and PDC3, respectively. The first conductive pattern CP1 may electrically connect the first driving connection unit CD1 connected to the first pixel driving unit PDC1 to the first cathode EL2_1. The second conductive pattern CP2 may electrically connect the second driving connection unit CD2 connected to the second pixel driving unit PDC2 to the second cathode EL2_2. In addition, the third conductive pattern CP3 may electrically connect the third driving connection unit CD3 connected to the third pixel driving unit PDC3 to the third cathode EL2_3.

[0138] The conductive pattern CP1 arranged in the first through hole TH1 connects the light emitting elements forming the first light emitting portion EP1 to the first pixel driving unit PDC1, the conductive pattern CP2 arranged in the second through hole TH2 connects the light emitting elements forming the second light emitting portion EP2 to the second pixel driving unit PDC2, and the conductive pattern CP3 arranged in the third through hole TH3 connects the light emitting elements forming the third light emitting portion EP3 to the third pixel driving unit PDC3. The conductive patterns will be described in more detail later.

[0139] In one embodiment, the driving connection part CD may be a part connected to the pixel driving part PDC. In this embodiment, the driving connection part CD may be connected to one electrode of a transistor constituting the pixel driving part PDC. In particular, the driving connection part CD may be connected to the drain of the sixth transistor T6 shown in FIG. 2a or the drain of the first transistor T1 shown in FIG. 2b. Thus, the position of the driving connection part CD may correspond to the position of a transistor (see TR in FIG. 5a) physically connected to the conductive pattern CP in the pixel driving part.

[0140] The first to third driving connection parts CD1, CD2, and CD3 may be aligned along the first direction DR1. As described above, the first to third driving connection parts CD1, CD2, and CD3 may correspond to the positions of the connection transistors constituting the first to third pixel driving parts PDC1, PDC2, and PDC3, respectively. The connection transistor may be a transistor including a connection node, at which the pixel driving part and the light emitting element are connected, as one electrode in one pixel, and may correspond to, for example, the sixth transistor T6 in FIG. 2a or the first transistor T1 in FIG. 2b. According to the present invention, the shape, position, and arrangement of the pixel driving part in all pixels may be easily configured and designed regardless of the shape, size, and emission color of the light emitting part.

[0141] In one embodiment, a plurality of through holes TH may be defined in the separator SPR so as to overlap each other. As described above, a part of the conductive pattern CP may be disposed in the through hole TH. The conductive pattern CP disposed in the through hole TH may be connected to the pixel driving unit CD.

[0142] In one embodiment, the through hole TH may include first to third through holes TH1, TH2, and TH3. The first to third through holes TH1, TH2, and TH3 may be defined so as not to overlap the light emitting portions EP1, EP2, and EP3 on a plane, but to overlap the separator SPR adjacent to each of the light emitting portions EP1, EP2, and EP3. The first to third through holes TH1, TH2, and TH3 may be defined so as to be spaced apart from an edge of the separator SPR and to overlap the inside of the separator SPR on a plane.

[0143] In Fig. 4a and Fig. 4b, the first through hole TH1 and the second through hole TH2 are shown overlapping with the first driving connection part CD1 and the second driving connection part CD2, respectively. However, the embodiment is not limited thereto, and the first through hole TH1 and the second through hole TH2 may be disposed at various positions of the conductive pattern CP when overlapping with the separator SPR. That is, the arrangement position of the contact part CP-H (Fig. 5b) of the conductive pattern CP for connection with the pixel driving part PDC may be freely selected within the range of overlapping with the separator SPR on a plane. When the first through hole TH1 and the second through hole TH2 are defined at positions not overlapping with the respective driving connection parts CD1 and CD2, the driving connection parts CD1 and CD2 may be extended in the form of a connection wiring and connected to the contact part CP-H (Fig. 5b) located at the first through hole TH1 and the second through hole TH2, respectively. Accordingly, in designing the pixel driving part PDC, restrictions imposed by the position and shape of the light emitting part in the arrangement of the contact part for electrical connection with the light emitting element are reduced, and the degree of freedom in design can be improved.

[0144] Meanwhile, in FIG. 4b and the like, the third through hole TH3 is shown to be separated from the third drive connection part CD3. When the third through hole TH3 overlaps with the separator SPR, it may be partitioned (defined) at various positions. In this case, the third drive connection part CD3 may be connected to the third through hole TH3 in the form of an extended wiring. However, the embodiment is not limited thereto, and the position of the third drive connection part CD3 may be designed to be arranged at a position overlapping the third through hole TH3 on a plane, different from that shown in the drawings.

[0145] Meanwhile, in one embodiment, the remaining portion of the conductive pattern CP extending from the first to third through holes TH1, TH2, and TH3 (the conductive pattern extension portion CP-F (FIG. 5b) described below) may also not overlap with the light emitting portions EP1, EP2, and EP3 in a plane. A portion of the extension portion CP-F (FIG. 5b) of the conductive pattern CP is the portion to which the light emitting element LD (FIG. 5a) is connected, and therefore may be provided at a position that does not overlap with the light emitting aperture OP-PDL.

[0146] That is, the portions of the conductive pattern CP connected to the cathodes EL2_1, EL2_2, and EL2_3 may be disposed at positions spaced apart from the light emitting opening OP-PDL (FIG. 5a) where the entire configuration of the light emitting units EP1, EP2, and EP3 overlap. However, the portions of the conductive pattern CP connected to the cathodes EL2_1, EL2_2, and EL2_3 may be disposed adjacent to the light emitting units EP1, EP2, and EP3, and therefore the conductive pattern CP and the cathodes EL2_1, EL2_2, and EL2_3 may be connected without separate connection wiring or connection pads. In one embodiment, the conductive pattern CP and the cathodes EL2_1, EL2_2, and EL2_3 may be disposed directly without connection wiring or the like, and electrically connected to the light emitting element LD (FIG. 5a) and the corresponding pixel driving unit PDC. Therefore, in the case of one embodiment, no space is required for arranging separate connecting wiring or connection pads, and therefore, the arrangement area of ​​the light-emitting parts EP1, EP2, and EP3 can be expanded or the number of the light-emitting parts EP1, EP2, and EP3 can be increased with the same area of ​​the display area DA, thereby improving the resolution of the display device according to one embodiment.

[0147] 4a, the second row Rk+1 light-emitting portion may be configured with the first row light-emitting units UT11 and UT12 having a shape and arrangement that are symmetrical with respect to an axis along the first direction DR1 or the second direction DR2. In this case, due to the shape and arrangement characteristics of the first row light-emitting units UT11 and UT12, the second row light-emitting units UT21 and UT22 may be configured with a light-emitting portion in a form in which the first row light-emitting units UT11 and UT12 are substantially shifted in the first direction DR1 or the second direction DR2. In other words, the second row, first column light-emitting unit UT21 may be configured with a light-emitting portion having the same shape as the first row, second column light-emitting unit UT12, and the second row, second column light-emitting unit UT22 may be configured with a light-emitting portion having the same shape as the first row, first column light-emitting unit UT11.

[0148] Meanwhile, referring to Fig. 4c, a first electrode EL1 (hereinafter, anode) of a light emitting element according to an embodiment of the present invention may be provided in common to a plurality of light emitting parts EP1, EP2, and EP3. That is, the anode EL1 may be formed of a single integrated layer over the entire display area DA, and therefore the anode EL1 layer may be disposed overlapping with the separator SPR. Alternatively, the anodes EL1 of the light emitting elements may be formed of independent conductive patterns spaced apart from each other and electrically connected to each other via other conductive layers, and therefore the anode EL1 pattern may be disposed without overlapping with the separator SPR.

[0149] As described above, the first power supply voltage VDD (FIG. 2a) is applied to the anode EL1, and a common voltage may be provided to all the light emitting parts EP1, EP2, and EP3. The anode EL1 may be connected to the first power supply line VDL (FIG. 2a) that provides the first power supply voltage VDD in the peripheral area NDA (FIG. 3a), or may be connected to the first power supply line VDL in the display area DA, and is not limited to any one of the embodiments.

[0150] Meanwhile, a plurality of openings may be defined in the anode EL1 according to the present invention, and the openings may penetrate the anode EL1 layer. The openings in the anode EL1 layer may be disposed at a position that does not overlap with the light-emitting portion EP, and may be defined at a position that generally overlaps with the separator SPR. The openings may facilitate the discharge of gas generated from the organic layer disposed below the anode EL1, for example, from the sixth insulating layer 60 (FIG. 5a) described later. This allows the gas in the organic layer disposed below the light-emitting element to be sufficiently discharged during the manufacturing process of the display panel, and the gas discharged from the organic layer after manufacturing may be reduced, thereby reducing the rate at which the light-emitting element deteriorates.

[0151] According to the present invention, the light emitting element can be easily connected to the pixel driver by changing only the cathode without changing the arrangement or shape of the light emitting element, by including a conductive pattern connecting the light emitting element and the pixel driver and arranging the through hole in which the contact part of the conductive pattern is arranged so as to overlap with the separator. In addition, since an additional contact pad or connecting wire for connecting the cathode of the light emitting element and the pixel driver can be omitted, the design freedom for the arrangement of the pixel driver can be improved, and the resolution can be easily improved by increasing the area of ​​the light emitting part of the display panel or increasing the number of the light emitting parts.

[0152] FIG. 5a is a cross-sectional view of a display panel according to an embodiment. FIG. 5b is an enlarged cross-sectional view of a portion of a display panel according to an embodiment. FIG. 5c is an enlarged cross-sectional view of a portion of a display panel according to an embodiment. FIG. 5a shows a cross-sectional view of a portion corresponding to line I-I' in FIG. 4b. FIG. 5b shows an enlarged cross-sectional view of region AA in FIG. 5a, and FIG. 5c shows an enlarged cross-sectional view of region BB in FIG. 5a. Hereinafter, the present invention will be described with reference to FIGS. 5a and 5c.

[0153] Referring to Fig. 5a, a display panel DP according to an embodiment may include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL. The driving element layer DDL may include a plurality of insulating layers 10, 20, 30, 40, 50, 60 disposed on the base layer BS, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, 60. The conductive patterns and the semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, 60 to configure a pixel driving unit PDC. For ease of explanation, Fig. 5a shows a cross section of any one of the regions in which one light emitting unit is disposed.

[0154] The base layer BS is a member that provides a base surface on which the pixel driving unit PDC is disposed. The base layer BS may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The base layer BS may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiment of the present invention is not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0155] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer and a silicon oxide (SiO x The silicon oxide layer and the amorphous silicon layer may include a base barrier layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymeric resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0156] The polymer resin layer may include a polyimide-based resin. The polymer resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene-based resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Meanwhile, in this specification, a "XX-based" resin means that it contains a functional group of "XX".

[0157] The insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BS may be formed by coating, deposition, etc. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned through multiple lithography processes to form holes in the insulating layer, or to form semiconductor patterns, conductive patterns, signal lines, etc.

[0158] The driving element layer DDL may include first to sixth insulating layers 10, 20, 30, 40, 50, and 60 sequentially stacked on the base layer BS, and a pixel driving unit PDC. FIG. 5a shows one transistor TR and second capacitors C1 and C2 of the pixel driving unit PDC. The transistor TR corresponds to a transistor connected to the light emitting element LD via the driving connection part CD and the conductive pattern CP, that is, a connection transistor connected to a node (the fourth node N4 in FIG. 2a or the second node N2 in FIG. 2b) corresponding to the cathode of the light emitting element LD, and may correspond to the sixth transistor T6 in FIG. 2a or the first transistor T1 in FIG. 2b. Meanwhile, although not shown, other transistors constituting the pixel driving unit PDC may have the same structure as the transistor TR (hereinafter, the connection transistor) shown in FIG. 5a. However, this is merely an exemplary description, and the other transistors constituting the pixel driving unit PDC may have a different structure from the connection transistor TR, and is not limited to any one embodiment. In one embodiment, the transistor TR connected to the conductive pattern CP may be an N-type transistor. However, the embodiment is not limited to this.

[0159] A first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 is illustrated as a single-layer silicon oxide layer. Meanwhile, an insulating layer described below may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer (multiple layer) structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0160] Meanwhile, the first insulating layer 10 may cover the lower conductive layer BCL. That is, the display panel DP may further include a lower conductive layer BCL arranged to overlap the connection transistor TR. The lower conductive layer BCL may block the electric potential due to the polarization phenomenon of the base layer BS from affecting the connection transistor TR. Also, the lower conductive layer BCL may block light incident on the connection transistor TR from below. At least one of an inorganic barrier layer and a buffer layer may be further arranged between the lower conductive layer BCL and the base layer BS.

[0161] The lower conductive layer BCL may include a reflective metal, for example, titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), etc.

[0162] In this embodiment, the lower conductive layer BCL may be connected to the source of the connection transistor TR (or transistor) through the source electrode W1. In this case, the lower conductive layer BCL may be synchronized with the source of the transistor TR. However, this is an exemplary illustration, and the lower conductive layer BCL may be connected to the gate of the transistor TR and synchronized with the gate. Alternatively, the lower conductive layer BCL may be connected to another electrode and a static voltage or a pulse signal may be applied independently. Alternatively, the lower conductive layer BCL may be provided in a form isolated from other conductive patterns. The lower conductive layer BCL according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0163] A transistor TR may be disposed on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2 O 3 However, the semiconductor pattern SP may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0164] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR, which are classified according to the degree of conductivity. The channel region CR may be a portion overlapping the gate electrode GE on a plane. The source region SR and the drain region DR may be portions separated with the channel region CR therebetween. If the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR may be a reduced region. Thus, the source region SR and the drain region DR have a relatively high content of reduced metal compared to the channel region CR. Alternatively, if the semiconductor pattern SP is polycrystalline silicon, each of the source region SR and the drain region DR may be a region doped at a high concentration.

[0165] The source region SR and the drain region DR have relatively high conductivity compared to the channel region CR. The source region SR may correspond to a source electrode of the connection transistor TR, and the drain region DR may correspond to a drain electrode of the connection transistor TR. As shown in FIG. 5a, a separate source electrode pattern W1 and a drain electrode pattern W2 connected to the source region SR and the drain region DR, respectively, may be further provided. In particular, the separate source electrode pattern W1 and the drain electrode pattern W2 may each be integrally formed with one of the lines constituting the pixel driving unit (PDC in FIG. 2a or PDC-1 in FIG. 2b), and are not limited to any one embodiment.

[0166] The second insulating layer 20 may overlap a plurality of pixels in common and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 is a single silicon oxide layer.

[0167] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR. The gate electrode GE may be disposed above the semiconductor pattern SP. However, this is merely an exemplary illustration, and the gate electrode GE may be disposed below the semiconductor pattern SP, and is not limited to any one embodiment.

[0168] The gate electrode GE may include, but is not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or alloys thereof.

[0169] A third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0170] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 of the plurality of conductive patterns W1, W2, CPE1, CPE2, and CPE3 configure a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart with a first insulating layer 10 and a second insulating layer 20 sandwiched therebetween.

[0171] In one embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BCL may have an integral shape, and the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0172] A third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may overlap the second capacitor electrode CPE2 on a plane while being spaced apart from the second capacitor electrode CPE2 with the third insulating layer 30 interposed therebetween. The third capacitor electrode CPE3 may constitute a second capacitor C2 together with the second capacitor electrode CPE2.

[0173] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0174] A source electrode pattern W1 and a drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to a source region SR of the connection transistor TR through a first contact hole CNT1, and the source region SR of the source electrode pattern W1 and the semiconductor pattern SP may function as a source of the connection transistor TR. The drain electrode pattern W2 may be connected to a drain region DR of the connection transistor TR through a second contact hole CNT2, and the drain electrode pattern W2 and the semiconductor pattern SP may function as a drain of the connection transistor TR. A fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2. A contact hole 50-H may be defined in the fifth insulating layer 50. Meanwhile, in this specification, the fifth insulating layer 50 may also be referred to as a lower insulating layer, and the contact hole 50-H defined in the fifth insulating layer 50 may be referred to as a lower hole.

[0175] A driving connection part CD may be disposed on the fifth insulating layer 50. The driving connection part CD may be disposed by filling a contact hole 50-H defined in the fifth insulating layer 50. In one embodiment, the pixel driver PDC and the light emitting element LD may be electrically connected through the driving connection part CD and the conductive pattern CP disposed on the driving connection part CD. That is, the driving connection part CD may be included as a part that electrically connects the connection transistor TR and the light emitting element LD. The driving connection part CD may be a connection node that connects the pixel driver PDC and the light emitting element LD connected through the conductive pattern CP. That is, the driving connection part CD may correspond to the fourth node N4 (FIG. 2a) shown in FIG. 2a or the second node N2 (FIG. 2b) shown in FIG. 2b. However, this is merely an exemplary description, and as long as the driving connection part CD can be connected to the light emitting element LD, it may be defined as a connection node with various elements among elements constituting the pixel driver PDC according to the design of the pixel driver PDC, and is not limited to any one embodiment.

[0176] The drive connection portion CD may have a three-layer structure. Specifically, the drive connection portion CD may include a first layer L1, a second layer L2, and a third layer L3, which are stacked in sequence along the third direction DR3. The second layer L2 may include a different material from the first layer L1. Also, the second layer L2 may include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. Also, the second layer L2 may have a relatively thicker thickness than the third layer L3. The second layer L2 may include a material with high conductivity. In one embodiment, the second layer L2 may include aluminum (Al).

[0177] Meanwhile, the first layer L1 may include a material having a lower etching rate than the second layer L2. That is, the second layer L2 may be made of a material having a higher etching selectivity to the first layer L1. Also, the third layer L3 may include a material having a lower etching rate than the second layer L2. That is, the second layer L2 may be made of a material having a higher etching selectivity to the third layer L3. For example, in one embodiment, the first layer L1 and the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). However, the embodiment is not limited thereto, and the driving connection part CD may have a single layer structure or a laminated structure having a structure different from the above-mentioned combination.

[0178] In Fig. 5a etc., the entire driving connection part CD is shown to be overlapped under the separator SPR. However, the embodiment is not limited thereto. If the pixel driving part PDC etc. is arranged to be spaced apart from the corresponding light emitting part EP without overlapping the separator SPR unlike the illustration in Fig. 5a etc., the driving connection part CD may be arranged in an extended form on the fifth insulating layer 50. In this case, a part of the driving connection part CD arranged on the fifth insulating layer 50 may not overlap with the separator SPR.

[0179] A sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be disposed so as to cover the driving connection portion CD. Meanwhile, in this embodiment, the sixth insulating layer 60 may also be referred to as an upper insulating layer. In one embodiment, each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general-purpose polymer such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), PMMA (polymethylmethacrylate), or PS (polystyrene), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof.

[0180] A through hole 60-H may be defined in the sixth insulating layer 60. The through hole 60-H defined in the sixth insulating layer 60 may correspond to a part of the through hole TH (FIG. 4a, etc.) described above. The through hole 60-H defined in the sixth insulating layer 60 may be referred to as a lower through hole. The lower through hole 60-H may be defined overlapping with the separator SPR. For example, the lower through hole 60-H may completely overlap with the separator SPR.

[0181] Also, the lower through-hole 60-H may overlap the driving connection portion CD and be defined above the driving connection portion CD. The lower through-hole 60-H defined in the sixth insulating layer 60 may be a portion where a part of the conductive pattern CP is disposed. The lower through-hole 60-H may be formed integrally with a through-hole PDL-H defined in a pixel defining film PDL, which will be described later. The lower through-hole 60-H may be integrated with the through-hole PDL-H defined in the pixel defining (defining) film PDL to define a through-hole TH. The conductive pattern CP may be connected to the driving connection portion CD via the through-hole TH.

[0182] A light emitting element layer LDL is disposed on the sixth insulating layer 60. The light emitting element layer LDL may include a pixel defining film PDL, a light emitting element LD, and a separator SPR. The pixel defining film PDL may be an organic layer. For example, the pixel defining film PDL may include general general-purpose polymers such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), PMMA (polymethylmethacrylate), and PS (polystyrene), polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0183] In one embodiment, the pixel defining (defining) film PDL has a property of absorbing light, but may have, for example, a blocking hue. That is, the pixel defining (defining) film PDL may include a black component (black coloring agent). The black component may include a black dye or a black pigment. The black component may include a metal such as carbon black or chromium, or an oxide thereof. The pixel defining (defining) film PDL may correspond to a light blocking pattern having a light blocking property.

[0184] In the pixel defining film PDL, an opening OP-PDL (hereinafter, a light emitting opening) exposing at least a part of a first electrode EL1 described later may be defined. A plurality of light emitting openings OP-PDL may be provided and arranged corresponding to each light emitting element. In the light emitting opening OP-PDL, all components of the light emitting element LD may be arranged overlapping each other, and the light emitting opening OP-PDL may be an area in which holes emitted by the light emitting element LD are displayed. Therefore, the shape of the light emitting portion EP shown in FIG. 4a etc. may substantially correspond to the shape of the light emitting opening OP-PDL on a plane.

[0185] A through hole PDL-H may be defined in the pixel definition (definition) film PDL. The through hole defined in the pixel definition (definition) film PDL may be referred to as an upper through hole PDL-H. The upper through hole PDL-H may be defined so as not to overlap with the light emitting opening OP-PDL. The upper through hole PDL-H may be defined so as to overlap with the lower through hole 60-H of the sixth insulating layer 60 described above. The lower through hole 60-H and the upper through hole PDL-H may be integrally formed to define a through hole TH. The through hole TH may be filled with a part of the conductive pattern CP. The upper through hole PDL-H may overlap with the separator SPR.

[0186] The light-emitting element layer LDL includes a light-emitting element LD, and the light-emitting element LD may include a first electrode EL1, an intermediate layer IML, and a second electrode layer EL2. The first electrode EL1 may be a semi-transmissive, transmissive, or reflective electrode. According to an embodiment of the present invention, the first electrode EL1 may include a reflective layer made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer disposed on the reflective layer. The transparent or semi-transparent electrode layer may be made of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 For example, the first electrode EL1 may include a stacked structure of ITO / Ag / ITO.

[0187] In one embodiment, the first electrode EL1 may be an anode of the light emitting element LD. That is, the first electrode EL1 may be connected to the first power supply line VDL (FIG. 2a) and may be applied with the first power supply voltage VDD (FIG. 2a). The first electrode EL1 may be connected to the first power supply line VDL in the display area DA (FIG. 3a or 3b) or may be connected to the first power supply line VDL in the peripheral area NDA (FIG. 3a or 3b). In the latter case, the first power supply line VDL may be disposed in the peripheral area NDA (FIG. 3a or 3b) and the first electrode EL1 may have a shape extended to the peripheral area NDA (FIG. 3a or 3b).

[0188] In the cross-sectional view of Fig. 5a, the first electrode EL1 overlaps the light emitting opening OP-PDL and does not overlap the separator SPR, but as described above in Fig. 4c, the first electrode EL1 of the light emitting element may have an integral shape and a mesh or lattice shape in which openings are defined in a part of the shape. In other words, as long as the same first power supply voltage VDD can be applied to the first electrodes EL1 of the plurality of light emitting elements, the shape of the first electrode EL1 may be variously provided and is not limited to any one embodiment.

[0189] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. In one embodiment, the first electrode EL1, the intermediate layer IML, and the second electrode EL2 may be stacked in sequence. The intermediate layer IML may include an emitting layer EML and a functional layer FNL. The light emitting element LD may include an intermediate layer IML having various structures and is not limited to any one embodiment. For example, the functional layer FNL may be provided in a plurality of layers, or may be provided in two or more layers spaced apart with the emitting layer EML therebetween. Alternatively, in one embodiment, the functional layer FNL may be omitted.

[0190] The light emitting layer EML may include an organic light emitting material. The light emitting layer EML may include an inorganic light emitting material or may be a mixed layer of an organic light emitting material and an inorganic light emitting material. In this embodiment, the light emitting layers EML included in each of the adjacent light emitting units EP may include light emitting materials that display different colors. For example, the light emitting layer EML included in each of the light emitting units EP may provide any one of blue, red, and green light. However, the light emitting layers EML disposed in all the light emitting units EP may include light emitting materials that display the same color. In this case, the light emitting layer EML may provide blue light or white light. In addition, FIG. 5a shows an embodiment in which the light emitting layer EML and the functional layer FNL have different shapes, but the light emitting layer EML and the functional layer FNL may be disposed in the same shape on a plane.

[0191] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. In particular, the functional layer FNL may be sub-positioned between the first electrode EL1 and the light-emitting layer EML, or may be disposed between the second electrode EL2 and the light-emitting layer EML. Alternatively, the functional layer FNL may be disposed both between the first electrode EL1 and the light-emitting layer EML and between the second electrode EL2 and the light-emitting layer EML. In this embodiment, the light-emitting layer EML is shown to be inserted in the functional layer FNK. However, this is an exemplary illustration, and the light-emitting layer EML and the functional layer FNL may include a layer disposed between the first electrode EL1 and / or a layer disposed between the light-emitting layer EML and the second electrode EL2, and each may be provided in a plurality of layers, and are not limited to any one embodiment.

[0192] The functional layer FNL can control the transfer of charges between the first electrode EL1 and the second electrode EL2. The functional layer FNL includes a hole injection / transport material and an electron injection / transport material. The functional layer FNL includes at least one of an electron blocking layer, a hole transport layer, a hole injection layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0193] The functional layer FNL may also be disposed on the pixel definition film PDL. The functional layer FNL may be disposed to extend from the light emitting opening OP-PDL onto the pixel definition film PDL so as to connect to one side of the conductive pattern CP.

[0194] The second electrode EL2 may be disposed on the intermediate layer IML. The second electrode EL2 may be disposed on the functional layer FNL, which is modulated and disposed on the pixel definition layer PDL. As described above, the second electrode EL2 may be connected to the conductive pattern CP and electrically connected to the pixel driving part PDC. That is, the second electrode EL2 may be electrically connected to the transistor TR via the conductive pattern CP.

[0195] The display panel DP may include a separator SPR. The separator SPR may be included in the light emitting element layer LDL. The separator SPR may be disposed on the pixel defining layer PDL. In one embodiment, the second electrode EL2 and the intermediate layer IML may be formed by common deposition on a plurality of pixels using an open mask. In this case, the second electrode EL2 and the intermediate layer IML may be divided by the separator SPR. As described above, the separator SPR may have a closed line shape for each light emitting portion, and therefore, the second electrode EL2 and the intermediate layer IML may have a shape divided for each light emitting portion. That is, the second electrode EL2 and the intermediate layer IML may be electrically independent for each adjacent pixel. In one embodiment, the conductive pattern CP may be disposed between the separator SPR and the pixel defining layer PDL, and as shown in FIG. 4a and FIG. 4b, each conductive pattern CP may be disposed to overlap the separator SPR along the shape of the separator SPR that divides the light emitting portion. Also, each of the first to third conductive patterns CP1, CP2, and CP3 may have a separated shape so as to surround the light emitting portion.

[0196] The separator SPR will be described in more detail with reference to Figures 5a to 5c. With reference to Figures 5a to 5c, the width of the upper surface of the separator SPR may be greater than the width of the lower surface. In one embodiment, the separator SPR may include a portion whose cross-sectional width gradually increases in the direction of the third direction axis DR3, which is the thickness direction. For example, the separator SPR may have an inverse tapered shape.

[0197] In one embodiment, the separator SPR may have a double inverse taper shape. Referring to FIG. 5b, the taper angle of the first side TP1 of the separator SPR with respect to the upper surface of the pixel defining film PDL and the taper angle of the second side TP2 of the separator SPR may be different from each other. The taper angles of the first side TP1 and the second side TP2 may be obtuse angles. For example, the taper angle of the first side TP1 with respect to the upper surface of the pixel defining film PDL may be smaller than the taper angle of the second side TP2 with respect to the upper surface of the pixel defining film PDL. However, the embodiment is not limited thereto.

[0198] In addition, in one embodiment, the first side surface TP1 and the second side surface TP2 may be formed to have different curvatures. At least one inflection point may be included between the first side surface TP1 and the second side surface TP2. Meanwhile, the shapes of the first side surface TP1 and the second side surface TP2 are not limited to those shown in the drawings, and the taper angles or curvatures of the first side surface TP1 and the second side surface TP2 may be variously modified.

[0199] In one embodiment, the separator SPR may include a lower pattern SPR-B adjacent to the pixel definition layer PDL and an upper pattern SPR-T disposed on the lower pattern. The upper pattern SPR-T may be disposed continuously on the lower pattern SPR-B. The upper pattern SPR-T and the lower pattern SPR-B may be integrally formed. Meanwhile, the upper pattern SPR-T and the lower pattern SPR-B may be formed so that their side surfaces have different curvatures. For example, an inflection portion may be included between the upper pattern SPR-T and the lower pattern SPR-B. However, this is an exemplary illustration, and the shape of the separator SPR may be variously set as long as the separator SPR can electrically disconnect the second electrode EL2 for each pixel. In one embodiment, the separator SPR may include a material having insulating properties, and may particularly include an organic insulating material. The separator SPR may include an inorganic insulating material, may be configured with multiple layers of an organic insulating material and an inorganic insulating material, or may include a conductive material according to an embodiment. The separator SPR may be a dividing structure that divides the light emitting portion EP and disconnects the second electrodes EL2 of the adjacent light emitting portions EP from each other. In other words, the separator SPR is not particularly limited to a specific type of material as long as the second electrodes EL2 can be electrically disconnected for each pixel.

[0200] In one embodiment, a conductive pattern CP may be disposed below the separator SPR. The conductive pattern CP may include a contact portion CP-H and an extension portion CP-F. In one embodiment, the extension portion CP-F may have a substantially flat upper surface. The extension portion CP-F may have a partially irregular uneven surface within an allowable error range in the process. Depending on the progress of a manufacturing process of the conductive pattern CP or a process of another layer manufactured after the formation of the conductive pattern CP, the extension portion CP-F may include a partially non-flat portion. For example, the upper surface of the extension portion CP-F may include a non-flat portion (roughness).

[0201] The conductive pattern CP may be formed by including a transparent conductive metal material. For example, the conductive pattern CP may be formed by using indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 The conductive layer may include a transparent conductive oxide (TCO) such as a transparent conductive oxide (TCO).

[0202] The contact part CP-H may be a part of the conductive pattern CP that is connected to the pixel driving part PDC and is substantially connected to the connection transistor TR. In one embodiment, the contact part CP-H of the conductive pattern CP may penetrate the pixel defining layer PDL and the sixth insulating layer 60 and be electrically connected to the drain region DR of the semiconductor pattern SP via the driving connection part CD and the drain electrode pattern W2.

[0203] The extension portion CP-F of the conductive pattern CP may be a portion connected to the light emitting element LD. The extension portion CP-F may be a portion disposed on an upper surface of the pixel defining layer PDL. The extension portion CP-F may be disposed under the separator SPR. The conductive pattern CP may include a portion that is exposed without being covered by the separator SPR. The second electrode EL2 may be connected to the exposed conductive pattern extension portion CP-F. That is, the second electrode EL2 of the light emitting element LD may be in direct contact with an exposed end of the conductive pattern extension portion CP-F.

[0204] 5a and 5b, the contact portion CP-H may be disposed by filling the through hole TH, and the extension portion CP-F may be extended from the contact portion CP-H and disposed on the pixel defining layer PDL. That is, the conductive pattern CP may include the contact portion CP-H having one end filled in the through hole TH, and the extension portion CP-F having the other end connected to the second electrode EL2 and thus connected to the contact portion CP-H.

[0205] In one embodiment, the contact portion CP-H may completely overlap the separator SPR. The extension portion CP-F may be disposed below the separator SPR. The extension portion CP-F may be disposed overlapping the separator SPR. In one embodiment, one edge of the extension portion CP-F may be covered by the separator SPR, and the other edge may be not covered by the separator SPR and may be exposed on the pixel defining layer PDL.

[0206] 5a and 5b, one side edge EL-CP of the extension part CP-F exposed on the pixel defining (defining) film PDL may not overlap the separator SPR on a plane, but may be disposed protruding toward the light emitting part EP. However, this is merely an example, and the embodiment is not limited thereto. For example, one side edge EL-CP of the extension part CP-F exposed on the pixel defining (defining) film PDL may overlap the edge EL-SP of the separator SPR on a plane, or may be spaced apart from the edge EL-SP of the separator SPR and overlap the separator SPR on a plane.

[0207] 5c, a second electrode EL2 (hereinafter referred to as a cathode) may be connected to one exposed end of the conductive pattern CP. The cathode EL2 may be connected to one exposed side surface ED-CP of the conductive pattern CP. One side surface ED-EL2 of the cathode EL2 may be connected to the exposed side surface ED-CP of the conductive pattern CP. That is, the cathode EL2 of the light emitting element LD may be connected in the form of a side wall contact to one side surface EL-CP of the conductive pattern CP.

[0208] In the embodiment shown in FIG. 5a and FIG. 5b, the thickness t cp In other words, the thickness t of the extension CP-F of the conductive pattern CP can be 1000 Å or more and 5000 Å or less. cp The thickness t of the conductive pattern CP may be 1000 Å or more and 5000 Å or less. By forming the conductive pattern CP to have a thickness of 1000 Å or more, the sidewall contact area of ​​the cathode EL2 can be sufficiently secured, and the quality of the electrical connection of the cathode EL2 can be secured well. cp The thickness of the light emitting device LD can be minimized by setting the thickness to 5000 Å or less.

[0209] Also, the intermediate layer IML may be connected to one side surface ED-CP of the conductive pattern CP. One side surface ED-FL of the intermediate layer IML may be connected to the exposed side surface ED-CP of the conductive pattern CP. The cathode EL2 may be disposed on the intermediate layer IML connected to the conductive pattern CP while being connected to one side surface EL-CP of the conductive pattern CP. The cathode EL2 may be disposed while covering the intermediate layer IML. Meanwhile, the intermediate layer IML connected to one side surface ED-CP of the conductive pattern CP may be at least a part of the functional layer FNL. The cathode EL2, the exposed upper surface of the conductive pattern CP, the separator SPR, and the like may be covered by the sealing layer ECL. Referring to FIG. 5a and FIG. 5c, the cathode EL2 and the intermediate layer IML constituting the light-emitting element LD may be disconnected by the separator SPR. A first end IML-E1 of the disconnected intermediate layer IML may be connected to one side ED-CP of the conductive pattern CP on the pixel definition film PDL, and the first end IML-E1 and a second end IML-E2 of the disconnected intermediate layer IML may be positioned on the separator SPR.

[0210] Also, the first end EL2-E1 of the disconnected cathode EL2 is connected to one side ED-CP of the conductive pattern CP on the first end IML-E1 of the intermediate layer IML, and the first end EL2-E1 and the second end EL2-E2 of the disconnected cathode EL22 may be disposed on the separator SPR. The second end EL2-E2 of the cathode EL2 may cover the second end IML-E2 of the intermediate layer IML. That is, the first portion including the first end IML-E1 of the disconnected intermediate layer IML and the first end EL2-E1 of the cathode EL2 is connected to one side end of the conductive pattern CP, and the second portion including the second end IML-E2 of the disconnected intermediate layer IML and the second end EL2-E2 of the cathode EL2 may be disposed on the separator SPR.

[0211] 5a to 5c, the first end IML-E1 of the disconnected intermediate layer IML and the first end EL2-E1 of the cathode EL2 may not overlap the separator SPR on a plane. That is, one side end ED-EL2 of the cathode EL2 and one side end ED-FL of the intermediate layer IML connected in a sidewall contact form to one exposed side surface ED-CP of the conductive pattern CP in the embodiment may not overlap the separator SPR on a plane.

[0212] A part of the cathode EL2 and a part of the intermediate layer IML that are disconnected and disposed on the separator SPR may be referred to as a dummy layer UP. The dummy layer UP may be disposed on the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML and may contain the same material as the cathode EL2. The second dummy layer UP2 may be formed in the same process as the cathode EL2 and may contain the same material as the intermediate layer IML. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the intermediate layer IML and the cathode EL2. In another embodiment, the display panel DP may not include the dummy layer UP.

[0213] 5a and 5b, the first ends EL2-E1 and IML-E1 of the cathode and intermediate layer may be located on the pixel definition layer PDL, separated from the separator SPR, and the second ends EL2-E2 and IML-E2 of the cathode and intermediate layer may be located on the side of the separator SPR, separated from the first ends EL2-E1 and IML-E1. On the other hand, even if the first ends EL2-E1 and IML-E1 and the second ends EL2-E2 and IML-E2 are connected without being distinguished from each other, if the thickness of the portion formed along the side of the separator SPR is thin and the electrical resistance is large, if the cathode EL2 is electrically disconnected between adjacent pixels, the cathode EL2 may be considered to be divided by the separator SPR.

[0214] According to the present invention, even if a separate patterning process for the cathode EL2 or the intermediate layer IML is not performed, or is formed thinly on the side of the separator SPR, the cathode EL2 or the intermediate layer IML may be divided for each pixel. Alternatively, as long as the cathode EL2 or the intermediate layer IML is electrically disconnected between adjacent pixels, the shape of the separator SPR may be modified in various ways and is not limited to any one embodiment.

[0215] 5a, an encapsulation layer ECL may be disposed on the light-emitting element layer LDL. The encapsulation layer ECL may cover the light-emitting element LD and cover the separator SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2, which are sequentially stacked. However, the encapsulation layer ECL may further include a plurality of inorganic layers and organic layers. The encapsulation layer ECL may also be a glass substrate.

[0216] The first and second inorganic layers IL1 and IL2 protect the light emitting element LD from moisture and oxygen outside the display panel DP, and the organic layer OL can protect the light emitting element LD from foreign matter such as particles remaining in the process of forming the first inorganic layer IL1. The first and second inorganic layers IL1 and IL2 can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer OL can include an acrylic organic layer, but the type of material is not limited to one of them.

[0217] The sensing layer ISL may sense an external input. In this embodiment, the sensing layer ISL may be formed on the encapsulation layer ECL by a continuous process. In this case, the sensing layer ISL may be expressed as being directly disposed on the encapsulation layer ECL. Disposed directly may mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. In other words, no separate adhesive member may be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is an exemplary illustration, and in the display panel DP according to one embodiment of the present invention, the sensing layer ISL may be formed separately and then coupled to the display panel DP via an adhesive member, and is not limited to any one embodiment.

[0218] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include first to third sensing insulating layers 71, 72, and 73. However, this is merely an exemplary illustration, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0219] Each of the first to third sensing insulation layers 71, 72, and 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The first to third sensing insulation layers 71, 72, and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulation layers 71, 72, and 73 may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0220] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing insulating layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0221] The single-layered sensing conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (ITO), etc. Alternatively, the conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, etc.

[0222] The multi-layered sensing conductive layer may include a metal layer, for example, a titanium (Ti) / aluminum (Al) / titanium (Ti) three-layer structure, or the multi-layered conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0223] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor that senses an external input at the sensing electrode ISL. The sensor may be driven in a capacitive manner, and may be driven by either a mutual capacitance manner or a self-capacitance manner. However, this is an exemplary description, and the sensor may be driven by a resistive film manner, an ultrasonic manner, or an infrared manner other than the capacitive manner, and is not limited to any one of the embodiments.

[0224] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide or may have a metal mesh shape made of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and shapes as long as the visibility of the image displayed by the display panel DP is not reduced, and are not limited to any one embodiment.

[0225] Fig. 6a is a cross-sectional view of a display panel according to an embodiment. Fig. 6b is an enlarged cross-sectional view of a portion of a display panel according to an embodiment. Fig. 6a may be a cross-sectional view showing a portion corresponding to Fig. 5a and corresponding to line I-I' of Fig. 4b. Fig. 6b shows an enlarged cross-sectional view of region BB-a of Fig. 6a.

[0226] The display panel DP-a according to one embodiment shown in Figures 6a and 6b differs from the display panel DP according to one embodiment shown in Figures 5a to 5c only in the connection position of the conductive pattern CP and the second electrode EL2 (hereinafter referred to as the cathode).

[0227] In the display panel DP-a according to an embodiment shown in Figures 6a and 6b, the cathode EL2 of the light emitting element LD may be connected in the form of side wall contact to one side EL-CP of the conductive pattern CP. Also, the intermediate layer IML may be connected to one side ED-CP of the conductive pattern CP. One side ED-FL of the intermediate layer IML may be connected to the exposed side ED-CP of the conductive pattern CP.

[0228] The cathode EL2 may be disposed on the intermediate layer IML connected to the conductive pattern CP while being connected to one side surface EL-CP of the conductive pattern CP. The cathode EL2 may be disposed while covering the intermediate layer IML.

[0229] In one embodiment, the contact portion CP-H may completely overlap the separator SPR. The extension portion CP-F may be disposed below the separator SPR. In one embodiment, one edge of the extension portion CP-F may be covered by the separator SPR, and the other edge may not be covered by the separator SPR and may be exposed above the pixel defining film PDL. Meanwhile, unlike the embodiment shown in Figures 5a to 5c, in the embodiment shown in Figures 6a and 6b, one edge EL-CP of the extension portion CP-F exposed above the pixel defining film PDL may overlap the separator SPR on a plane.

[0230] 6a and 6b, the first end IML-E1 of the disconnected intermediate layer IML and the first end EL2-E1 of the cathode EL2 may overlap the separator SPR on a plane. That is, one side end ED-EL2 of the cathode EL2 and one side end ED-FL of the intermediate layer IML, which are connected in a form of sidewall contact with one exposed side ED-CP of the conductive pattern CP in the embodiment, may overlap the separator SPR on a plane.

[0231] As described above, the display device according to the embodiment may include a conductive pattern CP having a separator SPR disposed therebelow. The conductive pattern CP may be disposed between the cathode EL2 and the driving connection part CD, and may electrically connect the light emitting element LD and the pixel definition film PDC. That is, the conductive pattern CP is directly connected to each of the cathode EL2 and the driving connection part CD, and therefore, a separate connection wire or connection pad for connecting the light emitting element LD and the transistor TR is not required, and the area of ​​the light emitting part EP in the display region may be increased. In addition, since no space is required for arranging a separate connection wire or connection pad, the degree of freedom in arranging the light emitting part EP is increased, and the number of the light emitting parts EP may be increased within the same area, and therefore the resolution of the display device may be improved.

[0232] Hereinafter, a display panel according to an embodiment will be described with reference to Figures 7a to 12. In the description of Figures 7a to 12, the contents that overlap with the contents described with reference to Figures 1 to 6b will not be described again, but differences will be mainly described.

[0233] FIG. 7a is a cross-sectional view of a display panel according to an embodiment. FIG. 7b is a cross-sectional view of a part of a display panel according to an embodiment, which is enlarged. FIG. 7c is a cross-sectional view of a part of a display panel according to an embodiment, which is enlarged. FIG. 7a may be a cross-sectional view showing a part corresponding to FIG. 5a, which corresponds to a part corresponding to line I-I' in FIG. 4b. FIG. 7b shows an enlarged cross-sectional view of an AA-1 region in FIG. 7a, and FIG. 7c shows an enlarged cross-sectional view of a BB-1 region in FIG. 7a. FIG. 8a is a cross-sectional view of a display panel according to an embodiment. FIG. 8b is a cross-sectional view of a part of a display panel according to an embodiment, which is enlarged. FIG. 8a may be a cross-sectional view showing a part corresponding to FIG. 5a, which corresponds to line I-I' in FIG. 4b. FIG. 8b shows a cross-sectional view of an enlarged BB-1a region in FIG. 8a.

[0234] The display panels DP-1 and DP-1a according to an embodiment shown in Figures 7a and 8b below differ from the display panels DP and DP-a according to an embodiment shown in Figures 5a to 6b in the connection form between the conductive pattern CP and the second electrode EL2 (hereinafter referred to as the cathode).

[0235] As described with reference to Figures 5a to 6b, the pixel driver PDC and the light emitting element LD may be electrically connected by the conductive pattern CP in the display panels DP-1 and DP-1a according to an embodiment shown in Figures 7a and 8b, etc. The cathode EL2 of the light emitting element LD is connected to the conductive pattern CP, and therefore the cathode EL2 may be electrically connected to the transistor TR through the conductive pattern CP.

[0236] The contact part CP-H may be a part of the conductive pattern CP that is connected to the pixel driving part PDC and is substantially connected to the connection transistor TR. In one embodiment, the contact part CP-H of the conductive pattern CP may penetrate the pixel defining layer PDL and the sixth insulating layer 60 and be electrically connected to the drain region DR of the semiconductor pattern SP via the driving connection part CD and the drain electrode pattern W2.

[0237] The extension portion CP-F of the conductive pattern CP may be a portion connected to the light emitting element LD. The extension portion CP-F may be a portion disposed on the upper surface of the pixel defining film PDL. The extension portion CP-F may be disposed below the separator SPR. The conductive pattern CP may include a portion that is exposed without being covered by the separator SPR. The second electrode EL2 may be connected to the exposed conductive pattern extension portion CP-F. That is, the second electrode EL2 of the light emitting element LD may be directly contacted with the exposed end of the conductive pattern extension portion CP-F.

[0238] 7a and 8b, the contact portion CP-H may be disposed to fill the through hole TH, and the extension portion CP-F may be extended from the contact portion CP-H and disposed on the pixel definition film PDL. The through hole TH may completely overlap the separator SPR. Thus, the contact portion CP-H may be disposed to overlap the separator SPR.

[0239] 7a and 8b, the cathode EL2 may be connected to one exposed end of the conductive pattern CP. The cathode EL2 may be connected to the upper surface CP-US of one exposed side of the conductive pattern CP. That is, the cathode EL2 of the light emitting element LD may be connected in the form of bottom contact to the upper surface CP-US of one side of the conductive pattern CP. In addition, the edge of the cathode EL2 may be disposed closer to the through hole TH than the edge of the functional layer FNL included in the intermediate layer IML.

[0240] In one embodiment, the thickness t cp1 That is, the thickness t of the extension CP-F of the conductive pattern CP may be 500 Å or less. cp1 The thickness t of the extension CP-F may be less than or equal to 500 Å. cp1 may be an average thickness reflecting a rough surface. By forming the conductive pattern CP to have a thickness of 500 Å or more, the bottom contact area of ​​the cathode EL2 is sufficiently secured, and the quality of the electrical connection of the cathode EL2 can be secured favorably. That is, by forming the conductive pattern CP to have a thickness of 500 Å or less, the step of the conductive pattern CP is minimized, and the intermediate layer IML and the cathode EL2 can be extended and easily disposed on the conductive pattern CP. In addition, the thickness t of the conductive pattern CP may be 500 Å or less. cp1 For example, the thickness t of the conductive pattern CP may be set to a sufficient thickness to electrically connect the cathode EL2 and the driving connection portion CD. cp1 can be 30 Å or more, but this is not a limiting example.

[0241] In the embodiment shown in Figs. 7a to 8b, the separator SPR may have a double inverse tapered shape. As described with reference to Fig. 5b, the taper angle of the first side TP1 of the separator SPR and the taper angle of the second side TP2 of the separator SPR with respect to the upper surface of the pixel defining layer PDL may be different from each other. In addition, in one embodiment, the first side TP1 and the second side TP2 may be formed to have different curvatures from each other. An inflection portion may be included between the first side TP1 and the second side TP2. The shapes of the first side TP1 and the second side TP2 are not limited to those shown in the drawings, and the taper angles or curvatures of the first side TP1 and the second side TP2 may be variously modified.

[0242] The separator SPR may include a lower pattern SPR-B adjacent to the pixel defining layer PDL, and an upper pattern SPR-T disposed on the lower pattern. The upper pattern SPR-T may be disposed continuously on the lower pattern SPR-B. The upper pattern SPR-T and the lower pattern SPR-B may be integrally formed. Meanwhile, the upper pattern SPR-T and the lower pattern SPR-B may be formed so that their side surfaces have different curvatures. For example, at least one inflection may be included between the upper pattern SPR-T and the lower pattern SPR-B. The upper pattern SPR-T has a cross section whose width gradually increases in the thickness direction, and the side surface of the upper pattern SPR-T may show a curved surface in a continuous state. Meanwhile, the lower pattern SPR-B may have a width that decreases from the pixel defining layer PDL toward the upper pattern SPR-T, or may have a width that is substantially unchanged in the thickness direction. That is, the upper pattern SPR-T and the lower pattern SPR-B may include side surfaces having different curvatures.

[0243] However, in one embodiment of Figures 7a to 8b, the shape of the separator SPR shown is an exemplary illustration, and the shape can be set in various ways as long as the separator SPR can electrically disconnect the cathode EL2 for each pixel.

[0244] 7a to 8b, a portion of the extension CP-F of the conductive pattern CP, which is provided with a small thickness so that the cathode EL2 can be sufficiently connected, may include a portion that is not covered by the cathode EL2 and the separator SPR. The exposed portion of the extension CP-F of the conductive pattern CP may be covered by the first inorganic layer IL1 of the sealing layer.

[0245] An intermediate layer IML may be connected to an upper surface CP-US of the conductive pattern CP1 exposed without being covered by the separator SPR. A cathode EL2 may be disposed on the intermediate layer IML connected to the conductive pattern CP while being connected to one side upper surface CP-US of the conductive pattern CP. The cathode EL2 may be disposed while covering the intermediate layer IML. The intermediate layer IML is adjacent to the light emitting portion EP and directly connected to the upper surface CP-US of the conductive pattern CP exposed below the separator SPR, and the cathode EL2 covers the intermediate layer IML and extends beyond the intermediate layer IML so that one side end portion is directly connected to the upper surface CP-US of the conductive pattern CP.

[0246] Meanwhile, the intermediate layer IML connected to one side of the upper surface CP-US of the conductive pattern CP may be a functional layer FNL. The cathode EL2, the exposed upper surface of the conductive pattern CP, the separator SPR, etc. may be covered by a sealing layer ECL.

[0247] 7a and 8b, the cathode EL2 and intermediate layer IML constituting the light emitting element LD may be disconnected by a separator SPR. A first end IML-E1 of the disconnected intermediate layer IML may be connected to an upper surface CP-US of one side of the conductive pattern CP on the pixel defining film PDL, and a second end IML-E2 of the intermediate layer IML disconnected from the first end IML-E1 may be disposed on the separator SPR.

[0248] In addition, the first end EL2-E1 of the disconnected cathode EL2 may be connected to one upper surface CP-US of the conductive pattern CP on the first end IML-E1 of the intermediate layer IML, and the first end EL2-E1 and the second end EL2-E2 of the disconnected cathode EL2 may be disposed on the separator SPR. The second end EL2-E2 of the cathode EL2 may cover the second end IML-E2 of the intermediate layer IML.

[0249] The part of the cathode EL2 and the part of the intermediate layer IML that are disconnected and disposed on the separator SPR may be referred to as a dummy layer UP (FIG. 5b). As described with reference to FIGS. 5a and 5b, the part of the cathode EL2 and the part of the intermediate layer IML that are disconnected and disposed on the separator SPR may be formed simultaneously during the formation of the cathode EL2 and the intermediate layer IML of the light-emitting layer, respectively. In an embodiment, the display panel DP may not include the dummy layer UP.

[0250] 7a and 8b, the first ends EL2-E1 and IML-E1 of the cathode and intermediate layer may be located on the conductive pattern CP, separated from the separator SPR, and the second ends EL2-E2 and IML-E2 of the cathode and intermediate layer may be located on the side of the separator SPR, separated from the first ends EL2-E1 and IML-E1. On the other hand, even if the first ends EL2-E1 and IML-E1 and the second ends EL2-E2 and IML-E2 are connected without being distinguished from each other, if the thickness of the portion formed along the side of the separator SPR is thin and the electrical resistance is high, if the cathode EL2 is electrically disconnected between adjacent pixels, the cathode EL2 may be considered to be divided by the separator SPR.

[0251] In the display panel DP-1 according to an embodiment shown in Figures 7a to 7c, the disconnected first end IML-E1 of the intermediate layer IML and the disconnected first end EL2-E1 of the cathode EL2 may overlap the separator SPR on a plane. That is, in one embodiment, the disconnected first end IML-B1 of the intermediate layer IML and the disconnected first end EL2-E1 of the cathode EL2, which are connected in the form of bottom contact at an upper surface CP-US of one side of the conductive pattern CP, may be located below the separator SPR and overlap the separator SPR on a plane.

[0252] The display panel DP-1a according to one embodiment shown in Figures 8a and 8b differs from the display panel DP-1 according to one embodiment shown in Figures 7a to 7c only in the position of connection between the conductive pattern CP and the second electrode EL2 (hereinafter referred to as the cathode).

[0253] In the display panel DP-1a according to an embodiment shown in Figures 8a and 8b, the disconnected first end IML-E1 of the intermediate layer IML and the first end EL2-E1 of the cathode EL2 may not overlap the separator SPR on a plane. That is, in one embodiment, one side edge of the extension part CP-F of the conductive pattern CP may be extended so as not to overlap the separator SPR, and the disconnected first end IML-B1 of the intermediate layer IML and the first end EL2-E1 of the cathode EL2, which are connected in the form of bottom contact at one side upper surface CP-US of the conductive pattern CP, may be separated below the separator SPR and may not overlap the separator SPR on a plane.

[0254] The display device according to the embodiment including the display panels DP-1 and DP-1a according to the embodiment described with reference to Figures 7a to 8b includes a conductive pattern CP disposed under the separator SPR, and the conductive pattern CP is directly disposed on each of the cathode EL2 and the driving connection part CD, so that no separate connection wiring or connection pad is required to connect the light emitting element LD and the transistor TR, and the area (proportion) of the light emitting part EP in the display region can be increased. In addition, since no space is required to arrange separate connection wiring or connection pads, the degree of freedom in the arrangement of the light emitting parts EP is increased, and the number of light emitting parts EP in the same area can be increased, so that the resolution of the display device can be improved.

[0255] Fig. 9 is a plan view showing a part of a display area in a display panel according to an embodiment. Figs. 10a and 10b may each show a cross section corresponding to a part of Fig. 9. Fig. 10a is a cross section showing a part corresponding to line II-II' in Fig. 9, and Fig. 10b is a cross section showing a part corresponding to line III-III' in Fig. 9. Meanwhile, Fig. 9 may be a plan view corresponding to Fig. 4a. Therefore, the contents regarding each configuration described with reference to Figs. 4a to 4c may also be applied to Fig. 9.

[0256] 9 also shows an area in which a total of four light emitting units UT are arranged in two rows and two columns, as in FIG 4a. In FIG 9, the spacing between the third light emitting portions EP3 included in different light emitting units spaced apart from each other in the second direction DR2 may be greater than the spacing between the first light emitting portion EP1 and the second light emitting portion EP2 spaced apart from each other in the second direction DR2.

[0257] Fig. 10a shows a separator SPR arranged between a first light-emitting portion EP1 and a second light-emitting portion EP2 arranged adjacent to each other, and a part of the light-emitting portion EP adjacent thereto, and Fig. 10b shows a separator SPR arranged between a third light-emitting portion EP3 included in a different light-emitting unit, and an adjacent light-emitting portion EP. In Fig. 10a and Fig. 10b, the configuration of the driving element layer DDL and the like is omitted. In the embodiment shown in Fig. 10a and Fig. 10b, the configuration of the driving element layer DDL can be applied in the same manner as that shown in Fig. 5a and the like.

[0258] 10a and 10b, the distance W between the conductive pattern CP disposed below the separator SPR and the light emitting portion EP is 10 mm. S , W L The larger the thickness t 2S , t 2S-L Therefore, the width WC of the cathode EL2, which is directly arranged with the conductive pattern CP, can be reduced. A-S , W.C. A-L becomes larger, and the connection quality of the cathode EL2 can be improved.

[0259] The separation distance W between the light emitting portion EP and the conductive pattern CP shown in FIG. L is the separation distance W between the light emitting portion EP and the conductive pattern CP shown in FIG. S Therefore, in the case of the portion shown in FIG. 10a, the thickness of the intermediate layer IML is t 1S and the thickness t of the part separated from the light emitting part EP and connected to the conductive pattern CP. 2S In the case of the portion shown in FIG. 10b, the thickness of the intermediate layer IML is t 1S-L and the thickness t of the portion separated from the light emitting portion EP and connected to the conductive pattern CP. 2S-L Therefore, in the case shown in FIG. 10b, it is easier to provide the cathode EL2 to cover the intermediate layer IML under the separator SPR than in the case shown in FIG. 10a. Therefore, the difference between the connection width W CA-STherefore, the connection width W of the cathode EL2 in the case shown in FIG. CA-L That is, the connection area of ​​the cathode EL2 in the case shown in Fig. 10b may be larger than the connection area of ​​the cathode EL2 in the case shown in Fig. 10a. Thus, in one embodiment, the area of ​​the cathode EL2 connected to the upper surface of the conductive pattern CP may be increased as the separation distance between adjacent light emitting portions increases.

[0260] Figures 11 and 12 are plan views showing a portion of a display panel according to an embodiment. Figures 11 and 12 may be cross-sectional views showing a portion corresponding to Figure 4a. Figures 11 and 12 show portions of display areas DA-a and DA-b, which correspond to Figure 4a.

[0261] 11 and 12 also show two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. The first row Rk light emitting unit includes light emitting units constituting the first row, first column light emitting unit UT11 and the first row, second column light emitting unit UT12, and the second row Rk+1 light emitting unit includes light emitting units constituting the second row, first column light emitting unit UT21 and the second row, second column light emitting unit UT22. In the embodiment shown in FIGS. 11 and 12, the shape of the light emitting unit including the light emitting units and the shape of the separator are different from those of the embodiment described with reference to FIG. 4a, etc. Therefore, in the embodiment shown in FIGS. 11 and 12, the contents described with reference to FIGS. 1 to 10b may be applied in the same manner, except for the contents related to the shapes of the light emitting units and the separators.

[0262] 11 and 12, each of the light emitting units UT11, UT12, UT21, and UT22 may include a first light emitting portion EP1-a, EP1-b, a second light emitting portion EP2-a, EP2-b, and a third light emitting portion EP3-a, EP3-b.

[0263] The first light-emitting units EP1-a and EP1-b, the second light-emitting units EP2-a and EP2-b, and the third light-emitting units EP3-a and EP3-b may emit light of different colors. For example, the first light-emitting units EP1-a and EP1-b may emit red light, the second light-emitting units P2-a and EP2-b may emit green light, and the third light-emitting units EP3-a and EP3-b may emit blue light, but the color combination is not limited to this. Also, at least two of the light-emitting units may emit light of the same color. For example, the first to third light-emitting units may all emit blue light or all emit white light.

[0264] Meanwhile, in the case of an embodiment shown in Fig. 11, the third light-emitting unit EP3-a may include two sub-light-emitting units EP31 and EP32 spaced apart from each other in the second direction DR2. Also, in the case of an embodiment shown in Fig. 12, the third light-emitting unit EP3-b may be provided as one region, and may be provided with an area larger than each of the first light-emitting unit EP1-b and the second light-emitting unit EP2-b.

[0265] 11 and 12, the first light emitting portion EP1-a, EP1-b, the second light emitting portion EP2-a, EP2-b, and the third light emitting portion EP3-a, EP3-b may each have a rectangular shape with curved (rounded) corners when viewed in a plan view. Also, compared to the shape of the light emitting units shown in Fig. 4a, etc., each light emitting unit may include a light emitting portion and be divided into a rectangular shape according to the shape of each light emitting portion.

[0266] Meanwhile, in the embodiment shown in Fig. 11 and Fig. 12, the separator SPR may be provided along the shape of the light emitting part so as to surround the light emitting part. The conductive patterns CP1, CP2, CP3 connecting the driving connection parts CD1, CD2, CD3 and the light emitting part are provided overlapping the separator SPR, and the through holes TH1, TH2, TH3 in which parts of the conductive patterns CP1, CP2, CP3 are arranged may be arranged overlapping the separator SPR. As described with reference to Fig. 4a to Fig. 8b, the conductive patterns CP1, CP2, CP3 arranged in the through holes TH1, TH2, TH3 are connected to the driving connection parts CD1, CD2, CD3, and parts of the conductive patterns CP1, CP2, CP3 arranged overlapping the separator SPR may be connected to the light emitting element LD (Fig. 5a). That is, even in the embodiment shown in Fig. 11 and Fig. 12, the connection wiring and the connection pad for connecting the pixel driving unit and the light emitting element may be omitted, and the light emitting units EP3-a and EP3-b may be extended and arranged in the portion for arranging them. Also, the separator SPR and the conductive patterns CP1, CP2, and CP3 may be provided according to the shape of the light emitting unit without considering the space for arranging the connection wiring and the connection pad, and a larger number of light emitting units may be arranged within the same area. That is, compared with the arrangement of the light emitting units shown in Fig. 4a, etc., in the display areas DA-a and DA-b shown in Fig. 11 and Fig. 12, the area of ​​the portion where the light emitting units are not arranged in one light emitting unit may be further reduced. As a result, the display device according to the embodiment may realize a high resolution.

[0267] The display device according to the embodiment includes a conductive pattern connecting the cathode of the light emitting element and the pixel driving unit, and the conductive pattern is overlapped with a separator, so that the area for arranging the conductive pattern can be minimized while facilitating electrical connection between the light emitting element and the pixel driving unit. The display device according to the embodiment provides a through hole in which a conductive pattern for electrically connecting the light emitting element and the pixel driving unit is arranged so as to overlap with the separator, and a separate connection wiring and connection pad for connecting the light emitting element and the pixel driving unit can be omitted, so that the arrangement area of ​​the light emitting unit is increased and the degree of freedom in arranging the light emitting unit is increased, thereby exhibiting improved resolution characteristics.

[0268] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or those having ordinary knowledge in the art that various modifications and variations of the present invention can be made without departing from the spirit and technical scope of the present invention as set forth in the claims below.

[0269] Therefore, the technical scope of the present invention should be determined not by the contents described in the detailed description of the specification, but by the claims.

[0270] According to a preferred specific embodiment, it is as follows.

[0271] The background and issues of this case are as follows (i) to (v).

[0272] (i) In an organic light-emitting display panel in which organic light-emitting elements (OLEDs) are arranged, a pixel electrode that is arranged for each sub-pixel and connected to a drive transistor of a pixel circuit is often adopted, in which a common electrode on the upper layer side of the organic light-emitting layer (the side farther from the base substrate and pixel circuit) is arranged on the lower layer side of the organic light-emitting layer (the side near the base substrate and pixel circuit). This is called an inverted OLED structure.

[0273] (ii) Inverted OLEDs are considered to be advantageous in improving stability against oxygen and moisture in the atmosphere, for example, when used as a flexible display panel with a resin base substrate. -Development of air-stable inverted organic electroluminescence devices https: / / www.nhk.or.jp / strl / publica / rd / 145 / 6.html

[0274] (iii) In an inverted OLED, a driving connection structure is required between the pixel electrode located above and the driving end of the pixel circuit located below, which includes a contact hole and a connecting electrode.

[0275] (iv) On the other hand, in order to electrically separate adjacent pixel electrodes, it is also common to provide a separator (SPR) that is overlaid on the pixel definition film (PDL) (for example, Patent Document 1).

[0276] (v) On the other hand, in recent years, there has been an increasing demand for higher definition displays for mobile devices such as smartphones and smart watches. Therefore, the above-mentioned driving connection structure must not impair the area of ​​the light-emitting portion of the organic light-emitting device (OLED), i.e., it should be located in the area of ​​the pixel defining layer (PDL). At the same time, the manufacturing process needs to be as efficient as possible.

[0277] In some specific embodiments of the present application, the following A7 to A9 or A7 to A11 are particularly based on the following A1 to A6.

[0278] A1 The lower first connecting electrode (driving connection part CD) and the upper second connecting electrode (conductive pattern CP) for connecting the driving end of the pixel circuit (drain electrode W2 of the driving transistor T1) to the upper pixel electrode (second electrode EL2) are arranged approximately within the area overlapping with the separator (SPR).

[0279] A2 The first connecting electrode (driving connection part CD) located between the first organic planarization layer (fifth insulating layer 50) and the second organic planarization layer (sixth insulating layer 60) covering it, as well as the first contact hole (contact hole CNT) covered by it, are located within the area where the entirety of the first connecting electrode (driving connection part CD) overlaps with the separator (SPR).

[0280] A3 A pixel defining film (PDL) is located on the second organic planarization layer (sixth insulating layer 60), and a reverse tapered separator (SPR) is located on a flat portion spaced apart from the edge of the pixel defining film (PDL).

[0281] A4 The second connecting electrode (conductive pattern CP) on the upper side is formed in a partial region thereof and is connected to the first connecting electrode (driving connection part CD) through a second contact hole (through hole TH) that penetrates the second organic planarization layer (sixth insulating layer 60) and the pixel defining film (PDL).

[0282] A5 The second connecting electrode (conductive pattern CP) is directly covered by the separator (SPR) at least on the side opposite to the light emitting portion (EP).

[0283] A6 The second connecting electrode (conductive pattern CP) has a portion on the light emitting portion (EP) side that is not directly covered by the separator (SPR) but is covered by the reverse tapered side end face of the separator (SPR).

[0284] A7 For convenience of the manufacturing process, the conductive layer of the pixel electrode (second electrode EL2) and the light-emitting layer (EML) are formed by deposition or the like so as to cover the entire display area, cover the flat upper surface of the separator (SPR), and are discontinuous at the inversely tapered side surface of the separator (SPR).

[0285] The A8 separator (SPR) has a large degree of taper (slope from the vertical) at the bottom and a small degree of taper at the top. In particular, the slope at the top gradually decreases as it goes upward, and at the point where it joins with the top surface, the slope is, for example, less than 15 degrees, less than 10 degrees, or less than 5 degrees.

[0286] A9 As a result of A8 above, the conductive layer of the light-emitting layer (EML) and the pixel electrode (second electrode EL2) is formed on the upper end of the side end surface of the separator (SPR), and protrudes in a tip shape toward the light-emitting layer (EML) side.

[0287] A10 In a preferred example, the side end surface (one side edge EL-CP) of the second connecting electrode (conductive pattern CP) on the side of the light-emitting layer (EML) is located at a position that coincides with or nearly coincides with the tip-shaped protruding end at the upper end of the side end surface of the separator (SPR).

[0288] A11 As a result of A10 above, contact between the second connecting electrode (conductive pattern CP) and the pixel electrode (second electrode EL2) as well as the light-emitting layer (EML) is made only at the side end surface of the second connecting electrode (conductive pattern CP) or only in the vicinity of this side end surface. [Explanation of symbols]

[0289] DD:Display device UT11, UT12, UT21, UT22: Light-emitting units EP, EP1, EP2, EP3: Light-emitting section CD, CD1, CD2, CD3: Drive connection parts CP, CP1, CP2, CP3: Conductive patterns TH, TH1, TH2, TH3: Through hole SPR: Separator

Claims

1. A base layer; a drive element layer disposed on the base layer, the drive element layer including a transistor, a plurality of insulating layers disposed on the transistor, and a drive connection portion electrically coupled to the transistor; a light emitting element layer including a pixel definition film disposed on the driving element layer, the pixel definition film defining a light emitting opening and a through hole not overlapping the light emitting opening, a light emitting element disposed in the light emitting opening, and a separator disposed on the pixel definition film; a conductive pattern including a contact portion disposed under the separator and filling the through hole, and an extension portion connected to the contact portion and disposed on an upper surface of the pixel defining layer, The light-emitting element includes an anode disposed on the driving element layer, an intermediate layer disposed above the anode, and a cathode disposed above the intermediate layer, The contact portion is electrically connected to the driving connection portion, and the extension portion is connected to the cathode on an upper surface of the pixel defining film.

2. The display device according to claim 1 , wherein the through-hole overlaps the separator and is spaced apart from an edge of the separator in a plan view.

3. a side of the extension portion adjacent to the light-emitting opening on the pixel-defining film extends from the separator; The display device according to claim 1 , wherein the cathode is connected to the exposed side surface of the extension.

4. the cathode and the intermediate layer are separated by the separator; The display device described in claim 3, wherein a first end of the disconnected intermediate layer is connected to the one side surface above the first pixel defining film, and a first end of the disconnected cathode is connected to the one side surface above the intermediate layer.

5. The display device according to claim 4 , wherein the first end of the intermediate layer and the first end of the cathode do not overlap the separator in a plan view.

6. The display device according to claim 4 , wherein the first end of the intermediate layer and the first end of the cathode overlap the separator on a plane.

7. the second end of the disconnected intermediate layer is disposed on the separator; 5. The display device of claim 4, wherein the second end of the disconnected cathode is disposed on the separator and on the intermediate layer.

8. The display device according to claim 3 , wherein the extension has a thickness of 1000 Å to 5000 Å.

9. one side end of the extension portion adjacent to the light-emitting opening on the pixel-defining film extends from the separator; The display device of claim 1 , wherein the cathode is connected to an exposed upper surface of the extension at the one side end.

10. the cathode and the intermediate layer are separated by the separator; a first end of the disconnected intermediate layer is disposed directly on the top surface; The display device of claim 9 , wherein a first end of the disconnected cathode is connected to the exposed top surface while covering the intermediate layer above the exposed top surface.

11. The display device according to claim 10 , wherein the first end of the intermediate layer and the first end of the cathode overlap the separator on a plane.

12. The display device according to claim 10 , wherein the first end of the intermediate layer and the first end of the cathode do not overlap the separator in a plan view.

13. the second end of the disconnected intermediate layer is disposed on the separator; The display device of claim 10 , wherein a second end of the disconnected cathode is disposed on the separator and on the intermediate layer.

14. The display device of claim 9, wherein the extension has a thickness of 500 Å or less.

15. The separator is a lower pattern adjacent to the pixel defining film; an upper pattern disposed contiguously on the lower pattern and having a width in cross section greater than a width of the lower pattern; The display device according to claim 1 , wherein in the cross section, a side surface of the separator includes an inflection portion between the lower pattern and the upper pattern.

16. The display device according to claim 1 , wherein the conductive pattern comprises a transparent conductive metal material.

17. 2. The display device of claim 1, wherein the drive connection portion includes a first layer including titanium, a second layer including aluminum arranged on the upper side of the first layer, and a third layer including titanium arranged on the upper side of the second layer, which are stacked in sequence.

18. the transistor includes a semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region; The display device of claim 1 , wherein the conductive pattern is electrically connected to the drain region through the driving connection portion.

19. 2. The display device according to claim 1, wherein the transistor is an N-type transistor.

20. A base layer; a transistor disposed on the base layer; a lower insulating layer disposed over the transistor, the lower insulating layer having a lower hole defined therein; a driving connection portion filling the lower hole and disposed on the lower insulating layer, the driving connection portion being electrically connected to the transistor; an upper insulating layer covering the drive connection portion on the lower insulating layer; a pixel defining film disposed on the upper insulating layer and defining a light emitting opening; a separator disposed on the pixel defining film without overlapping with the light emitting opening; a conductive pattern disposed by filling a through hole defined by penetrating the upper insulating layer and the pixel defining layer and overlapping the separator; a light-emitting element including a light-emitting layer disposed on the upper insulating layer and disposed in the light-emitting opening, a first electrode disposed below the light-emitting layer, a second electrode disposed above the light-emitting layer, and a functional layer disposed at least one of between the first electrode and the light-emitting layer and between the light-emitting layer and the second electrode; A display device, wherein one end of the conductive pattern is connected to the driving connection portion, and the other end of the conductive pattern is connected to the second electrode on the pixel defining film.

21. The conductive pattern is a contact portion filled in the through hole and including the one end; The display device of claim 20 , further comprising: an extension portion connected to the contact portion, including the other end, and disposed on an upper surface of the pixel defining film.

22. the second electrode and the functional layer extending from the light emitting opening toward the separator are disconnected by the separator, a first portion, which is an end portion of the disconnected second electrode and one side of the functional layer, is connected to the other end of the conductive pattern; The display device according to claim 20 , wherein a second portion, which is the other end of the disconnected second electrode and the functional layer, is disposed on the separator.

23. The display device according to claim 22 , wherein in each of the first portion and the second portion, the second electrode is disposed on the functional layer.

24. The display device according to claim 22 , wherein the first portion is disposed directly on a side surface or an upper surface of the other end of the conductive pattern.

25. the first portion includes the functional layer disposed directly on an upper surface of the conductive pattern and a second electrode disposed directly on the functional layer; The display device according to claim 22 , wherein an edge of the second electrode is disposed closer to the through-hole on a planar basis than an edge of the functional layer.

26. the transistor includes a semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region; The display device of claim 20, wherein the conductive pattern electrically connects the drain region and the second electrode through the driving connection portion.

27. A plurality of light emitting units each emitting light of a different wavelength, A separator that divides the light emitting portion; a pixel definition film disposed below the separator, the pixel definition film defining a light-emitting opening in which each of the light-emitting portions is disposed and a through-hole not overlapping the light-emitting opening; a light-emitting element disposed corresponding to each of the light-emitting portions, the light-emitting element including an anode, an intermediate layer disposed above the anode, and a cathode disposed above the intermediate layer; a driving element layer including a transistor and disposed below the pixel definition film; a conductive pattern filling the through hole, electrically connecting the cathode and the transistor, and disposed under the separator.

28. The display device according to claim 27 , wherein the through hole entirely overlaps the separator in a plan view.

29. 28. The display device according to claim 27, wherein, on a plane, the conductive pattern is in the form of a closed line that surrounds each of the light-emitting portions along the shape of the separator.

30. The light emitting unit includes a first light emitting unit, a second light emitting unit, and a third light emitting unit that are spaced apart from each other on a plane, the conductive pattern includes a first conductive pattern surrounding the first light emitting portion, a second conductive pattern surrounding the second light emitting portion, and a third conductive pattern surrounding the third light emitting portion; The display device of claim 29 , wherein each of the first conductive pattern, the second conductive pattern, and the third conductive pattern has a closed line shape on a plane.

31. the conductive pattern includes a contact portion filling the through hole, and an extension portion connected to the contact portion and disposed between the pixel definition film and the separator, 28. The display device of claim 27, wherein the extension and the cathode are connected.

32. 32. The display device of claim 31, wherein the cathode is disposed directly on a side or top surface of the extension.

33. The larger the separation distance between adjacent light emitting units, The display device of claim 31 , wherein the thickness of the intermediate layer adjacent to the conductive pattern is reduced.

34. The cathode is connected to the upper surface of the conductive pattern exposed on the underside of the separator; The display device of claim 31 , wherein the contact area of ​​the cathode with the upper surface of the conductive pattern increases as the distance between adjacent light emitting portions increases.

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