Semiconductor device

Abstract

To avoid voltage input which exceeds a withstand voltage with respect to an internal circuit which assumes signal processing.SOLUTION: An semiconductor device (10) comprises: an input terminal (IN) which receives input voltage (Vin); a voltage dividing circuit (110) which is connected to the input terminal, and has a specific node (115) to which the input voltage is added or a partial pressure of the input voltage is added; a signal generation circuit (120) which is connected to the specific node, and generates a signal according to the voltage of the specific node; a control circuit (130) which controls a state of the voltage dividing circuit to a first state in which the input voltage is added to the specific node or a second state in which the partial pressure of the input voltage is added to the specific node based on setting information; and a forcing partial pressure instruction circuit (140) which is connected to the input terminal, and forcibly controls the state of the voltage dividing circuit to the second state without depending on a control content of the control circuit, when the input voltage is higher than a threshold voltage (Vth).SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] There is a semiconductor device that has an input terminal and performs signal processing according to a voltage input to the input terminal. For example, there is a semiconductor device that monitors whether the input voltage is higher than a predetermined upper limit voltage or lower than a predetermined lower limit voltage, and outputs a signal according to the monitoring result. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-204164 A

[0004] [overview] In this type of semiconductor device, it is necessary to prevent a voltage exceeding the withstand voltage from being input to the internal circuitry responsible for signal processing.

[0005] A semiconductor device according to one embodiment of the present disclosure includes an input terminal configured to receive an input voltage, a voltage divider circuit connected to the input terminal and having a specific node to which the input voltage is applied or a divided voltage of the input voltage is applied, a signal generating circuit connected to the specific node and configured to generate a signal corresponding to the voltage of the specific node, a control circuit configured to control a state of the voltage divider circuit to a first state in which the input voltage is applied to the specific node or a second state in which a divided voltage of the input voltage is applied to the specific node based on setting information, and a forced voltage division instruction circuit connected to the input terminal and configured to forcibly control the state of the voltage divider circuit to the second state regardless of the control content of the control circuit when the input voltage is higher than a threshold voltage. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is an overall configuration diagram of a system according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a configuration diagram of a main part of a semiconductor device according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a modified configuration diagram of a main part of a semiconductor device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a modified configuration diagram of a main part of a semiconductor device according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a configuration diagram of a main part of a semiconductor device according to a first example of an embodiment of the present disclosure. [Figure 6] FIG. 6 is a configuration diagram of a main part of a semiconductor device according to a second embodiment of the present disclosure. [Figure 7] FIG. 7 relates to a third example belonging to an embodiment of the present disclosure and is a corresponding circuit diagram in the case where a semiconductor device is provided with a plurality of input terminals. [Figure 8] FIG. 8 is a modified configuration diagram of a voltage divider circuit in a semiconductor device according to a fifth example of the embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductor may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] A level refers to a level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal of interest, when the signal of interest has a high level, the inverse signal of the signal of interest has a low level, and when the signal of interest has a low level, the inverse signal of the signal of interest has a high level.

[0010] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate can be considered to be short-circuited to the source. Hereinafter, the on state and off state of any transistor may be simply expressed as on and off.

[0011] For any signal having a high or low signal level, the period during which the signal level is high is called a high-level period, and the period during which the signal level is low is called a low-level period. The same applies to any voltage having a high or low voltage level.

[0012] Unless otherwise specified, the connection between multiple parts that form a circuit, such as any circuit elements, wiring, nodes, etc., may be understood to refer to an electrical connection.

[0013] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other equations including physical quantities other than voltage.

[0014] FIG. 1 shows the overall configuration of a system 1 according to an embodiment of the present disclosure. The system 1 includes a semiconductor device 10, an upper device 20, and a bus 30. The semiconductor device 10 and the upper device 20 are connected to each other via a bus 30 composed of a plurality of communication wirings. The semiconductor device 10 and the upper device 20 can perform two-way communication via the bus 30. The bus 30 may be a serial bus or a parallel bus. When the bus 30 is a serial bus, the two-way communication between the semiconductor device 10 and the upper device 20 may be, for example, 2 communication by I2C (Inter-Integrated Circuit) or communication by SPI (Serial Peripheral Interface).

[0015] The upper device 20 is an external device (external circuit) provided outside the semiconductor device 10, and can transmit various commands to the semiconductor device 10 via the bus 30. The semiconductor device 10 can perform operations according to commands from the upper device 20. As described above, any communication between the semiconductor device 10 and the upper device 20 is performed via the bus 30, but the description of the bus 30 may be omitted below.

[0016] The semiconductor device 10 and the upper device 20 are each connected to the ground. A power supply voltage is supplied to each of the semiconductor device 10 and the upper device 20. The power supply voltage is a positive DC voltage. The semiconductor device 10 and the upper device 20 are each driven based on the power supply voltage supplied to itself. The power supply voltage for the semiconductor device 10 and the power supply voltage for the upper device 20 may be different from each other, but in this embodiment, it is assumed that they are a common power supply voltage VDD. That is, the power supply voltage VDD is supplied to each of the semiconductor device 10 and the upper device 20.

[0017] A signal source SS is provided outside the semiconductor device 10. An input voltage Vin is supplied to the semiconductor device 10 from the signal source SS. More specifically, the semiconductor device 10 is provided with an input terminal IN for receiving the input voltage Vin, and the input voltage Vin from the signal source SS is supplied to the input terminal IN. The number of input voltages Vin supplied to the semiconductor device 10 may be one, or may be two or more. When the number of input voltages Vin supplied to the semiconductor device 10 is two or more, the semiconductor device 10 is provided with input terminals IN equal to the number of input voltages Vin, and a corresponding input voltage Vin is supplied to each input terminal IN.

[0018] The semiconductor device 10 has a functional circuit that operates in response to the input voltage Vin. The operation of the functional circuit is arbitrary. In the following, unless otherwise specified, it is assumed that the semiconductor device 10 functions as a voltage monitoring device. In this case, the system 1 can be called a voltage monitoring system 1.

[0019] The semiconductor device 10 (functional circuit) executes a voltage monitoring process for monitoring the level of the input voltage Vin. The voltage monitoring process is performed when the input voltage Vin exceeds a predetermined upper limit voltage VH LIM Upper limit monitoring process monitors whether the input voltage Vin exceeds a predetermined lower limit voltage VL LIM A lower limit monitoring process monitors whether the input voltage Vin falls below the upper limit voltage VH LIM to lower limit voltage VL LIM This is a window monitoring process that monitors whether the voltage falls within the upper limit voltage VH LIM and lower limit voltage VL LIM is set in advance. Upper limit voltage VH LIM and lower limit voltage VL LIM The values ​​of VH are arbitrary, but at least LIM is the lower limit voltage VL LIM For example, the upper limit voltage VH LIM is 3.1V (volts), and the lower limit voltage VL LIM is 2.9V.

[0020] The semiconductor device 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the case to the outside of the semiconductor device 10. The semiconductor device 10 is formed by sealing the semiconductor chip in a case made of resin. Each circuit in the semiconductor device 10 is formed in the semiconductor integrated circuit. The input terminal IN is one of a plurality of external terminals provided in the semiconductor device 10. In addition, the plurality of external terminals also include a power supply terminal that receives a power supply voltage VDD, a ground terminal that is connected to the ground, and communication terminals that are connected to each communication wiring that constitutes the bus 30. The semiconductor device 10 is provided with an internal power supply circuit (not shown) that generates one or more internal power supply voltages based on the power supply voltage VDD, and each circuit in the semiconductor device 10 can be driven based on the internal power supply voltage.

[0021] As described above, the semiconductor device 10 may be provided with two or more input terminals IN, but here, attention is focused on one input terminal IN, and a configuration provided in the semiconductor device 10 corresponding to the focused input terminal IN is shown in FIG. 2. FIG. 2 is a configuration diagram of the main parts of the semiconductor device 10. The semiconductor device 10 includes a voltage dividing circuit 110 and an internal block BLK. The internal block BLK is an internal circuit (a circuit provided inside the semiconductor device 10) that performs signal processing according to the input voltage Vin. A signal generating circuit 120 and a control circuit 130 are provided in the internal block BLK. The control circuit 130 has a memory 131. The semiconductor device 10 further includes a forced voltage division instruction circuit 140 and a drive circuit 150.

[0022] The voltage divider circuit 110 includes two voltage dividing resistors 111 and 112, a transistor 113 that functions as a changeover switch, and a transistor 114 that functions as a short-circuit switch. The transistors 113 and 114 are N-channel MOSFETs. The voltage divider circuit 110 is provided with a node 115 (specific node).

[0023] The resistors 111 and 112 and the transistor 113 are connected in series with each other, and the series circuit of the resistors 111 and 112 and the transistor 113 is provided between the input terminal IN and the ground. The transistor 114 is connected in parallel with the resistor 111. Specifically, a first end of the resistor 111 and a drain of the transistor 114 are connected to the input terminal IN, and a second end of the resistor 1111 and a source of the transistor 114 are connected to a node 115. A first end of the resistor 112 is connected to the node 115, and a second end of the resistor 112 is connected to the drain of the transistor 113. A source of the transistor 113 is connected to the ground. A signal Sd output from the drive circuit 150 is input to the gate of the transistor 114. A signal Se output from the drive circuit 150 is input to the gate of the transistor 113. The voltage at the node 115 is referred to as a voltage Vp.

[0024] Depending on the states (on / off states) of the transistors 113 and 114, the input voltage Vin or a divided voltage of the input voltage Vin is applied to the node 115. That is, the state of the voltage divider circuit 110 is either a direct application state or a divided voltage application state as described below.

[0025] In the direct application state, transistor 113 is off and transistor 114 is on. In the direct application state, input terminal IN is shorted to node 115 through transistor 114, so that the input voltage Vin at input terminal IN is directly applied to node 115. Therefore, in the direct application state, voltage Vp is equal to input voltage Vin.

[0026] In the divided voltage application state, the transistor 113 is on and the transistor 114 is off. The on-resistance value of the transistor 113 is sufficiently smaller than the values ​​of the resistors 111 and 112, so the on-resistance of the transistor 113 is ignored (considered to be zero). Then, in the divided voltage application state, a voltage Vp according to the formula "Vp=Vin×R112 / (R111+R112)" is applied to the node 115. R111 and R112 shown in this formula and in each formula described later represent the values ​​of the resistors 111 and 112, respectively. The voltage Vp in the divided voltage application state is a divided voltage of the input voltage Vin.

[0027] The signal generating circuit 120 is connected to the node 115, and therefore a voltage Vp is input to the signal generating circuit 120. The signal generating circuit 120 generates a signal Sp according to the voltage Vp. The signal generating circuit 120 outputs the generated signal Sp to the control circuit 130. The control circuit 130 can perform various signal processing on the signal Sp. Specific configuration examples and operation examples of the signal generating circuit 120 and the control circuit 130 will be described later, but the above-mentioned voltage monitoring processing is realized by the signal generating circuit 120 and the control circuit 130.

[0028] The voltage monitoring process realized by the signal generating circuit 120 and the control circuit 130 includes a monitoring result output process that outputs the monitoring result signal Sz to an external circuit provided outside the semiconductor device 10. The external circuit that receives the output of the monitoring result signal Sz may be the upper device 20, or may be a circuit other than the upper device 20. The monitoring result output process is performed by the control circuit 130, and the monitoring result signal Sz is generated and output by the control circuit 130. The monitoring result signal Sz indicates the result of monitoring by the voltage monitoring process. For example, an output circuit (not shown) having an open drain configuration is provided in the semiconductor device 10, and the control circuit 130 uses the output circuit to output the monitoring result signal Sz to the external circuit. The monitoring result signal Sz has a value of "1" or "0". The monitoring result signal Sz may be output to the upper device 20 via the bus 30.

[0029] When the voltage monitoring process is the upper limit monitoring process, the control circuit 130 detects that “Vin>VH LIMWhen it is determined that the condition "Vin≦VH" is satisfied, the monitor output signal Sz of "1" is output. LIM When it is determined that the condition "Vin>VH" is satisfied, the monitoring result signal Sz of "0" is output. When the voltage monitoring process is the upper limit monitoring process, the monitoring result signal Sz of "1" is output. LIM " is satisfied, and the monitoring result signal Sz of "0" indicates that "Vin≦VH LIM " is established.

[0030] When the voltage monitoring process is the lower limit monitoring process, the control circuit 130 <VL LIM When it is determined that the condition "Vin ≧ VL" is satisfied, the monitor output signal Sz of "1" is output. LIM When it is determined that the condition "Vin" is satisfied, the monitoring result signal Sz of "0" is output. When the voltage monitoring process is the lower limit monitoring process, the monitoring result signal Sz of "1" is output. <VL LIM " is satisfied, and the monitoring result signal Sz of "0" indicates that "Vin ≧ VL LIM " is established.

[0031] When the voltage monitoring process is a window monitoring process, the control circuit 130 determines whether “Vin>VH LIM " or "Vin <VL LIM When it is determined that the condition "VL" is satisfied, the monitor result signal Sz of "1" is output. LIM ≦Vin≦VH LIM When it is determined that the condition "Vin>VH" is satisfied, a monitoring result signal Sz of "0" is output. When the voltage monitoring process is a window monitoring process, a monitoring result signal Sz of "1" is output. LIM " or "Vin <VL LIM " indicates that the monitoring result signal Sz is "0" LIM ≦Vin≦VH LIM " is established.

[0032] The control circuit 130 also generates and outputs a signal Sa. The signal Sa has a high level or a low level, and is supplied to a logical sum circuit 151, which will be described later.

[0033] The forced voltage division indication circuit 140 includes a comparator 141. The comparator 141 is provided with a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal of the comparator 141 is connected to the input terminal IN and receives the input voltage Vin. A threshold voltage Vth having a predetermined positive DC voltage value (for example, 0.8V) is input to the inverting input terminal of the comparator 141. The threshold voltage Vth is generated within the semiconductor device 10 based on the power supply voltage VDD. The comparator 141 compares the input voltage Vin and the threshold voltage Vth supplied to the non-inverting input terminal and the inverting input terminal, and outputs a signal Sb corresponding to the comparison result from its output terminal. The comparator 141 outputs a high-level signal Sb when the input voltage Vin is higher than the threshold voltage Vth, and outputs a low-level signal Sb when the input voltage Vin is lower than the threshold voltage Vth. That is, the high-level signal Sb indicates the establishment of "Vin > Vth", and the low-level signal Sb indicates the establishment of "Vin < Vth". When "Vin = Vth", the signal Sb becomes high level or low level.

[0034] The drive circuit 150 includes an OR circuit 151 and inverter circuits 152 and 153. The OR circuit 151 is a two-input OR circuit, and the signal Sa from the control circuit 130 and the signal Sb from the comparator 141 are input to the OR circuit 151. The OR circuit 151 generates and outputs the logical sum signal of the signals Sa and Sb as the signal Sc. That is, the OR circuit 151 outputs a low-level signal Sc only when both the signals Sa and Sb have a low level, and outputs a high-level signal Sc when at least one of the signals Sa and Sb has a high level. The signal Sc is supplied to the inverter circuit 152 and the control circuit 130.

[0035] The inverter circuit 152 outputs an inverted signal of the signal Sc as a signal Sd. Therefore, when the signal Sc has a high level, the signal Sd has a low level, and when the signal Sc has a low level, the signal Sd has a high level. The signal Sd is supplied to the inverter circuit 153 and also to the gate of the transistor 114. The inverter circuit 153 outputs an inverted signal of the signal Sd as a signal Se. Therefore, when the signal Sd has a high level, the signal Se has a low level, and when the signal Sd has a low level, the signal Se has a high level. The signal Se is supplied to the gate of the transistor 113.

[0036] During a high-level period of the signal Se, the transistor 113 is on, and during a low-level period of the signal Se, the transistor 113 is off. The low-level of the signal Se has the ground potential. The high-level potential of the signal Se is set so that the gate-source voltage of the transistor 113 is higher than the gate threshold voltage of the transistor 113 during the high-level period of the signal Se. The transistor 114 is on during a high-level period of the signal Sd, and the transistor 114 is off during a low-level period of the signal Sd. The low-level of the signal Sd has the ground potential. The high-level potential of the signal Sd is set taking into account the upper limit of the fluctuation range of the input voltage Vin so that the gate-source voltage of the transistor 114 is higher than the gate threshold voltage of the transistor 114 during the high-level period of the signal Sd.

[0037] The drive circuit 150 outputs a high-level signal Sc from the OR circuit 151 to set the transistor 113 on and the transistor 114 off, thereby setting the state of the voltage divider circuit 110 to the divided voltage application state. The drive circuit 150 outputs a low-level signal Sc from the OR circuit 151 to set the transistor 113 off and the transistor 114 on, thereby setting the state of the voltage divider circuit 110 to the direct voltage application state.

[0038] The control circuit 130 determines the level of signal Sa based on the mode setting information given to the semiconductor device 10. The mode setting information has a value of "0" or "1".

[0039] When the mode setting information has a value of "0", the control circuit 130 operates in the non-divided voltage mode. In the non-divided voltage mode (i.e., when the mode setting information has a value of "0"), the control circuit 130 outputs a low-level signal Sa. The low-level signal Sa is a signal for directly controlling the state of the voltage dividing circuit 110 to the applied state. That is, when the control circuit 130 attempts to directly control the state of the voltage dividing circuit 110 to the applied state based on the mode setting information of "0", it outputs a low-level signal Sa.

[0040] During the low-level period of signal Sa, if signal Sb is at a low level (i.e., if signal Sb indicates that "Vin < Vth" holds), the drive circuit 150 actually sets the state of the voltage dividing circuit 110 to the directly applied state according to the low-level signal Sa (i.e., according to the control content of the control circuit 130). However, even if signal Sa is at a low level, if signal Sb is at a high level (i.e., if signal Sb indicates that "Vin > Vth" holds), the drive circuit 150 sets the state of the voltage dividing circuit 110 to the voltage-divided applied state regardless of the level of signal Sa (i.e., regardless of the control content of the control circuit 130).

[0041] That is, the forced voltage division instruction circuit 140 has a function of forcibly controlling the state of the voltage dividing circuit 110 to the voltage-divided applied state regardless of the control content of the control circuit 130 when the input voltage Vin is higher than the threshold voltage Vth. When the input voltage Vin is higher than the threshold voltage Vth, the drive circuit 150 sets the state of the voltage dividing circuit 110 to the voltage-divided applied state by giving priority to the control of the forced voltage division instruction circuit 140 over the control of the control circuit 130.

[0042] On the one hand, when the mode setting information has a value of "1", the control circuit 130 operates in the voltage division mode. In the voltage division mode (i.e., when the mode setting information has a value of "1"), the control circuit 130 outputs a high-level signal Sa. The high-level signal Sa is a signal for controlling the state of the voltage division circuit 110 to the voltage division application state. That is, when the control circuit 130 attempts to control the state of the voltage division circuit 110 to the voltage division application state based on the mode setting information of "1", it outputs the high-level signal Sa.

[0043] During the high-level period of the signal Sa, the drive circuit 150 always sets the state of the voltage division circuit 110 to the voltage division application state according to the high-level signal Sa (i.e., according to the control content of the control circuit 130), regardless of the level of the signal Sb (i.e., regardless of whether "Vin<Vth" is true or not).

[0044] The mode setting information is stored in the memory 131. The value of the mode setting information in the memory 131 is determined based on the mode setting command transmitted from the host device 20 to the semiconductor device 10. The mode setting command instructs to set the value of the mode setting information to "0" or "1". When the mode setting command from the host device 20 is received by the semiconductor device 10, the control circuit 130 sets the value of the mode setting information to "0" or "1" according to the specified content of the received mode setting command. The initial value of the mode setting information may be "1".

[0045] The memory 131 has a volatile memory such as a RAM (Random Access Memory) and a non-volatile memory such as a flash memory. The volatile memory may have a storage unit classified as a register. The mode setting information may be stored in the non-volatile memory in the memory 131. In this case, once the mode setting information stored in the non-volatile memory is retained even after the semiconductor device 10 restarts after the supply of the power supply voltage VDD to the semiconductor device 10 is cut off. However, the mode setting information may also be stored in the volatile memory in the memory 131.

[0046] In the semiconductor device 10 provided with an input terminal IN for voltage monitoring, a mode is set in advance in the control circuit 130 according to the expected level of the input voltage Vin (the mode of the control circuit 130 is set to either the voltage division mode or the non-voltage division mode). That is, if it is expected that a voltage higher than the withstand voltage of the internal block BLK will be applied as the input voltage Vin, the control circuit 130 is set to the voltage division mode. This makes it possible to monitor the level of the input voltage Vin while avoiding violation of the withstand voltage of the internal block BLK. Also, if it is expected that the maximum value of the input voltage Vin is lower than the withstand voltage of the internal block BLK, it is permissible to set the control circuit 130 to the non-voltage division mode, and the use of the non-voltage division mode makes it possible to monitor the level of a relatively low input voltage Vin with high accuracy.

[0047] However, when the control circuit 130 is operating in the non-voltage-dividing mode, an input voltage Vin exceeding the withstand voltage of the internal block BLK may be applied to the input terminal IN due to some irregular factor (such as a failure or surge on the signal source SS side). For example, when the withstand voltage of the internal block BLK is 2.3V and the control circuit 130 is operating in the non-voltage-dividing mode, consider a case where the input voltage Vin rises from around 0V to 6V due to some irregular factor. In this case, if the voltage-dividing circuit 110 is maintained in a direct application state, a voltage Vp of 6V exceeding the withstand voltage of the internal block BLK will be input to the internal block BLK, causing a problem of violation of the withstand voltage. If elements with a withstand voltage of 7V are used as each circuit element in the internal block BLK, no problem will occur, but an increase in withstand voltage will lead to an increase in the chip area, and therefore an increase in the size and cost of the semiconductor device 10. Although the problem can be avoided by constantly keeping the voltage divider circuit 110 in a divided voltage application state, in that case, the voltage monitoring accuracy deteriorates when the level of the input voltage Vin is low (the effect of the offset in the internal block BLK becomes greater).

[0048] Considering these, the semiconductor device 10 according to this embodiment is provided with a forced voltage division instruction circuit 140, which forcibly sets the state of the voltage division circuit 110 to a voltage division application state regardless of the control contents of the control circuit 130 when an input voltage Vin exceeding the threshold voltage Vth is applied to the input terminal IN even when the control circuit 130 is operating in a non-voltage division mode. This makes it possible to prevent an increase in chip area due to an increase in the element voltage resistance while suppressing the withstand voltage violation as described above, which is advantageous in terms of cost. Since the voltage division circuit 110 can be switched between execution and non-execution of voltage division depending on the level of the input voltage Vin, it is also possible to avoid deterioration of voltage monitoring accuracy when the level of the input voltage Vin is low.

[0049] In order to avoid a breakdown voltage violation in the internal block BLK, the threshold voltage Vth is set lower than the breakdown voltage of the internal block BLK (the breakdown voltage of a circuit element provided in the internal block BLK and connected to the node 115 to receive the voltage Vp). For example, when the breakdown voltage of the internal block BLK is 2.3V, the threshold voltage Vth is set to 0.8V.

[0050] During the low-level period of the signal Sa, there is a slight delay until the state of the voltage-dividing circuit 110 switches from the direct application state to the divided voltage application state as a result of the signal Sb switching from the low level to the high level. Therefore, when the voltage-dividing circuit 110 is in the direct application state, for example, when the input voltage Vin rises sharply from near 0V to a voltage exceeding the withstand voltage of the internal block BLK, there remains a possibility that the voltage Vp will exceed the withstand voltage of the internal block BLK even for a short period of time, depending on the situation. In order to reliably avoid this, as shown in FIG. 3, a capacitor Cp connected between the node 115 and the ground may be added to the semiconductor device 10 (for example, it may be added to the voltage-dividing circuit 110 or the internal block BLK).

[0051] Furthermore, by providing the transistor 114, the input voltage Vin can be transmitted to the node 115 at high speed in the direct application state. However, when high speed voltage monitoring is not required, the transistor 114 can be omitted from the semiconductor device 10 (specifically, from the voltage divider circuit 110) as shown in Fig. 4. When the transistor 114 is omitted, the input voltage Vin is transmitted to the node 115 through the resistor 111 in the direct application state, so that when the input voltage Vin fluctuates, the voltage Vp may transiently differ from the input voltage Vin, but the voltage Vp is steadily equal to the input voltage Vin.

[0052] Below, several specific configuration examples, operation examples, application techniques, modified techniques, etc. will be described among the multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. In the cases where there are matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple embodiments shown below can also be applied to any other embodiment (i.e., any two or more of the multiple embodiments can also be combined).

[0053] <<First Example>> A first embodiment will be described. Fig. 5 is a configuration diagram of a main part of a semiconductor device 10 according to the first embodiment. A signal generating circuit 120A and a control circuit 130A in Fig. 5 are the signal generating circuit 120 and the control circuit 130 according to the first embodiment, respectively. The signal generating circuit 120A has a buffer amplifier 121 and an AD converter 122. A digital signal Sdig output from the AD converter 122 corresponds to the signal Sp (see Fig. 2) according to the first embodiment.

[0054] The buffer amplifier 121 is an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal. The non-inverting input terminal of the buffer amplifier 121 is connected to the node 115 and thus receives the voltage Vp. The inverting input terminal and the output terminal of the buffer amplifier 121 are shorted. Therefore, the buffer amplifier 121 functions as a voltage follower and outputs the voltage Vp at the node 115 with a sufficiently low impedance. The output voltage Vp of the buffer amplifier 121 is referred to as a voltage Vp1. Strictly speaking, the voltage Vp1 may differ from the voltage Vp by a small amount, but the voltage Vp1 can be considered to be substantially equal to the voltage Vp. Therefore, hereinafter, it is considered that "Vp1=Vp".

[0055] The AD converter 122 executes an AD conversion process to convert the output voltage Vp1 of the buffer amplifier 121 into a digital signal Sdig. The execution timing of the AD conversion process is specified by the control circuit 130A. The control circuit 130A may cause the AD converter 122 to perform the AD conversion process periodically at a predetermined interval. The digital signal Sdig has a digital value proportional to the value of the voltage Vp1. Since "Vp=Vp1", the digital signal Sdig has a digital value proportional to the value of the voltage Vp. In other words, the value of the voltage Vp is indicated by the digital signal Sdig. The digital signal Sdig is input from the AD converter 122 to the control circuit 130A.

[0056] The control circuit 130A performs signal processing according to the digital signal Sdig. The output signal Sc of the OR circuit 151 is input to the control circuit 130A. Based on the signal Sc, the control circuit 130A can correctly determine whether the current state of the voltage dividing circuit 110 is set to a direct application state or a divided voltage application state.

[0057] During a low-level period of the signal Sc, the control circuit 130A recognizes that the voltage-dividing circuit 110 is in a direct application state. That is, during a low-level period of the signal Sc, the control circuit 130A recognizes that the equation "Vin=Vp=Vp1" holds, and then specifies the value of the input voltage Vin based on the digital signal Sdig.

[0058] During a high-level period of the signal Sc, the control circuit 130A recognizes that the voltage-dividing circuit 110 is in a voltage-dividing state. That is, during a high-level period of the signal Sc, the control circuit 130A recognizes that the formula "Vin×R112 / (R111+R112)=Vp=Vp1" holds, and then specifies the value of the input voltage Vin based on the digital signal Sdig.

[0059] The control circuit 130A performs a monitoring result output process based on the specified value of the input voltage Vin. That is, when the voltage monitoring process implemented by the control circuit 130A is an upper limit monitoring process, the control circuit 130A outputs a result of "Vin>VH" based on the specified value of the input voltage Vin. LIM When the voltage monitoring process implemented by the control circuit 130A is the lower limit monitoring process, the control circuit 130A determines the value of the monitoring result signal Sz by determining whether or not the specified input voltage Vin has been satisfied. <VL LIM When the voltage monitoring process implemented by the control circuit 130A is a window monitoring process, the control circuit 130A determines the value of the monitoring result signal Sz by determining whether or not “Vin>VH LIM " and "Vin <VL LIM The value of the monitoring result signal Sz is determined by judging whether the "monitoring result" is successful or not.

[0060] For example, when the value of the mode setting information is "0" corresponding to the non-voltage division mode, the signal Sc is maintained at a low level during the period when the input voltage Vin is lower than the threshold voltage Vth, and the voltage divider circuit 110 is maintained in a direct application state corresponding to the non-voltage division mode. If the input voltage Vin then exceeds the threshold voltage Vth, the signal Sc is maintained at a high level during the period when "Vin>Vth" is satisfied, and the voltage divider circuit 110 enters a voltage division application state. If the input voltage Vin then returns to a state lower than the threshold voltage Vth, the signal Sc returns to a low level, and the voltage divider circuit 110 returns to a direct application state corresponding to the non-voltage division mode.

[0061] Further, especially when the total number of input terminals IN provided in the semiconductor device 10 is 1, it is also possible to omit the buffer amplifier 121 in the semiconductor device 10 of FIG. 5. At this time, the voltage Vp itself at the node 115 is supplied to the AD converter 122 as the voltage Vp1.

[0062] <<Second Embodiment>> The second embodiment will be described. FIG. 6 is a configuration diagram of a main part of the semiconductor device 10 according to the second embodiment. The signal generation circuit 120B and the control circuit 130B in FIG. 6 are the signal generation circuit 120 and the control circuit 130 according to the second embodiment, respectively. The signal generation circuit 120B includes comparators 125 and 126 and voltage sources 127 and 128. Signals S125 and S126 output from the comparators 125 and 126 constitute the signal Sp (see FIG. 2) according to the second embodiment. The voltage monitoring process realized by the signal generation circuit 120B and the control circuit 130B is a window monitoring process.

[0063] Each of the comparators 125 and 126 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The non-inverting input terminal of the comparator 125 and the inverting input terminal of the comparator 126 are both connected to the node 115, and thus receive the voltage Vp. The voltage source 127 generates a determination voltage V1 and supplies the determination voltage V1 to the inverting input terminal of the comparator 125. The voltage source 128 generates a determination voltage V2 and supplies the determination voltage V2 to the non-inverting input terminal of the comparator 126. The voltage sources 127 and 128 are variable voltage sources, and vary the determination voltages V1 and V2 according to the control of the control circuit 130B. However, the determination voltage V1 is higher than the determination voltage V2.

[0064] The comparator 125 compares the voltages Vp and V1 supplied to itself, and outputs a signal S125 indicating the comparison result of the voltages Vp and V1 to the control circuit 130B. The signal S125 is a binary signal having a high level or a low level. The comparator 125 outputs a high-level signal S125 when "Vp > V1" holds, outputs a low-level signal S125 when "Vp < V1" holds, and outputs a high-level or low-level signal S125 when "Vp = V1" holds.

[0065] Comparator 126 compares the voltages Vp and V2 supplied to itself and outputs a signal S126 indicating the comparison result of the voltages Vp and V2 to the control circuit 130B. The signal S126 is a binary signal having a high level or a low level. Comparator 126 outputs a high-level signal S126 when "Vp < V2" holds, outputs a low-level signal S126 when "Vp > V2" holds, and outputs a high-level or low-level signal S126 when "Vp = V2" holds.

[0066] The control circuit 130B performs signal processing according to the signals S125 and S126. The output signal Sc of the OR circuit 151 is input to the control circuit 130B. The control circuit 130B can correctly determine whether the current state of the voltage dividing circuit 110 is set to either the direct application state or the voltage division application state based on the signal Sc.

[0067] During the low-level period of the signal Sc, the control circuit 130B recognizes that the voltage dividing circuit 110 is in the direct application state. During the low-level period of the signal Sc, the control circuit 130B controls the voltage sources 127 and 128 so that the determination voltage V1 coincides with the above-mentioned upper limit voltage VH LIM and the determination voltage V2 coincides with the above-mentioned lower limit voltage VL LIM (in other words, adjusts the determination voltages V1 and V2).

[0068] During the high-level period of the signal Sc, the control circuit 130B recognizes that the voltage dividing circuit 110 is in the voltage division application state. During the high-level period of the signal Sc, the control circuit 130B controls the voltage sources 127 and 128 so that the equations "V1 = VH LIM ×R112 / (R111 + R112)" and "V2 = VL LIM ×R112 / (R111 + R112)" hold (in other words, adjusts the determination voltages V1 and V2).

[0069] In both the low-level period and the high-level period of the signal Sc, if the signal S125 has a high level, the control circuit 130B determines that "Vin > VHLIM " is established, and if the signal S126 has a high level, "Vin <VL LIM " is established, and if both signals S125 and S126 have a low level, "VL LIM ≦Vin≦VH LIM " is determined to be true.

[0070] For example, when the value of the mode setting information is "0" corresponding to the non-voltage division mode, the signal Sc is maintained at a low level during the period when the input voltage Vin is lower than the threshold voltage Vth, and the voltage divider circuit 110 is maintained in a direct application state corresponding to the non-voltage division mode. If the input voltage Vin then exceeds the threshold voltage Vth, the signal Sc is maintained at a high level during the period when "Vin>Vth" is satisfied, and the voltage divider circuit 110 enters a voltage division application state. If the input voltage Vin then returns to a state lower than the threshold voltage Vth, the signal Sc returns to a low level, and the voltage divider circuit 110 returns to a direct application state corresponding to the non-voltage division mode.

[0071] 6 may be modified to delete the comparator 126 and the voltage source 128 from the signal generating circuit 120B in FIG. 6 (hereinafter, referred to as an upper limit monitoring modification). When the upper limit monitoring modification is applied, the voltage monitoring process realized by the signal generating circuit 120B and the control circuit 130B becomes an upper limit monitoring process. The control circuit 130B related to the upper limit monitoring modification determines whether or not "Vin>VH" is satisfied if the signal S125 has a high level. LIM " is satisfied, and if the signal S125 has a low level, "Vin≦VH LIM " is determined to be true.

[0072] Alternatively, a modification in which the comparator 125 and the voltage source 127 are deleted from the signal generating circuit 120B in Fig. 6 (hereinafter referred to as a lower limit monitoring modification) may be applied. When the lower limit monitoring modification is applied, the voltage monitoring process realized by the signal generating circuit 120B and the control circuit 130B becomes a lower limit monitoring process. The control circuit 130B related to the lower limit monitoring modification outputs "Vin <VL LIM " is established, and if the signal S126 has a low level, "Vin ≧ VLLIM " is determined to be true.

[0073] <<Third Example>> A third embodiment will be described. As shown in FIG. 7, the semiconductor device 10 may be provided with a plurality of input terminals IN. That is, the semiconductor device 10 may be provided with input terminals IN for a plurality of channels. In this case, an input voltage Vin is input from a signal source SS to each of the plurality of input terminals IN. In FIG. 7, the signal source SS is shown as if it were a single signal source, but the signal source SS may be composed of a plurality of signal sources. In the third embodiment, the semiconductor device 10 is provided with a plurality of input terminals IN. In the following, the plurality of input terminals IN will be referred to as input terminals IN of the first to n-th channels. n represents any integer of 2 or more. The input voltage Vin input to the input terminal IN of the i-th channel will be referred to as the input voltage Vin of the i-th channel. i represents a natural number equal to or less than n. When i and j represent different natural numbers equal to or less than n, the input voltage Vin of the i-th channel and the input voltage Vin of the j-th channel are different from each other.

[0074] The semiconductor device 10 according to the third embodiment is provided with a monitoring circuit 170 for each input terminal IN, and therefore is provided with first to n-th channel monitoring circuits 170. The monitoring circuit 170 corresponding to the input terminal IN of the i-th channel is the monitoring circuit 170 of the i-th channel.

[0075] When the first embodiment and the third embodiment are combined, the circuit shown in FIG. 5 is provided in each monitoring circuit 170. However, the control circuit 130A is shared among the monitoring circuits 170 of the first to n-th channels. That is, when the first embodiment and the third embodiment are combined, the monitoring circuits 170 of the first to n-th channels each have a voltage dividing circuit 110, a signal generating circuit 120A, a forced voltage division instruction circuit 140, and a driving circuit 150, and generate a digital signal Sdig according to the input voltage Vin for each channel. In addition, the AD converter 122 of the signal generating circuit 120A may be shared among the monitoring circuits 170 of the first to n-th channels. In this case, only one AD converter 122 is provided in the semiconductor device 10, and a multiplexer (not shown) is provided between the buffer amplifiers 121 of the first to n-th channels and the single AD converter 122. Then, the output voltages Vp1 of the buffer amplifiers 121 of the first to n-th channels are sequentially supplied one by one to a single AD converter 122 via a multiplexer, so that AD conversion processing is performed sequentially on the voltages Vp of each channel.

[0076] The control circuit 130A according to the combination of the first and third embodiments specifies the value of the input voltage Vin for each channel based on the digital signal Sdig, and performs monitoring result output processing for each channel based on the specified value of the input voltage Vin. In the third embodiment, the monitoring result signal Sz is composed of the monitoring result signals Sz of the first to n-th channels, and the value of the monitoring result signal Sz is determined for each channel.

[0077] When the second and third embodiments are combined, the circuit shown in Fig. 6 is provided in each monitoring circuit 170. However, the control circuit 130B is shared among the monitoring circuits 170 of the first to n-th channels. That is, when the second and third embodiments are combined, the monitoring circuits 170 of the first to n-th channels each have a voltage dividing circuit 110, a signal generating circuit 120B, a forced voltage division instruction circuit 140, and a driving circuit 150, and generate signals S125 and S126 according to the input voltage Vin for each channel.

[0078] The control circuit 130B according to the combination of the second and third embodiments performs monitoring result output processing for each channel based on the signals S125 and S126. In the third embodiment, the monitoring result signal Sz is composed of the monitoring result signals Sz of the first to n-th channels, and the value of the monitoring result signal Sz is determined for each channel. The above-mentioned upper limit monitoring modification may be applied to the control circuit 130B, in which case the control circuit 130B performs monitoring result output processing for each channel based on the signal S125. The above-mentioned lower limit monitoring modification may be applied to the control circuit 130B, in which case the control circuit 130B performs monitoring result output processing for each channel based on the signal S126.

[0079] In the third embodiment, the above-mentioned mode setting information is set for each channel. That is, the mode setting information for the first to n-th channels is stored in the memory 131 of the control circuit 130 (130A or 130B). The control circuit 130 determines the level of the signal Sa based on the mode setting information for each channel. That is, when the mode setting information for the first channel has a value of "0", the control circuit 130 (130A, 130B) outputs a low-level signal Sa to the logical sum circuit 151 in the drive circuit 150 of the first channel, and when the mode setting information for the first channel has a value of "1", the control circuit 130 (130A, 130B) outputs a high-level signal Sa to the logical sum circuit 151 in the drive circuit 150 of the first channel. Similarly, when the mode setting information of the second channel has a value of "0", the control circuit 130 (130A, 130B) outputs a low-level signal Sa to the logical sum circuit 151 in the drive circuit 150 of the second channel, and when the mode setting information of the second channel has a value of "1", the control circuit 130 (130A, 130B) outputs a high-level signal Sa to the logical sum circuit 151 in the drive circuit 150 of the second channel. The same applies to the other channels.

[0080] <<Fourth Example>> A fourth embodiment will be described. The semiconductor device 10 may be provided with a mode setting terminal, which is an external terminal for specifying mode setting information. In this case, the control circuit 130 (130A, 130B) may determine whether the value of the mode setting information is "0" or "1" based on the voltage at the mode setting terminal. In this case, for example, the voltage at the mode setting terminal being equal to or higher than a predetermined mode determination voltage indicates that the value of the mode setting information is "1", and the voltage at the mode setting terminal being lower than the predetermined mode determination voltage indicates that the value of the mode setting information is "0".

[0081] When the third and fourth embodiments are combined, n mode setting terminals may be provided in the semiconductor device 10 as mode setting terminals for the first to n-th channels, and it may be determined for each channel whether the value of the mode setting information is "0" or "1" based on the voltage at the mode setting terminal. The total number of mode setting terminals provided in the semiconductor device 10 may be less than n, and one mode setting terminal may be assigned to two or more channels.

[0082] <<Fifth Example>> A fifth embodiment will be described. In the voltage dividing circuit 110, the transistor 113 may be provided between the resistors 111 and 112, not between the resistor 112 and the ground. That is, in the voltage dividing circuit 110, as shown in Fig. 8, the first terminal of the resistor 111 may be connected to the input terminal IN, the second terminal of the resistor 111 and the drain of the transistor 113 may be connected to a node 115, the first terminal of the resistor 112 may be connected to the source of the transistor 113, and the second terminal of the resistor 112 may be connected to the ground. Although not particularly shown in Fig. 8, a transistor 114 may be connected in parallel to the resistor 111, similar to the configuration of Fig. 2.

[0083] <<Sixth Example>> A sixth embodiment will now be described. In the sixth embodiment, some modified techniques and supplementary matters for the above items will be described.

[0084] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0085] The channel types of FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel without departing from the spirit of the above.

[0086] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0087] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0088] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0089] A semiconductor device (10) according to one aspect of the present disclosure has a configuration (first configuration) including an input terminal (IN) configured to receive an input voltage (Vin), a voltage divider circuit (110) connected to the input terminal and having a specific node (115) to which the input voltage is applied or a divided voltage of the input voltage is applied, a signal generating circuit (120) connected to the specific node and configured to generate a signal corresponding to the voltage of the specific node, a control circuit (130) configured to control a state of the voltage divider circuit to a first state (direct application state) in which the input voltage is applied to the specific node or a second state (divided voltage application state) in which a divided voltage of the input voltage is applied to the specific node based on setting information, and a forced voltage division instruction circuit (140) connected to the input terminal and configured to forcibly control the state of the voltage divider circuit to the second state regardless of the control content of the control circuit when the input voltage is higher than a threshold voltage (Vth).

[0090] This prevents excessive voltage from being applied to the signal generating circuit. The function of the forced voltage division instruction circuit makes it possible to avoid a voltage violation without increasing the element voltage resistance, thereby avoiding increases in chip area and cost that would accompany an increase in element voltage resistance. In addition, since the voltage division circuit can switch between performing and not performing voltage division depending on the input voltage level, the signal generating circuit can evaluate the input voltage level with high accuracy when the input voltage level is low.

[0091] The semiconductor device according to the first configuration described above may further include a drive circuit (150) configured to set the state of the voltage divider circuit to the first state or the second state in response to a first signal (Sa) output from the control circuit based on the setting information and a second signal (Sb) output from the forced voltage division instruction circuit based on a comparison result between the input voltage and the threshold voltage, and the drive circuit may be configured (second configuration) to set the state of the voltage divider circuit to the second state by prioritizing control of the forced voltage division instruction circuit over control of the control circuit when the second signal indicates that the input voltage is higher than the threshold voltage.

[0092] In the semiconductor device according to the second configuration, the control circuit may be configured to output the first signal at a first level (e.g., a low level) when controlling the state of the voltage divider circuit to the first state, and to output the first signal at a second level (e.g., a high level) when controlling the state of the voltage divider circuit to the second state, and the drive circuit may set the state of the voltage divider circuit to the second state regardless of the second signal when the first signal has the second level, set the state of the voltage divider circuit to the first state when the second signal indicates that the input voltage is lower than the threshold voltage when the first signal has the first level, and set the state of the voltage divider circuit to the second state when the second signal indicates that the input voltage is higher than the threshold voltage (third configuration).

[0093] In the semiconductor device according to any one of the first to third configurations, the voltage divider circuit may have a series circuit of a first resistor (111), a second resistor (112), and a changeover switch (113) provided between the input terminal and ground, the first resistor is provided between the input terminal and the specific node, the second resistor and the changeover switch are provided between the specific node and ground, and the changeover switch is set to off in the first state and the changeover switch is set to on in the second state (fourth configuration).

[0094] In the semiconductor device according to the fourth configuration, the voltage divider circuit may further include a short-circuit switch (114) connected in parallel to the first resistor, and the short-circuit switch may be set to on in the first state and the short-circuit switch may be set to off in the second state (fifth configuration).

[0095] This makes it possible to transmit the input voltage to the specific node at high speed in the first state.

[0096] In the semiconductor device according to any one of the first to fifth configurations, the signal generating circuit may have an AD converter (122) configured to convert the voltage of the specific node into a digital signal, and the control circuit may be configured to output a signal corresponding to the digital signal (sixth configuration).

[0097] This allows, for example, the monitoring result of the input voltage to be output from the control circuit.

[0098] In the semiconductor device according to any one of the first to fifth configurations, the signal generating circuit may have a comparator (125, 126) configured to compare the voltage of the specific node with a determination voltage, and the control circuit may be configured to output a signal according to the comparison result of the comparator (seventh configuration).

[0099] This allows, for example, the monitoring result of the input voltage to be output from the control circuit. [Explanation of symbols]

[0100] 1 System 10 Semiconductor device 20 Upper device 30 Bus SS signal source IN Input terminal Vin Input voltage VDD Power supply voltage 110 Voltage divider circuit 111, 112 Resistor 113, 114 Transistors 115 nodes (specific nodes) 120, 120A, 120B signal generation circuit 121 Buffer amplifier 122 A / D converter 125, 126 Comparator 127, 128 Voltage Source 130, 130A, 130B Control circuit 131 Memory 140 Forced voltage division indication circuit 141 Comparator 150 Drive circuit 151 OR circuit 152, 153 Inverter circuit 170 Monitoring circuit Vp, Vp1 voltage V1, V2 judgement voltage Sa~Se, Sp signals Cp Capacitor Sdig Digital Signal

Claims

1. an input terminal configured to receive an input voltage; a voltage divider circuit connected to the input terminal and having a specific node to which the input voltage is applied or a divided voltage of the input voltage is applied; a signal generating circuit connected to the specific node and configured to generate a signal corresponding to a voltage of the specific node; a control circuit configured to control a state of the voltage divider circuit based on setting information to a first state in which the input voltage is applied to the specific node or a second state in which a divided voltage of the input voltage is applied to the specific node; a forced voltage division instruction circuit connected to the input terminal and configured to forcibly control the state of the voltage division circuit to the second state regardless of the control content of the control circuit when the input voltage is higher than a threshold voltage. , semiconductor device.

2. a drive circuit configured to set a state of the voltage divider circuit to the first state or the second state in response to a first signal output from the control circuit based on the setting information and a second signal output from the forced voltage division instruction circuit based on a comparison result between the input voltage and the threshold voltage, When the second signal indicates that the input voltage is higher than the threshold voltage, the drive circuit prioritizes control of the forced voltage division instruction circuit over control of the control circuit, thereby setting the state of the voltage division circuit to the second state. The semiconductor device according to claim 1 .

3. the control circuit outputs the first signal at a first level when controlling the state of the voltage divider circuit to the first state, and outputs the first signal at a second level when controlling the state of the voltage divider circuit to the second state; The drive circuit includes: setting a state of the voltage divider circuit to the second state regardless of the second signal when the first signal has the second level; When the first signal has the first level, a state of the voltage divider circuit is set to the first state when the second signal indicates that the input voltage is lower than the threshold voltage, and a state of the voltage divider circuit is set to the second state when the second signal indicates that the input voltage is higher than the threshold voltage. The semiconductor device according to claim 2 .

4. the voltage divider circuit has a series circuit of a first resistor, a second resistor, and a changeover switch provided between the input terminal and ground, the first resistor is provided between the input terminal and the specific node, and the second resistor and the changeover switch are provided between the specific node and ground, In the first state, the changeover switch is set to OFF, and in the second state, the changeover switch is set to ON.

4. The semiconductor device according to claim 1.

5. the voltage divider circuit further includes a short-circuit switch connected in parallel to the first resistor, In the first state, the shorting switch is set to ON, and in the second state, the shorting switch is set to OFF. The semiconductor device according to claim 4 .

6. the signal generating circuit includes an AD converter configured to convert the voltage of the specific node into a digital signal; The control circuit outputs a signal corresponding to the digital signal.

4. The semiconductor device according to claim 1.

7. the signal generating circuit includes a comparator configured to compare the voltage of the particular node with a determination voltage; The control circuit outputs a signal according to a comparison result of the comparator.

4. The semiconductor device according to claim 1.

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