Semiconductor device

Abstract

To provide a highly reliable semiconductor device.SOLUTION: A semiconductor device 1 includes a semiconductor substrate 10 partitioned into an active region and an inactive region. A gate electrode 32 provided inside each of a plurality of trenches TR is electrically connected to gate wiring 26 in the inactive region. In the inactive region, a gate insulating film 34 covers a top face of the semiconductor substrate 10 to separate the top face of the semiconductor substrate 10 from the gate wiring 26. An interval distance between adjacent trenches is longer in the inactive region than that in the active region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device having a trench gate. [Background technology]

[0002] In order to improve the electrical characteristics of a semiconductor device having a trench gate, technological development is being carried out to narrow the interval between adjacent trench gates. For example, by narrowing the interval between adjacent trench gates, a bulk channel effect can be exerted in the body region between the adjacent trench gates. In the body region where the bulk channel effect is exerted, electrons can flow even at a position away from the gate insulating film. Therefore, the influence of scattering caused by the interface between the gate insulating film and the body region is reduced, and the mobility of electrons is improved. An example of such a semiconductor device is disclosed in Patent Document 1, Non-Patent Documents 1 and 2. Note that, here, the reason for narrowing the interval between adjacent trench gates is explained using the bulk channel effect as an example, but the reason for narrowing the interval between adjacent trench gates is not limited to this example. In general, by narrowing the interval between adjacent trench gates, the area that becomes the current path increases, and therefore the on-resistance of the semiconductor device decreases. This specification proposes a technology that is useful when it is desired to narrow the interval between adjacent trench gates for various reasons. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] UK Patent Publication No. 2572442 [Non-patent literature]

[0004] [Non-Patent Document 1] J.-P. Colinge, "FinFETs and Other Multi-Gate Transistors", Springer, 2007. [Non-Patent Document 2] Yuan Taur, "An Analytical Solution to a Double-Gate MOSFET with Undoped Body," IEEE Electron Device Letters, vol. 21, no. 5, pp. 245-247, May 2000. [Non-Patent Document 3] T. Kato et al., "Enhanced Performance of 50 nm Ultra-Narrow-Body Silicon Carbide MOSFETs based on FinFET effect," ISPSD, 2020, pp. 62-65. Summary of the Invention [Problem to be solved by the invention]

[0005] A gate wiring for inputting a gate voltage to each gate electrode of the plurality of trench gates is disposed on a semiconductor substrate so as to cross the plurality of trench gates. Therefore, the gate wiring is also present on the semiconductor substrate between adjacent trench gates. In order to electrically insulate the upper surface of the semiconductor substrate between adjacent trench gates and the gate wiring, a gate insulating film is provided on the upper surface of the semiconductor substrate below the gate wiring. According to the study by the present inventor, it has been found that when the interval between adjacent trench gates is narrow, an electric field is concentrated in the gate insulating film below the gate wiring. Such electric field concentration can cause an increase in gate leakage current, dielectric breakdown of the gate insulating film, and a decrease in the life of the gate insulating film. The present specification aims to provide a semiconductor device having high reliability by mitigating the electric field concentration in the gate insulating film below the gate wiring. [Means for solving the problem]

[0006] The semiconductor device disclosed in this specification may include a semiconductor substrate (10) partitioned into an active region and a non-active region, a bottom electrode (22) covering a bottom surface of the semiconductor substrate, a top electrode (24) covering at least a portion of an active region of an upper surface of the semiconductor substrate, a gate wiring (26) covering at least a portion of a non-active region of an upper surface of the semiconductor substrate, a plurality of trenches (TR) provided in an upper layer portion of the semiconductor substrate, the plurality of trenches including a first trench and a second trench spaced apart from the first trench, a gate insulating film (34) covering an inner surface of each of the first trench and the second trench, and a gate electrode (32) provided inside each of the first trench and the second trench and separated from the semiconductor substrate by the gate insulating film, the gate electrode being separated from the top electrode by an interlayer insulating film (42) in the active region and electrically connected to the gate wiring in the non-active region. The semiconductor substrate may have an n-type first semiconductor region (14), a p-type second semiconductor region (16) provided on the first semiconductor region and disposed between the first trench and the second trench, and an n-type third semiconductor region (18) provided on the second semiconductor region and disposed between the first trench and the second trench. In the active region, the third semiconductor region may be in contact with the top electrode. In the inactive region, a gate insulating film may cover the top surface of the semiconductor substrate and separate the top surface of the semiconductor substrate from the gate wiring. The distance between the first trench and the second trench may be longer in the inactive region than in the active region.

[0007] In the semiconductor device, the distance between the first trench and the second trench is short in the active region. This improves the electrical characteristics of the semiconductor device. On the other hand, in the semiconductor device, the distance between the first trench and the second trench is long in the inactive region. This makes the distance between the first trench and the second trench long below the gate wiring disposed in the inactive region. This alleviates the electric field concentration in the gate insulating film formed on the upper surface of the semiconductor substrate below the gate wiring. In this way, the semiconductor device can alleviate the electric field concentration below the gate wiring in the inactive region while improving the electrical characteristics in the active region. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a plan view of a main portion of the semiconductor device of the present embodiment, and is a schematic plan view of the main portion in a state in which an interlayer insulating film, a source electrode, and a gate wiring provided on a semiconductor substrate have been removed. [Diagram 2] 2 is a cross-sectional view of a main portion of the semiconductor device according to the present embodiment, which is a schematic cross-sectional view of the main portion taken along line II-II in FIG. [Diagram 3] 3 is a cross-sectional view of a main portion of the semiconductor device according to the present embodiment, which is a schematic cross-sectional view of the main portion taken along line III-III in FIG. [Figure 4] FIG. 11 is a plan view of a main part of a semiconductor device according to a modified example of the present embodiment, and is a schematic plan view of the main part in a state where an interlayer insulating film, a source electrode, and a gate wiring provided on a semiconductor substrate are removed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the semiconductor device disclosed in this specification will be described with reference to the drawings. For the purpose of clarity of illustration, reference numerals may be given to only one of repeatedly arranged components.

[0010] As shown in FIGS. 1 to 3, the semiconductor device 1 is a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The semiconductor device 1 includes a semiconductor substrate 10 that is partitioned into an active region and a non-active region. The material of the semiconductor substrate 10 is not particularly limited, and may be, for example, silicon carbide (SiC). Alternatively, the material of the semiconductor substrate 10 may be, for example, silicon, a nitride semiconductor, or gallium oxide. The "active region" is a region of the semiconductor substrate 10 through which a current mainly flows. The "non-active region" is a region of the semiconductor substrate 10 through which substantially no current flows, and is a region located around the "active region".

[0011] The semiconductor device 1 further includes a drain electrode 22 provided to cover the lower surface of the semiconductor substrate 10, a source electrode 24 provided to cover at least a portion of an active region on the upper surface of the semiconductor substrate 10, a gate wiring 26 provided to cover at least a portion of a non-active region on the upper surface of the semiconductor substrate 10, and a plurality of trench gates 30 provided in the upper layer of the semiconductor substrate 10. The drain electrode 22 is an example of a lower surface electrode, and the source electrode 24 is an example of an upper surface electrode. As shown in FIGS. 2 and 3, the semiconductor substrate 10 includes an n + A drain region 12 of n-type, a drift region 14 of n-type, a body region 16 of p-type, and + and a source region 18 of the same type.

[0012] The drain region 12 is provided at a position exposed on the lower surface of the semiconductor substrate 10. The drain region 12 contains a high concentration of n-type impurities, and is in contact with a drain electrode 22 that covers the lower surface of the semiconductor substrate 10.

[0013] The drift region 14 is provided on the drain region 12 and separates the drain region 12 from the body region 16. The drift region 14 contacts the bottom surface and the lower side surface of the trench gate 30. The concentration of n-type impurities contained in the drift region 14 is lower than the concentration of n-type impurities contained in the drain region 12. The drift region 14 is an example of a first semiconductor region.

[0014] The body region 16 is provided on the drift region 14 and is arranged in an upper layer portion of the semiconductor substrate 10. The body region 16 separates the drift region 14 from the source region 18. The body region 16 is provided between adjacent trench gates 30 and contacts each side surface of the adjacent trench gates 30. The body region 16 is electrically connected to the source electrode 24 via a contact region in a cross section not shown. The body region 16 is an example of a second semiconductor region.

[0015] The source region 18 is provided on the body region 16, and is disposed at a position exposed on the upper surface of the semiconductor substrate 10. The source region 18 is provided between adjacent trench gates 30, and contacts each side surface of the adjacent trench gates 30. The source region 18 contains a high concentration of n-type impurities, and contacts a source electrode 24 that covers the upper surface of the semiconductor substrate 10 in the active region. The source region 18 is an example of a third semiconductor region.

[0016] A plurality of trenches TR are formed in the upper layer of the semiconductor substrate 10. Each of the plurality of trenches TR extends from the upper surface of the semiconductor substrate 10 through the source region 18 and the body region 16 to reach the drift region 14. When the semiconductor substrate 10 is viewed in plan, each of the plurality of trenches TR extends along one direction in the plane of the semiconductor substrate 10 and is spaced apart from one another along a direction perpendicular to the longitudinal direction. The inner surface of each of the plurality of trenches TR is covered with a gate insulating film 34. A gate electrode 32 is embedded inside each of the plurality of trenches TR. The gate electrode 32 is separated from the semiconductor substrate 10 by the gate insulating film 34. In this manner, a trench gate 30 is provided in each of the plurality of trenches TR.

[0017] As shown in FIG. 2, in the active region, an interlayer insulating film 42 is provided on the gate electrode 32 of the trench gate 30, and the gate electrode 32 and the source electrode 24 are separated from each other. As shown in FIG. 3, in the inactive region, the interlayer insulating film 42 is not provided on the gate electrode 32 of the trench gate 30, and the gate electrode 32 is in contact with the gate wiring 26. The gate wiring 26 is also disposed so as to cross the multiple trench gates 30. In the portion where the gate wiring 26 is disposed, a gate insulating film 34 is provided on the upper surface of the semiconductor substrate 10 between the adjacent trench gates 30. As a result, in the portion where the gate wiring 26 is disposed, the upper surface of the semiconductor substrate 10 and the gate wiring 26 are separated by the gate insulating film 34.

[0018] As shown in FIGS. 1 to 3, the trenches TR are formed to include a wide portion and a narrow portion along the longitudinal direction when the semiconductor substrate 10 is viewed in a plane. As a result, the interval between adjacent trenches TR (i.e., the shortest distance between the side of one trench TR and the side of the other trench TR) has a short distance portion and a long distance portion when the semiconductor substrate 10 is viewed in a plane. In this example, the wide portions of the trenches TR are disposed in the active region, so that the interval between adjacent trenches TR in the active region (D1 in FIG. 2) is relatively short. On the other hand, the narrow portions of the trenches TR are disposed in the inactive region, so that the interval between adjacent trenches TR in the inactive region (D2 in FIG. 3) is relatively long. In this example, the trenches TR have narrow portions at their longitudinal ends, so that the interval between adjacent trenches TR is long at their longitudinal ends. Alternatively to this example, the multiple trenches TR may be configured to have a narrow portion at any position in the longitudinal direction, as shown in FIG. 4, so that the spacing between adjacent trenches TR is longer at any position in the longitudinal direction.

[0019] As described above, in the active region, the interval between adjacent trenches TR (D1 in FIG. 2) is formed short. In the active region, the interval between adjacent trenches TR is adjusted to a size that allows the bulk channel effect to be exerted in the body region 16. In this example, the interval between adjacent trenches TR in the active region is 150 nm or less. When the material of the semiconductor substrate 10 is silicon carbide, it is known that the bulk channel effect is exerted in the body region 16 when the interval between adjacent trenches TR is 150 nm or less.

[0020] As described above, the interval between adjacent trenches TR (D2 in FIG. 2) is formed long in the inactive region. In the inactive region, the interval between adjacent trenches TR is adjusted during the manufacturing process so that the radius of curvature of the shoulder 44 of the trench TR is larger in the inactive region than in the active region, as described later. The shoulder 44 of the trench TR is a corner formed by the side surface of the trench TR and the upper surface of the semiconductor substrate 10. In this example, the interval between adjacent trenches TR in the inactive region is 180 nm or more. In this case, the radius of curvature of the shoulder 44 of the trench TR is 90 nm or more, and the electric field concentration in the gate insulating film 34 covering the shoulder 44 of the trench TR is effectively alleviated.

[0021] The trenches TR may be formed by forming a plurality of trenches in the upper layer of the semiconductor substrate 10 using a dry etching technique, and then performing a rounding process in which a heat treatment is performed in a hydrogen atmosphere or an argon atmosphere. It has been found that such rounding does not substantially occur in an active region where the interval between adjacent trenches TR is short, but occurs effectively in a non-active region where the interval between adjacent trenches TR is long. That is, even without using a mask or the like for limiting the processing range of the rounding process, the radius of curvature of the shoulder portion 44 of the trench TR in the non-active region can be made larger than the radius of curvature of the shoulder portion 44 of the trench TR in the active region based on the interval between adjacent trenches TR. Note that the rounding process may be performed, instead of the above-mentioned heat treatment, by, for example, an isotropic CDE method or an isotropic dry etching method after forming a plurality of trenches in the upper layer of the semiconductor substrate 10.

[0022] Next, the operation of the semiconductor device 1 will be described. When the semiconductor device 1 is used, the semiconductor device 1, a load (for example, a motor), and a power source are connected in series. A power supply voltage is applied to the series circuit of the semiconductor device 1 and the load. The power supply voltage is applied in a direction in which the drain side (drain electrode 22) of the semiconductor device 1 has a higher potential than the source side (source electrode 24). In this embodiment, the interval distance (D1 in FIG. 2) between adjacent trenches TR in the active region is 150 nm or less. As a result, since the width of the body region 16 is sufficiently narrow, when the potential of the gate electrode 32 is increased, a channel is formed not only in the vicinity of the gate insulating film 34 but also in the body region 16 away from the gate insulating film 34. A channel (i.e., a bulk channel) is formed in the entire body region 16. In the semiconductor device 1, the source region 18 and the drift region 14 are connected via such a bulk channel.

[0023] When turning off the semiconductor device 1, a potential lower than the gate threshold voltage is applied to the gate electrode 32. Then, the channel formed in the body region 16 disappears, and the semiconductor device 1 turns off.

[0024] In the semiconductor device 1, the interval between adjacent trenches TR in the active region is short. Therefore, the bulk channel effect is exerted in the body region 16 of the active region, and the on-resistance of the semiconductor device 1 is reduced. On the other hand, in the semiconductor device 1, the interval between adjacent trenches TR in the inactive region is long. Therefore, the interval between adjacent trenches TR is long below the gate wiring 26 arranged in the inactive region. This alleviates the electric field concentration in the gate insulating film 34 formed on the upper surface of the semiconductor substrate 10 below the gate wiring 26. In particular, in the semiconductor device 1, the radius of curvature of the shoulder portion 44 of the trench TR is formed large in the inactive region by the rounding process, so that the radius of curvature of the shoulder portion 44 of the trench TR covered by the gate insulating film 34 below the gate wiring 26 is also formed large. This allows the electric field concentration in the gate insulating film 34 below the gate wiring 26 to be well alleviated. In this way, in the semiconductor device 1, the electric field concentration below the gate wiring 26 in the inactive region can be alleviated while improving the electrical characteristics in the active region.

[0025] In the above embodiment, the semiconductor device 1 is a MOSFET. However, the semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor).

[0026] In the above-described embodiment, in order to make the interval between adjacent trenches TR relatively longer in the inactive region, the width of the trench TR is formed relatively shorter in the inactive region than in the active region. Therefore, the aspect ratio (trench depth / trench width) of the trench TR in the inactive region is adjusted to a predetermined value or less so that good embedding of polysilicon, which is the material of the gate electrode 32, is ensured even in the inactive region. In the semiconductor device 1 in which the semiconductor substrate 10 is silicon carbide, when the trench depth is 1 μm, the trench width may be 400 nm or less (i.e., the aspect ratio may be 2.5 or less).

[0027] In the semiconductor device 1 of the above-described embodiment, the semiconductor substrate 10 is made of silicon carbide. In the semiconductor substrate 10 made of silicon carbide, the mobility of electrons is particularly low near the interface with the gate insulating film 34. For this reason, the bulk channel type semiconductor device 1 disclosed in this specification is particularly useful when using a semiconductor substrate 10 made of silicon carbide.

[0028] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0029] 1: semiconductor device, 10: semiconductor substrate, 12: drain region, 14: drift region, 16: body region, 18: source region, 22: drain electrode, 24: source electrode, 26: gate wiring, 30: trench gate, 32: gate electrode, 34: gate insulating film, 42: interlayer insulating film, 44: shoulder portion, TR: trench

Claims

1. A semiconductor device (1), A semiconductor substrate (10) partitioned into active and non-active areas; A lower electrode (22) covering the lower surface of the semiconductor substrate; an upper surface electrode (24) covering at least a portion of an active region of the upper surface of the semiconductor substrate; a gate wiring (26) covering at least a portion of a non-active region of the upper surface of the semiconductor substrate; A plurality of trenches (TR) provided in an upper layer portion of the semiconductor substrate, the plurality of trenches including a first trench and a second trench spaced apart from the first trench; a gate insulating film (34) covering the inner surfaces of the first trench and the second trench; a gate electrode (32) provided inside each of the first trench and the second trench and separated from the semiconductor substrate by the gate insulating film, the gate electrode being separated from the upper electrode by an interlayer insulating film (42) in the active region and electrically connected to the gate wiring in the non-active region; The semiconductor substrate is A first semiconductor region (14) of n-type; a p-type second semiconductor region (16) provided on the first semiconductor region and disposed between the first trench and the second trench; a third semiconductor region (18) of n-type provided on the second semiconductor region and disposed between the first trench and the second trench; In the active region, the third semiconductor region is in contact with the upper electrode, In the non-active region, the gate insulating film covers an upper surface of the semiconductor substrate and separates the upper surface of the semiconductor substrate from the gate wiring; A semiconductor device, wherein a distance between the first trench and the second trench is longer in the non-active area than in the active area.

2. 2. The semiconductor device according to claim 1, wherein a distance between said first trench and said second trench in said active region is such that said second semiconductor region exhibits a bulk channel effect.

3. 2. The semiconductor device of claim 1, wherein a radius of curvature of the shoulders of the first and second trenches is greater in the non-active area than in the active area.

4. The semiconductor device according to claim 1 , wherein the material of the semiconductor substrate is silicon carbide.

5. 5. The semiconductor device according to claim 4, wherein a distance between said first trench and said second trench in said active region is 150 nm or less.

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