Delta-sigma modulator and delta-sigma modulation method

Abstract

To more effectively reduce the influence of an operation error that may occur near the boundary between signal blocks of output signals.SOLUTION: A delta-sigma modulator (1100, 2000) includes: a distribution unit (120) configured to divide an input signal into a plurality of signal blocks; a signal processing unit (110) that, for each of the plurality of signal blocks, applies a delay to the signal block with a predetermined delay amount; a parallel circuit unit (130, 150) that includes delta-sigma modulation circuits configured to be arranged in parallel, execute delta-sigma modulation processing on the plurality of signal blocks in parallel, and output a plurality of output signals corresponding to the plurality of signal blocks; and a coupling unit (140) configured to execute coupling processing of coupling the plurality of output signals to each other.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present disclosure relates to a delta-sigma modulation device and a delta-sigma modulation method. [Background technology]

[0002] In the field of wireless communication, technological developments are underway to achieve high-speed communication in order to cope with increasing traffic.

[0003] Usually, to realize high-speed communication, a wireless communication device needs to have a high-speed and high-precision digital-to-analog converter (DAC). However, since the price and power consumption of such a DAC are generally high, there is a problem that the manufacturing cost and power consumption of a wireless communication device equipped with a DAC are generally high.

[0004] In order to solve the above-mentioned problems, a delta-sigma modulation device can be used. The delta-sigma modulation device converts a multi-bit digital signal, which is an input signal, into a bit string of one bit, and outputs the bit string as an output signal. The output signal is passed through a low-pass filter having a pass band equal to the signal band of the input signal. This makes it possible to obtain an analog signal that is almost equivalent to the input signal.

[0005] The use of a delta-sigma modulator eliminates the need for a DAC, thereby reducing the manufacturing costs and power consumption of wireless communication devices. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2005-006273 A Summary of the Invention [Problem to be solved by the invention]

[0007] For example, when processing a high-speed digital signal having a sampling frequency exceeding 1 Gsamples / sec, it is difficult to process such a digital signal using only one delta-sigma modulation circuit. Patent Document 1 discloses a delta-sigma modulator that separates an input signal, provides the separated input signal to a plurality of paths, and performs delta-sigma modulation in parallel in each of the plurality of paths. With this configuration, high-speed digital signals can be processed.

[0008] On the other hand, a configuration in which delta-sigma modulation is performed in parallel in each of a plurality of paths has a problem in that calculation errors occur near the boundaries of signal blocks of the output signal.

[0009] The present disclosure provides a technique for effectively reducing the influence of calculation errors that may occur near boundaries of signal blocks in an output signal. [Means for solving the problem]

[0010] A delta-sigma modulation device according to one embodiment of the present invention includes a distribution unit configured to divide an upsampled input signal into a plurality of signal blocks, a signal processing unit that imparts a delay to each of the plurality of signal blocks by a predetermined delay amount, a parallel circuit unit arranged in parallel and configured to perform delta-sigma modulation processing on the plurality of signal blocks in parallel, and a combination unit configured to perform a combination process to combine the plurality of output signals.

[0011] A method performed by a computing device according to one aspect of the present invention includes splitting an upsampled input signal into a plurality of signal blocks, for each of the plurality of signal blocks, delaying the signal block by a predetermined delay amount, performing a delta-sigma modulation process in parallel on the plurality of signal blocks, and performing a combining process to combine the plurality of output signals. Effect of the Invention

[0012] According to the above configuration, it is possible to more effectively reduce the influence of calculation errors that may occur near the boundaries of signal blocks of an output signal, compared with the technology described in Patent Document 1. Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief description of the drawings]

[0013] [Figure 1] 1 illustrates an example of the configuration of a delta-sigma modulation device 100. [Diagram 2] FIG. 2 illustrates an example of the configuration of a delta-sigma modulation circuit 200. [Diagram 3] FIG. 2 illustrates an example of the configuration of a delta-sigma modulation circuit 300. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of an error feedback type delta-sigma modulation circuit 400. [Diagram 5] 1 is a diagram showing an example of the relationship between an input signal to a parallel circuit section 130 and an output signal from a combining section 140. FIG. [Figure 6] 11 is a table showing the circuit state of the delta-sigma modulation circuit 131-1 in the process of processing signal block #J. [Figure 7] 11 is a table showing the circuit state of the delta-sigma modulation circuit 132-1 in the process of processing signal block #J+1. [Figure 8] 11 is a table showing the circuit state of the delta-sigma modulation circuit 132-1 in the process of processing signal block #J+1. [Figure 9] FIG. 13 is a diagram showing an example of an area in a signal block where a calculation error may occur. [Figure 10] 11 is a graph showing an example of a calculation error due to discontinuity calculated by simulation. [Figure 11] FIG. 1 illustrates an example of a configuration of a delta-sigma modulation device 1100. [Figure 12] 4 shows the relationship between a signal before a delay is applied and a signal after a delay is applied. [Figure 13] FIG. 13 is a diagram showing an example in which a delay is applied to a signal block. [Figure 14] 1 is a graph showing constellation calculation results for a signal processed by a delta-sigma modulator. [Figure 15] 1 is a graph showing constellation calculation results for a signal processed by a delta-sigma modulator. [Figure 16] 1 is a graph showing constellation calculation results for a signal processed by a delta-sigma modulator. [Figure 17] 1 is a graph showing constellation calculation results for a signal processed by a delta-sigma modulator. [Figure 18] 11 is a flowchart showing the flow of processing executed by delta-sigma modulation device 1100. [Figure 19] FIG. 19 illustrates an example of an information processing device 1900 for implementing the delta-sigma modulation device 1100. [Figure 20] FIG. 2 illustrates an example of the configuration of a delta-sigma modulation device 2000. [Figure 21] 13 is a flowchart showing the flow of processing executed by the delta-sigma modulation device 2000. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, one or more embodiments will be described with reference to the accompanying drawings. In this disclosure, the drawings are related to one or more embodiments. In this specification and drawings, elements that can be similarly described are given the same reference numerals to avoid redundant description.

[0015] The explanation will be given in the following order: 1. First embodiment 1-1. Overview of the embodiment 1-2. Details of the embodiment 1-3.Hardware configuration 2. Second embodiment 3. Third embodiment 4. Other embodiments

[0016] <<1. First embodiment>> The first embodiment will be described below.

[0017] <1-1. Overview of the embodiment> For example, assume that a high-speed digital signal having a sampling frequency exceeding 1 Gbps is to be processed, and since the operating frequency of a hardware circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) is lower than the sampling frequency of the input signal, it is difficult to process the input signal using only one delta-sigma modulation circuit.

[0018] In order to solve the above problems, a delta-sigma modulation device including a plurality of delta-sigma modulation circuits may be used. In this configuration, the plurality of delta-sigma modulation circuits are arranged in parallel. The delta-sigma modulation device divides an input signal into a plurality of signal blocks of a predetermined data length, and inputs the plurality of signal blocks to the plurality of delta-sigma modulation circuits, respectively. With this configuration, high-speed digital signals can be processed.

[0019] 1 is a diagram showing an example of a configuration of a delta-sigma modulation device 100. The delta-sigma modulation device 100 includes a signal processing section 110, a distribution section 120, a parallel circuit section 130, and a combining section 140.

[0020] The signal processing unit 110 upsamples the multi-bit digital data that is the input signal. The signal processing unit 110 also applies a delay to the digital data that it processes. These will be described in detail later.

[0021] The distributor 120 includes a first storage unit 121 and a first selection unit 122. The first storage unit 121 stores multi-bit digital data, which is an input signal. The first selection unit 122 receives the digital data from the first storage unit 121. The first selection unit 122 divides the digital data into a plurality of signal blocks. The first selection unit 122 inputs the plurality of signal blocks to the parallel circuit unit 130.

[0022] The parallel circuit unit 130 includes a plurality of filter circuits 131 and 132. The plurality of filter circuits 131 and 132 are arranged in parallel. The first selection unit 122 inputs a plurality of signal blocks to the plurality of filter circuits 131 and 132, respectively. The signal block input to the filter circuit 131 and the signal block input to the filter circuit 132 are different (i.e., they do not overlap with each other).

[0023] The filter circuit 131 includes a delta-sigma modulation circuit 131-1. The delta-sigma modulation circuit 131-1 performs delta-sigma modulation processing on a plurality of data included in a signal block. As described later, the signal block has a predetermined data length. The delta-sigma modulation circuit 131-1 performs processing in order from the first data to the last data included in the signal block. The delta-sigma modulation circuit 131-1 outputs an output signal (a bit string of 1 bit) to the combining unit 140.

[0024] Similarly, the filter circuit 132 includes a delta-sigma modulation circuit 132-1. The delta-sigma modulation circuit 132-1 performs delta-sigma modulation processing on a plurality of data included in a signal block. The delta-sigma modulation circuit 132-1 performs processing in order from the first data to the last data included in the signal block. The delta-sigma modulation circuit 132-1 outputs an output signal (a bit string of 1 bit) to the combining unit 140.

[0025] The combining unit 140 includes a second storage unit 141 and a second selection unit 142. The second storage unit 141 stores an output signal from the delta-sigma modulation circuit 131-1 and an output signal from the delta-sigma modulation circuit 132-1. The second selection unit 142 outputs a plurality of output signals stored in the second storage unit 141. The second selection unit 142 outputs the processing results (1-bit bit strings) of the signal blocks input to the second storage unit 141 in order starting from the earliest.

[0026] Hereinafter, for the sake of explanation, the signal block data input to the delta-sigma modulation circuit is referred to as “input data.” The processing result (i.e., the output signal) output from the delta-sigma modulation circuit is referred to as “output data.”

[0027] 2 is a diagram showing an example of the configuration of a delta-sigma modulation circuit 200. The delta-sigma modulation circuit 200 is an Nth-order delta-sigma modulation circuit. N represents the order of the delta-sigma modulation circuit. The larger the value of N, the better the noise shaping performance, which is a feature of the delta-sigma modulation circuit. In this example, for simplicity of explanation, N=3, but the present invention is not limited to this configuration. A fourth-order or higher delta-sigma modulation circuit may also be used.

[0028] The delta-sigma modulation circuit 200 includes integrators 210-1, 210-2, and 210-3, adder-subtractors 220-1, 220-2, and 220-3, a quantization section 230, and a delay unit 240.

[0029] The integrators 210-1, 210-2, and 210-3 are connected in series. The adder-subtractors 220-1, 220-2, and 220-3 are disposed on the input sides of the integrators 210-1, 210-2, and 210-3, respectively.

[0030] The output signal of integrator 210-1 is input to quantization section 230. Quantization section 230 quantizes the output signal of integrator 210-1 and outputs a 1-bit bit string as output data. The output data is stored in delay device 240. Thereafter, the output data is fed back to adder-subtractors 220-1, 220-2, and 220-3.

[0031] Therefore, the adder-subtractor 220-3 outputs a signal calculated from the input data and the output data to the integrator 210-3 as an output signal. The integrator 210-3 processes the output signal of the adder-subtractor 220-3 and outputs the output signal to the adder-subtractor 220-2. The adder-subtractor 220-2 outputs a signal calculated from the output signal of the integrator 210-3 and the output data to the integrator 210-2 as an output signal. The integrator 210-2 processes the output signal of the adder-subtractor 220-2 and outputs the output signal to the adder-subtractor 220-1. The adder-subtractor 220-1 outputs a signal calculated from the output signal of the integrator 210-2 and the output data to the integrator 210-1 as an output signal. The integrator 210-1 processes the output signal of the adder-subtractor 220-1 and outputs the output signal to the quantization unit 230.

[0032] The integrators 210-1, 210-2, and 210-3 have the same configuration. Here, only the integrator 210-1 will be described, and descriptions of the other integrators 210-2 and 210-3 will be omitted. The integrator 210-1 includes an adder-subtractor 211-1 and a delay unit 212-1. The output signal of the adder-subtractor 211-1 is fed back to the adder-subtractor 211-1 via the delay unit 212-1.

[0033] 2, the delta-sigma modulation circuit 200 is a type of infinite impulse response (IIR) filter. The delta-sigma modulation circuit 200 includes a quantization unit 230 arranged on a feedback path, and outputs a 1-bit bit string as output data.

[0034] Fig. 3 is a diagram showing an example of the configuration of a delta-sigma modulation circuit 300. The delta-sigma modulation circuit 300 is a modified example of the configuration of the delta-sigma modulation circuit 200 in Fig. 2. The delta-sigma modulation circuit 300 is also called an "error feedback type Nth order delta-sigma modulation circuit." Note that in this example, N=3 for ease of explanation, but the present invention is not limited to this configuration. A fourth or higher order delta-sigma modulation circuit may also be used.

[0035] The delta-sigma modulation circuit 300 includes adders / subtractors 310-1, 310-2, and 310-3, feedback amount calculation sections 320-1, 320-2, and 320-3, a quantization section 330, and an adder / subtractor 340.

[0036] The adder-subtractor 310-3 outputs a signal calculated from the input data and the output signal of the feedback amount calculation unit 320-3 to the adder-subtractor 310-2 as an output signal. The adder-subtractor 310-2 outputs a signal calculated from the output signal of the adder-subtractor 310-3 and the output signal of the feedback amount calculation unit 320-2 to the adder-subtractor 310-1 as an output signal. The adder-subtractor 310-1 outputs a signal calculated from the output signal of the adder-subtractor 310-2 and the output signal of the feedback amount calculation unit 320-1 to the quantization unit 330 as an output signal.

[0037] The quantization unit 230 quantizes the output signal of the adder-subtractor 310-1 and outputs a 1-bit data string as output data. The adder-subtractor 340 outputs the output signal of the adder-subtractor 310-1 and a signal calculated from the output data as an output signal to the feedback amount calculation unit 320-1. The output signal of the adder-subtractor 340 is also fed back to the feedback amount calculation units 320-2 and 320-3.

[0038] The feedback amount calculation units 320-1, 320-2, and 320-3 have the same configuration. Here, the feedback amount calculation unit 320-1 will be described. The feedback amount calculation unit 320-1 includes a multiplier 321-1, a delay unit 322-1, and a coefficient memory unit 323-1. The coefficient memory unit 323-1 stores a feedback gain A1. The output signal of the adder-subtractor 340 is input to the multiplier 321-1 via the delay unit 322-1. The multiplier 321-1 multiplies the output signal of the adder-subtractor 340 by the feedback gain A1, and outputs the multiplication result to the adder-subtractor 310-1.

[0039] The other feedback amount calculation units 320-2 and 320-3 differ from the feedback amount calculation unit 320-1 in the following points: A coefficient memory 323-2 of the feedback amount calculation unit 320-2 stores a feedback gain A2. A coefficient memory 323-3 of the feedback amount calculation unit 320-3 stores a feedback gain A3.

[0040] As described above, the delta-sigma modulation circuit 300 has a configuration in which the output signal of the adder-subtractor 340 (i.e., the error signal between the input signal and output signal of the quantization section 330) is fed back to the adders-subtractors 310-1, 310-2, and 310-3 via the feedback amount calculation sections 320-1, 320-2, and 320-3.

[0041] When all of the feedback gains A1, A2, and A3 are 1, the configuration of the delta-sigma modulation circuit 200 in Fig. 2 is equivalent to the configuration of the delta-sigma modulation circuit 300 in Fig. 3. On the other hand, the delta-sigma modulation circuit 300 can be implemented with fewer components (e.g., adders / subtractors and delayers) than the delta-sigma modulation circuit 200. The delta-sigma modulation circuit 300 has an advantage over the delta-sigma modulation circuit 200 in that the circuit scale of the delta-sigma modulation circuit 300 can be made smaller than that of the delta-sigma modulation circuit 200.

[0042] Furthermore, in the delta-sigma modulation circuit 300, the feedback amount calculation section 320-1 multiplies the error signal (i.e., the output signal of the adder-subtractor 340) by a feedback gain A1. The feedback amount calculation sections 320-2 and 320-3 can also perform similar processing. There is also an advantage that the noise shaping characteristics can be controlled by adjusting the feedback gains A1, A2, and A3.

[0043] In the following, one or more embodiments using an error feedback type Nth order delta-sigma modulation circuit will be described, where N=2 for simplicity of explanation.

[0044] Fig. 4 is a diagram showing an example of the configuration of an error feedback type delta-sigma modulation circuit 400. Regarding the delta-sigma modulation circuit 400, the same components as those in the delta-sigma modulation circuit 300 in Fig. 3 are given the same reference numerals, and duplicated explanations will be omitted.

[0045] 3, the delta-sigma modulation circuit 400 further includes an adjustment unit 350. When the leading data of a signal block is input as input data, the adjustment unit 350 initializes the values ​​of the delay devices 322-1 and 322-2.

[0046] FIG. 5 is a diagram showing an example of the relationship between the input signal to the parallel circuit section 130 and the output signal from the combining section 140. As shown in FIG.

[0047] The first selection unit 122 of the distribution unit 120 divides the digital data into a number of signal blocks of a predetermined time length. Here, the signal block has a predetermined data length "I". That is, the signal block includes I data segments. Each of the I data segments is a collection of data into which the data block is divided at a predetermined time length. In addition, identification numbers (signal block numbers) are assigned in order from the signal block with the earliest input time. The Jth (J is a natural number) signal block is expressed as "signal block #J".

[0048] The xth data of signal block #J is expressed as "a(J,x)". The smaller the value of J or x, the earlier the data to which that value is assigned is input. As described above, if signal block #3 includes I data segments, the first (first) data of signal block #3 is expressed as a(3,1), and the Ith (last) data is expressed as a(3,I).

[0049] The first selection unit 122 alternately inputs a plurality of signal blocks to the filter circuits 131 and 132, starting from signal block #1 that was input earliest. For example, the first selection unit 122 inputs a certain signal block #J to the filter circuit 131, and inputs the next signal block #J+1 to the filter circuit 132. The first selection unit 122 repeatedly executes such an operation.

[0050] Through the above operations, the first selection unit 122 distributes the odd-numbered signal blocks to the filter circuits 131 in the order in which they were input to the distribution unit 120. The first selection unit 122 distributes the even-numbered signal blocks to the filter circuits 132 in the order in which they were input to the distribution unit 120.

[0051] The delta sigma modulation circuit 131-1 of the filter circuit 131 processes I data segments (input data) included in a signal block in the input order, and outputs output data corresponding to the signal block to the second storage unit 141 of the combining unit 140. The delta sigma modulation circuit 132-1 of the filter circuit 132 processes I data segments (input data) included in a signal block in the input order, and outputs output data corresponding to the signal block to the second storage unit 141 of the combining unit 140. The delta sigma modulation circuits 131-1 and 132-1 each have the configuration shown in FIG. 4. Just before the delta sigma modulation circuit 131-1 processes the first data of each signal block, the adjustment unit 350 sets the values ​​of the delay units 322-1 and 322-2 to initial values. For example, zero is used as the initial value. Similarly, immediately before the delta-sigma modulation circuit 132-1 processes the leading data of each signal block, the adjustment section 350 sets the values ​​of the delay devices 322-1 and 322-2 to their initial values.

[0052] Here, the value obtained by multiplying the time length of a signal block (= the number of data segments included in a signal block × the sampling time) by the number of filter circuits (in this example, 2) is referred to as the "first time." If the filter circuits 131 and 132 complete the processing within the first time, the filter circuits 131 and 132 can execute the processing in real time. In other words, if the drive frequency of the hardware circuit is equal to or greater than 1 / (the sampling frequency) the number of filter circuits, the filter circuits 131 and 132 can execute the processing in real time.

[0053] The second selection section 142 of the combining section 140 outputs data in order from the data stored in the second storage section 141 earliest in time (that is, the data processed by the parallel circuit section 130 earliest in time).

[0054] For example, in the example of FIG. 5, at time t0, the first selection unit 122 starts inputting the signal block #1 to the filter circuit 131. At time t1, the delta sigma modulation circuit 131-1 of the filter circuit 131 starts processing the signal block #1. At time t2, the second selection unit 142 of the combining unit 140 starts outputting the processing result of the signal block #1. In parallel with this processing, the delta sigma modulation circuit 132-1 of the filter circuit 132 executes processing on the signal block #2. At time t3, the delta sigma modulation circuit 132-1 ends the processing on the signal block #1. At time t4, the second selection unit 142 ends the output of the processing result of the signal block #1. Thereafter, the second selection unit 142 starts outputting the processing result of the signal block #2.

[0055] According to the above configuration, high-speed digital data can be processed by a hardware circuit having a drive frequency lower than the sampling frequency of the input signal.

[0056] However, the above configuration has a problem that a calculation error occurs near the boundary between successive signal blocks. The delta-sigma modulation circuits 131-1 and 132-1 process temporally successive signal blocks in parallel. For example, assume that the delta-sigma modulation circuit 131-1 processes a preceding signal block, and the delta-sigma modulation circuit 132-1 processes a succeeding signal block. In this case, the delta-sigma modulation circuit 131-1 cannot notify the delta-sigma modulation circuit 132-1 of the state (final state) at the time when it processes the last data of the signal block. This problem will be described with reference to Figs. 6 and 7.

[0057] Each row of the tables in Figures 6 and 7 may be referred to as a "circuit state" when processing the data of the signal block. In particular, the circuit state for the data at the beginning of the signal block may be referred to as an "initial state." Furthermore, the circuit state for the data at the end of the signal block may be referred to as a "final state."

[0058] Hereinafter, J is an odd number. It is assumed that the delta-sigma modulation circuit 131-1 processes a preceding signal block #J, and the delta-sigma modulation circuit 132-1 processes a succeeding signal block #J+1.

[0059] Fig. 6 is a table showing the circuit state of the delta-sigma modulation circuit 131-1 in the process of processing signal block #J. Specifically, Fig. 6 shows combinations of the values ​​of the delay devices 322-1 and 322-2 and the output value (error signal) of the adder-subtracter 340 in the process of processing data (data segment) a(J,I-2) to data a(J,I).

[0060] For example, in the row of data a(J,I-2), the value of the delay unit 322-1 is d(J,I-3), and the value of the delay unit 322-2 is d(J,I-4). d(J,I-3) corresponds to the output value of the adder-subtractor 340 when the data a(J,I-3) is processed. d(J,I-4) corresponds to the output value of the adder-subtractor 340 when the data a(J,I-4) is processed. Therefore, when the data a(J,I-2) is processed, the output value of the adder-subtractor 340 one time before d(J,I-3), the output value of the adder-subtractor 340 two times before d(J,I-4), and the data a(J,I-2) are used to obtain d(J,I-2) as the output value of the adder-subtractor 340. The same applies to the other rows.

[0061] Fig. 7 is a table showing the circuit state of the delta-sigma modulation circuit 132-1 in the process of processing the signal block #J+1. Specifically, Fig. 7 shows combinations of the values ​​of the delay devices 322-1 and 322-2 and the output value (error signal) of the adder-subtracter 340 in the process of processing data a(J+1,1) to a(J+1,3).

[0062] Here, there is a problem that the circuit state in the first row of the table in Fig. 7 cannot be realized. This is for the following reason. When the delta-sigma modulation circuit 132-1 processes the data a(J+1,1), the delta-sigma modulation circuit 131-1 has not yet completed the processing (for example, see Fig. 5). Specifically, the delta-sigma modulation circuit 131-1 has not yet completed the processing for the data a(J,I-1) and the processing for the data a(J,I). The delta-sigma modulation circuit 132-1 cannot receive the value to be stored in the delay unit 322-1 (i.e., d(J,I)) and the value to be stored in the delay unit 322-2 (i.e., d(J,I-1)) from the delta-sigma modulation circuit 131-1.

[0063] Therefore, the delta-sigma modulation circuit 132-1 has no choice but to process the data a(J+1,1) using initial values ​​(eg, the most probable values) as the values ​​of the delay devices 322-1 and 322-2.

[0064] Fig. 8 is a table showing the circuit state of the delta-sigma modulation circuit 132-1 in the process of processing the signal block #J+1, and shows an example in which initial values ​​are set as the values ​​of the delay devices 322-1 and 322-2. The initial value is preferably the value with the highest occurrence probability among the output values ​​of the adder-subtractor 340, but for simplicity, it is assumed to be zero in the following. Therefore, in Fig. 8, the initial value is assumed to be zero. For example, immediately before the delta-sigma modulation circuit 132-1 processes the first data a(J+1,1) of the signal block #J+1, the adjustment unit 350 sets the values ​​of the delay devices 322-1 and 322-2 to their initial values ​​(=zero).

[0065] As described above, when processing the first data a(J+1,1) of signal block #J+1, the delta-sigma modulation circuit 132-1 cannot use the circuit state (i.e., the final state) when processing the last data a(J,I) of the preceding signal block #J. Therefore, for example, the output value d(J+1,1) of the adder-subtractor 340 in the table of Fig. 7 and the output value d'(J+1,1) of the adder-subtractor 340 in the table of Fig. 8 may be different data strings.

[0066] The output signal of the combiner 140 is passed through an analog low-pass filter to remove quantization noise that spreads on both sides of the signal spectrum. When such processing is performed for each of the patterns in Figures 7 and 8 and the signals are compared, errors may occur near the boundaries of the signal blocks. Hereinafter, such errors are referred to as "computation errors due to discontinuities." Note that if the data string happens to have a small difference between the signals d(J+1,x) and d'(J+1,x), the computation errors due to discontinuities will be minimal.

[0067] The region in which a calculation error occurs due to discontinuity is a certain time region from the beginning and end of a signal block, which depends on the impulse response length of the transmission path from the output of delta-sigma modulation device 100 to the low-pass filter.

[0068] In the following, for simplicity, it is assumed that only a low-pass filter is arranged in the subsequent stage of the parallel delta-sigma modulation device (delta-sigma modulation circuits 131-1 and 132-1), and the time domain in which calculation errors occur due to discontinuity depends on the impulse response length of the low-pass filter.

[0069] For example, the impulse response length of the low-pass filter is set to l times (l is a real number equal to or greater than zero) the sampling interval of the output signal of the parallelized delta-sigma modulation device. In this case, the low-pass filter can be represented by an FIR (Finite Impulse Response) filter. This FIR filter has L taps, and the value of the filter coefficient of each tap is the impulse response.

[0070] For simplicity, in the following, we assume that the number of taps L of the FIR filter representing the low-pass filter is an odd number, and that the tap with the maximum absolute value of the filter coefficient is located in the center of the FIR filter. The position of that tap is L j =(L+1) / 2.

[0071] In this case, the output value of signal block #(J+1) is d'(J+1,1) to d'(J+1,Lj -1) to (L j -1) data segments are the L j In this case, the output signal of the FIR filter is the output value of the preceding signal block #J, d'(J,I-(L j Since it is affected by the data segment from d'(J,I) to d'(J,I), there is a possibility that calculation errors will occur due to discontinuity.

[0072] Similarly, the output value of signal block #(J+1), d'(J+1,I-(L j -1)+1) to d'(J+1,I) j -1) data segments are the L j In this case, the output signal of the FIR filter is affected by the data segment from d'(J+2,1) to d'(J+2,Lj-1), which is the output value of the subsequent signal block #(J+2), so there is a possibility that a calculation error will occur due to discontinuity.

[0073] In other words, the calculation error due to discontinuity is j −1) This can occur for output values ​​of data segments.

[0074] FIG. 9 shows an area where a calculation error may occur within a signal block processed by the filter circuit 131 (delta sigma modulation circuit 131-1) and the filter circuit 132 (delta sigma modulation circuit 132-1).

[0075] 9 shows the input signal to delta-sigma modulation device 100, and the gray frame shows data on the symbol map. The second row shows digital data obtained by upsampling the input signal by signal processing unit 110.

[0076] In the example shown in Fig. 9, signal block #(J+5) is distributed to filter circuit 131, and signal block #(J+6) is distributed to filter circuit 131. As shown in Fig. 9, in signal block #(J+5) processed by filter circuit 131, calculation errors are likely to occur within a predetermined region from the beginning and end. Similarly, in signal block #(J+6) processed by filter circuit 132, calculation errors are likely to occur within a predetermined region from the beginning and end.

[0077] Fig. 10 is a graph showing an example of a calculation error due to discontinuity calculated by simulation. The horizontal axis is time. The vertical axis is the square error between a signal obtained by passing an output signal in a configuration including the delta-sigma modulation circuits arranged in parallel through an analog low-pass filter, and a signal obtained by passing an output signal in a configuration not including the delta-sigma modulation circuits arranged in parallel through an analog low-pass filter. In the calculation of Fig. 10, an OFDM signal with a signal bandwidth of 1 GHz and a sampling frequency of 12.5 GSps is used as an input signal, and the data length of the signal block is 10,000.

[0078] In Figure 10, the impulse-like squared error occurring at a period of 0.8 μs (= 1 / 12.5 GSps × 10,000 pieces) is a calculation error caused by discontinuity. The magnitude of the calculation error caused by discontinuity varies. This is for the following reason. If the value of the delay device 322-1 and the output value of the adder / subtractor 340 in the final state of the delta-sigma modulation circuit responsible for processing the preceding signal block are significantly different from the initial value (= zero), a large squared error will occur, but if the values ​​happen to be close, the squared error will be small.

[0079] The invention described in Patent Document 1 does not impart a delay to a signal that is to be processed between multiple paths, nor does it reduce the effects of calculation errors that may occur near the boundaries of signal blocks in the output signal.

[0080] One or more embodiments described below provide a technique for reducing the effects of calculation errors that may occur near boundaries of signal blocks in an output signal more effectively than the related techniques described above (e.g., Patent Document 1).

[0081] <1-2. Details of the embodiment> Figure 11 is a diagram showing an example of the configuration of a delta-sigma modulation device 1100. Figure 11 shows a more detailed configuration of the delta-sigma modulation device 100 described with reference to Figure 1. With regard to delta-sigma modulation device 1100, the same components as those in the above-described delta-sigma modulation device 100 are given the same reference numerals, and duplicated explanations will be omitted.

[0082] The signal processing unit 110 includes an upsampling processing unit 111 and a delay adding unit 112. Multi-bit width digital data, which is an input signal, is processed by the upsampling processing unit 111 and the delay adding unit 112.

[0083] The upsampling processing unit 111 upsamples the input signal at a sampling rate that is at least twice as fast as the input signal, and outputs the upsampled signal to the delay adding unit 112. The upsampling process may involve inserting one or more zeros into a predetermined section of temporally continuous digital data, and then passing the data through a low-pass filter. The upsampling process may involve inserting one or more values ​​identical to the digital data into a predetermined section of temporally continuous digital data (called a primary hold process), and then passing the data through a filter that offsets the aperture effect caused by the primary hold process. The upsampling process may involve a combination of the above two processes.

[0084] One type of upsampling process is the sample-and-hold process, which doubles the sampling rate and repeats the bits of the input signal twice. For example, if the input data sequence is x(0), x(1), x(2), x(3), ..., the sample-and-hold process results in the data sequence x(0), x(0), x(1), x(1), x(2), x(2), x(3), x(3), ....

[0085] Hereinafter, the ratio of the sampling frequency of the signal after upsampling processing to the sampling frequency of the input signal to the upsampling processing unit 111 will be referred to as an oversampling factor.

[0086] The noise transfer function of delta-sigma modulation generally forms a high-pass filter. As a result, the quantization noise added by the 1-bit quantization process of delta-sigma modulation is at a low level relative to the input signal level in the low frequency region near DC, but is at a high level in the high frequency region. This characteristic is called noise shaping of delta-sigma modulation.

[0087] The wider the frequency range that can be expressed by the digital data of the input signal of delta-sigma modulation, that is, the higher the sampling frequency of the digital data, the wider the frequency range near DC where quantization noise is suppressed. This results in a higher SNR of the output signal of delta-sigma modulation. Therefore, in order to improve the signal quality of the output signal of delta-sigma modulation, it is desirable for the oversampling factor in the above-mentioned upsampling process to be large. However, it should be noted that if the oversampling factor is large, the number of parallel circuits increases, making it impossible to implement the circuit in an integrated circuit such as an FPGA or an ASIC.

[0088] The delay imparting unit 112 imparts a delay of a predetermined time to the signal input from the upsampling processing unit 111, and outputs the delayed signal to the distribution unit 120. The delay imparted to the signal is set to, for example, q times (q is an integer) the sampling interval (the reciprocal of the sampling frequency). In this case, the delay imparting unit 112 may be composed of q delay devices.

[0089] As described above, the object of this embodiment is to reduce the influence of calculation errors that may occur near the boundaries of signal blocks of the output signal. In accordance with this object, the delay imparting unit 112 imparts a delay to the signal input from the upsampling processing unit 111 so as to reduce the influence of calculation errors that may occur near the boundaries of signal blocks of the output signal.

[0090] When the delay adding unit 112 adds a delay to the input signal, this means that when the first selection unit 122 of the distribution unit 120 divides the input signal into signal blocks, the positions of the boundaries of each signal block are shifted forward in time.

[0091] FIG. 12 shows the relationship between before and after a delay is applied to a signal. For example, the upper part of FIG. 12 shows a data string from the beginning to the 25th data of an upsampled input signal before a delay is applied, which is divided into signal blocks including five data segments with a signal block length I=5. The dotted lines show the positions of the boundaries of the signal blocks. On the other hand, the lower part of FIG. 12 shows a signal to which a delay of 2 has been applied to the input signal in the upper part, and it can be seen that the signal in the upper part is shifted backward in time by two data segments (to the right in FIG. 12) compared to the signal in the upper part. Note that x, which is a data segment generated by applying a delay, may be the initial value of a delayer (for example, zero), etc. The first selection unit 122 divides data into signal block lengths I (I=5 in FIG. 12) from the beginning of the input signal, and therefore it can be seen that the positions of the boundaries of the signal blocks are shifted forward in time for the signal before the delay is applied.

[0092] By shifting the position of the boundary forward in time, the upsampled data located at the same time as the pre-upsampling data is not placed in the area near the boundary of each signal block. Hereinafter, the above process will be described as "adding a delay to a signal block" or "delaying a signal block."

[0093] 5 and 7, when the delta-sigma modulation circuit 132-1 shown in Fig. 5 processes the data a(J+1,1), the delta-sigma modulation circuit 131-1 has not yet completed the processing. Therefore, the delta-sigma modulation circuit 132-1 cannot receive the value to be stored in the delay unit 322-1 (i.e., d(J,I)) and the value to be stored in the delay unit 322-2 (i.e., d(J,I-1)) from the delta-sigma modulation circuit 131-1.

[0094] The calculation error that may occur near the boundary of the signal block may be caused by the above-mentioned. That is, in a configuration in which a plurality of delta-sigma modulation circuits process a plurality of signal blocks in parallel, a calculation error may occur when a second delta-sigma modulation circuit processes a predetermined data segment (second data segment) in a second signal block that follows the first signal block before a first delta-sigma modulation circuit completes processing of a predetermined data segment (first data segment) in the first signal block. The second data segment is a data segment that follows the first data segment.

[0095] In this embodiment, the delay imparting unit 112 imparts a predetermined delay to each signal block processed by each of the delta-sigma modulation circuits. The delay depends on the impulse response length of the transmission path from the output of the delta-sigma modulation device 1100 to the low-pass filter.

[0096] Figure 13 shows an example of adding a delay to a signal block, in comparison with the example shown in Figure 9. In Figure 13, a delay is added to the signal block by a delay amount d (time) corresponding to an area where calculation errors are likely to occur, and the signal block is then processed. By adding a delay to the signal block in this way, it is possible to process the signal block while avoiding areas where calculation errors are likely to occur.

[0097] Desirably, the delay providing unit 112 provides a delay to each signal block such that after the first delta-sigma modulation circuit has completed processing a first data segment in the first signal block, the second delta-sigma modulation circuit processes a second data segment in the second signal block.

[0098] The signal block to which the delay has been applied by the delay applying unit 112 is output to the distribution unit 120, which divides the signal into signal blocks and distributes them to the delta-sigma modulation circuits 131-1 and 131-2. The delay applied to the input signal by the delay applying unit 112 causes a shift on the time axis to occur in the digital data included in the signal blocks distributed to the delta-sigma modulation circuits 131-1 and 131-2.

[0099] As described above, before the delta-sigma modulation circuit 131-1 completes the processing of the first segment in the signal block #J, the delta-sigma modulation circuit 131-2 processes the second segment in the signal block #J+1, which causes a calculation error due to discontinuity in the time domain near the boundary between the signal blocks. The second data segment is a data segment following the first data segment. By applying a predetermined delay to the input signal by the delay applying unit 112, a change occurs in the data that is affected by the calculation error due to discontinuity.

[0100] For example, assume that the delay applied by delay unit 112 to signal block #J+1 is zero (no delay is applied), that is, that a calculation error due to discontinuity has occurred in the output values ​​of data a(J+1,1) to a(J+1,I) of signal block #(J+1).

[0101] In this case, if the amount of delay applied by delay applying unit 112 is changed to q=5 (q is the sampling interval (the reciprocal of the sampling frequency)), the digital data included in signal block #(J+1) changes to a(J,I-4) to a(J,I) and a(J+1,1) to a(J+1,I-5). A calculation error occurs due to discontinuity in the output values ​​of the first of these, a(J,I-4) to a(J,I) and a(J+1,1) to a(J+1,I-5).

[0102] As described above, by applying a delay using delay applying section 112, it is possible to adjust data in which calculation errors occur due to discontinuity.

[0103] In this embodiment, the delay imparting unit 112 imparts delays to signal blocks to be processed in parallel with respect to the input signal, thereby reducing the influence of calculation errors due to discontinuity.

[0104] In this embodiment, the delay adding unit 112 adjusts the delay amount d so that after a first delta-sigma modulation circuit among the multiple delta-sigma modulation circuits has completed processing a first signal block, a second delta-sigma modulation circuit processes a second signal block subsequent to the first signal block. This delay amount d is adjusted so as not to affect the signal quality after demodulation processing of the received signal in the receiver.

[0105] As described above, if the input signal after upsampling processing by the upsampling processing unit 111 is represented by x(i), the input signal before upsampling processing is represented by x(kj), where k is the oversampling factor. As described above, the first selection unit 122 divides the input data into J signal blocks, and each signal block is divided into I data segments.

[0106] The input signal x(kj) before upsampling is a modulated signal, which represents a data string of symbol points of the modulation method. The digital data from x(kj+1) to x(kj-1) is interpolated by the upsampling process of the upsampling processor 111.

[0107] Here, the bit string output as a result of processing x(i) by the parallel delta-sigma modulation device (delta-sigma modulation circuits 131-1 and 132-1) is denoted as y(i), and the signal obtained by passing the bit string y(i) through a low-pass filter is denoted as z(i).

[0108] If we assume that no calculation error occurs due to discontinuity, the difference between the value of x(i) and the value of z(i) is very small, and the value of x(i) and the value of z(i) can be considered to be the same. In this case, the modulated signal x(kj) itself can be obtained by performing a 1 / k-fold downsampling process on z(i) to extract z(kj).

[0109] Note that because the quantization error due to delta-sigma modulation is added even within the signal band of x(i), strictly speaking the value of x(i) and the value of z(i) do not match perfectly; however, since the feedback loop gains A1 and A2 are usually selected so that the difference is small, they can be considered to be identical.

[0110] On the other hand, if we assume that a calculation error due to discontinuity occurs in y(kj), a difference occurs between the value of x(kj) and the value of z(kj), and z(kj) deviates from the symbol point, thereby degrading the signal quality of z(i).

[0111] In this embodiment, the delay amount d is adjusted so that data x(kj) on the symbol point of the modulation method is not placed as much as possible in the area from the data at the beginning and end of each signal block to the impulse response length of the low-pass filter. This makes it possible to prevent the influence of calculation errors due to discontinuity.

[0112] In the following, the tap length L of the FIR filter representing the low-pass filter is L = 2L as mentioned above. j +1(L j is an integer equal to or greater than zero).

[0113] Let I = kp (p is an integer equal to 1 or greater that is equal to I when multiplied by the oversampling factor k) for signal block length I, and assume that x(0) is placed at the beginning of signal block #1 when the delay d = 0. In this case, x(kp(J-1)), which is included in the set of data represented by x(kj), is placed at the beginning of signal block #J (J is an integer equal to 1 or greater), and a calculation error occurs in the output y(kp(J-1)) due to discontinuity.

[0114] d≧L j When a delay corresponding to the delay amount d satisfying -1 is applied to x(i), x(kp(J-1)) is calculated as (L j Therefore, y(kp(J-1)) will not be included in the (-1)th data segment. Therefore, no calculation error due to discontinuity occurs in y(kp(J-1)).

[0115] where d ≥ k-(L j If a delay amount d that satisfies (d(p-1)) is applied to x(i), then y(k(p-1)), which is the output of x(k(p-1)) placed near the end of signal block #J, will be affected by the output value of the data placed near the beginning of signal block #(J+1) when it passes through the low-pass filter, causing a calculation error due to discontinuity.

[0116] From the above, the delay amount d is L j -1≦d≦k-(L j -1)-1. Under the condition that both the left and right inequalities in the above inequality regarding the delay amount d are equal, the effect of calculation errors of discontinuities occurring in both y(kp(J-1)) and y(k(pJ-1)) can be reduced. The value of the delay amount d under this condition is d=L j -1=(k-1) / 2~k / 2.

[0117] Therefore, by adding a delay of about 1 / 2 the oversampling factor k, it is possible to suppress calculation errors due to discontinuities occurring in z(kj).

[0118] In addition, when the tap length L of the FIR filter representing the low-pass filter is larger than the oversampling factor k, there is no solution that satisfies the above inequality, but generally there is a solution for L that has a peak value. j The impulse response values ​​of the k taps in total, centered on the th tap, are large and dominant. Therefore, in this case, by adding a delay of about 1 / 2 the oversampling factor k, it is possible to suppress calculation errors caused by discontinuities that occur in z(kj).

[0119] The smaller the tap length L of the FIR filter representing the low-pass filter, the narrower the time domain in which calculation errors due to discontinuity occur. In order to reduce the tap length L, it is necessary to expand the passband width of the low-pass filter, but this poses the problem of a decrease in the performance of removing the quantization noise added by delta-sigma modulation. To solve this problem, it is necessary to increase the cutoff frequency of the noise pass function of delta-sigma modulation by increasing the order of delta-sigma modulation or adjusting the feedback loop gain, thereby separating the quantization noise as much as possible from the signal band.

[0120] So far, we have expressed low-pass filters using FIR filters, and the L j Although it has been assumed that the th tap is located in the center, even if it is not located in the center, it is possible to deal with the case by fine-tuning the value of the delay amount d from the above k / 2.

[0121] Fig. 14 is a graph showing the result of calculating the constellation when a 256QAM modulated signal is input to a parallel delta-sigma modulation device, the output signal is passed through an ideal low-pass filter with rectangular frequency characteristics, and then demodulated. Here, the oversampling factor is k=64, and the signal block length is I=k×256=16384. Fig. 14 is a graph showing the result of calculating the constellation when the delay amount d is set to d=0.

[0122] The EVM (Error Vector Magnitude) shown in FIG. 14 is 0.53.

[0123] Fig. 15 is a graph showing the results of calculating the constellation when a 256QAM modulated signal is input to a parallel delta-sigma modulator, the output signal is passed through an ideal low-pass filter with rectangular frequency characteristics, and then demodulated. Here, the oversampling factor is k=64, and the signal block length is I=k×256=16384. Fig. 15 is a graph showing the results of calculating the constellation when the delay amount d is set to d=k / 4=16.

[0124] The EVM shown in FIG. 15 is 0.39, and it is clear that the EVM when a delay of 1 / 4 the oversampling factor is applied is improved to about 1 / 2 of the case when no delay is applied.

[0125] Fig. 16 is a graph showing the results of calculating the constellation when a 256QAM modulated signal is input to a parallel delta-sigma modulator, the output signal is passed through an ideal low-pass filter with rectangular frequency characteristics, and then demodulated. Here, the oversampling factor is k=64, and the signal block length is I=k×256=16384. Fig. 16 is a graph showing the results of calculating the constellation when the delay amount d is set to d=k / 2=32.

[0126] The EVM shown in FIG. 16 is 0.24, and it is clear that the EVM when a delay of 1 / 2 the oversampling factor is applied is improved to about 1 / 2 of the EVM when no delay is applied.

[0127] Fig. 17 is a graph showing the results of calculating the constellation when a 256QAM modulated signal is input to a parallel delta-sigma modulator, the output signal is passed through an ideal low-pass filter with rectangular frequency characteristics, and then demodulated. Here, the oversampling factor is K=64, and the signal block length is I=k×256=16384. Fig. 17 is a graph showing the results of calculating the constellation when the delay amount d is set to d=3k / 4=48.

[0128] The EVM shown in FIG. 17 is 0.40, and it is clear that the EVM when a delay of 3 / 4 of the oversampling factor is applied is improved to about 1 / 2 of the case when no delay is applied.

[0129] As described above, by adding a delay to the input signal (signal after upsampling processing) to parallel circuit section 130 and not placing data contained in the input signal (signal before upsampling processing) to delta-sigma modulation device 1100 in an area where calculation errors occur due to discontinuity near the beginning of a signal block, it is possible to prevent degradation of signal quality when demodulating the output signal of the delta-sigma modulation device.

[0130] Next, a description will be given of the flow of processing executed by delta-sigma modulation apparatus 1100. FIG.

[0131] In the signal processing unit 110, the upsampling processing unit 111 upsamples the input signal, and outputs the upsampled signal to the delay adding unit 112 (1801).

[0132] The delay imparting unit 112 imparts a delay to the signal input from the upsampling processing unit 111, and outputs the delayed signal to the distribution unit 120 (1802). The delay is imparted by calculating the amount of delay d, as described above.

[0133] In the distribution unit 120, the first selection unit 122 divides the signal (digital data) input from the signal processing unit 110 into a plurality of blocks and distributes the blocks to the delta-sigma modulation circuits 131-1 and 132-1 (1803). At this time, a delay is applied to each of the signal blocks (#1, #2, ... #J) by a delay amount d.

[0134] In the parallel circuit unit 130, the delta-sigma modulation circuits 131-1 and 132-1 each perform delta-sigma modulation processing on the signal block distributed from the distribution unit 120 (1804). At this time, processing is performed for each of I data segments in the signal block. The processed signal is output to the combination unit 140.

[0135] In the combining unit 140, the second selecting unit 142 outputs the signal input from the delta-sigma modulation circuit 131-1 and the signal input from the delta-sigma modulation circuit 132-1 in order starting from the signal block processing results (1-bit bit strings) (1805).

[0136] This completes the description of the flow of processing executed by delta-sigma modulation device 1100. According to the above configuration, it is possible to effectively suppress calculation errors due to discontinuities.

[0137] <1-3. Hardware configuration> Next, a description will be given of a hardware configuration for implementing delta-sigma modulation device 1100. Fig. 19 is a diagram showing an example of an information processing device 1900 for implementing delta-sigma modulation device 1100.

[0138] The information processing device 1900 includes a processor 1910, a memory 1920, an input interface 1930, and an output interface 1940. The processor 1910, the memory 1920, the input interface 1930, and the output interface 1940 are connected to each other via a bus 1950.

[0139] The processor 1910 may include, for example, one or more of a central processing unit (CPU), a micro processing unit (MPU), and a microcontroller. The processor 1910 executes a program 1918 stored in a memory 1920 to realize a delta-sigma modulation device according to one or more of the above embodiments.

[0140] The memory 1920 is an element that temporarily or permanently stores programs (instructions) 1918 and data used to execute various processes in the delta-sigma modulation device. The memory 1920 includes volatile memory and non-volatile memory. The volatile memory may include, for example, a random access memory (RAM). The non-volatile memory may include, for example, one or more of a read only memory (ROM), a hard disk drive (HDD), and a solid state drive (SSD). The memory 1920 includes an input signal storage unit 1921 for temporarily storing an input signal, and an output signal storage unit 1823 for temporarily storing an output signal.

[0141] The input interface 1930 is an interface for receiving input from a user or another information processing device, and the output interface 1940 is an interface for outputting to a display unit (not shown) or another information processing device.

[0142] As described above, the first embodiment has been described. According to the configuration of the first embodiment, it is possible to effectively suppress calculation errors due to discontinuities, compared to the conventional technology.

[0143] <<2. Second embodiment>> Next, a second embodiment will be described. The second embodiment includes a configuration having three or more delta-sigma modulation circuits arranged in parallel.

[0144] Fig. 20 is a diagram showing an example of the configuration of a delta-sigma modulation device 2000. The delta-sigma modulation device 2000 includes a signal processing unit 110, a distribution unit 120, a parallel circuit unit 150, and a coupling unit 140. The signal processing unit 110, the distribution unit 120, and the coupling unit 140 are similar to the signal processing unit 110, the distribution unit 120, and the coupling unit 140 described with reference to Fig. 1, and therefore description thereof will be omitted.

[0145] The parallel circuit unit 150 includes a plurality of filter circuits 151, 152, ... 15n (n is an integer equal to or greater than 3). The plurality of filter circuits 151 to 15n are arranged in parallel. The first selection unit 122 inputs a plurality of signal blocks to the plurality of filter circuits 151 to 15n, respectively. The signal blocks input between the filter circuits 151 to 15n are different (i.e., do not overlap with each other).

[0146] The filter circuit 151 includes a delta-sigma modulation circuit 151-1. The filter circuit 152 includes a delta-sigma modulation circuit 152-1. The filter circuit 15n includes a delta-sigma modulation circuit 15n-1. The delta-sigma modulation circuits 151-1 to 15n-1 are similar to the delta-sigma modulation circuits 131-1 and 132-1 described with reference to FIG. 1, and therefore description thereof will be omitted.

[0147] The distributor 120 (first selector 122) distributes the signal blocks to each of the filter circuits 151 to 15n. The distribution method may be, for example, a round robin method to distribute the signal blocks in order and evenly, but is not necessarily limited to such a method. Also, for example, when the number of filter circuits arranged in parallel is an even number and the number of signal blocks to be distributed is an odd number, the signal blocks are not necessarily distributed evenly to the filter circuits.

[0148] For the signal blocks distributed by the distribution unit 120, the preceding signal block serves as a reference signal block for the signal block following the given signal block. For example, assume that signal block (J+2) is distributed to the filter circuit 152 (delta-sigma modulation circuit 152-1) and signal block (J+3) is distributed to the filter circuit 153 (delta-sigma modulation circuit 153-1). In this case, signal block (J+2) serves as a reference signal block for signal block (J+3).

[0149] In the above example, the delta-sigma modulation circuit 153-1 applies a delay to the signal block (J+3) so that the processing of the predetermined data segment in the reference signal block (J+2) is completed when the predetermined data segment in the signal block (J+3) is processed. The predetermined data segment in the signal block (J+3) is the data segment following the predetermined data segment in the reference signal block (J+2).

[0150] Next, a description will be given of the flow of processing executed by delta-sigma modulation device 2000. FIG. 21 is a flowchart for explaining an example of the flow of processing executed by delta-sigma modulation device 2000.

[0151] In the signal processing unit 110, the upsampling processing unit 111 upsamples the input signal, and outputs the upsampled signal to the delay adding unit 112 (2101).

[0152] The delay imparting unit 112 imparts a delay to the signal input from the upsampling processing unit 111, and outputs the delayed signal to the distribution unit 120 (2102). The delay is imparted by calculating the amount of delay d, as described above.

[0153] In the distribution unit 120, the first selection unit 122 divides the signal (digital data) input from the signal processing unit 110 into a plurality of blocks and distributes the blocks to the delta-sigma modulation circuits 151-1 to 15n-1 (2103). The distribution is performed, for example, by adopting a round robin method. At this time, a delay of a delay amount d is applied to each of the signal blocks (#1, #2, ... #J).

[0154] In the parallel circuit unit 150, the delta-sigma modulation circuits 151-1 and 15n-1 each perform delta-sigma modulation processing on the signal block distributed from the distribution unit 120 (2104). At this time, processing is performed for each of I data segments in the signal block. The processed signal is output to the combining unit 140.

[0155] In the combining unit 140, the second selecting unit 142 outputs the signals input from the delta-sigma modulation circuits 151-1 to 15n-1 in order starting from the processing results (1-bit bit strings) of the signal blocks (2105).

[0156] As described above, the second embodiment has been described. According to the configuration of the second embodiment, even with three or more delta-sigma modulation circuits arranged in parallel, it is possible to efficiently suppress calculation errors due to discontinuity.

[0157] <<3. Third embodiment>> Next, a third embodiment will be described. The third embodiment includes a configuration in which the number of parallel processes by a plurality of delta-sigma modulation circuits and / or the number / length of signal blocks into which an input signal is divided are variable.

[0158] The configuration of the delta-sigma modulation device according to the third embodiment is similar to the configuration of the delta-sigma modulation device described with reference to FIG. 20, and therefore description thereof will be omitted.

[0159] In the third embodiment, delta-sigma modulation processing is executed by three or more delta-sigma modulation circuits arranged in parallel. Such a configuration can speed up the processing, but the power consumption increases due to more circuits being executed among the plurality of delta-sigma modulation circuits.

[0160] Also, by dividing the signal block into a larger number / smaller length, more signal blocks are processed in parallel, so the processing speed can also be increased, but the overhead for adding delay to each signal block increases.

[0161] In the third embodiment, when distributing the input signal, the number of parallel processes by the delta-sigma modulation circuit is set to an appropriate number. For example, in a configuration where delta-sigma modulation circuits 151-1 to 15n-1 are arranged in parallel, the input signal is distributed to delta-sigma modulation circuits 151-1 to 15s-1 according to the application or the like (s is an integer of 1 or more).

[0162] The number of parallel processes may be specified by an input parameter according to the application. For example, in applications that require high-speed processing, s>n, that is, the number of parallel processes is increased. On the other hand, in applications that do not require high-speed processing, s<n, that is, the number of parallel processes is decreased in order to reduce overhead and power consumption.

[0163] The number of parallel processes may be dynamically determined depending on the size of the input signal (data) or the like. In this case, the first selection unit 122 determines the number of parallel processes according to the length of the data.

[0164] In addition to or instead of the above, when distributing the input signal, by setting the number / length of the signal blocks to be distributed, the number of signal blocks to be divided is set to an appropriate number. For example, depending on the application or the like, a case where the input signal is divided into J signal blocks and a case where the input signal is divided into J' signal blocks are determined.

[0165] The number of signal blocks to be divided may be specified by an input parameter according to the application. For example, in applications that require high-speed processing, J’>J, that is, the number of signal blocks to be divided is increased. On the other hand, in applications that do not require high-speed processing, J’<J, that is, the number of signal blocks to be divided is decreased in order to reduce overhead and the like.

[0166] The number of signal blocks to be divided may be dynamically determined by, for example, the size of the input signal (data). In this case, the first selection unit 122 determines the number of signal blocks to be divided according to the length of the data.

[0167] As described above, the third embodiment has been explained. According to the configuration according to the third embodiment, the input signal can be processed with an appropriate number of parallel processes / number of signal blocks to be divided according to the application and the like.

[0168] <<4. Other Embodiments>> Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments. It will be understood by those skilled in the art that these embodiments are merely examples and that various modifications can be made without departing from the scope and spirit of the present disclosure.

[0169] For example, the steps in the processes described in this specification do not necessarily have to be executed in time series in the order described in the sequence diagram. For example, the steps in the process may be executed in an order different from the order described as the sequence diagram, or may be executed in parallel. Also, some of the steps in the process may be deleted, and further steps may be added to the process.

[0170] Also, a method executed by a computer device including the processing of the above components may be provided. Also, a program for causing a processor in a computer device to execute the processing of the above components may be provided. Furthermore, a non-transitory computer readable medium having the program recorded thereon may be provided. Naturally, such an apparatus, module, method, program, and non-transitory computer readable medium are also included in the scope of the present disclosure.

[0171] A part or all of the above-described embodiments may be described as, but is not limited to, the following supplementary notes.

[0172] (Appendix 1) a distributor configured to divide the upsampled input signal into a plurality of signal blocks; a signal processing unit that applies a delay to each of the plurality of signal blocks by a predetermined delay amount; a parallel circuit unit arranged in parallel and configured to perform delta-sigma modulation processing on the plurality of signal blocks in parallel to output a plurality of output signals corresponding to the plurality of signal blocks; a combining unit configured to perform a combining process for combining the plurality of output signals; A delta-sigma modulator comprising:

[0173] (Appendix 2) 2. The delta-sigma modulation device according to claim 1, wherein the signal processing unit is further configured to determine the delay amount based on an impulse response.

[0174] (Appendix 3) The output signal is passed through a filter; the impulse response is based on an impulse response length of a transmission path from an output of the delta-sigma modulation device to the filter; 3. The delta-sigma modulation device of claim 2.

[0175] (Appendix 4) The signal processing unit includes: determining the delay amount based on an upsampling ratio for upsampling the input signal; 4. The delta-sigma modulation device of claim 1, further configured as follows:

[0176] (Appendix 5) 5. The delta-sigma modulation device according to claim 4, wherein the signal processing unit is further configured to determine the delay amount based on a value obtained by adding 1 / 2 of the upsampling magnification to an integer multiple of the upsampling magnification.

[0177] (Appendix 6) the parallel circuit unit includes a first filter circuit and a second filter circuit, the first filter circuit processes a first signal block of the plurality of signal blocks; the second filter circuit processes a second signal block subsequent to the first signal block among the plurality of signal blocks; The signal processing unit is further configured to determine the delay amount such that the first filter circuit completes processing a first data segment in the first signal block before the second filter circuit processes a second data segment in the second signal block; The second data segment is a data segment subsequent to the first data segment. 6. A delta-sigma modulation device according to any one of claims 1 to 5.

[0178] (Appendix 7) 7. The delta-sigma modulation device according to claim 1, wherein the distribution unit is further configured to determine a number into which the signal block is to be divided, and to divide the input signal into the plurality of signal blocks based on the determined number.

[0179] (Appendix 8) The distributor is further configured to determine the number of parallel processes for performing the delta-sigma modulation processes in parallel; the parallel circuit unit is further configured to perform the delta-sigma modulation processing on the plurality of signal blocks in parallel based on the determined number of parallel processing. 8. A delta-sigma modulation device according to any one of claims 1 to 7.

[0180] (Appendix 9) 1. A method implemented by a computing device, comprising: Dividing the upsampled input signal into a plurality of signal blocks; for each of the plurality of signal blocks, delaying the signal block by a predetermined delay amount; performing delta-sigma modulation processing on the plurality of signal blocks in parallel to output a plurality of output signals corresponding to the plurality of signal blocks; performing a combining process for combining the plurality of output signals; A method comprising:

[0181] (Appendix 10) When executed, the method causes a processor in a computing device to: Dividing the upsampled input signal into a plurality of signal blocks; for each of the plurality of signal blocks, delaying the signal block by a predetermined delay amount; performing delta-sigma modulation processing on the plurality of signal blocks in parallel to output a plurality of output signals corresponding to the plurality of signal blocks; performing a combining process for combining the plurality of output signals; A program to execute. [Explanation of symbols]

[0182] 1100, 2000: Delta Sigma Modulator 110: Signal processing unit 120:Distribution section 130, 150: Parallel circuit section 140: Junction

Claims

1. a distributor configured to divide the upsampled input signal into a plurality of signal blocks; a signal processing unit that applies a delay to each of the plurality of signal blocks by a predetermined delay amount; a parallel circuit unit arranged in parallel and configured to perform delta-sigma modulation processing on the plurality of signal blocks in parallel to output a plurality of output signals corresponding to the plurality of signal blocks; a combining unit configured to perform a combining process for combining the plurality of output signals; A delta-sigma modulator comprising:

2. The delta-sigma modulation device according to claim 1 , wherein the signal processing unit is further configured to determine the delay amount based on an impulse response.

3. The output signal is passed through a filter; the impulse response is based on an impulse response length of a transmission path from an output of the delta-sigma modulation device to the filter; 3. The delta-sigma modulation device according to claim 2.

4. The signal processing unit includes: determining the delay amount based on an upsampling ratio for upsampling the input signal; 4. The delta-sigma modulation device according to claim 1, further configured to:

5. 5. The delta-sigma modulation device according to claim 4, wherein the signal processing unit is further configured to determine the delay amount based on a value obtained by adding 1 / 2 of the upsampling factor to an integer multiple of the upsampling factor.

6. the parallel circuit unit includes a first filter circuit and a second filter circuit, the first filter circuit processes a first signal block of the plurality of signal blocks; the second filter circuit processes a second signal block subsequent to the first signal block among the plurality of signal blocks; The signal processing unit is further configured to determine the delay amount such that the first filter circuit completes processing a first data segment in the first signal block before the second filter circuit processes a second data segment in the second signal block; The second data segment is a data segment subsequent to the first data segment.

2. The delta-sigma modulation device according to claim 1.

7. The delta-sigma modulation device according to claim 1 , wherein the distributor is further configured to determine a number into which the signal block is to be divided, and to divide the input signal into the plurality of signal blocks based on the determined number.

8. The distributor is further configured to determine the number of parallel processes for performing the delta-sigma modulation processes in parallel; the parallel circuit unit is further configured to perform the delta-sigma modulation processing on the plurality of signal blocks in parallel based on the determined number of parallel processing.

2. The delta-sigma modulation device according to claim 1.

9. 1. A method implemented by a computing device, comprising: Dividing the upsampled input signal into a plurality of signal blocks; for each of the plurality of signal blocks, delaying the signal block by a predetermined amount of delay; performing delta-sigma modulation processing on the plurality of signal blocks in parallel to output a plurality of output signals corresponding to the plurality of signal blocks; performing a combining process for combining the plurality of output signals; A method comprising:

10. When executed, the method causes a processor in a computing device to: Dividing the upsampled input signal into a plurality of signal blocks; for each of the plurality of signal blocks, delaying the signal block by a predetermined delay amount; performing delta-sigma modulation processing on the plurality of signal blocks in parallel to output a plurality of output signals corresponding to the plurality of signal blocks; performing a combining process for combining the plurality of output signals; A program to execute.

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